ASAHI KASEI
[AK8817/18]
AK8817/18
NTSC/PAL Digital Video Encoder
General Description
The AK8817/18 is a Digital Video Encoder for Portable and Mobile application. ITU-R BT.601 level compatible Y, Cb,and Cr
signals which correspond to 27MHz or square pixel are encoded into either NTSC or PAL compatible composite video signal.
Interface is made in HSYNC-, VSYNC- synchronized slave-mode operation or ITU-R.Bt656. AK8817/18 has 75ohm driver with
LPF.
It is possible to encode the VBID(CGMS-A) and WSS signal on the output video signal.
Host Control interface is I2C Bus I/F.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
NTSC-M, PAL-B, D, G, H, I Composite Video encoding
Y:Cb:Cr 4:2:2
H/V Slave Operation / ITU-R.BT656 Interface
Y filtering: 2 x over-sampling
C filtering: 4 x over-sampling
9bit DAC
Setup
Macrovision Rev.7.1.1L （*1） AK8818）
VBID ( CGMS-A ) Compatible
WSS Compatible
Operation Clock rate : 27MHz or Square-pixel Clock rate(NTSC:24.5454MHz/PAL29.50MHz)
Video Amp with LPF
On-chip Color Bar Output
Black Burst Output
Power Supply (AVDD, DVDD) 2.7V - 3.3V
I/F Power Supply (PVDD) 1.6V - 3.3V
Power Down mode
Monolithic CMOS
41pin FBGA(4mm x 4mm) / 48pin LQFP (7mm x 7mm) (*2)
(Notice *1) This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other
intellectual rights. The use of Macrovision’s copy protection technology in the device must be authorized by
Macrovision and is intended for home and other limited pay-per -view use only, unless otherwise authorized in
written by Macrovision. Reverse engineering or disassembly is prohibited.
(Notice *2) This data sheet is compiled from package option devices. You will actually use, please refer to data
sheet for each package.
Rev.001E
1
2009 / 12
ASAHI KASEI
[AK8817/18]
Block Diagram
CLKIN
CLKINV
RSTN PDN
SCL
SDA
VREF
CLK
Generator
CGMS
u-p I/F
Register
Timing Controller
D[7:0]
Input Data Control
Synchronization Control
VDI
HDI
IREF
VREF
Generator
SYNC
Generator
Y
Y
LPF Filter
(x 2 Interpolator)
Cb
Cr
Cb/Cr
LPF Filter
(x 2 Interpolator)
SAG
6dB AMP
LPF
9-bit
DAC
U
Cos
SubCarrier
Generator
Color Bar Gen
B.B. Gen
C
Sin
VOUT
DACOUT
Chroma
LPF Filter
(x 2 Interpolator)
TEST
LOGIC
UD[4:0]
V
PVDD PVSS DVDD DVSS
Rev.001E
AVDD AVSS
2
TEST ATPG
2009 / 12
ASAHI KASEI
[AK8817/18]
Ordering Guide
AK8817VG
AK8818VG
AK8817VQ
AK8818VQ
41pin FBGA
41pin FBGA
48pin LQFP
48pin LQFP
Pin Assignment
7
6
5
4
3
2
1
A
B
C
D
E
F
G
Bottom View
[AK8817vG Pin Assignment]
A
B
C
D
E
F
G
1
NC
AVDD
VREF
UD3
UD1
CLKINV
NC
2
DACOUT
AVSS
IREF
UD4
UD2
UD0
CLKIN
3
SAG
BVSS
INDEX
4
VOUT
DVSS
5
DVDD
PDN
DVSS
DVDD
D7
D6
D5
D4
6
RSTN
SCL
HDI
PVSS
D0
D3
D2
7
NC
ATPG
SDA
VDI
PVDD
D1
TEST
6
RSTN
SCL
HDI
PVSS
D0
D3
D2
7
NC
ATPG
SDA
VDI
PVDD
D1
TEST
TOP View
[AK8818VG Pin Assignment]
A
B
C
D
E
F
G
1
NC
AVDD
VREF
UD3
UD1
CLKINV
NC
2
DACOUT
AVSS
IREF
UD4
UD2
UD0
CLKIN
3
SAG
BVSS
INDEX
4
VOUT
DVSS
5
DVDD
PDN
DVSS
DVDD
D7
D5
D6
D4
TOP View
Rev.001E
3
2009 / 12
ASAHI KASEI
[AK8817/18]
AK8817VQ / AK8818VQ
NC
NC
TEST
D1
D0
PVDD
PVSS
VDI
HDI
SDA
SCL
NC
36 35 34 3332 31 30 29 28 2726 25
ATPG
PDN
RSTN
DVSS
DVDD
NC
VOUT
BVSS
SAG
AVSS
DACOUT
NC
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
NC
D2
D3
24
23
22
21
20
19
18
17
16
15
14
13
NC
NC
D4
D5
D6
D7
DVDD
DVSS
CLKIN
CLKINV
NC
1 2 3 4 5 6 7 8 9 10 11 12
NC
NC
UD0
UD1
UD2
UD3
UD4
VREF
IREF
AVDD
NC
NC
AK8817VQ
NC
D2
TEST
D1
D0
PVDD
PVSS
VDI
HDI
SDA
SCL
NC
36 35 34 3332 31 30 29 28 2726 25
ATPG
PDN
RSTN
DVSS
DVDD
NC
VOUT
BVSS
SAG
AVSS
DACOUT
NC
37
38
39
40
41
42
43
44
45
46
47
48
D3
D4
D5
D6
D7
DVDD
DVSS
CLKIN
CLKINV
NC
1 2 3 4 5 6 7 8 9 10 11 12
NC
NC
UD0
UD1
UD2
UD3
UD4
VREF
IREF
AVDD
NC
NC
AK8818VQ
Rev.001E
4
2009 / 12
ASAHI KASEI
[AK8817/18]
Pin Functional Description
AK8817VG / AK8818VG
AK8818 is different pin assignment from AK8817.
Pin#
Pin Name
I/O
G2
CLKIN
I
F1
CLKINV
I
B5
PDN
I
A6
RSTN
I
C7
SDA
I
B6
SCL
I
F4
D7
I
G4
D6
I
F5
D5
I
G4
D5
I
F5
D6
I
G5
D4
I
F6
D3
I
G6
D2
I
F7
D1
I
E6
D0
I
C6
HDI
I
D7
VDI
I
C1
VREF
O
C2
IREF
O
A2
DACOUT
O
VOUT
SAG
AVDD
AVSS
DVDD
DVSS
O
I/O
P
G
P
G
A4
A3
B1
B2
A5, G3
B4, F3
Rev.001E
Functional Outline
Clock input pin.
Input a clock which is synchronized with data.
When to input 601 data : 27 MHz.
When to input square pixel data : 24.5454 MHz ( NTSC )/ 29.50 MHz ( PAL )
Internal clock is inverted (internal operation timing edge is inverted.)
Connect to either PVDD or PVSS(DGND).
Power Down Pin. After returning from PD mode to normal operation, RESET
Sequence should be done to AK8817/18.
“L “(GND level): Power-down
“H “: normal operation
Reset input pin. In order to initialize the device , an initialization must be made in
accordance with the reset sequence.
“L “ : reset
“H “ : normal operation
Hi-Z input is acceptable to this pin at PDN = L.
I2C data pin.
This pin is pulled-up to PVDD.
Hi-Z input is possible when PDN is at low.
SDA input is not accepted during the reset sequence operation.
I2C clock input pin
An input level of lower-than-PVDD should be input.
Hi-Z input is possible when PDN is at low.
SCL input is not accepted during the reset sequence operation.
Data Video Signal input pin (MSB).
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin. (AK8817)
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin. (AK8817)
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin. (AK8818)
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin. (AK8818)
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin (LSB).
Hi-Z input is acceptable to this pin at PDN = L.
Horizontal SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Vertical SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
On-chip VREF output pin.
AVSS level is output on this pin at PDN = L.
Connect this pin to Analog Ground via a 0.1 uF or larger capacitor.
IREF output pin. Connect this pin to Analog ground via a 12k ohm resistor
( better than +/- 1% accuracy ).
DAC output pin. Connect this pin to Analog ground via a 390 ohm resistor
( better than +/- 1% accuracy ).
Video output pin.
SAG Compensation Input pin
Analog power supply pin.
Analog ground pin.
Digital power supply pin (digital core power supply).
Digital ground pin (digital core ground).
5
2009 / 12
ASAHI KASEI
[AK8817/18]
E7
D6
PVDD
PVSS
P
G
B3
BVSS
G
G7
B7
TEST
ATPG
I
I
D2
D1
E2
E1
F2
UD4
UD3
UD2
UD1
UD0
O
O
O
I/O
I/O
C3
A1, A7,
G1
N.C.
-
Index pin. For normal operation, left open.
N.C.
-
For normal operation, left open.
Rev.001E
Power supply pin for chip pad.
Ground pin for PVDD.
Substrate ground pin.
Connect this pin to Analog ground
For normal operation, connect to ground.
For normal operation, connect to ground.
Test output pin. For normal operation, left open.
Test output pin. For normal operation, left open.
Test output pin. For normal operation, left open.
Test I/O pin. For normal operation, left open.
Test I/O pin. For normal operation, left open.
6
2009 / 12
ASAHI KASEI
[AK8817/18]
AK8817VQ/AK8818VQ
Pin#
Pin Name
I/O
Functional Outline
1
N.C.
-
For normal operation, left open.
2
N.C.
-
For normal operation, left open.
3
AVDD
P
Analog power supply pin.
IREF output pin. Connect this pin to Analog ground via a 12k ohm resistor
( better than +/- 1% accuracy ).
On-chip VREF output pin.
AVSS level is output on this pin at PDN = L.
Connect this pin to Analog Ground via a 0.1 uF or larger capacitor.
4
IREF
O
5
VREF
O
6
UD4
O
Test output pin. For normal operation, left open.
7
UD3
O
Test output pin. For normal operation, left open.
8
UD2
O
Test output pin. For normal operation, left open.
9
UD1
O
Test output pin. For normal operation, left open.
10
UD0
O
Test output pin. For normal operation, left open.
11
N.C.
-
For normal operation, left open.
12
N.C.
-
For normal operation, left open.
13
N.C.
-
For normal operation, left open.
14
CLKINV
I
15
CLKIN
I
16
DVSS
G
Digital ground pin (digital core ground).
17
DVDD
P
Digital power supply pin (digital core power supply).
18
D7
I
19
D6
I
20
D5
I
21
D4
I
22
D3
I
23
D2 (17)
N.C. (18)
I
Internal clock is inverted (internal operation timing edge is inverted.)
Connect to either DVDD or DGND.
Clock input pin.
Input a clock which is synchronized with data.
When to input 601 data : 27 MHz.
When to input square pixel data : 24.5454 MHz ( NTSC )/ 29.50 MHz ( PAL )
Data Video Signal input pin (MSB).
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
AK8817: Video Data Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
AK8818:
N.C.
For normal operation, left open.
24
N.C.
-
For normal operation, left open.
25
N.C.
-
For normal operation, left open.
26
N.C. (17)
D2 (18)
I
27
TEST
I
28
D1
I
29
D0
I
30
PVDD
P
AK8817: N.C.
For normal operation, left open.
AK8818: Video Data Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Rev.001E
For normal operation, connect to ground.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin (LSB).
Hi-Z input is acceptable to this pin at PDN = L.
Power supply pin for chip pad.
7
2009 / 12
ASAHI KASEI
[AK8817/18]
Pin#
Pin Name
I/O
31
PVSS
G
32
VDI
I
Functional Outline
Ground pin for PVDD.
Vertical SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Horizontal SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
I2C data pin.
This pin is pulled-up to PVDD.
Hi-Z input is possible when PDN is at low.
SDA input is not accepted during the reset sequence operation.
I2C clock input pin
An input level of lower-than-PVDD should be input.
Hi-Z input is possible when PDN is at low.
SCL input is not accepted during the reset sequence operation.
33
HDI
I
34
SDA
I/O
35
SCL
I
36
N.C.
-
For normal operation, left open.
37
ATPG
I
For normal operation, connect to ground.
Power Down Pin. After returning from PD mode to normal operation, RESET
Sequence should be done to AK8817/18VQ.
“L “(GND level): Power-down
“H “: normal operation
Reset input pin. In order to initialize the device , an initialization must be made in
accordance with the reset sequence.
“L “ : reset
“H “ : normal operation
Hi-Z input is acceptable to this pin at PDN = L.
38
PDN
I
39
RSTN
I
40
DVSS
G
Digital ground pin (digital core ground).
41
DVDD
P
Digital power supply pin (digital core power supply).
42
N.C.
-
For normal operation, left open.
43
VOUT
O
Video output pin.
44
BVSS
G
Substrate ground pin.
Connect this pin to Analog ground
45
SAG
O
SAG Compensation Input pin
46
AVSS
G
Analog ground pin.
47
DACOUT
O
48
N.C.
-
For normal operation, left open.
MODE / PIN name
IREF
VREF
DACOUT
VOUT
PDN＝L
PDN=H、DAC=L
VIDEOAMP=L
PDN=H、DAC=H
VIDEOAMP=L
PDN=H、DAC=H
VIDEOAMP=H
Hi-Z
Hi-Z
Output
Outpu
Hi-Z
Hi-Z
DAC Power Down
Hi-Z
Hi-Z
VIDEOAMP Power Down
Output
Output
Output
VIDEOAMP Power Down(1)
Output
Output
Output
Output
DAC output pin. Connect this pin to Analog ground via a 390 ohm resistor
( better than +/- 1% accuracy ).
Analog Output pin status
DAC: Sub Address 0x00 bit7 0: L->DACOFF 1: H->DACON
VIDEOAMP: Sub Address 0x01 bit3,4 00: L->VIDEOAMP_OFF 01,10: H-> VIDEOAMP_ON
Note1) Video Amp becomes power down. Since DACOUT pin and VOUT pin are connected with RESISTOR in the LSI,
DACOUT pin are not Hi-Z. In case of using only DAC, VOUT pin and SAG pin should be open states.
Rev.001E
8
2009 / 12
ASAHI KASEI
[AK8817/18]
Electrical Characteristics
(1) Absolute Maximum Ratings
Parameter
Supply voltage
DVDD, AVDD, PVDD
Min
Max
Units
-0.3
4.5
V
Digital Input pin voltage
(VinP)
-0.3
PVDD +0.3
V
Input pin current (Iin)
-10
10
mA
Note
D[7:0], HDI, VDI,
RSTN, PDN,
CLKIN,
CLKINV,SCL,
SDA
Exclude Power
supply pin.
-40
Storage temperature
125
°C
(Note1)
Power supply voltages are values where each ground pin ( DVSS = AVSS = PVSS ) is at 0 V( voltage reference ).
All power supply ground pins DVSS, AVSS and PVSS should be at same potential.
(2) Recommended Operating Conditions
(2-1) AK8817VG/AK8818VG
Parameter
Min
Typ.
Max
Units
Conditions
Supply voltage *
3.0
3.3
V
AVDD = DVDD
2.7
AVDD,DVDD
Interface power supply
1.6
1.8
DVDD
V
PVDD
Operating temperature
-40
85
°C
(Ta)
* Power supply voltages are values where each ground pin ( PVSS = AVSS = PVSS ) is at 0 V( voltage reference ).
All power supply ground pins DVSS, AVSS and PVSS should be at same potential.
(2-2) AK8817VQ/AK8818VQ
Parameter
Min
Typ.
Max
Units
Conditions
Supply voltage *
3.0
3.6
V
AVDD = DVDD
2.7
AVDD,DVDD
Interface power supply
1.6
1.8
DVDD
V
PVDD
Operating temperature
-40
105
°C
(Ta)
* Power supply voltages are values where each ground pin ( PVSS = AVSS = PVSS ) is at 0 V( voltage reference ).
All power supply ground pins DVSS, AVSS and PVSS should be at same potential.
Rev.001E
9
2009 / 12
ASAHI KASEI
[AK8817/18]
(3) DC Characteristics
(3-1) AK8817VG / AK8818VG
< Operating voltage: DVDD 2.7V~3.3V / PVDD 1.6 V~DVDD, loading condition 15 pF, temperature -40~+85°C >
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Digital input H voltage (VIH)
VIH
Digital input L voltage (VIL)
VIL
Digital input leak current
I2C (SDA) L output
0.8PVDD
V
PVDD=1.6 - DVDD
0.2PVDD
V
PVDD=1.6 - DVDD
IL
+/-10
uA
VOLC
0.4
V
IOLC = 3mA
( Note )
Digital output pins refer to D[7:0], HDI, VDI, PDN, RSTN, SCL, SDA,CLKIN and CLKINV pin outputs in general term.
(3-2) AK8817VQ / AK8818VQ
< Operating voltage: DVDD 2.7V~3.6V / PVDD 1.6 V~DVDD, loading condition 15 pF, temperature -40~+105°C >
Parameter
Symbol
Min
Typ
Max
Units
Conditions
2.7V≦PVDD≦DVDD
0.7PVDD
V
Digital input H voltage (VIH)
VIH
1.6V≦PVDD＜2.7V
0.8PVDD
2.7V≦PVDD≦DVDD
0.3PVDD
V
Digital input L voltage (VIL)
VIL
1.6V≦PVDD＜2.7V
0.2PVDD
Digital input leak current
I2C (SDA) L output
IL
+/-10
uA
VOLC
0.4
V
IOLC = 3mA
( Note )
Digital output pins refer to D[7:0], HDI, VDI, PDN, RSTN, SCL, SDA,CLKIN and CLKINV pin outputs in general term.
Rev.001E
10
2009 / 12
ASAHI KASEI
[AK8817/18]
(4) Analog Characteristics
Parameter
DAC resolution
DAC integral non-linearity ( error )
DAC differential non-linearity ( error )
DAC output full scale voltage
DAC output offset voltage
Video Amp Output Gain
Video Amp Full scale Level
Video Amp THD
Video Amp S/N
Symbol
1.18
5.0
-45
LPF Ripple
-1
LPF Stop Band Level
20
LPF Group Delay
On-chip reference voltage (VREF)
Reference voltage drift
1.17
AK8817VG / AK8818VG < AVDD = 3.0 V, temperature 25 °C >
AK8817VQ / AK8818VQ < AVDD = 3.3 V, temperature 25 °C >
Min
Typ
Max
Units
9
bit
+/- 0.6
+/- 2.0
LSB
+/- 0.4
+/- 1.0
LSB
1.28
1.38
V
Note1)
5.0
mV
Note2)
6.0
7.0
dB
Amp Input Level 1Vpp
2.0
Vpp
Note3)
100kHz
5.5MHz Note4)
-51
dB
100kHz
5.5MHz Note4)
54
dB
100kHz - 5.5MHz
+/- 0.5
+1
dB
0dB = 100kHz input
27MHz
30
dB
0dB = 100kHz input
10
100
ns
|GD3MHz - GD6MHz|
1.23
1.30
V
-50
ppm/°C
Note1) Values are when a 390 ohm output load, a 12k ohm IREF pin resistor and on-chip VREF are used.
Full scale output current is calculated as Iout = full scale output voltage ( typ. 1.28 V ) / 390 ohm = typ. 3.28 mA.
Note2) A voltage referenced to VSS when a decimal zero voltage is input to DAC.
Note3) VOUT Output Level Output Load Resistor: 150ohm, Load Capacitor: 15pF Internal Color Bar output
Note4) Output signal from DAC to which Input data corresponded 1Vpp. This signal is input to AMP.
Load resistor is 150ohm and Load capacitor is 15pF as shown bellow figure at (5) Current Consumption.
Rev.001E
11
2009 / 12
ASAHI KASEI
[AK8817/18]
(5) Current consumption
(5-1) AK8817VG / AK8818VG
Parameter
Total power consumption
Power-down current 1
Digital part operating current 1
Analog part operating current 1
Analog part operating current 2
Analog part operating current 3
Symbol
< Operating voltage : DVDD = AVDD = PVDD = 3.0 V, Ta = +25 °C >
Min
Typ
Max
Units
27
35
mA
Note1)
10
30
uA
Note2)
13
mA
Note3)
14
mA
Note4)
5.5
mA
Note5)
0.8
mA
Note6)
(5-1) AK8817VQ / AK8818VQ
Parameter
Total power consumption
Power-down current 1
Digital part operating current 1
Analog part operating current 1
Analog part operating current 2
Analog part operating current 3
Symbol
< Operating voltage : DVDD = AVDD = PVDD = 3.3 V, Ta = +25 °C >
Min
Typ
Max
Units
29
38
mA
Note1)
10
30
uA
Note2)
13
mA
Note3)
14
mA
Note4)
5.5
mA
Note5)
0.8
mA
Note6)
Note1) operation at 27 MHz, NTSC mode on-chip 75% color bar output is enabled and Video Amp output is “ on “ ( no
external output loads are connected except for recommended components. ). 15pF capacitors in following figure represent
PCB layout-capacitor.
AK8817
1uF
AK8817
75ohm
SAG
100uF
75ohm
SAG
47uF
VOUT
15pF
75ohm
15pF
VOUT
15pF
75ohm
15pF
SAG Compensation OFF
SAG Compensation ON
Note2) measuring conditions :
input / output settings after power-down sequence are, PDN pin is at GND level, CLKOUT and SDO output are at high
level ( power supply voltage ) with no external connection, input voltage on those input pins is 1/2 level of power supply
which are set to accept Hi-Z input at power-down, and TEST = ATPG = GND ( or left open ).
Power supplies are AVDD = DVSS = PVDD.
Each ground pin ( DVSS, AVSS, PVSS ) is always 0 V ( voltage reference ).
Note3) Operation at 27 MHz, NTSC mode on-chip 75% color bar output is enabled.
Note4) DAC ON, Video Amp On SAG Compensation On
Note5) DAC ON, Video Amp Off (SAG Compensation Off)
Note6) DAC Off, Video Amp Off (SAG Compensation Off)
Rev.001E
12
2009 / 12
ASAHI KASEI
[AK8817/18]
AC Timing
loading condition : CL = 15 pF
AK8817VG / AK8818VG < DVDD 2.7 V ~ 3.3 V / PVDD 1.6 V ~ DVDD, Ta at -40 ~ +85 °C >
AK8817VQ / AK8818VQ < DVDD 2.7 V ~ 3.3 V / PVDD 1.6 V ~ DVDD, Ta at -40 ~ +105°C >
(1) CLK
fCLKI
tCLKIL
1/2 PVDD
tCLKIH
VIH
CLKIN
Parameter
VIL
Symbol
Min.
Typ.
Max
Unit
24.5454
CLKIN
fCLKI
MHz
27
29.50
CLK duty ratio
pCLKID
40
CLK Accuracy
60
%
100
ppm
Conditions
PIXRT=1
NTSC
PIXRT=0
NTSC/PA
PIXRT=1
PAL
tCLKIL, tCLKIH : minimum pulse width 12 nS ( tr/tf10%-90%Level Rising/Falling time ≤ 2nS)
Rev.001E
13
2009 / 12
ASAHI KASEI
[AK8817/18]
(2) Pixel Data Input Timing
VIH
CLKIN
VIL
tDH
tDS
D[7:0]
HDI
VDI
CLKINV = Low
Parameter
Symbol
Min.
Typ.
Max
Unit
Data Setup Time
tDS
5
nsec
Data Hold Time
tDH
8
nsec
Conditions
When CLKINV = High, similar tDS and tDH are specified at the falling edge of CLKOUT.
(3) HSYNC pulse width
pHSW
HSYNC
Parameter
HDI Pulse Width
Symbol
pHSW
Min.
Typ.
15
116
15
128
Max
Unit
Conditions
NTSC
(24.5454MHz)
CLKs
27MHz
PAL
(29.50MHz)
* typical values are calculated by converting the HSYNC pulse width of Analog Video specification into number of system
clock pulses.
15
Rev.001E
14
139
2009 / 12
ASAHI KASEI
[AK8817/18]
(4) Reset
(4-1) Reset Timing
RSTN
pRES
1
2
99
100
CLKIN
Parameter
RSTN Pulse Width
Symbol
Min.
pRES
100
Typ.
Max
Unit
CLKs
(4-2) Power Down Sequence / Reset Sequence
Before PDN setting ( PDN to low ), Reset must be enabled for a duration of longer-than-100 clock time.
After PDN release ( PDN to high ), Reset must be enabled for 10 mS or longer till analog part reference voltage &
current are stabilized.
(CLKOUT=H)
CLKIN
sRES
hRES
RSTN
VIH
VIL
VIH
PDN
GND
Parameter
RSTN Pulse Width
Symbol
Min.
sRES
100
Typ.
Max
Unit
CLKs
Time from PDN to high to RSTN to
hRES
10
msec
high
SCL low duration before RSTN to
tSCLL
50
nsec
rise
At power-down, all control signals must be surely connected to either the selected power supply or ground level, and not
to VIH / VIL levels.
Rev.001E
15
2009 / 12
ASAHI KASEI
[AK8817/18]
(4-3) Power Down Sequence/Power up sequence
AVDD/DVDD
PVDD
PDN
RSTN
VREF
10mS(min)
Recover from Power Down state
(4-4) Power On Reset
After Power up, It is necessary to make reset sequence until Analog Reference voltage(VREF) becomes stable.
PVDD/DVDD/AVDD should be power up at same time or 1st PVDD power up and AVDD/DVDD makes up.
2.7V
AVDD
DVDD
1.6V
PVDD
0.8PVDD
PDN
RSTN
0.2PVDD
VREF
10mS(min)
item
RESETN Pulse width
Symbol
pRES_PON
Min
10
Typ
Max
Unit
msec
Note
Remark: Reset sequence requires clock input.
Rev.001E
16
2009 / 12
ASAHI KASEI
[AK8817/18]
(5) I2C Bus Input/Output Timing < Ta = -30 ~ +85 °C >
tBUF
tHD:STA
tR
tSU:STO
tF
VSDAH
SDA
VSDAL
tF
tR
VSDAH
SCL
VSDAL
tSU:STA
tLOW
(5-1) Timing 1
VSDAH: 0.8PVDD
VSDAL : 0.2PVDD
Parameter
Symbol
Min.
tBUF
1.3
usec
tHD:STA
0.6
usec
Clock Pulse Low Time
tLOW
1.3
usec
Input Signal Rise Time
tR
300
nsec
Input Signal Fall Time
tF
300
nsec
Bus Free Time
Hold Time (Start Condition)
Max.
Unit
Setup Time(Start Condition)
tSU:STA
0.6
usec
Setup Time(Stop Condition)
tSU:STO
0.6
usec
The above I2C bus related timing is specified by the I2C Bus Specification, and it is not limited by the device
performance. For details, please refer to the I2C Bus Specification.
(5-2) Timing 2
tHD:DAT
VSDAH
VSDAL
SDA
tHIGH
VSDAH
VSDAL
SCL
tSU:DAT
VSDAH: 0.8PVDD
VSDAL : 0.2PVDD
Parameter
Symbol
Min.
Data Setup Time
tSU:DAT
100 (note1)
Data Hold Time
tHD:DAT
0.0
tHIGH
0.6
Clock Pulse High Time
Max.
Unit
nsec
0.9 (note2)
usec
usec
note 1 : when to use I2C Bus Standard mode, tSU:DAT >- 250 ns must be met.
note 2 : when the AK8817/18 is used in such bus interface where tLOW is not extended ( at minimum specification of
tLOW ), this condition must be met.
Rev.001E
17
2009 / 12
ASAHI KASEI
[AK8817/18]
Device Control Interface
The AK8817/18 is controlled via I2C Bus Control Interface.
[ I2C SLAVE Address ]
2C Slave Address is 0x40
[ I2C Control Sequence ]
(1) Write Sequence
When the Slave Address of the AK8817/18 Write mode is received at the first byte, Sub Address at the second byte and
Data at the third and succeeding bytes are received.
There are 2 operations in Write Sequence - a sequence to write at every single byte, and a sequential write operation to
write multiple bytes successively.
(a) 1 Byte Write Sequence
Slave
S
w
A
Address
8-bits
1bit
Sub
Address
8-bits
A
Data
A
1bit
8-bits
1bit
Stp
(b) Multiple Bytes ( m-bytes ) Write Sequence ( Sequential Write Operation )
Sub
Slave
Data(n+
S
w
A
Address
Data(n)
A
A
Address
1)
(n)
8-bits
1bit
8-bits
1bit
8-bits
1bit
8-bits
A
….
Data(n+m)
A
8-bits
1bit
1bit
stp
(2) Read Sequence
When the Slave Address of the AK8817/18 Read mode is received, Data at the second and succeeding bytes are
transmitted.
S
Slave
Address
8-bits
w
A
Sub
Address
(n)
A
1
8-bits
1
rS
Slave
Address
8-bits
R
A
Data1
A
Data2
A
Data3
A
1
8-bits
1
8-bits
1
8-bits
1
…
Data n
Ā
8-bits
1
stp
Abbreviated terms listed above mean :
S, rS
A
Astp
R/W
: Start Condition
: Acknowledge ( SDA Low )
: Not Acknowledge ( SDA High )
: Stop Condition
1 : Read
0 : Write
: to be controlled by the Master Device. Micro-computer interface is output normally .
: to be controlled by the Slave Device. To be output by the AK8817/18.
Rev.001E
18
2009 / 12
ASAHI KASEI
[AK8817/18]
Video Encoder Functional Outline
(1) Reset
(1-1) Reset of Serial Interface part ( asynchronous reset )
Reset is made by setting RSTN pin to low.
(1-2) Reset of other than Serial Interface blocks
Reset is made by keeping RSTN pin low for a longer than 100 clock time, in normal operation.
(1-3) at Power-On-Reset ( including power-down release case )
Follow the power-on-reset sequence.
At the completion of each initialization, all internal registers are set to default values ( refer to Register Map ). Right after
the reset, Video output of the AK8817/18 is put into Hi-Z condition.
(2) Power-Down
It is possible to put the device into power-down mode by setting the AK8817/18 power-down pin to GND.
Transition to power-down mode should be followed by the power-down sequence. As for the recover from the
power-down mode, it should be followed by the power-down release sequence.
(3) Master Clock
A following clock should be input as a Master clock.
In Encoder Mode operation ( a synchronized clock with input data is required )
When ITU-R BT.601 data is input
When Square Pixel data is input
( PIXRT-bit = 0 )
( PIXRT-bit = 1 )
NTSC Encoder
27MHz
24.5454MHz
PAL Encoder
27MHz
29.50MHz
(4) Video Signal Interface
Video input signal ( data ) should be synchronized in either of the following methods :
* Slave mode operation where synchronization is made with HSYNC ( HDI ) / VSYNC ( VDI ).
* ITU-R BT. 656 I / F ( EAV decode ) (only 27MHz operation)
(5) Pixel Data
Input data to the AK8817/18 is YCbCr ( 4:2:2 ).
Data with
Y : 16 ~ 235 and CbCr : 16 ~ 240
should be input.
(6) Video Signal Conversion
Video Re-Composition module converts the multiplexed data ( ITU-R BT.601 Level Y, Cb, Cr ) into interlaced
NTSC-M and PAL-B, D, G, H, I data. Video encoding setting is done by “Control 1 Register “.
Rev.001E
19
2009 / 12
ASAHI KASEI
[AK8817/18]
(7) Luminance Signal Filter ( Luma Filter )
Luminance signal is output via LPF ( see x2 Luma Filter in the block diagram ).
10
0
0.0 1.0 2.0
Gain[dB]
-10
3.0 4.0 5.0 6.0 7.0 8.0
9.0 10.0 11.0 12.0 13.0
-20
-30
-40
-50
frequency[MHz]
(8) Chroma Signal Filter ( Chroma Filter )
Chroma input signal components ( Cb, Cr ) prior to the modulation go through a 1.3 MHz Band Limiting Filter
( see 4:2:2 to 4:4:4 x2 interpolator in the block diagram ).
Chroma signal which is modulated by the sub-carrier is output via a low pass filter ( Chroma LPF in the block diagram ).
Frequency response of each filter is shown below.
4:2:2 to 4:4:4 Interpolator Filter
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Gain[dB]
-10
-20
-30
-40
-50
Frequency[MHz]
x 2 Interpolator Filter
10
0
Gain[dB]
-10
0.0 1.0 2.0
3.0 4.0 5.0 6.0 7.0 8.0
9.0 10.0 11.0 12.0 13.0
-20
-30
-40
-50
frequency[MHz]
Rev.001E
20
2009 / 12
ASAHI KASEI
[AK8817/18]
(9) Color Burst Signal
Burst signal is generated by a 32 bit digital frequency synthesizer.
Color Burst Frequency is selected by mode setting of NTSC / PAL.
NTSC-M
Subcarrier Freq
(MHz)
3.57954545
PAL-B,D,G,H,I
4.43361875
Standerd
Video Process 1
VMOD-bit
0
1
Burst Signal Table
(10) Sub - Carrier Reset
A function to reset sub-carrier by Color Frame sequence.
Reset function can be turned “OFF “ by setting SCR-bit of Control 1 Register.
Default value is set to enable Sub-carrier reset.
SCR
NTSC
PAL
0
1
Sub-carrier phase is reset in every 2 Frames
( 4 Fields )
Sub-carrier phase is reset inevery 4 Frames
( 8 Fields )
Sub-carrier reset is not done
Sub-carrier reset is not done
(11) Setup processing
Setup processing can be performed on Video signal by Control 2 Register Setup-bit.
Following processing is made on Luminance signal ( Y signal ) and Chroma signal ( C signal ) by the Setup processing.
Y Setup = Y x 0.925 + 7.5 IRE where Y setup is the Luminance signal after Setup processing.
C Setup = C x 0.925
where C Setup is the Chroma signal after Setup processing.
(12) Video DAC
The AK8817/18 has a 9 Bit resolution, current-drive DAC as a video DAC which runs at 29.5 / 24.5454 MHz or 27.00MHz
clock frequency.
This DAC is designed to output 1.28 V o-p at full scale under the following conditions loading resistance of 390 ohms,
VREF at 1.23 V and IREF pin resistor of 12k ohms.
[ VREF ] pin should be connected to ground via a 0.1 uF or larger capacitor.
DAC output can be turned “ON” or “OFF” by register setting and current consumption can be lowered.
When the output is turned off, it is put into high impedance condition.
Rev.001E
21
2009 / 12
ASAHI KASEI
[AK8817/18]
(13) Video Amp
AK8817/18 has Video amp that can drive 150ohm with Low pass filter. It can also possible to compensate SAG distortion.
To compensate SAG external capacitor is 47uF and 1uF as shown following figure. Recommendation voltage when SAG
compensation circuit is used is 3V or more.
VOUT pin and SAG pin should be shorten when SAG Compensation is not used. Output pin should make AC coupling.
SAG Compensation circuit can be set on or off with setting register.
In case of not using internal Video amp (Only DAC use case), Video Amp becomes power down. In this case SAG and
VOUT should be Open.
AK8817
1uF
AK8817
75ohm
SAG
100uF 75ohm
SAG
VOUT
VOUT
47uF
SAG Compensation ON
SAG Compensation Off
VAMPMD[1:0]
00
Operation
Video Amp OFF + SAG Compensation OFF
01
Video AMP ON + SAG Compensation ON
10
Video Amp ON + No SAG Compensation
11
Reserved
Rev.001E
22
Conditions
Only DAC output
Recommendation Voltage of
DVDD/AVDD is 3v or more.
SAG pin and VOUT should be
shorten.
2009 / 12
ASAHI KASEI
[AK8817/18]
(14) Video Data Interface Timing
Data is captured by a clock which is fed on CLKIN pin.
The Video Encoder receives a clock from a controller ( refer to the following diagram ).
In Slave mode operation, Synchronization is made with HDI / VDI.
In ITU-R BT.656 mode operation, HDI / VDI are not required.
C L K IN
(H D I)
C o n t r o lle r
(V D I)
AK8817
D [7 :0 ]
Rev.001E
23
2009 / 12
ASAHI KASEI
[AK8817/18]
(14-2) Video Interface mode
The AK8817/18 synchronizes with input signal by the following, 2 interface modes.
(a) Slave-mode interface where synchronization is made with externally-fed synchronization signals HDI / VDI
( HDI / VDI interface )
(b) ITU-R BT.656 Interface mode ( 656 interface )
interface mode setting is controlled by [REC656]-bit of Control 2 Register.
REC656-bit
0
1
Operation
HDI / VDI Slave mode
ITU-R BT.656 Interface mode
(a-1) Timing signal ( HDI / VDI ) VS Data input relation
Horizontal Synchronization ( in-line Pixel Sync ) is made with HDI synchronization timing signal.
Vertical Synchronization ( in-line Frame Line Sync ) is made with VDI synchronization timing signal.
Recognition of Video Field ( Odd Field or Even Field ) is made by VDI input signal which is referenced with HDI.
In normal operation, the AK8817/18 checks changes of HDI and VDI at the clock edge ( CLK synchronization )
which becomes a data capture reference position.
At a pixel position where HDI is judged to become “ Low “, it is recognized as 0H (zero th position ).
Cb0 data position depends on input data rate ( ITU-R BT.601 or Square Pixel data ).
Cb0 Data
NTSC Encoder
PAL Encoder
At ITU-R BT.601 Data input
244th data
264th data
At Square Pixel data input
236th data
310th data
Video Field is recognized by the VDI relation with HDI.
Field recognition is made as follows :
The AK8817/18 distinguishes at every Field if it is Odd Field ( 1st Field ) or not. Even Field Sync signal is not usually input.
1 ) Recognition timing of Odd Field is decided by those timing signal relations which are fed on HDI and VDI pins.
When the VDI falling pulse is input on VDI input pin during the time from 3 clocks prior to the falling edge of
HDI timing pulse which is fed on HDI input till 3 clocks prior to the rising edge of HDI timing pulse, the Line is
recognized to be Line 4.
Line4/Line1(NTSC/PAL)
Line5/Line2(NTSC/PAL)
Line6/Line3(NTSC/PAL)
HDI
3CLK
VDI
3CLK
2 ) Whenever Horizontal / Vertical SYNC signal inputs are not fed as expected in the Video Specifications, in term of
timing and # of pulses ( kept at “ High “ level ), the AK8817/18 continues to self-run the operation which is based on the
Sync
signals, fed just before.
But it is recommended to feed Sync signals as specified every time in order to prevent erroneous operation.
3 ) VD pulse input at other than Odd Field synchronization is ignored ( Synchronization is made with Odd Field only ).
Rev.001E
24
2009 / 12
ASAHI KASEI
[AK8817/18]
(a-2) Horizontal Synchronization ( Pixel Data synchronization within a Line )
(a-2-1) at ITU-R BT. 601 data input case
(a-2-1-1) NTSC
1715
0
244
245
246
247
248
(0x10) (0x80) (0x10) (0x80) (0x10) Cb0
Y0
Cr0
Y1
Cb1
1683 1684
1713 1714
CLKIN
(27.00MHz)
DTI[7:0]
Cr359 Y719 (0x80) (0x10) (0x10) (0x80)
0H
HDI
Active Video Area
244T
720 x 2 Clock
* ) when D [7:0], HDI and CLKIN are in same phase relation as a timing example above, the AK8817/18 takes input data at
the falling edge of each CLKIN if CLKEDGE-bit = 1.(CLKINV = 1.)
* ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 / 0xFF
codes in non Hi-Z state should be input.
(a-2-1-2) PAL
1727
0
264
265
266
267
268
(0x10) (0x80) (0x10) (0x80) (0x10) Cb0
Y0
Cr0
Y1
Cb1
1702 1703 1704
1725 1726
CLKIN
(27.00MHz)
DTI[7:0]
Cr359 Y719 (0x80) (0x10) (0x10) (0x80)
H0
HDI
Active Video Area
264T
720 x 2 Clock
*) when D [7:0], HDI and CLKIN are in same phase relation as a timing example above, the AK8817/18 takes input data at
the falling edge of each CLKIN if CLKEDGE-bit = 1. .( CLKINV = 1.)
* ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 / 0xFF
codes in non Hi-Z state should be input.
Rev.001E
25
2009 / 12
ASAHI KASEI
[AK8817/18]
(a-2-2) at Square Pixel Rate input case
(a-2-2-1) NTSC
1559
0
TBD
236
237
238
239
240
Y0
Cr0
Y1
Cb1
1514
1515
1516
CLKIN
(24.5454MHz)
(0x10) (0x80) (0x10) (0x80) (0x10) Cb0
D[7:0]
Cr319 Y639 (0x80) (0x10)
H0
HDI
Active Video Area
640 x 2 Clock
* ) when D [7:0], HDI and CLKIN are in same phase relation as a timing example above, the AK8817/18 takes input data at
the falling edge of each CLKIN if CLKINV = 1.
* ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 / 0xFF
codes in non Hi-Z state should be input.
(a-2-2-2) PAL
1887
0
TBD
310
311
312
313
314
Cb0
Y0
Cr0
Y1
Cb1
1844
1845
1846
CLKIN
(29.5MHz)
D[7:0]
(0x10) (0x80) (0x10) (0x80) (0x10)
Cr383 Y767 (0x80) (0x10)
H0
HDI
Active Video Area
768 x 2 Clock
* ) when D [7:0], HDI and CLKIN are in same phase relation as a timing example above, the AK8817/18 takes input data at
the falling edge of each CLKIN if CLKINV-bit = 1. .(CLKINV = 1.)
* ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 / 0xFF
codes in non Hi-Z state should be input.
Rev.001E
26
2009 / 12
ASAHI KASEI
[AK8817/18]
( a-3 ) HDI and VDI relation in each Frame
( a-3-1 ) NTSC ( Frame ) 525 Line
480 active lines
The First Field ( ODD )
263 lines
240 lines
525
1
2
3
4
5
6
7
22
23
261
262
263
264
525
1
2
HDI
VDI
* )VDI negative-going should be fed during the time from 3 clocks prior to negative-going of HDI at L4 till 3 clocks prior to positive-going of HDI.
VDI positive-going can occurs at arbitrary location, but keep VDI low for 3 line duration time as a rough idea.
The Second Field ( EVEN )
262 lines
240 lines
263
264
265
266
267
268
269
270
285
286
524
HDI
VDI
High
* ) VDI negative-going is not required for the Second Field. It is required for the First Field only ( VDI fed during the Second Field is ignored ).
Rev.001E
27
2009 / 12
ASAHI KASEI
[AK8817/18]
( a-3-2 ) PAL ( Frame ) 625 Line
576 active lines
The First Field ( ODD )
313lines
288lines
625
1
2
3
4
5
22
23
24
310
311
312
313
314
HDI
VDI
* ) VDI negative-going should be fed during the time from 3 clocks prior to negative-going of HDI at L1 till 3 clocks prior to positive-going of HDI.
VDI positive-going can occur at arbitrary location, but as a rough idea, keep VDI low for 2.5, or 2 or 3 line- duration time.
Data fed at Line 23 is not output on Video output
The Second Field (EVEN)
313lines
288lines
313
314
315
316
317
318
335
336
337
623
624
625
1
2
HDI
VDI
High
*) VDI negative-going is not required for the Second Field. It is required for the First Field only ( VDI fed during the Second Field is ignored ).
Data fed at Line 623 is not output.
Rev.001E
28
2009 / 12
ASAHI KASEI
[AK8817/18]
( b-1 ) ITU-R BT.656 Interface mode
The AK8817/18 makes a synchronization with an incoming signal by decoding EAV in the signal when ITU-R BT.656
encoded signal is input.
EAV code is located at the following position in the Video stream ( this mode of operation is not supported in the Square
Pixel clock operation ).
Y/Cb/Cr
Data#
525system
Data#
625system
Cb
EAV
Y Cr
Y
Cb
Y
Cr
Y
Cb
Y
Cr
Y
Cb
SAV
Y Cr
Y
Cb
Y
Cr
Y
Cb
360 720 360 721 361 722 361 723
368 736 368
855 428 856 428 857
0
0
0
1
1
360 720 360 721 361 722 361 723
366 732 366
861 431 862 431 863
0
0
0
1
1
CLKIN
33/ 25T(525/ 625)
243/ 263T(525/ 625)
276/ 288T(525/ 625)
HDI
Rev.001E
29
2009 / 12
ASAHI KASEI
[AK8817/18]
( 1 ) EAV Synchronization
an EAV code which is encoded on input signal is decoded, and the device makes synchronization with its timing.
EAV / SAV codes are as follows.
Those codes succeeding 0xFF- 0x00- 0x00 which are fed as input data in 8-bit form become EAV / SAV codes.
EAV / SAV codes have following meanings, starting with MSB.
Bit Number
WORD
VALUE
0
0xFF
1
0x00
2
0x00
3
0xxx
MSB
7
1
0
0
1
6
1
0
0
F
5
1
0
0
V
4
1
0
0
H
3
1
0
0
P3
2
1
0
0
P2
LSB
0
1
0
0
P0
1
1
0
0
P1
here,
F
= 0 : Field 1
= 1 : Field 2
V
= 0 : other than Filed Blanking (V-Blanking)
= 1 : Filed Blanking (V-Blanking)
H = 0 : SAV
= 1 : EAV
P3, P2, P1, P0 : Protection Bit
Protection Bit and F / V / H relation is shown in the following table.
F
V
H
P3
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
P2
0
1
0
1
1
0
1
0
P1
0
0
1
1
1
1
0
0
P0
0
1
1
0
1
0
0
1
At NTSC data input case
Cb
Y
Cr
Y
359 718 359 719
Cb
360
Y
Cr
720 360
EAV
Y
721
……
Cb
428
Y
Cr
856 428
SAV
Y
857
Cb
0
Y
0
Cr
0
Y
1
At PAL data input case
Cb
Y
Cr
Y
359 718 359 719
Cb
360
Y
Cr
720 360
EAV
Y
721
……
Cb
431
Y
Cr
862 431
SAV
Y
863
Cb
0
Y
0
Cr
0
Y
1
Rev.001E
30
2009 / 12
ASAHI KASEI
[AK8817/18]
( 1-1 ) EAV / SAV Code and Line Synchronization
The AK8817/18 makes Vertical synchronization ( Line synchronization ) when F-bit in EAV makes transition from
“ 1 “ to “ 0 “.
F-bit of EAV / SAV and Line relation is as follows
F-bit
NTSC
PAL
0
Line4 – Line265
Line1 – Line312
Line266 – Line525
1
Line313 – Line625
Line1 – Line3
For reference, V-bit of EAV / SAV and Line relation is also shown below.
Field
V-bit
NTSC
PAL
Start (V=1)
Line1 – Line19
Line624 – Line625 – Line22
Field 1
End (V=0)
Line20 – Line263
Line23 – Line310
Start (V=1)
Line264 – Line282
Line311 – Line335
Field 2
End (V=0)
Line283 – Line525
Line336 – Line623
Digital
Line-No.
1
2
3
4
5
7
8
9
synchronization is made at this timing
F-bit
Digital
Line-No.
6
263
264
265
266
267
268
269
270
271
272
F-bit
Line Synchronization by EAV at NTSC input case
Digital
Line-No.
622
623
624
625
1
3
4
5
6
synchronization is made at this timing
F-bit
Digital
Line-No.
2
310
311
312
313
314
315
316
317
318
319
F-bit
Line Synchronization by EAV at PAL input
Rev.001E
31
2009 / 12
ASAHI KASEI
[AK8817/18]
(15) On-chip Color Bar
The AK8817/18 can output Color Bar signal.
Color Bar signal to be generated has 100 % amplitude and 75 % Saturation levels.
Color Bar signal is output by setting register.
When to output Color Bar signal, there are 2 modes of operation – one is external Sync timing mode for normal
operation, and the other is internal self-operation mode.
In internal self-operating mode, required timing is internally generated automatically. Namely, it is no need to input
synchronization timing from outside of the chip.
Operation mode setting is done by Control 1 Register .
When BBG-bit is set, BBG-bit is prioritized ( Black Burst is output ).
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
100%White
Synctip Level
Cb
Y
Cr
WHITE
128
235
128
YELLOW
44
162
142
CYAN
156
131
44
GREEN
72
112
58
Blanking Level
The following values are code for ITU-R. BT601
MAGENTA
RED
BLUE
BLACK
184
100
212
128
84
65
35
16
198
212
114
128
(16) Black Burst Signal generation function
The AK8817/18 can output Black Burst signal ( Black level output ).
When to output Black Burst signal, there are 2 modes of operation – one is external Sync timing mode for normal
operation , and the other is internal self-operation mode.
In internal self-operation mode, required timing is internally generated automatically. Namely, it is no need to input
synchronization timing from outside of the chip.
When BBG-bit of [ Control 1 Register ] is set to “1”, same operation is processed as in the case where fixed-16 Y signal
and
fixed-128 Cb / Cr signal outputs are input.
Operation mode setting is done by Control 1 Register setting.
Rev.001E
32
2009 / 12
ASAHI KASEI
[AK8817/18]
(17) Video ID
The AK8817/18 supports to encode the Video ID ( EIAJ CPR-1204 ) which distinguishes the aspect ratio etc..
This is also used as CGMS ( Copy Generation Management System ).
Turning “ON/OFF” of this function is made by setting both VMOD-bit = 0 and VBID-bit = 1 of { Control 1 Register (0x00) }.
And data to be set is written into { VBID / WSS Data1 & 2 Registers ( 0x02,0x03 )}.
Video ID information is the highest order of priority information among VBI information
VBID Data Update timing .
VSYNC
S et C ontro l R egister
u-P D a ta
N EW D AT A
DATA
O LD D A T A
N EW D AT A
VBID Code assignment
20 bit data is configured with WORD0 = 2 bit, WORD1 = 4 bit, WORD2 = 8 bit and CRC = 6 bit.
CRC is automatically calculated and added by the AK8817/18.
Default values of CRC polynomial expression X6 + X + 1 are all ones.
-data configuration
bit1
bit20
DATA
WORD0
2bit
WORD1
4bit
WORD2
8bit
CRC
6bit
VBID Waveform
Ref.
bit1 bit2 bit3
•••
bit20
70IRE +/- 10IRE
0IRE + 10 IRE
− 5 IRE
2.235usec +/- 50nsec
11.2usec +/- 0.3usec
49.1usec +/- 0.44usec
1H
525/60 System
70IRE
20/283
Amplitude
Encode Line
Rev.001E
33
2009 / 12
ASAHI KASEI
[AK8817/18]
( 17 ) WSS function
The AK8817/18 supports to encode the WSS ( ITU-R. BT.1119 ) which distinguishes the aspect ratio and sets CGMS-A
etc..
Turning “ON/OFF“ of this function is made by setting both VMOD-bit = 1 and WSS-bit = 1 of { Control 1 Register ( 0x00 ) }.
And data to be set is written into { VBID / WSS Data1 & 2 Registers ( 0x02, 0x03 )}.
WSS Data Update timing
VSYNC
S et C ontro l R egister
u-P D a ta
N EW D AT A
DATA
O LD D A T A
N EW D AT A
WSS Waveform
500mV +/- 5%
0H
27.4usec
1.5usec
10.5usec
11.0 +/- 0.25usec
38.4usec
44.5usec
Encode line : former half of Line 23 ( Blank output during latter half )
Coding : Bi-phase modulation coding
Clock : 5 MHz ( Ts = 200 nS )
Encoding details as follows
Run-in
Start code
29 elements
24 elements
0x1F1C71C7
0x1E3C1F
Rev.001E
Group 1
Aspect ratio
24 elements
Bit numbering
0 1 2 3
LSB
MSB
0 : 000111
1 : 111000
34
Group 2
Enhanced
Services
24 elements
Bit numbering
4 5 6 7
LSB
MSB
0 : 000111
1 : 111000
Group 3
Subtitles
18 elements
Bit numbering
8 9 10
LSB
MSB
0 : 000111
1 : 111000
Group4 Reserved
18 elements
Bit numbering
11 12 13
LSB
MSB
0 : 000111
1 : 111000
2009 / 12
ASAHI KASEI
[AK8817/18]
SYNC Signal waveform, Burst Waveform generator
(1) NTSC-J
S y n c r is e t im e
50%
B u r s t H e ig h t
90%
B u rs t
H o r iz o n ta l
r e f e r e n c e p o in t
50%
50%
S ync Le ve l
10%
S yn c
H . r e f . t o B u r s t S ta r t
measurement
point
Total line period(derived)
Sync Level
Sync rise time
Horizontal Sync width
Horizontal reference point to
burst start
Burst *
Burst Height **
value
Consumer Quality
tolerance
units
10% - 90%
50%
63.556
40
140
4.7
+/- 3
Max 250
+/- 0.1
usec
IRE
nsec
usec
50%
19
defined by SC/H
cycles
50%
9
40
+/- 1
+/- 3
cycles
IRE
* there is a case where tolerance of Sync rise time is added to Sync width tolerance.
* Measurement of Burst time length is made between the Burst start point which is defined as the zero-cross point,
preceding the first half-cycle of the sub-carrier where Burst amplitude becomes higher than 50 % level and the Burst end
point, defined in the same manner.
19 cycles +/-10°
9 cycles +/- 1cycle
50%
NTSC Signal
Rev.001E
35
2009 / 12
ASAHI KASEI
[AK8817/18]
(2) Vertical Sync Signal timing ( NTSC )
3H
3H
3H
0 .5 H
1
2
3
4
5
3H
6
7
8
3H
9
21
3H
0 .5 H
263
264
265
266
267
268
269
270
271
G
I
272
273
285
H
I
I
I
40IRE
+/-3IRE
Serration Pulse
Equalizing Pulse
Equalizing Pulse and Serration Pulse
Symbol
G
H
G
I
Pre-equalizing pulse width
Vertical serration pulse width
Post-equalizing pulse width
Sync rise time
Measurement
point
50%
50%
50%
Value
2.3
4.7
2.3
140
Recommended
tolerance
+/- 0.1
+/- 0.2
+/- 0.1
Max 250
units
usec
usec
usec
nsec
* there is a case where tolerance of Sync rise time is added to Pulse width tolerance.
Rev.001E
36
2009 / 12
ASAHI KASEI
[AK8817/18]
(3) PAL-B,D,G,H,I
S y n c r is e t im e
50%
B u r s t H e ig h t
90%
B u rs t
H o r iz o n ta l
r e f e r e n c e p o in t
50%
50%
S yn c L e ve l
10%
H o r iz o n ta l S y n c
H . r e f . t o B u r s t S ta r t
measurement
point
Total line period(derived)
Sync Level
Sync rise time
Horizontal Sync width
Horizontal reference point to
burst start
Burst *
Burst Height **
value
Consumer Quality
tolerance
units
10% - 90%
50%
64.0
300
0.2
4.7
+/- 20
Max 0.3
+/- 0.2
usec
mV
usec
usec
50%
5.6
+/- 0.1
usec
50%
10
300
+/- 1
+/- 30
cycles
mV
* there is case where tolerance of Sync rise time is added to Sync width tolerance.
Rev.001E
37
2009 / 12
ASAHI KASEI
[AK8817/18]
(4) Vertical Sync Signal timing and Burst Phase
PAL-B,D,G,H,I
A
308
620
308
620
309
310
621
622
309
311
623
310
621
622
312
624
311
623
313
625
312
624
314
1
313
625
315
2
314
1
316
3
315
2
317
4
316
3
318
5
317
4
319
320
A
B
6
7
A
B
318
319
A
B
5
B
7
322
321
322
8
320
6
321
8
A : Phase of Burst : nominal Value + 135°
B : Phase of Burst : nominal Value - 135°
Since Burst frequency and Line frequency are not practically in integer-multiple relation, specified phase value is not
exactly 135 degrees.
Diagram below shows phase direction.
G
I
H
I
I
I
300mV
+/-30mV
Serration Pulse
Equalizing Pulse
Equalizing Pulse and Serration Pulse
Symbol
G
H
G
I
Pre-equalizing pulse width
Vertical serration pulse width
Post-equalizing pulse width
Sync rise time
Measurement
point
50%
50%
50%
Value
2.35
4.7
2.35
200
Recommended
tolerance
+/- 0.1
+/- 0.2
+/- 0.1
Max 300
units
usec
usec
usec
nsec
* there is a case where tolerance of Sync rise time is added to Pulse width tolerance.
Rev.001E
38
2009 / 12
ASAHI KASEI
[AK8817/18]
Register Map
Address
0x00
0x01
0x02
0x03
Register
Control 1 Register
Control 2 Register
VBID/WSS Data 1 Register
VBID/WSS Data 2 Register
Default
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
0x04
Input Control Register
0x00
R/W
0x05
Device ID & Revision ID Register
0x17
R
Rev.001E
39
Function
Mode set Register
Mode set Register
VBID data is set, WSS data is set
VBID data is set, WSS data is set
Input control register for out-of-standard quality input
signal
Register for Device ID and Revision ID
2009 / 12
ASAHI KASEI
[AK8817/18]
Control 1 Register (R/W) [Address 0x00]
Sub Address 0x00
bit 7
bit 6
DAC
BBG
0
bit 5
CBG
0
0
Control 1 Register Definition
BIT Register Name
bit 0
VMOD
bit 1
bit 4
bit 3
MASMD
WSS
Default Value
0
0
R/W
Video Mode bit
R/W
SCR
Sub-Carrier Reset bit
R/W
bit 2
VBID
VBID Set bit
R/W
bit 3
WSS
WSS Set bit
R/W
bit 4
MASMD
Master Mode bit
R/W
bit 5
CBG
Color Bar Generator
bit
R/W
bit 6
BBG
Black Burst Generator
bit
R/W
bit 7
DAC
DAC Set bit
R/W
Rev.001E
bit 2
VBID
bit 1
SCR
0
0
Default Value 0x00
bit 0
VMOD
0
Definition
0: NTSC
1: PAL
0 : Sub-Carrier Reset
1 : Sub-Carrier Reset off
0 : VBID OFF
1 : VBID ON
0 : WSS OFF
1 : WSS ON
Master Mode bit to set Sync mode when Color Bar signal and
Black Burst signal are generated
0 : operation by an external Sync timing
1 : operation by an internal self-operating mode ( master
mode )
note ) Master mode bit is still valid in normal data input, but
output video is not synchronized.
0: OFF
1: ON
when BBG is set, BBG is prioritized.
0 : OFF
1 : ON
0 : DAC OFF
1 : DAC ON
40
2009 / 12
ASAHI KASEI
[AK8817/18]
Control 2 Register (R/W) [Address 0x01]
Sub Address 0x01
bit 7
bit 6
Reserved
Reserved
0
bit 5
Reserved
0
0
bit 4
bit 3
VAMPMD1
VAMPMD0
Default Value
0
0
Control 2 Register Definition
BIT Register Name
bit 0
PIXRT
bit 1
R/W
Pixel Rate Set bit
R/W
REC656
Rec656 Set bit
R/W
bit 2
SETUP
Setup bit
R/W
bit 3
~
bit 4
VAMPMD0
~
VAMPMD1
VIdeo Amp Mode Set
bit
R/W
bit 5
~
bit 7
Reserved
Reserved bit
R/W
Rev.001E
bit 2
SETUP
0
Default Value 0x00
bit 1
bit 0
REC656
PIXRT
0
0
Definition
Pixel rate setting is done.
0 : ITU-R BT.601 data input ( at 27 MHz rate )
1 : Square Pixel data input
NTSC : 24.5454 MHz
PAL : 29.50 MHz
Synchronization mode setting is done.
0 : synchronization is made with HDI / VDI input.
1 : synchronization is made with ITU-R BT.656 data input
Set-up setting is done
0 : with no set-up
1 : with 7.5 IRE set-up
Operation mode for Video Amp.
VAMPMD[1:0]
00: Video Amp OFF + SAG Compensation OFF
01: Video AMP ON + SAG Compensation ON
10: Video Amp ON + No SAG Compensation
11: Reserved
Set “0”
41
2009 / 12
ASAHI KASEI
[AK8817/18]
VBID/WSS 1 Register (R/W) [Address 0x02]
VBID/WSS 2 Register (R/W) [Address 0x03]
Video ID and WSS data setting are made. A common data register is used for both video ID and WSS data.
When VBID bit of mode register is set in NTSC mode, data is for VBID data ,and when WSS bit of Control 1 Register is set
in
PAL mode, data is for WSS data.
When VBID-bit is “1” and VMOD-bit is “0” in Control 1 Register , the following bits are assigned.
Sub Address 0x02
bit 7
bit 6
VBID7
VBID8
0
0
Sub Address 0x03
bit 7
bit 6
Reserved
Reserved
0
0
bit 5
VBID9
0
bit 5
VBID1
0
default Value 0x00
bit 1
bit 0
VBID13
VBID14
bit 4
bit 3
VBID10
VBID11
Default Value
0
0
bit 2
VBID12
0
0
bit 4
bit 3
VBID2
VBID3
Default Value
0
0
bit 2
VBID4
bit 1
VBID5
0
0
0
default Value 0x00
bit 0
VBID6
0
Note ) “0” should be written into reserved bits.
VBID1 ---- VBID14 above correspond to the bit 1 ---- bit 14 which are described at { VBID Data Code Assignment } in
{ ( 14 ) Video ID } section.
A 6-bit CRC code from bit 15 ~ bit 20 is automatically added by the AK8817/18.
Data is retained till data is updated to a new one.
Following bits are assigned when WSS-bit is “1” and VMOD-bit is “1” in Control 1 Register .
Sub Address 0x02
bit 7
bit 6
G2-7
G2-6
0
0
Sub Address 0x03
bit 7
bit 6
Reserved
Reserved
0
0
bit 5
G2-5
0
bit 5
G4-13
0
bit 4
bit 3
G2-4
G1-3
Default Value
0
0
bit 2
G1-2
bit 1
G1-1
0
0
bit 4
bit 3
G412
G4-11
Default Value
0
0
bit 2
G3-10
bit 1
G3-9
0
0
default Value 0x00
bit 0
G1-0
0
default Value 0x00
bit 0
G3-8
0
Note ) WSS data is written with 0x01 first, then 0x02 in this order.
When the 2nd byte ( 0x02 ) of WSS data is written, the AK8817/18 interprets that data is updated to a new one and then
encodes it to the next video line ( Line 23 ).
Data is retained till data is updated to a new one.
Rev.001E
42
2009 / 12
ASAHI KASEI
[AK8817/18]
Input Control Register (R/W) [Address 0x04]
This is an out-of-standard quality input signal control register.
Sub Address 0x04
bit 7
bit 6
Reserved
CBCR
0
0
bit 5
VD2
0
Adjustment of Sync input timing is made.
BIT Register Name
HD0
bit 0
~
HDI Input Delay
~
HD2
bit 2
VD0
bit 3
~
VDI Input Delay
~
VD2
bit 5
bit 6
CBCR
Exchange CbCr
bit 7
Reserved
Reserved
Rev.001E
bit 4
VD1
0
bit 3
VD0
0
R/W
bit 2
HD2
0
default Value 0x00
bit 1
bit 0
HD1
HD0
0
0
Definition
R/W
HDI signal input is delayed by the set value.
HD [ 2:0 ] system clock count delay ( + 0 ~ + 7 CLK delay )
R/W
VDI signal input is delayed by the set value.
VD [ 2:0 ] system clock count delay ( + 0 ~ + 7 CLK delay )
R/W
R/W
Cb, Cr timing data are interchanged at CBCR = 1.
Reserved
43
2009 / 12
ASAHI KASEI
[AK8817/18]
Device ID and Revision ID Register (R) [Address 0x05]
Register to show Device ID & Revision of the AK8817/18.
Device ID for AK8817/18 is 0x17(decimal)
Initial Version of the Revision ID is 0x00.
Revision number is modified only when a control software needs to be modified.
Sub Address 0x5
bit 7
bit 6
Rev1
REV0
0
0
bit 5
DEV5
0
Device ID and Revision ID Register Definition
BIT Register Name
DEV0
bit 0
~
Device ID bit
~
DEV2
bit 5
bit 6
~
bit 7
Rev.001E
REV0
~
REV2
Revision ID bit
bit 4
DEV4
1
R/W
bit 3
DEV3
0
bit 2
DEV2
1
bit 1
DEV1
1
default Value 0x17
bit 0
DEV0
1
Definition
R
To show Device ID
Device ID is 0x17h.
R
To show Revision information
Revision ID is updated when software modification is to be
expected.
It is 0x00.
44
2009 / 12
ASAHI KASEI
[AK8817/18]
System Connection Example
AK8817/18
HSYNC
VSYNC
D[7:0]
PVDD
PVDD
SAG
PVSS
HDI
VDI
VOUT
75 ohm
47uF
CLKIN
Clock
1uF
DACOUT
u-P
I2C
SDA
390ohm
SCL
RSTN
PDN
VREF
Digital 3.0V
0.1uF
DVDD
DVSS
TEST
IREF
ATPG
12kohm
CLKINV
AVSS
AVDD
Analog 3.0V
0.1uF
DVSS
Rev.001E
10uF
AVSS
45
2009 / 12
ASAHI KASEI
[AK8817/18]
Package Drawing
41pin FBGA
4.0 ± 0.1
φ 0.05
A
41 - φ 0.3 ± 0.05
M S AB
7
6
5
4
3
2
1
A
B
B
D
3.0
4.0 ± 0.1
C
E
F
G
0.5
0.5
3.0
Package molding compound:
Interposer material:
Solder ball material:
Rev.001E
0.08 S
0.25 ± 0.05
1.0MAX
S
Epoxy
BT resin
SnAgCu
46
2009 / 12
ASAHI KASEI
[AK8817/18]
AK8817VQ / AK8818VQ
48 LQFP
9.00±0.20
7.00
25
37
24
48
13
7.00
9.00±0.20
36
12
1
0.50
0.10
0゜～ 10゜
M
0.50±0.20
0.10
Rev.001E
47
S
1.60MAX
1.4TYP
1.00
S
0.10±0.07
0.17±0.05
0.19±0.05
2009 / 12
ASAHI KASEI
[AK8817/18]
Package Marking Drawing
AK8817VG / AK8818VG
8817
XXXX
a. Package Type:
b. Number of Pins:
c. Product Number:
d. Control Code:
BGA
41pins (Including INDEX pin )
8817
XXXXX (4 digits)
8818
XXXX
a. Package Type:
b. Number of Pins:
c. Product Number:
d. Control Code:
Rev.001E
BGA
41pins (Including INDEX pin )
8818
XXXXX (4 digits)
48
2009 / 12
ASAHI KASEI
[AK8817/18]
AK8817VQ / AK8818VQ
AKM
AK8817VQ
XXXXXXX
1
AKM: AKM Logo
AK8817VQ: Marketing Code
XXXXXXX (7 digits): Date Code
AKM
AK8818VQ
XXXXXXX
1
AKM: AKM Logo
AK8818VQ: Marketing Code
XXXXXXX (7 digits): Date Code
Rev.001E
49
2009 / 12
ASAHI KASEI
[AK8817/18]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or
use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency
exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or
other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with
the express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, unclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or
damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise
places the product with a third party to notify that party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any
and all claims arising from the use of said product in the absence of such notification.
Rev.001E
50
2009 / 12