[AKD5388-A] AKD5388-A AK5388 Evaluation Board Rev.4 GENERAL DESCRIPTION AKD5388 is an evaluation board for the digital audio 24bit 216kHz 4ch A/D converter, AK5388. The AKD5388-A includes the input circuit and also has a digital interface transmitter. Further, the AKD5388-A can achieve the interface with digital audio systems via opt-connector. AKD5388-A is an evaluation board for AK5388, of 216kHz sampling 24bit 4ch A/D converter for professional audio. AKD5388-A has analog input buffer circuits, clock generator circuits, and digital audio interfaces. Therefore it can achieve the interface with digital audio systems via optical connector. And it can achieve the direct interface with AKEMD’s D/A converter evaluation boards of via 10-line flat cable. Ordering guide AKD5388-A --- AK5388 Evaluation Board FUNCTION • DIT with optical output • BNC connector for an external clock input -15V +15V +5V +3.3V AGND DGND REG +3.3V REG +5V JP9 EXT JP10 24.576MHz XRIN2 AVDD1 DVDD AVDD2 RIN2 BVSS VCC (+5V) Clock Generator DVSS LIN2 PORT1 Opt Out XLIN2 Input Buffer AK5388 AK4101A (DIT) XRIN2 RIN2 PORT2 Opt Out LIN2 XLIN2 PORT3 DSP Data PORT4 DSP Data 10pin Header Figure 1. AKD5388-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM090205> 2009/03 -1- [AKD5388-A] Operation sequence 1) Set up the power supplies lines. Name of connecto r +15V Color of connector Voltage Used for Red +12~15V Regulator T1, Regulator T2. OP-Amplifier -15V +5V Blue Orange -12~-15V +4.75~+5.25V +3.3V Green +3.0~+3.6V VCC Orange +4.75~+5.25V AGND DGND Black Black 0V 0V Comment and attention OP-Amplifier AVDD of AK5388, Analog input buffer circuit DVDD of AK5388 AK4101A, Logic circuit Analog ground Digital ground Default Setting This connector should be connected. And this connector is used when AVDD of AK5388 is supplied from regulator T1 and DVDD of AK5388 is supplied from regulator T2. In this case, JP9 and JP10 should be REG side. When this is REG side, +5V and +3.3V connector should be open. (Default) This connector should be connected. This connector is used when AVDD of AK5388 is supplied from +5V connector without regulator T1. In this case, JP9 should be +5V side. This connector is used when DVDD of AK5388 is supplied from +3.3V connector without regulator T2. In this case, JP10 should be +3.3V side. This connector should be connected. +15V This connector should be connected. This connector is used when DGND is supplied besides AGND. In this case, JP15 should be open. (Default) 0V 0V -15V Open Open +5V Table 1. Power supply lines (Note) Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK5388 and AK4101A should be reset once bringing SW3 = “L” upon power-up. Note: When AK5388 is TDM mode, the AK4101A does not support the TDM mode. Therefore, PORT1 and PORT2 cannot be used. Also, when the sampling frequency is used by 96kHz or more, PORT1 and PORT2 cannot be used. Please use PORT3 (DSP1) and PORT4 (DSP2). Evaluation mode (1) Slave mode (1-1) A/D evaluation using DIT function of AK4101A PORT1 and PORT2 are used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX197). It is possible to connect AKEMD’s D/A converter evaluation boards on the digital-amplifier, which equips DIR input. Nothing should be connected to PORT3 (DSP1) and PORT4 (DSP2). In case of using external clock through a BNC connector (J9), select EXT on JP11 (MCLK) and short JP16 (XTE) and JP17 (EXT). JP4 BICK JP5 LRCK JP16 XTE JP11 XTL XTL <KM090205> JP17 EXT EXT 2009/03 -2- [AKD5388-A] (1-2) Feeding all clocks from PORT3 (DSP1) Under the following set-up, all external clocks (MCLK, BICK, LRCK) can be fed through PORT3 (DSP1). The A/D converted data is output from SDTO1/SDTO2 of PORT3 (DSP1). Also, the A/D converted data is output through optical connector (TOTX197). JP4 BICK JP5 LRCK JP16 XTE JP11 XTL XTL JP17 EXT EXT (2) Master mode (2-1) A/D evaluation using DIT function of AK4101A PORT1 and PORT2 are used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX197). It is possible to connect AKEMD’s D/A converter evaluation boards on the digital-amplifier, which equips DIR input. Nothing should be connected to PORT3 (DSP1) and PORT4 (DSP2). In case of using external clock through a BNC connector (J9), select EXT on JP11 (MCLK) and short JP16 (XTE) and JP17 (EXT). JP4 BICK JP5 LRCK JP16 XTE JP11 XTL XTL JP17 EXT EXT (2-2) Feeding all clocks from PORT3 (DSP1) Under the following set-up, all external clocks (MCLK, BICK, LRCK) can be fed through PORT3 (DSP1). The A/D converted data is output from SDTO1/SDTO2 of PORT3 (DSP1). Also, the A/D converted data is output through optical connector (TOTX197). JP4 BICK JP5 LRCK JP16 XTE JP11 XTL XTL JP17 EXT EXT (3) Cascade TDM mode (3-1) Evaluation of cascade TDM mode that uses two AKD5388-A PORT3 (DSP1) and PORT4 (DSP2) are used. In case of using external clock through a BNC connector (J9), select EXT on JP11 (MCLK) and short JP16 (XTE) and JP17 (EXT). JP4 BICK JP5 LRCK JP16 XTE JP11 XTL XTL <KM090205> JP17 EXT EXT 2009/03 -3- [AKD5388-A] Default configuration of switch and jumper pins SW1-1 SW1-2 SW1-3 SW1-4 SW1-5 SW1-6 SW1-7 SW1-8 Name M_SN CKS2 CKS1 CKS0 TDM1 TDM0 MONO HPFE Setting OFF ON OFF OFF OFF OFF OFF OFF SW2-1 SW2-2 SW2-3 Name DIF CKS1 CKS0 Setting OFF ON ON Table 2. Switch setting JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 Name TEST1 TEST2 TEST3 BICK LRCK TDMIN D-SEL1 D-SEL2 AVDD DVDD Setting Short Short Short Short Short GND SDTO1 SDTO1 REG REG Name Setting JP11 MCLK XTL JP12 CLK X/2 JP13 BCFS X2/4 JP14 LRFS X2/256 JP15 GND Open JP16 XTE Open JP17 EXT Short JP18 LIN1-BNC Short JP19 LIN1-BNC Short JP20 RIN1-BNC Short Table 3. Jumper pins setting JP21 JP22 JP23 JP24 JP25 Name RIN1-BNC LIN2-BNC LIN2-BNC RIN2-BNC RIN2-BNC Setting Short Short Short Short Short Other jumper pins set up 1. JP6 (TDMIN) : Input data selection to TDMIN EXT : Select data of SDTO1 of PORT3(DSP1) or PORT4(DSP2) is input. In this case, either JP7 or JP8 is set to TDMIN. Separated. GND : 0V is input. <Default> 2. JP7 (D-SEL1) : Selection to SDTO1 of PORT3 SDTO1 : Connects with SDTO1 of AK5388. <Default> TDMIN : Connects with TDMIN of AK5388. 3. JP8 (D-SEL2) : Selection to SDTO1 of PORT4 SDTO1 : Connects with SDTO1 of AK5388. <Default> TDMIN : Connects with TDMIN of AK5388. 4. JP9 (AVDD) : Select AVDD for AK5388 +5V : Supply from +5V connector. REG : Supply from regulator T1. In this case, +5V connector should be open. <Default> 5. JP10 (DVDD): Select DVDD for AK5388 +3.3V : Supply from +3.3V connector. REG : Supply from regulator T2. In this case, +3.3V connector should be open. <Default> <KM090205> 2009/03 -4- [AKD5388-A] 6. JP12 (CLK), JP13 (BCFS), JP14 (LRFS) : Select clock frequency fs=48kHz : <Default> JP12 JP13 JP14 CLK LRFS BCFS X/4 X/2 X/1 X2/4 X2/2 X2/1 X2/256 X2/128 X2/64 fs=96kHz : JP14 LRFS JP12 CLK JP13 BCFS X/4 X/2 X/1 X2/4 X2/2 X2/1 X2/256 X2/128 X2/64 fs=192kHz : JP14 LRFS JP12 CLK JP13 BCFS X/4 X/2 X/1 X2/4 X2/2 X2/1 X2/256 X2/128 X2/64 Other frequency: Please set JP12, JP13, and JP14 properly. 7. JP15 (GND) : Analog ground and Digital ground OPEN : Separated. <Default> SHORT : Common. (The connector “DGND” can be open.) 8. JP18, JP19 (LIN1-BNC) : Input terminal selection of LIN1 OPEN : Select to XLR connector (J1). SHORT : Select to RCA connector (J5). <Default> 9. JP20, JP21 (RIN1-BNC) : Input terminal selection of RIN1 OPEN : Select to XLR connector (J2). SHORT : Select to RCA connector (J6). <Default> 10. JP22, JP23 (LIN2-BNC) : Input terminal selection of LIN2 OPEN : Select to XLR connector (J3). SHORT : Select to RCA connector (J7). <Default> 11. JP24, JP25 (RIN2-BNC) : Input terminal selection of RIN2 OPEN : Select to XLR connector (J4). SHORT : Select to RCA connector (J8). <Default> <KM090205> 2009/03 -5- [AKD5388-A] DIP Switch Setting [SW1] (MODE1): Setting the evaluation mode for AK5388 ON is “H”, OFF is “L”. No. 1 2 3 4 5 6 7 8 Name M_SN CKS2 CKS1 CKS0 TDM1 TDM0 MONO HPFE OFF (“L”) Slave mode ON (“H”) Master mode See Table 6 See Table 7 MONO mode OFF MONO mode ON High pass filter OFF High pass filter ON Table 4. Mode setting of AK5388 Default OFF (“L”) ON (“H”) OFF (“L”) OFF (“L”) OFF (“L”) OFF (“L”) OFF (“L”) OFF (“L”) [SW2] (MODE2): Setting the evaluation mode for AK5388 and AK4101A ON is “H”, OFF is “L”. No. 1 3 4 Name DIF CKS1 CKS0 OFF (“L”) MSB justified ON (“H”) I2S Compatible See Table 8 Default OFF (“L”) ON (“H”) ON (“H”) Table 5. Mode setting of AK5388 and AK411A M_SN L H CKS2 CKS1 CKS0 MCLK Frequency L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H 128fs (108KHz < fs ≤ 216KHz) 192fs (108KHz < fs ≤ 216KHz) 256fs (8KHz ≤ fs ≤ 54KHz) 256fs (54KHz < fs ≤ 108KHz) Auto (8KHz ≤ fs ≤ 216KHz) 384fs (8KHz ≤ fs ≤ 54KHz) 512fs (8KHz < fs ≤ 54KHz) 768fs (8KHz ≤ fs ≤ 54KHz) 128fs (108KHz < fs ≤ 216KHz) 192fs (108KHz < fs ≤ 216KHz) 256fs (8KHz ≤ fs ≤ 54KHz) 256fs (54KHz < fs ≤ 108KHz) 384fs (54KHz ≤ fs ≤ 108KHz) 384fs (8KHz ≤ fs ≤ 54KHz) 512fs (8KHz < fs ≤ 54KHz) 768fs (8KHz ≤ fs ≤ 54KHz) Default Table 6. MCLK Frequency Setting of AK5388 TDM1 L L H H TDM0 L H L H Mode BICK Normal 48 ∼ 128fs TDM256 256fs N/A N/A TDM128 128fs Table 7. Mode setting of AK5388 <KM090205> Default 2009/03 -6- [AKD5388-A] CKS1 L L H H CKS0 MCLK fs L 128fs 28k ∼ 192kHz H 256fs 28k ∼ 108kHz L 384fs 28k ∼ 54kHz H 512fs 28k ∼ 54kHz Table 8. MCLK Frequency Setting of AK4101A Default Note: AK4101A does not support MCLK=768fs. The function of the toggle SW Upper-side is “H” and lower-side is “L”. [SW3] (PDN): Resets of AK5388 and AK4101A. Keep “H” during normal operation. <KM090205> 2009/03 -7- [AKD5388-A] Analog input buffer circuit An analog input buffer circuit example (1st order HPF; fc=0.70Hz, 2nd order LPF; fc=304kHz, gain=-14.5dB) is shown in Figure 2. The analog signal is able to input through XLR or RCA connectors. (For RCA input, jumper should be short. For XLR input, jumper should be open.) The input level of this circuit is +/-15.4Vpp (AK5388: +/-2.9Vpp Typ.). When using this circuit, analog characteristics at fs=48kHz is DR=118dB, S/(N+D)=TBDdB. 4.7k 4.7k Analog In 620 JP VP+ Vin- + 15.4Vpp 68µ Bias VP- 1n 3.3k 10 + 2.9Vpp AK5388 AIN+ NJM5534D NJM5534D XLR 24.2n VA+ 620 10k JP Bias 10k 1n 3.3k - + 10µ 68µ Vin+ 0.1µ 10 AK5388 AIN- + NJM5534D Bias VA=+5V VP=±15V 2.9Vpp Figure 2. Analog input buffer circuits examples Fin 1Hz 10Hz Frequency Response -1.56dB -0.02dB Table 9. Frequency Response of HPF Fin Frequency Response 20kHz 40kHz 6.144MHz -0.005dB -0.02dB -15.6dB Table 10. Frequency Response of LPF * AKEMD assumes no responsibility for the trouble when using the circuit examples. <KM090205> 2009/03 -8- [AKD5388-A] MEASUREMENT RESULTS [Measurement condition] • Measurement unit • MCLK • BICK • fs • Bit • Power Supply • Interface • Temperature : Audio Precision, System Two Cascade : 512fs (fs=48kHz), 256fs (fs=96kHz), 128fs (fs=192kHz) : 64fs : 48kHz, 96kHz, 192kHz : 24bit : AVDD = 5.0V(REG), DVDD = 3.3V(REG) : DSP Data (10pin Header : PSIA) : Room [Measurement Results] Result L1ch / R1ch L2ch / R2ch Parameter ADC Analog Input Characteristics: S/(N+D): Filter=none (fs=48kHz, -1dBFS, BW=20kHz) (fs=96kHz, -1dBFS, BW=40kHz) (fs=192kHz, -1dBFS, BW=40kHz) D-Range: Filter=A-weighted (fs=48kHz, -60dBFS, BW=20kHz) (fs=96kHz, -60dBFS, BW=40kHz) (fs=192kHz, -60dBFS, BW=40kHz) S/N: Filter=A-weighted (fs=48kHz, -60dBFS, BW=20kHz) (fs=96kHz, -60dBFS, BW=40kHz) (fs=192kHz, -60dBFS, BW=40kHz) S/N MONO mode: Filter=A-weighted (fs=48kHz, BW=20kHz) (fs=96kHz, BW=40kHz) (fs=192kHz, BW=40kHz) <KM090205> Unit 112.3 / 110.2 108.8 / 107.4 108.8 / 107.4 110.0 / 111.0 107.4 / 107.9 107.3 / 108.3 dB dB dB 120.0 / 119.9 119.4 / 119.5 119.5 / 119.7 119.9 / 120.0 119.5 / 119.5 119.6 / 119.6 dB dB dB 120.2 / 120.0 119.3 / 119.5 119.5 / 119.6 120.1 / 120.1 119.5 / 119.4 119.7 / 119.6 dB dB dB 123.0 / 123.0 122.4 / 122.5 122.6 / 122.6 123.1 / 123.1 122.5 / 122.5 122.6 / 122.6 dB dB dB 2009/03 -9- [AKD5388-A] [ADC Plot: fs=48kHz] AKM AK5388 S/(N+D) vs. Input Level AVDD=5V, DVDD=3.3V, MCLK=512fs, fs=48kHz, fin=1kHz -80 -85 -90 -95 -100 -105 d B F S -110 -115 -120 -125 -130 -135 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dBr Figure 3. S/(N+D) vs. Input Level AKM AK5388 S/(N+D) vs. Input Frequency AVDD=5V, DVDD=3.3V, MCLK=512fs, fs=48kHz, -1dBFS Input -80 -85 -90 -95 -100 -105 d B F S -110 -115 -120 -125 -130 -135 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 4. S/(N+D) vs. Input Frequency <KM090205> 2009/03 - 10 - [AKD5388-A] AKM AK5388 Linearity AVDD=5V, DVDD=3.3V, MCLK=512fs, fs=48kHz, fin=1kHz +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 5. Linearity AKM AK5388 Frequency Response AVDD=5V, DVDD=3.3V, MCLK=512fs, fs=48kHz, -1dBFS Input -0.5 -0.6 -0.7 -0.8 -0.9 d B F S -1 -1.1 -1.2 -1.3 -1.4 -1.5 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Hz Figure 6. Frequency Response <KM090205> 2009/03 - 11 - [AKD5388-A] AKM AK5388 Crosstalk (Red=Lch, Blue=Rch) AVDD=5V, DVDD=3.3V, MCLK=512fs, fs=48kHz, -1dBFS Input -70 -80 -90 -100 -110 -120 d B -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 7. Crosstalk AKM AK5388 FFT AVDD=5V, DVDD=3.3V, MCLK=512fs, fs=48kHz, -1dBFS Input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k Hz Figure 8. FFT Plot <KM090205> 2009/03 - 12 - [AKD5388-A] AKM AK5388 FFT AVDD=5V, DVDD=3.3V, MCLK=512fs, fs=48kHz, -60dBFS Input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 9. FFT Plot AKM AK5388 FFT AVDD=5V, DVDD=3.3V, MCLK=512fs, fs=48kHz, No Signal Input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k Hz Figure 10. FFT Plot <KM090205> 2009/03 - 13 - [AKD5388-A] [ADC Plot: fs=96kHz] AKM AK5388 S/(N+D) vs. Input Level AVDD=5V, DVDD=3.3V, MCLK=256fs, fs=96kHz, fin=1kHz -80 -85 -90 -95 -100 -105 d B F S -110 -115 -120 -125 -130 -135 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dBr Figure 11. S/(N+D) vs. Input Level AKM AK5388 S/(N+D) vs. Input Frequency AVDD=5V, DVDD=3.3V, MCLK=256fs, fs=96kHz, -1dBFS Input -80 -85 -90 -95 -100 -105 d B F S -110 -115 -120 -125 -130 -135 -140 40 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 12. S/(N+D) vs. Input Frequency <KM090205> 2009/03 - 14 - [AKD5388-A] AKM AK5388 Linearity AVDD=5V, DVDD=3.3V, MCLK=256fs, fs=96kHz, fin=1kHz +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 13. Linearity AKM AK5388 Frequency Response AVDD=5V, DVDD=3.3V, MCLK=256fs, fs=96kHz, -1dBFS Input -0.5 -0.6 -0.7 -0.8 -0.9 d B F S -1 -1.1 -1.2 -1.3 -1.4 -1.5 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k 22.5k 25k 27.5k 30k 32.5k 35k 37.5k 40k Hz Figure 14. Frequency Response <KM090205> 2009/03 - 15 - [AKD5388-A] AKM AK5388 Crosstalk (Red=Lch, Blue=Rch) AVDD=5V, DVDD=3.3V, MCLK=256fs, fs=96kHz, -1dBFS Input -70 -80 -90 -100 -110 -120 d B -130 -140 -150 -160 -170 -180 40 50 100 200 500 1k 2k 5k 10k 20k 40k 20k 40k Hz Figure 15. Crosstalk AKM AK5388 FFT AVDD=5V, DVDD=3.3V, MCLK=256fs, fs=96kHz, -1dBFS Input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 40 50 100 200 500 1k 2k 5k 10k Hz Figure 16. FFT Plot <KM090205> 2009/03 - 16 - [AKD5388-A] AKM AK5388 FFT AVDD=5V, DVDD=3.3V, MCLK=256fs, fs=96kHz, -60dBFS Input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 40 50 100 200 500 1k 2k 5k 10k 20k 40k 20k 40k Hz Figure 17. FFT Plot AKM AK5388 FFT AVDD=5V, DVDD=3.3V, MCLK=256fs, fs=96kHz, No Signal Input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 40 50 100 200 500 1k 2k 5k 10k Hz Figure 18. FFT Plot <KM090205> 2009/03 - 17 - [AKD5388-A] [ADC Plot: fs=192kHz] AKM AK5388 S/(N+D) vs. Input Level AVDD=5V, DVDD=3.3V, MCLK=128fs, fs=192kHz, fin=1kHz -80 -85 -90 -95 -100 -105 d B F S -110 -115 -120 -125 -130 -135 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dBr Figure 19. S/(N+D) vs. Input Level AKM AK5388 S/(N+D) vs. Input Frequency AVDD=5V, DVDD=3.3V, MCLK=128fs, fs=192kHz, -1dBFS Input -80 -85 -90 -95 -100 -105 d B F S -110 -115 -120 -125 -130 -135 -140 90 200 500 1k 2k 5k 10k 20k 50k 80k Hz Figure 20. S/(N+D) vs. Input Frequency <KM090205> 2009/03 - 18 - [AKD5388-A] AKM AK5388 Linearity AVDD=5V, DVDD=3.3V, MCLK=128fs, fs=192kHz, fin=1kHz +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 21. Linearity AKM AK5388 Frequency Response AVDD=5V, DVDD=3.3V, MCLK=128fs, fs=192kHz, -1dBFS Input -0.5 -0.6 -0.7 -0.8 -0.9 d B F S -1 -1.1 -1.2 -1.3 -1.4 -1.5 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 70k 75k 80k Hz Figure 22. Frequency Response <KM090205> 2009/03 - 19 - [AKD5388-A] AKM AK5388 Crosstalk (Red=Lch, Blue=Rch) AVDD=5V, DVDD=3.3V, MCLK=128fs, fs=192kHz, -1dBFS Input -70 -80 -90 -100 -110 -120 d B -130 -140 -150 -160 -170 -180 90 200 500 1k 2k 5k 10k 20k 50k 80k 50k 80k Hz Figure 23. Crosstalk AKM AK5388 FFT AVDD=5V, DVDD=3.3V, MCLK=128fs, fs=192kHz, -1dBFS Input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 90 200 500 1k 2k 5k 10k 20k Hz Figure 24. FFT Plot <KM090205> 2009/03 - 20 - [AKD5388-A] AKM AK5388 FFT AVDD=5V, DVDD=3.3V, MCLK=128fs, fs=192kHz, -60dBFS Input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 90 200 500 1k 2k 5k 10k 20k 50k 80k 50k 80k Hz Figure 25. FFT Plot AKM AK5388 FFT AVDD=5V, DVDD=3.3V, MCLK=128fs, fs=192kHz, No Signal Input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 90 200 500 1k 2k 5k 10k 20k Hz Figure 26. FFT Plot <KM090205> 2009/03 - 21 - [AKD5388-A] Revision History Date (yy/mm/dd) Manual Revision Board Revision Reason Page 07/06/27 08/02/12 KM090200 KM090201 0 1 First Edition Change Change 8 Modification 9-21 08/07/07 KM090202 2 Change Modification 08/11/04 KM090203 3 09/01/05 KM090204 3 09/03/02 KM090205 4 Modification Change Device revision was changed. Rev. A -> Rev. C Circuit diagram was changed. R: 91ohm -> 10ohm, OP-amp: LME49710-> NJM5534D PORT1, PORT2: TOTX197-> TOTX176 Update of measurement results Device revision was changed. Rev. C -> Rev. D 9-21 Change Change Modification Modification Contents 9-21 10,14, 18 9-21 Update of measurement results Device revision was changed. Rev. D -> Rev. E Circuit diagram was changed. R300, R301:Add 20ohm, C300, C301:Add 220pF. R1300, R1301:Add 20ohm, C1300, C1301:Add 220pF. Update of measurement results Update of Plots. Figure 3, Figure 11, Figure 19 Update of measurement results Circuit diagram was changed. C300,C301,C1300,C1301:Deleted C121,C122,C123,C124,C1121,C1122,C1123,C1124 :24.2nF -> 15nF C3,C4,C1003,C1004: 10uF -> 100uF R15,R17,R19,R21: 10kohm -> 11kohm IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. <KM090205> 2009/03 - 22 - 5 4 3 2 1 34 35 36 37 38 39 40 41 42 43 44pin 44 CN1004 C1121 15n 2 3 C C1001 10u + 4 JP1001 5 C1054 0.1u VREFL2 VCOM2 34 0.1u 35 36 37 LIN2+ 38 LIN2- 39 TEST3 C1058 0.1u 15n 40 41 100u C1059 LIN1+ 02 LIN1- 03 AVSS1 04 AVDD1 05 TEST1 RIN2+ U1001 TEST1 6 06 BVSS 7 07 CKS0 CN1003 VREFP2 + JP1003 TEST3 C1123 15n RIN1+ 43 42 VCOM1 VREFP1 01 1 0.1u VREFL1 44 0.1u C1122 RIN1- C1057 C1004 2.2u + C1056 CN1001 C1039 2.2u + + C1038 100u D 33 RIN2- 32 AVSS2 31 AVDD2 30 TEST2 29 33 C1124 15n 32 31 C1055 0.1u C1002 10u C 30 JP1002 29 TEST2 AK5388 BVSS 28 DVSS 27 28 27 C1061 0.1u + C1003 open + D R1300 20 R1301 20 R1063 C1006 10u 8 08 CKS1 DVDD 26 9 09 CKS2 HPFE 25 25 10 10 PDN MONO 24 24 11 11 M_SN DIF 23 23 26 TDM1 22 21 TDM0 TDMIN 22 21 20 GND 19 18 17 10u 16 + 15 14 13 EXT 0.1u C1005 12 20 OVF C1060 CN1002 44pin JP1006 TDMIN 19 SDTO2 18 SDTO1 17 16 DVSS DVDD 15 LRCK 14 13 12 44pin BICK B MCLK B 44pin A A Title Size A3 Date: 5 4 3 2 AKD5388-A 44LQFP-SUB Document Number Rev 4 AK5388 Thursday, February 12, 2009 Sheet 1 1 of 1 3 RIN1+ RIN1- AVDD 2 LIN2- LIN2+ 37 4 38 5 1 AVDD 34 35 36 39 40 41 42 43 44pin 44 CN4 LIN1+ 01 1 C121 15n LIN1- 2 AVDD 3 C1 10u + C C54 0.1u CKS0 AVSS1 TEST1 6 06 BVSS 7 07 CKS0 35 VREFL2 34 + 36 VCOM2 38 37 LIN2+ RIN1- VREFP2 AVSS2 31 AVDD2 30 TEST2 29 BVSS 28 DVSS 27 RIN2+ 32 RIN2- C55 0.1u 31 AVDD C2 10u JP2 TEST2 29 28 27 C61 0.1u C6 10u 10 PDN MONO 24 24 11 11 M_SN DIF 23 23 TDM1 R12 44pin EXT 44pin TDMIN TEST1 OVF M_SN CKS2 CKS1 CKS0 TDM1 TDM0 MONO HPFE 4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MODE1 47k 51 51 51 51 51 51 +3.3V SW1 9 8 7 6 5 4 3 2 1 22 21 20 19 18 17 15 14 13 12 CN2 B 10k M_SN CKS2 CKS1 CKS0 A Title Size A3 Date: 5 DIF R59 15k 22 TDM0 21 26 JP6 TDMIN GND + 10u DVDD R1 R2 R3 R4 R5 R6 DVDD RP1 2 4 6 8 10 DSP1 JP7 D-SEL1 SDTO1 SDTO1 TDMIN JP8 D-SEL2 1 3 5 7 9 20 OVF 19 18 17 DVSS 16 15 14 13 0.1u C5 MCLK BICK LRCK SDTO1 SDTO2 TDMIN 10 SDTO2 25 SDTO1 25 DVDD HPFE LRCK CKS2 BICK 09 C60 C 30 9 MCLK BICK LRCK SDTO1 SDTO2 MCLK BICK LRCK SDTO1 SDTO2 32 DVDD PORT3 A RIN2- 33 C124 15n CKS2 PORT4 DSP2 33 CKS1 SBICK 1 3 5 7 9 CN3 8 SLRCK 2 4 6 8 10 LIN2- 40 41 RIN1+ 42 AK5388 16 BICK 43 U1 12 JP4 0.1u 26 44pin LRCK 0.1u CKS1 M_SN JP5 15n 100u C58 RIN2+ MCLK B 03 05 TEST1 15n 2.2u C59 08 PDN R58 15k LIN1- 5 R11 10k 02 AVDD1 JP1 C123 LIN1+ 04 4 VCOM1 VREFP1 CN1 0.1u VREFL1 44 0.1u JP3 C122 TEST3 39 C57 TEST3 2.2u C56 D C4 + 100u C39 + + C38 + C3 open + D R300 20 R301 20 R63 3 2 AKD5388-A Document Number Rev 4 AK5388 Thursday, February 12, 2009 Sheet 1 1 of 5 5 4 3 2 1 R43 620 C114 1n -V 2 XLB-3-31PCV C10 10u J1 C79 0.1u C109 open Bal-(Low) 3 3 2 2 R42 620 Bal+(High) C113 1 GND 4 6 LIN1-BNC BiasL1 2 3 U11 R50 10 6 LIN1+ NJM5534D + 7 NJM5534D R34 3.3k 7 4 C46 68u JP18 + U10 - 3 1n -V + 2 NJM5534D +V XLIN1 -V R22 4.7k D LIN1- 1 R23 4.7k J5 LIN1 MR-552LS White R51 10 6 7 BiasL1 3 + LIN1-BNC BiasL1 R15 + 11k U12 + R30 560 R14 10k 4 JP19 AVCC R35 3.3k - D C47 68u +V C +V C R45 620 C116 1n -V 4 3 RIN1-BNC J2 C80 0.1u C110 B open Bal-(Low) 3 XRIN1 3 2 2 R44 620 C115 Bal+(High) 1 GND 4 RIN1-BNC 3 U14 R52 10 6 RIN1+ NJM5534D + 7 NJM5534D BiasR1 2 7 4 - 6 R36 3.3k + C48 68u JP20 + 3 U13 - 2 B -V -V R24 4.7k 1n 1 R25 4.7k J6 RIN1 MR-552LS Red RIN1- NJM5534D +V XLB-3-31PCV C11 10u R53 10 6 7 BiasR1 BiasR1 R17 + 11k U15 + R31 560 R16 10k 2 + JP21 AVCC R37 3.3k - C49 68u +V +V -15V -V for LME49710MA C84 0.1u + C15 10u C17 10u C86 0.1u + + C82 0.1u C19 10u C88 0.1u + C13 10u C21 10u C90 0.1u + L4 short C23 10u C92 0.1u + A A +15V +V for LME49710MA L3 short + C12 10u C81 0.1u + C14 10u C83 0.1u + C16 10u C85 0.1u + C18 10u C87 0.1u + C20 10u C89 0.1u + C22 10u C91 0.1u Title Size A3 Date: 5 4 3 2 AKD5388-A Document Number Rev 4 INPUT1 Tuesday, February 10, 2009 Sheet 1 2 of 5 5 4 3 2 1 R47 620 C118 1n -V 2 XLB-3-31PCV C24 10u J3 C93 0.1u C111 open Bal-(Low) 3 3 2 2 R46 620 C117 Bal+(High) 1 GND 4 6 LIN2-BNC BiasL2 2 3 U17 R54 10 6 LIN2+ NJM5534D + 7 NJM5534D R38 3.3k 7 4 C50 68u JP22 + U16 - 3 1n -V + 2 NJM5534D +V XLIN2 -V R26 4.7k D LIN2- 1 R27 4.7k J7 LIN2 MR-552LS White R55 10 6 7 BiasL2 3 + LIN2-BNC BiasL2 R19 + 11k U18 + R32 560 R18 10k 4 JP23 AVCC R39 3.3k - D C51 68u +V C +V C R49 620 C120 1n -V 4 3 RIN2-BNC XLB-3-31PCV C25 10u J4 C94 0.1u C112 B open Bal-(Low) 3 +V XRIN2 3 2 2 R48 620 C119 Bal+(High) 1 GND B 4 RIN2-BNC 3 U20 R56 10 6 RIN2+ NJM5534D + 7 NJM5534D BiasR2 2 7 4 - 6 R40 3.3k + C52 68u JP24 + 3 U19 - 2 1n -V -V R28 4.7k RIN2- NJM5534D 1 R29 4.7k J8 RIN2 MR-552LS Red R57 10 6 7 BiasR2 BiasR2 R21 + 11k U21 + R33 560 R20 10k 2 + JP25 AVCC R41 3.3k - C53 68u +V +V -15V -V for LME49710MA C98 0.1u + C29 10u C31 10u C100 0.1u + + C96 0.1u C33 10u C102 0.1u + C27 10u C35 10u C104 0.1u + L5 short C37 10u C106 0.1u + A A +15V +V for LME49710MA L6 short + C26 10u C95 0.1u + C28 10u C97 0.1u + C30 10u C99 0.1u + C32 10u C101 + 0.1u C34 10u C103 + 0.1u C36 10u C105 0.1u Title Size A3 Date: 5 4 3 2 AKD5388-A Document Number Rev 4 INPUT2 Tuesday, February 10, 2009 Sheet 1 3 of 5 5 4 3 2 1 VCC D D VCC + C9 10u C64 0.1u 34 DIF0 35 VDD 36 DIF1 37 DIF2 38 U1 39 U2 40 U3 41 U4 42 V12 43 V34 TRANS 44 DIF VCC PDN 1 PDN TXP1 33 MCLK 2 MCLK TXN1 32 VCC U3 C 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 1 19 G1 G2 VCC GND 20 10 74ACT541 3 SDTI1 4 SDTI2 U2 TXP2 31 TXN2 30 VCC C67 0.1u VCC 5 SDTI3 VSS 29 6 SDTI4 VDD 28 7 VDD TXP3 27 8 VSS TXN3 26 9 BICK TXP4 25 10 LRCK TXN4 24 11 FS0 CKS1 23 + C7 10u C62 0.1u AK4101A C63 0.1u 4 3 2 1 R65 4.3k C8 10u IN VCC IF GND R64 4.3k 5 5 6 6 IN VCC IF GND 5 5 6 6 TOTX176 TOTX176 C VCC + SDTO1 SDTO2 BICK LRCK PORT2 PORT1 4 3 2 1 VSS 22 CKS0 21 20 BLS ANS 19 C4 18 C3 17 C2 16 C1 15 FS3 14 13 12 FS2 B FS1 B DIF RP2 VCC SW2 1 DIF CKS1 2 CKS0 3 4 3 2 1 6 5 4 MODE2 47k A A Title Size A3 Date: 5 4 3 2 AKD5388-A Document Number Rev 4 AK4101A Tuesday, February 10, 2009 Sheet 1 4 of 5 5 4 DGND JP15 3 TEST2 AGND +5V AGND 2 1 +3.3V J13 T45_OR J14 T45_GR GND D C42 47u + AVDD VCC +5V X1 24.576MHz +15V T1 NJM78M05FA L1 short IN C107 5p C108 5p R60 R9 REG R62 OUT GND C68 0.1u C69 0.1u + AVCC C43 47u + R8 JP9 AVDD C44 47u +3.3V DVDD +3.3V 0 +15V open T2 uPC3533HF L2 short IN 0 R61 REG 0 0 OUT GND C70 0.1u D R10 JP10 DVDD C71 0.1u C45 47u + 1M U9 1 3 5 9 11 13 14 7 VCC C C77 0.1u 1A 2A 3A 4A 5A 6A VCC GND 2 4 6 8 10 12 1Y 2Y 3Y 4Y 5Y 6Y XTL JP11 MCLK MCLK X VCC J9 EXT BNC-R-PC VCC JP17 R7 51 C75 0.1u U7 4 3 2 1 10 11 12 13 1PR 1CK 1D 1CLR 2PR 2CK 2D 2CLR 14 7 VCC GND 1Q 1Q B VCC C74 0.1u 2Q 2Q + CLK 9 8 U6 1 9 10 7 2 3 4 5 6 16 8 CLR RCO LOAD QA ENT QB ENP QC CLK QD A B C D VCC GND VCC 15 14 13 12 11 C73 0.1u 10 CLK 11 RST 16 8 VDD VSS Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1 X2/1 X2/2 X2/4 X2/64 X2/128 X2/256 JP13 2 1 10k VCC 1 3 C40 47u C41 47u BCFS JP14 SLRCK B LRFS C76 0.1u 1 3 5 9 11 13 14 7 1A 2A 3A 4A 5A 6A VCC GND 1Y 2Y 3Y 4Y 5Y 6Y 2 4 6 8 10 12 U4 6 5 4 3 2 1 U8 2 + C65 47u SBICK RP3 A C 74HC4040 R13 C78 0.1u -15V 74AC163 VCC SW3 PDN +15V 74AC74 VCC H -15V J12 T45_BLUE X2 X/1 X/2 X/4 5 6 U5 L AGND J11 T45_BLACK JP12 EXT D1 HSU119 +15V J10 T45_RED VCC EXT 74HCU04 DGND J15 T45_BLACK VCC J16 T45_OR + JP16 XTE PDN 47k SLRCK SBICK M_SN 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 1 19 DIR G RP4 B1 B2 B3 B4 B5 B6 B7 B8 18 17 16 15 14 13 12 11 VCC GND 20 10 6 5 4 3 2 1 VCC 47k C72 0.1u 74ACT245 A 74HC14 Title Size A3 Date: 5 4 3 2 AKD5388-A Document Number Rev 4 LOGIC Tuesday, February 10, 2009 Sheet 1 5 of 5