HOLTEK HT16L21V110

HT16L21
RAM Mapping 32×4 LCD Driver
Feature
Applications
• Logic operating voltage: 1.8V~5.5V
• Leisure products
• LCD operating voltage (VLCD): 2.4V~6.0V
• Games
• External VLCD pin to supply LCD operating voltage
• Telephone display
• Internal 32kHz RC oscillator
• Audio combo display
• Bias: 1/2 or 1/3; Duty:1/4
• Video player display
• Internal LCD bias generation with voltage-follower
buffers
• Kitchen appliance display
• Integrated regulator to adjust LCD operating voltage:
3.0V, 3.2V, 3.3V, 3.4V, 4.4V, 4.5V, 4.6V, 5.0V
• Household appliance
• Measurement equipment display
• Consumer electronics
• Integrated LED driver
• Support I2C or SPI 3-wire serial interface
controlled by IFS pin
General Description
The HT16L21 device is a memory mapping and
multi-function LCD controller/driver. The display
segments of the device are 128 patterns (32 segments
and 4 commons) display. It can also support LED
drive outputs on certain Segment pins. The software
configuration feature of the HT16L21 device
makes it suitable for multiple LCD applications
including LCD modules and display subsystems.
The HT16L21 device communicates with most
microprocessors/microcontrollers via a two-wire
bidirectional I2C or a three-wire SPI interface.
• Four selectable LCD frame frequencies:
64Hz or 85.3Hz or 128Hz or 170.6Hz
• 32×4 bits RAM for display data storage
• Max. 32×4 pixel: 32 segments and 4 commons
• Support two driver output mode segment/LED on
SEG24~SEG31/LED7~LED0
• Versatile blinking modes: off, 0.5Hz, 1Hz, 2Hz
• R/W address auto increment
• Low power consumption
• Manufactured in silicon gate CMOS process
• Package types: 44LQFP
Rev. 1.10
1
December 27, 2011
HT16L21
Block Diagram
VDD voltage supported range
RSTB
VDD
Power_on reset
VSS
SDA/DIO
Internal RC
Oscillator
SCL/CLK
CSB
Column
/Segment
driver
output
Timing
generator
I2C or 3-wire
Controller
8
Display RAM
COM0
COM3
IFS
VE bit
VLCD
Regulator
SEG0
R
－
OP1
＋
R
Segment
/LED driver
output
LCD
Voltage
Selector
SEG23
SEG24/LED7
－
OP0
＋
R
SEG31/LED0
LCD bias generator
VLCD voltage supported range
Pin Assignment
SEG23
LED7/SEG24
LED6/SEG25
LED5/SEG26
LED4/SEG27
LED3/SEG28
LED2/SEG29
LED1/SEG30
LED0/SEG31
VSS
IFS
CSB
CLK/SCL
DIO/SDA
RSTB
VDD
VLCD
COM0
COM1
COM2
COM3
SEG0
44 43 42 41 40 39 38 37 36 35 34
33
1
32
2
31
3
30
4
29
5
HT16L21
28
44 LQFP
6
27
7
26
8
25
9
24
10
23
11
12 13 14 15 16 17 18 19 20 21 22
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Rev. 1.10
2
December 27, 2011
HT16L21
Pin Description
Pin Name
Type
Description
Serial data input/output pin
SDA/DIO
●●Serial data (SDA) input/output for 2-wire I2C interface is an NMOS
open drain structure.
I/O
●●Serial data (DIO) input/output for 3-wire SPI interface is a CMOS
input/output structure.
Serial clock input pin
●●Serial data (SCL) is clock input for 2-wire I2C interface.
●●Serial data (CLK) is clock input for 3-wire SPI interface
SCL/CLK
I
CSB
I
Chip select pin
This pin is available for 3-wire SPI interface and not used for I2C interface.
IFS
I
Communication interface select pin
This pin is used to select the communication interface. When this pin is
connected to VDD, the device communicates with MCU or microprocessors
via a 2-wire I2C interface. When this pin is connected to VSS, the device
communicates with MCU or microprocessors using a 3-wire SPI interface.
COM0~COM3
O
LCD common outputs
SEG0~SEG23
O
LCD segment outputs
SEG24/LED7~SEG31/LED0
O
LCD segment/LED multiplexed driver outputs
RSTB
I
Reset input pin
1. This pin is used to initialize all the internal registers and the commands pin.
2. If use internal power on reset circuit only, the RSTB pin must be connected
to VDD.
VDD
—
Positive power supply
VSS
—
Negative power supply, ground.
VLCD
—
LCD power supply pin
Approximate Internal Connections
SCL, SDA (for schmit Trigger type)
DIO (for Schmitt trigger type)
COM0~COM4; SEG0~SEG31
VDD
Vselect-on
Vselect-off
VSS
VSS
IFS, RSTB
LED0~7
CSB, CLK (for schmit Trigger type)
VDD
VDD
VSS
VSS
Rev. 1.10
VSS
3
December 27, 2011
HT16L21
Absolute Maximum Ratings
Storage temperature .......................... -55°C to +150°C
Operating temperature ........................ -40°C to +85°C
Supply voltage ......................... VSS−0.3V to VSS+6.6V
Input voltage ........................... VSS−0.3V to VDD+0.3V
LED driver output current (total).........................88mA
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings"
may cause substantial damage to the device. Functional operation of this device at other conditions beyond
those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device
reliability.
Timing Diagrams
I2C Timing
SDA
tBUF
tSU:DAT
tf
tLOW
tSP
tHD:STA
tr
SCL
tHD:STA
tHD:DAT
S
tSU:STA
tHIGH
tAA
tSU:STO
P
Sr
S
SDA
OUT
SPI Timing
tCSW
90%
90%
VDD
CSB
10%
10%
tCSL
tSYS
tCSH
90%
CLK
90%
tCW
10%
tDS
90%
90%
10%
10%
VSS
tHS
90%
10%
10%
VDD
tCW
10%
90%
VSS
VDD
DIO
(INPUT )
tPD
VSS
tPD
90%
90%
10%
10%
VDD
DIO
(OUTPUT )
Rev. 1.10
4
VSS
December 27, 2011
HT16L21
Reset Timing
80%
tSR
0.9V
VDD
tRSON
0.9V
tPOF
tRW
50%
RSTB
Data
transfer
50%
tRSOFF
50%
50%
tRSOFF
50%
tRSOFF
50%
50%
Note: 1. If the conditions of reset timing are not satisfied in power ON/OFF sequence, the internal power on reset
(POR) circuit will not operate normally.
2. If the VDD drops lower than the minimum operating voltage during operating, the conditions of power on
reset timing must also be satisfied. That is the VDD drop to 0.9V and keep at 0.9V for 10ms (min.) before
rising to the normal operating voltage.
3. Data transfers on the I2C interface or SPI 3-wire serial interface should at least be delayed for 1ms after
the power-on sequence to ensure that the reset operation is complete.
D.C. Characteristics
Symbol
Parameter
VSS=0V; VDD=1.8V to 5.5V; Ta=-40~85°C
Test Condition
Condition
VDD
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
—
—
1.8
—
5.5
V
VLCD
LCD Operating Voltage
—
—
2.4
—
6.0
V
VIH
Input High Voltage
—
CSB, CLK, DIO, RSTB
0.7VDD
—
VDD
V
VIL
Input Low Voltage
—
CSB, CLK, DIO, RSTB
0
—
0.3VDD
V
IIL
Input Leakage Current
—
VIN=VSS or VDD
-1
—
1
μA
-2
—
—
mA
IOH
IOL
IDD
ILCD1
ILCD2
ISTB1
Rev. 1.10
High Level Output
Current
2.0V
3.3V VOH=0.9VDD for DIO pin
-6
—
—
mA
5.0V
-12
—
—
mA
Low Level Output
Current
2.0V
3
—
—
mA
3.3V VOL=0.4V for SDA/DIO pin
6
—
—
mA
5.0V
9
—
—
mA
2.0V No load, fLCD=64Hz, 1/3bias, LCD
3.3V display on, Internal system oscillator on,
VLCD pin input voltage=5V,
5.0V disable integrated regulator
—
1
2.5
μA
Operating Current
—
2
5
μA
—
4
10
μA
Operating Current
2.0V
No load, fLCD=64Hz, 1/3bias, LCD
display on, Internal system oscillator on,
VLCD pin input voltage=5V,
disable integrated regulator
—
25
40
μA
Operating Current
No load, fLCD=64Hz, 1/3bias, LCD
display on, Internal system oscillator on,
2.0V
VLCD pin input voltage=5.5V,
regulator output is set to 5V
—
30
52
μA
3.3V
No load, 1/3bias, LCD display off,
internal system oscillator off
—
—
1
μA
5.0V
VLCD pin input voltage =5V,
disable integrated regulator
—
—
2
μA
Standby Current for VDD
5
December 27, 2011
HT16L21
Symbol
Parameter
Standby Current for
VLCD
ISTB2
Vreg
Regulator Output
LCD Common Sink
Current
IOL1
LCD Common Source
Current
IOH1
LCD Segment Sink
Current
IOL2
LCD Segment Source
Current
IOH2
IOL3
LED Sink Current
Test Condition
VDD
Condition
Min.
Typ.
Max.
Unit
3.3V
No load, 1/3bias, LCD display off,
internal system oscillator off
—
—
1
μA
5.0V
VLCD pin input voltage =5V,
disable integrated regulator
—
—
2
μA
VLCD pin input voltage=5.5V, regulator
output is set to 4.5V, Ta=-40°C~85°C
4.35
4.5
4.65
V
VLCD pin input voltage=5.5V, regulator
output is set to 4.5V, Ta=25°C
4.42
4.5
4.58
V
VLCD=3.3V, VOL=0.33V,
disable integrated regulator
250
400
—
μA
VLCD=5V, VOL=0.5V,
disable integrated regulator
500
800
—
μA
VLCD=3.3V, VOH=2.97V,
disable integrated regulator
-140
-230
—
μA
VLCD=5V, VOH=4.5V,
disable integrated regulator
-300
-500
—
μA
VLCD=3.3V, VOL=0.33V,
disable integrated regulator
250
400
—
μA
VLCD=5V, VOL=0.5V,
disable integrated regulator
500
800
—
μA
VLCD=3.3V, VOH=2.97V,
disable integrated regulator
-140
-230
—
μA
VLCD=5V, VOH=4.5V,
disable integrated regulator
-300
-500
—
μA
VLCD=3.3V, VOL=1V,
when SP1 bit is set to “1”
10
—
—
mA
VLCD=5.0V, VOL=2V,
when SP1 bit is set to “1”
20
—
—
mA
—
—
—
—
—
—
Note: 1. Please use the integrated regulator when the regulator output voltage is less than (VLCD−0.5V).
2. If 8 LEDs turn on at the same time, total current of LED drivers can not be allowed more than 80mA.
Rev. 1.10
6
December 27, 2011
HT16L21
A.C. Characteristics
Unless otherwise specified, VDD =1.8 to 5.5V; VSS = 0 V; Ta =-40~85°C
Symbol
Parameter
—
fLCD1
fLCD2
Test Condition
LCD Frame Frequency
—
—
fLCD3
tSR
VDD Slew Rate
tPOF
VDD Off Times
RSTB Input Time
RSTB Pulse Width
tRSOFF
Wait Time for Data
Transfers
Max.
Frame frequency is set
to 64Hz
57.6
64
70.4
Frame frequency is set
to 85.3Hz
76
85.3
94.0
Frame frequency is set
to 128Hz
115.2
128
140.8
Frame frequency is set
to170.6Hz
152
170.6
188.0
Frame frequency is set
to 64Hz
51.2
64
83.0
Frame frequency is set
to 85.3Hz
68
85.3
111
Frame frequency is set
to 128Hz
102.4
128
166
Frame frequency is set
to170.6Hz
136
170.6
222
Frame frequency is set
to 64Hz
45.0
—
64
Frame frequency is set
to 85.3Hz
59.0
—
85.3
Frame frequency is set
to 128Hz
90.0
—
128
Frame frequency is set
to170.6Hz
118.0
—
170.6
0.05
—
—
V/ms
VDD drop down to 0.9V
10
—
—
ms
When RSTB signal is externally input
from a microcontroller etc.
250
—
—
ns
—
100
—
ms
400
—
—
ns
1
—
—
ms
Ta=25°C,
VDD=3.3V
Ta=-40~85°C,
VDD=2.5~5.5V
Ta=-40~85°C
VDD=1.8~2.5V
3.3
3.3
5.0
5.0
3.3
5.0
tRW
Typ.
—
5.0
3.3
tRSON
Min.
Condition
VDD
3.3
5.0
3.3
5.0
R=100kΩ and C=0.1μF
(see application circuit)
When RSTB signal is externally input
from a microcontroller etc.
2-wire I2C or 3-wire SPI interface
Unit
Hz
Hz
Hz
Note: fLCD = 1/tLCD
Rev. 1.10
7
December 27, 2011
HT16L21
A.C. Characteristics – I2C Interface
Unless otherwise specified, VSS=0V; VDD=1.8V to 5.5V; Ta=-40~85°C
Symbol
fSCL
Parameter
VDD=1.8V to 5.5V VDD=3.0V to 5.5V
Condition
Clock Frequency
—
Unit
Min.
Max.
Min.
Max.
—
100
—
400
kHz
4.7
—
1.3
—
μs
4
—
0.6
—
μs
tBUF
Bus Free Time
Time in which the bus
must be free before a new
transmission can start
tHD: STA
Start Condition Hold Time
After this period, the first
clock pulse is generated
tLOW
SCL Low Time
—
4.7
—
1.3
—
μs
tHIGH
SCL High Time
—
4
—
0.6
—
μs
tSU: STA
Start Condition Setup
Time
4.7
—
0.6
—
μs
tHD: DAT
Data Hold Time
—
0
—
0
—
ns
tSU: DAT
Data Setup Time
—
250
—
100
—
ns
tR
SDA and SCL Rise Time
Note
—
1
—
0.3
μs
tF
SDA and SCL Fall Time
Note
—
0.3
—
0.3
μs
tSU: STO
Stop Condition Set-Up
Time
—
4
—
0.6
—
μs
tAA
Output Valid from Clock
—
—
3.5
—
0.9
μs
tSP
Input Filter Time Constant
Noise suppression time
(SDA and SCL pins)
—
20
—
20
ns
Only relevant for repeated
START condition
Note: These parameters are periodically sampled but not 100% tested.
A.C. Characteristics – SPI Interface
Unless otherwise specified, VSS=0V; VDD=1.8V to 5.5V; Ta=-40~85°C
Symbol
Parameter
tSYS
Clock Cycle Time
tCW
Clock Pulse Width
tDS
Test Condition
Condition
VDD
—
Min.
Typ.
Max.
Unit
For write data
250
—
—
ns
For read data
1000
—
—
ns
—
For write data
50
—
—
ns
—
For read data
400
—
—
ns
Data Setup Time
—
For write data
50
—
—
ns
tDH
Data Hold Time
—
For write data
50
—
—
ns
tCSW
“H” CSB Pulse Width
—
ns
tCSL
CSB Setup Time
(CSB↓―CLK↑)
—
tCSH
CS Hold Time (CLK↑―CSB↑)
—
tPD
DATA Output Delay Time
(CLK―DIO)
Rev. 1.10
—
50
—
—
For write data
—
50
—
—
ns
For read data
400
—
—
ns
2
—
—
μs
—
—
350
ns
—
CO=15pF
8
tPD=10% to 90%
tPD=90% to 10%
December 27, 2011
HT16L21
Characteristics Curves – fLCD vs. VDD vs. Temperature
LCD Frame Frequency fLCD is Set to 64Hz
LCD Frame Frequency fLCD is Set to 85.3Hz
100
80
90
60
LCD frame frequency (Hz)
LCD frame frequency (Hz)
70
-40℃
-20℃
50
0℃
40
25℃
30
65℃
85℃
20
10
80
-40℃
70
-20℃
60
0℃
50
25℃
40
65℃
30
85℃
20
10
0
0
1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
1.2 1.5 1.8 2.1 2.4 2.7 3
VDD (V)
LCD Frame Frequency fLCD is Set to 128Hz
LCD Frame Frequency fLCD is Set to 170.6Hz
160
200
140
180
120
LCD frame frequency (Hz)
LCD frame frequency (Hz)
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
VDD (V)
-40℃
100
-20℃
0℃
80
25℃
60
65℃
85℃
40
20
160
140
-40℃
120
-20℃
0℃
100
25℃
80
65℃
60
85℃
40
20
0
1.2 1.5 1.8 2.1 2.4 2.7 3
0
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
1.2 1.5 1.8 2.1 2.4 2.7 3
VDD (V)
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
VDD (V)
Functional Description
Reset Function
When the RSTB pin is pulled to a low level, a
reset operation is executed and it will initialize all
functions. The status of the internal circuits after
initialization is as follows:
Power-On Reset
When the power is applied, the device is initialized
by an internal power-on reset circuit. The status of the
internal circuits after initialization is as follows:
• All common outputs are set to VLCD.
• All common outputs are set to VLCD.
• All segment outputs are set to VLCD.
• All segment outputs are set to VLCD.
• The 1/3 bias drive mode is selected.
• The 1/3 bias drive mode is selected.
• The system oscillator and the LCD bias generator
are off state.
• The system oscillator and the LCD bias generator
are off state.
• LCD display is off state.
• LCD display is off state.
• Integrated regulator is disabled.
• Integrated regulator is disabled.
• The segment/LED shared pin is set as the segment
pin.
• Internal voltage adjustment function is enabled.
• Frame frequency is set to 64Hz.
• The segment/LED shared pins are set as the
segment pins.
• Blinking function is switched off.
• Frame frequency is set to 64Hz.
• Blinking function is switched off.
Rev. 1.10
9
December 27, 2011
HT16L21
Display Memory – RAM Structure
respectively. The following diagram is a data transfer
format for I2C or SPI interface.
The display RAM is static 32×4-bits RAM which
stores the LCD data. Logic “1” in the RAM bit-map
indicates the “on” state of the corresponding LCD
segment; similarly, logic 0 indicates the “off” state.
MSB
LCD
The contents of the RAM data are directly mapped
to the LCD data. The first RAM column corresponds
to the segments operated with respect to COM0. In
multiplexed LCD applications the segment data of the
second, third and fourth column of the display RAM
are time-multiplexed with COM1, COM2 and COM3
D7
LSB
D6
D5
D4
D3
D2
D1
D0
LED LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0
LCD Display or LED output data transfer format for
I2C or SPI interface
32×4 Display Mode
When the SP1 bit is set to “0” and the SP0 bit is set to “0” or “1”, the drive mode is selected as 32 segments by
4 commons. This drive mode is also the default setting after a reset.
Output
COM3
COM2
COM1
COM0
Output
COM3
COM2
COM1
COM0
SEG1
—
—
—
—
SEG0
—
—
—
—
Address
00H
SEG3
—
—
—
—
SEG2
—
—
—
—
01H
SEG5
—
—
—
—
SEG4
—
—
—
—
02H
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
SEG31
—
—
—
—
SEG30
—
—
—
—
0FH
—
D7
D6
D5
D4
—
D3
D2
D1
D0
Data
RAM mapping of 32×4 display mode
28×4 Display Mode
When the SP1 bit is set to “1” and the SP0 bit is set to “0”, the drive mode is selected as 28 segments by
4 commons together with 4 LED driving outputs.
Output
COM3
COM2
COM1
COM0
Output
COM3
COM2
COM1
COM0
SEG1
—
—
—
—
SEG0
—
—
—
—
Address
00H
SEG3
—
—
—
—
SEG2
—
—
—
—
01H
SEG5
—
—
—
—
SEG4
—
—
—
—
02H
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
SEG27
—
—
—
—
SEG26
—
—
—
—
0DH
—
D7
D6
D5
D4
—
D3
D2
D1
D0
Data
RAM mapping of 28×4 display mode
24×4 Display Mode
When the SP1 bit is set to “1” and the SP0 bit is set to “1”, the drive mode is selected as 24 segments by
4 commons together with 8 LED driving outputs.
Output
COM3
COM2
COM1
COM0
Output
COM3
COM2
COM1
COM0
Address
SEG1
—
—
—
—
SEG0
—
—
—
—
00H
SEG3
—
—
—
—
SEG2
—
—
—
—
01H
SEG5
—
—
—
—
SEG4
—
—
—
—
02H
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
SEG23
—
—
—
—
SEG22
—
—
—
—
0BH
—
D7
D6
D5
D4
—
D3
D2
D1
D0
Data
RAM mapping of 24×4 display mode
Rev. 1.10
10
December 27, 2011
HT16L21
System Oscillator
external VLCD pin and also integrates an internal
regulator. The LCD voltage may be temperature
compensated externally through the Voltage supply to
the VLCD pin. The internal regulator can also provide
the LCD operating voltage. Therefore, the full-scale
LCD voltage (VOP) is obtained from (VLCD–VSS) or
(Vreg–VSS).
The timing for the internal logic and the LCD drive
signals are generated by an internal oscillator. The
System Clock frequency (fSYS) determines the LCD
frame frequency. During initial system power on the
System Oscillator will be in the stop state.
Fractional LCD biasing voltages, known as 1/2 or 1/3
bias voltage, are obtained from an internal voltage
divider of four series resistors connected between VLCD
and VSS. The centre resistor can be���������������������
��������������������
switched out of circuits to provide a 1/2 bias voltage level configuration.
LCD Bias Generator
The LCD supply power can come from the external
VLCD pin or the internal regulator output voltage
determined using the Internal Voltage Adjustment
(IVA) setting command. The device provides an
LCD Drive Mode Waveforms
• When the LCD drive mode is selected as 1/4 duty and 1/2 bias, the waveform and LCD display is shown as
follows:
tLCD
VLCD
VLCD
COM0
COM0
State1
State1
(on)
(on)
(VLCD+VSS)/2
(VLCD+VSS)/2
LCD segment
LCD segment
VSS
VSS
VLCD
VLCD
COM1
COM1
State2
State2
(off)
(off)
(VLCD+VSS)/2
(VLCD+VSS)/2
VSS
VSS
VLCD
VLCD
COM2
COM2
(VLCD+VSS)/2
(VLCD+VSS)/2
VSS
VSS
VLCD
VLCD
COM3
COM3
(VLCD+VSS)/2
(VLCD+VSS)/2
VSS
VSS
VLCD
VLCD
SEG n
SEG n
(VLCD+VSS)/2
(VLCD+VSS)/2
VSS
VSS
VLCD
VLCD
(VLCD+VSS)/2
SEG n+1
(VLCD+VSS)/2
SEG n+1
VSS
VSS
VLCD
VLCD
(VLCD+VSS)/2
SEG n+2
(VLCD+VSS)/2
SEG n+2
VSS
VSS
VLCD
VLCD
SEG n+3
SEG n+3
(VLCD+VSS)/2
(VLCD+VSS)/2
VSS
VSS
Waveforms for 1/4 duty drive mode with1/2 bias (VOP=VLCD−VSS)
Note: tLCD = 1/fLCD
Rev. 1.10
11
December 27, 2011
HT16L21
• When the LCD drive mode is selected as 1/4 duty and 1/3 bias, the waveform and LCD display is shown as
follows:
tLCD
VLCD
VLCD
COM0
COM0
State1
State1
(on)
(on)
VLCD- Vop/3
VLCD- Vop/3
LCD segment
LCD segment
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM1
COM1
State2
State2
(off)
(off)
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM2
COM2
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM3
COM3
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n
SEG n VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+1
SEG n+1 VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+2
SEG n+2 VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+3
SEG n+3VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
Waveforms for 1/4 duty drive mode with 1/2 bias (VOP=VLCD−VSS)
Note: tLCD = 1/fLCD
Rev. 1.10
12
December 27, 2011
HT16L21
Segment Driver Outputs
Frame Frequency
The LCD drive section includes 32 segment outputs
SEG0~SEG31 or 24 segment outputs SEG0~SEG23
which should be connected directly to the LCD
panel. The segment output signals are generated in
accordance with the multiplexed LED signals and
with the data resident in the display latch. The unused
segment outputs should be left open-circuit when less
than 32 or 24 segment outputs are required.
The device provides four frame frequencies selected
with Frame Frequency command known as 64Hz,
85.3Hz, 128Hz and 170.6Hz respectively.
LED Function
The LED pins are NMOS-structured output pins.
The Data for the LED output is contained in the
LED output setting command, starting from the most
significant bit. When a written data bit for a LED pin
is set to 1, the corresponding driving LED lights up
while the LED is switched off when the written data
bit is 0. The LED pins are pin-shared with the LCD
segment pins and can be selected using the SP1 and
SP0 bits in the Drive Mode command.
Column Driver Outputs
The LCD drive section includes 4 column outputs
COM0~COM3 which should be connected directly
to the LCD panel. The column output signals are
generated in accordance with the selected LCD
drive mode. The unused column outputs should be
left open-circuit if less than 4 column outputs are
required.
I2C Serial Interface
Address Pointer
I2C Operation
The addressing mechanism for the display RAM is
implemented using the address pointer. This allows
the loading of an individual display data byte, or a
series of display data bytes, into any location of the
display RAM. The sequence commences with the
initialization of the address pointer by the Display
Data Input command.
The device supports I2C serial interface. The I2C bus
is for bidirectional, two-line communication between
different ICs or modules. The two lines are a serial
data line, SDA, and a serial clock line, SCL. Both
lines are connected to the positive supply via pull-up
resistors with a typical value of 4.7KΩ. When the bus
is free, both lines are high. Devices connected to the
bus must have open-drain or open-collector outputs
to implement a wired-or function. Data transfer is
initiated only when the bus is not busy.
Blinking Function
The device contains versatile blinking capabilities.
The whole display can be blinked at frequencies
selected by the Blinking Frequency command. The
blinking frequency is a subdivided ratio of the system
frequency. The ratio between the system oscillator
and blinking frequencies depends on the blinking
mode in which the device is operating, as shown in
the following table:
Blinking Mode
Blinking Frequency (Hz)
0
Blink off
1
2
2
1
3
0.5
Rev. 1.10
Data Validity
The data on the SDA line must be stable during the
high period of the serial clock. The high or low state
of the data line can only change when the clock signal
on the SCL line is Low as shown in the diagram.
SDA
SCL
Data line stable;
Data valid
13
Change of data
allowed
December 27, 2011
HT16L21
START and STOP Conditions
• A high to low transition on the SDA line while SCL is high defines a START condition.
• A low to high transition on the SDA line while SCL is high defines a STOP condition.
• START and STOP conditions are always generated by the master. The bus is considered to be busy after the
START condition. The bus is considered to be free again a certain time after the STOP condition.
• The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In some respects, the
START(S) and repeated START (Sr) conditions are functionally identical.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Byte Format
Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit,
MSB, first.
P
SDA
Sr
SCL
S
or
Sr
1
2
7
8
9
1
2
3-8
P
or
Sr
9
ACK
ACK
Acknowledge
• Each bytes of eight bits is followed by one acknowledge bit. This Acknowledge bit is a low level placed on the
bus by the receiver. The master generates an extra acknowledge related clock pulse.
• A slave receiver which is addressed must generate an Acknowledge, ACK, after the reception of each byte.
• The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it
remains stable low during the high period of this clock pulse.
• A master receiver must signal an end of data to the slave by generating a not-acknowledge, NACK, bit on the
last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line high
during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition.
Data Output
by Transmitter
not acknowledge
Data Outptu
by Receiver
acknowledge
SCL From
Master
S
1
2
START
condition
Rev. 1.10
7
8
9
clock pulse for
acknowledgement
14
December 27, 2011
HT16L21
Slave Addressing
• The slave address byte is the first byte received following the START condition form the master device. The
first seven bits of the first byte make up the slave address. The eighth bit defines a read or write operation to be
performed. When the R/W bit is “1”, then a read operation is selected. A “0” selects a write operation.
• The HT16L21 device address bits are “0111000”. When an address byte is sent, the device compares the first
seven bits after the START condition. If they match, the device outputs an Acknowledge on the SDA line.
Slave Address
MSB
LSB
0
1
1
1
0
0
0
R/W
I2C Interface Write Operation
Byte Write Operation
• Single Command Type
A Single Command write operation requires a START condition, a slave address with an R/W bit, a command
byte and a STOP condition for a single command write operation.
Slave Address
S
0
1
1
1
Command byte
0
0
0
0
P
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Write ACK
ACK
1st
I2C Single Command Type Write Operation
• Compound Command Type
A Compound Command write operation requires a START condition, a slave address with an R/W bit, a
command byte, a command setting byte and a STOP condition for a compound command write operation.
Slave Address
S
0
1
1
1
0
0
0
0
Command byte
Command setting
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Write ACK
ACK
1st
P
ACK
2nd
I2C Compound Command Type Write Operation
• Display RAM Single Data Byte
A display RAM data byte write operation requires a START condition, a slave address with an R/W bit, a
display data input command byte, a valid Register Address byte, a Data byte and a STOP condition.
Slave Address
S
0
1
1
1
0
Command byte
0
0
0
1
Write ACK
0
0
0
0
1st
0
Register Address byte
0
0
X
ACK
X
X
X
A3
2nd
A2
Data byte
A1
A0
D7
ACK
D6
D5
D4
D3
D2
D1
P
D0
ACK
I2C Display RAM Single Data Byte Write Operation
Rev. 1.10
15
December 27, 2011
HT16L21
Display RAM Page Write Operation
I2C Interface Display RAM Read Operation
After a START condition the slave address with the
R/W bit is placed on the bus followed with a display
data input command byte and the specified display
RAM Register Address of which the contents are
written to the internal address pointer. The data to be
written to the memory will be transmitted next and
then the internal address pointer will be incremented
by 1 to indicate the next memory address location
after the reception of an acknowledge clock pulse.
After the internal address point reaches the maximum
memory address, the address pointer will be reset to
00H.
In this mode, the master reads the HT16L21 data
after setting the slave address. Following the R/W
bit (="0") is an acknowledge bit, a command byte
and the register address byte which is written to the
internal address pointer. After the start address of the
Read Operation has been configured, another START
condition and the slave address transferred on the bus
followed by the R/W bit (="1"). Then the MSB of the
data which was addressed is transmitted first on the
I2C bus. The address pointer is only incremented by
1 after the reception of an acknowledge clock. That
means that if the device is configured to transmit
the data at the address of AN+1, the master will read
and acknowledge the transferred new data byte and
the address pointer is incremented to A N+2. After
the internal address pointer reaches the maximum
memory address, the address pointer will be reset to
00H.
The maximum memory address is show as below.
SP1
SP0
0
X
Maximum Memory Address
0FH
1
0
0DH
1
1
0BH
This cycle of reading consecutive addresses will
continue until the master sends a STOP condition.
Command byte
Slave Address
S
0
1
1
1
0
0
0
0
1
Write
0
0
0
D6
D5
D4
0
0
0
X
X
X
X
A3
1st
D2
D1
A1
A0
ACK
ACK
Data byte
D3
A2
2nd
ACK
Data byte
D7
0
Register Address byte
D0
D7
D6
D5
D4
1st data
Data byte
D3
D2
D1
D0
D7
D6
D5
2nd data
D4
D3
D2
D1
Nth data
ACK
ACK
ACK
ACK
P
D0
2
I C Interface N Bytes Display RAM Data Write Operation
Command byte
Slave Address
S
0
1
1
1
0
0
0
0
1
Write
0
0
0
0
Register Address byte
0
0
0
X
X
X
X
A3
A2
A1
P
A0
2nd
1st
ACK
ACK
ACK
0
Slave Address
S
0
1
1
1
0
Data byte
Data byte
0
0
1
Read
D7
D6
D5
D4
D3
D2
D1
D7
D0
D5
D4
D3
D2
D1
D0
D7
2nd data
1st data
ACK
D6
Data byte
ACK
D6
D5
D4
D3
Nth data
ACK
D2
D1
D0
P
NACK
ACK
I2C Interface N Bytes Display RAM Data Read Operation
Rev. 1.10
16
December 27, 2011
HT16L21
SPI Serial Interface
SPI Interface Write Operation
Byte Write Operation
SPI Operation
• Single Command Type
A Single Command write operation is activated
by the CSB signal going low. The 8-bit command
byte is shifted from the MSB into the shift register
at each CLK rising edge.
The device also includes a 3-wire SPI serial interface.
The SPI operations are described as follows:
• The CSB pin is used to activate the data transfer.
When the CSB pin is at a high level, the SPI
operation will be reset and stopped. If the CSB pin
changes state from high to low, data transmission
will start.
• Compound Command Type
For a compound command, an 8-bit command
byte is first shifted into the shift register followed
by an 8-bit command setting. Note that the CLK
high pulse width, after the command byte has been
shifted in, must remain at this level for at least
2μs after which the command setting data can be
consecutively shifted in.
• The data is transferred from the MSB of each byte
and is shifted into the shift register on each CLK
rising edge.
• The input data is automatically latched into the
internal register for each 8-bit input data after the
CSB signal goes low.
• Display RAM Single Data Byte
The display RAM single data write operation
consists of a display data input (write) command, a
register address and a write data byte.
• For read operations, the MCU should assert a high
pulse on the CSB pin to change the data transfer
direction from input mode to output mode on the
DIO pin after sending the command byte and the
setting values. If the MCU sets the CSB signal to a
high level again after receiving the output data, the
data direction on the DIO pin will be changed into
input mode and the read operation will end.
CSB
CLK
Command byte
• For a read operation, the data is output on the DIO
pin at the CLK falling edge.
DIO
• For display RAM data read/write operations using
the SPI interface, the read/write control bit is
contained in the Display Data Input Command.
Refer to the Display Data Input Command
description for more details.
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
SPI Single Command Type Write Operation
CSB
2μs(min)
CLK
DIO
Command byte
Command setting
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SPI Compound Command Type Write Operation
CSB
2μs(min)
2μs(min)
CLK
Display Data Input command byte
DIO
1
0
0
0
0
0
0
Data byte
Register Address byte
0
X
X
X
X
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SPI Display RAM Single Data Byte Write Operation
Rev. 1.10
17
December 27, 2011
HT16L21
The maximum memory address is show as below.
Display RAM Page Write Operation
The display RAM Page write operation consists of
a display data write command, a register address of
which the contents are written to the internal address
pointer followed by N bytes of written data. The
data to be written to the memory will be transmitted
next and then the internal address pointer will be
automatically incremented by 1 to indicate the next
memory address location. After the internal address
point reaches the maximum memory address, the
address pointer will be reset to 00H.
SP1
SP0
0
X
Maximum Memory Address
0FH
1
0
0DH
1
1
0BH
CSB
CLK
2μs(min)
2μs(min)
Display Data Input Command byte
DIO
1
0
0
0
0
0
X
X
X
X
A3
A2
2μs(min)
A1
A0
D7
D6
D5
D4
D3
Data
byte
Data byte
Data byte
Register Address byte
0
0
2μs(min)
D2
D1
D0
D7
D6
D5
1st data
D4
D3
2nd data
D2
D1
D0
D7
3rd data
CSB
CLK
2μs(min)
Data byte
DIO
D0
(N-1)th
data
D7
D6
D5
D4
D3
D2
D1
D0
Nth data
SPI Interface N Bytes Display RAM Data Write Operation
Rev. 1.10
18
December 27, 2011
HT16L21
SPI Interface Display RAM Read Operation
reception of each data byte. That means that if the
device is configured to transmit the data at the address
of AN+1, the master will read the transferred data byte
and the address pointer is incremented to AN+2. After
the internal address pointer reaches the maximum
memory address, the address pointer will be reset to
00H.
In this mode, the master reads the device data after
sending the Display Data Input command when the
CSB pin changes state from high to low. Following
the read/write control bit, which is contained in the
Display Data Input command, is the register address
byte which is written to the internal address pointer.
After the start address of the Read Operation has
been configured, another CSB high pulse is placed
on the bus and then the MSB of the data which was
addressed is transmitted first on the SPI bus. The
address pointer is only incremented by 1 after the
This cycle of reading consecutive addresses will
continue until the master pulls the CSB line to a high
level to terminate the data transfer.
CSB
CLK
2μs(min)
2μs(min)
Display data Input command byte
DIO
1
0
0
0
0
0
0
X
X
X
X
A3 A2 A1 A0
Data
byte
Data byte
Data byte
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1st data
2nd data
Register Address byte
1
2μs(min)
D7
3rd data
CSB
CLK
2μs(min)
Data byte
DIO
D0
(N-1)th
data
D7 D6 D5 D4 D3 D2 D1 D0
Nth data
SPI Interface N Bytes Display RAM Data Read Operation
Rev. 1.10
19
December 27, 2011
HT16L21
Command Summary
Software Reset Command
This command is used to initialize the HT16L21 device.
Function
Byte
Soft Reset Command
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
R/W
Def
1
0
1
0
1
0
1
0
—
W
—
st
1
Note:
●●When this software reset command is executed, all the command registers are initialized to the
default values.
●●After the reset command is executed, the device will experience an internal initialization for 1ms.
●●Normal operation can be executed after the device initialization is complete.
●●During the initialization period, no commands can be executed.
●●If the programmed command is not defined, the function will not be affected.
The status of the internal circuits after initialization is as follows:
●●All segment/common outputs are set to VLCD.
●●The 1/3 bias drive mode is selected.
●●The system oscillator and the LCD bias generator are in an off state.
●●The LCD display is in an off state and the integrated regulator is disabled.
●●The segment/LED shared pin is setup as a segment pin.
●●The frame frequency is set to 64Hz.
●●The blinking function is switched off.
Drive Mode Command
Function
Byte
(MSB)
Bit6 Bit5
Bit7
Bit4
Bit3
Bit2
Bit1
(LSB)
Note R/W
Bit0
Def
Drive mode setting command
1st
1
0
0
0
0
0
1
0
—
W
—
Duty, Bias and pin-shared setting
2nd
X
X
SP1
SP0
X
X
X
Bias
—
W
00H
Note:
Bit0
Bias
0
1/3 bias
1
1/2 bias
Segment/LED shared pin selected
SP1
SP0
Segment 28~31/LED3~0
Segment 24~27/LED7~4
0
X
Set as segment pins
Set as segment pins
1
0
Set as LED pins
Set as segment pins
1
1
Set as LED pins
Set as LED pins
●●Power on status: The1/3 bias drive mode is selected and also the segment output pins are selected.
●●If the programmed command is not defined, the function will not be affected.
Rev. 1.10
20
December 27, 2011
HT16L21
Display Data Input Command
This command sends data from MCU to the memory MAP of the HT16L21 device.
Function
Byte
Display Data
Input/output
Command
1st
Address pointer
2nd
(MSB)
(LSB)
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Bit7
Bit0
1
0
0
0
0
0
0
Note
R/W
Def
0
Write operation
W
—
R
—
W
00H
R/W
Def
1
0
0
0
0
0
0
1
Read operation for 3-wire
SPI interface used only.
X
X
X
X
A3
A2
A1
A0
Display data start address
of memory map
Note:
SP1
SP0
0
X
0FH
1
0
0DH
1
1
0BH
Maximum Memory Address
●●Power on status: The address is set to 00H.
●●If the programmed command is not defined, the function will not be affected.
System Mode Command
This command controls the internal system oscillator on/off and display on/off.
Function
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Note
Bit0
System mode setting
command
1st
1
0
0
0
0
1
0
0
—
W
—
System oscillator and
Display on/off Setting
2nd
X
X
X
X
X
X
S
E
—
W
00H
Note:
Bit
Internal System Oscillator
LCD Display
X
off
off
0
on
off
1
on
on
S
E
0
1
1
●●Power on status: Display off and disable the internal system oscillator.
●●If the programmed command is not defined, the function will not be affected.
Rev. 1.10
21
December 27, 2011
HT16L21
Frame Frequency Command
This command selects the frame frequency.
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Note R/W
Bit0
Function
Byte
Def
Frame frequency command
1st
1
0
0
0
0
1
1
0
—
W
—
Frame frequency setting
2nd
X
X
X
X
X
X
F1
F0
—
W
02H
R/W
Def
Note:
Bit [1:0]
Frame Frequency
F1, F0
00
85.3Hz
01
170.6Hz
10
64Hz
11
128Hz
●●Power on status: Frame frequency is set to 64Hz.
●●If the programmed command is not defined, the function will not be affected.
Blinking Frequency Command
This command defines the blinking frequency of the display modes.
Function
Byte
(MSB)
Bit6
Bit7
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Note
Bit0
Blinking frequency command
st
1
1
0
0
0
1
0
0
0
—
W
—
Blinking frequency setting
2nd
X
X
X
X
X
X
BK1
BK0
—
W
00H
Note:
Bit
Blinking Frequency
BK1
BK0
0
0
Blinking off
0
1
2Hz
1
0
1Hz
1
1
0.5Hz
●●Power on status: Blinking function is switched off.
●●If the programmed command is not defined, the function will not be affected.
LED Output Command
This command defines the blinking frequency of the display modes.
Function Byte
LED output
command
1st
LED output
data
2nd
(MSB)
Bit6
Bit7
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
1
1
0
0
—
1
0
0
0
X
X
X
X
R/W Def
W
LED3 LED2 LED1 LED0 When [SP1:SP0]=10 used
LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 When [SP1:SP0]=11 used
—
W 00H
Note:
●●The LED registers and latches are cleared after a new configuration is written into the SP1 and SP0
bits in the Drive Mode command.
●●If the programmed command is not defined, the function will not be affected.
Rev. 1.10
22
December 27, 2011
HT16L21
Internal Voltage Adjustment (IVA) Setting Command
The internal voltage (VLCD) adjustment can provide sixteen kinds of regulator voltage adjustment options by setting
the LCD operating voltage adjustment command.
Function
Byte
Internal voltage
adjustment
(IVA) Setting
1st
Internal voltage
adjust control
2nd
(MSB)
(LSB)
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Bit7
Bit0
1
0
X
X
0
X
0
VE
1
X
0
V2
1
V1
Note
0
V0
R/W Def
—
●●The “VE” bit is used
to enable or disable
the internal regulator
adjustment for the LCD
voltage.
●●The V3~V0 bits can be
used to adjust the VLCD
voltage.
W
—
W
00H
Note:
VE
Regulator Adjustment
0
Off – bias voltage is supplied from VLCD pin
1
On – bias voltage is supplied from the internal regulator
V2
V1
V0
Regulator Output Voltage (V)
0
0
0
3.0V
0
0
1
3.2V
0
1
0
3.3V
0
1
1
3.4V
1
0
0
4.4V
1
0
1
4.5V
1
1
0
4.6V
1
1
1
5.0V
●●Power on status: Disable the internal regulator.
●●When the VLCD voltage is lower than 3.5V, it is recommended to disable the internal regulator so that
the VLCD voltage is directly connected to the internal bias voltage generator.
●●Caution: Use the internal regulator when the “Regulator output voltage<VLCD−0.5V”
●●If the programmed command is not defined, the function will not be affected.
Rev. 1.10
23
December 27, 2011
HT16L21
Operation Flow Chart
Access procedures are illustrated below using flowcharts.
Initialization
Power On
Set Internal LCD bias and
segment/LED share pin
Set Internal LCD frame frequency
Set LCD blinking frequency
Next processing
Display Data Read/Write (Address Setting)
Start
Address setting
Display RAM data write
Display on and enable internal system clock
Next processing
Rev. 1.10
24
December 27, 2011
HT16L21
Application Circuit
I2C Interface
[SP1:SP0]=0x
• RSTB pin is connected to a MCU
VDD
LCD panel
4.7K
4.7K
SCL
MCU
COM0~COM3
SEG0~31
COM0~COM3
SEG0~31
SDA
HT16L21
IFS
VDD
RSTB
VDD
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
• RSTB pin is connected to external resistor and capacitor
VDD
LCD panel
4.7K
4.7K
SCL
MCU
COM0~COM3
SEG0~31
COM0~COM3
SEG0~31
SDA
HT16L21
IFS
VDD
RSTB
0.1uF
VDD
100K
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
• Use internal power on reset circuit only, the RSTB pin must be connected to VDD
VDD
LCD panel
4.7K
4.7K
SCL
MCU
COM0~COM3
SEG0~31
COM0~COM3
SEG0~31
SDA
VDD
HT16L21
IFS
RSTB
VDD
VSS
0.1uF
VDD
Rev. 1.10
25
VLCD
0.1uF
VLCD
December 27, 2011
HT16L21
[SP1:SP0]=10
• RSTB pin is connected to a MCU
VDD
LCD panel
4.7K
COM0~COM3
4.7K
SEG0~27
VLCD
SCL
MCU
COM0~COM3
SDA
RLED*4 LED*4
SEG0~27
LED0
LED1
HT16L21
LED2
IFS
VDD
RSTB
LED3
VDD
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
• RSTB pin is connected to external resistor and capacitor
VDD
LCD panel
4.7K
COM0~COM3
4.7K
SEG0~27
VLCD
SCL
MCU
COM0~COM3
SDA
RLED*4 LED*4
SEG0~27
LED0
LED1
HT16L21
LED2
IFS
VDD
LED3
RSTB
0.1uF
VDD
100K
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
• Use internal power on reset circuit only, the RSTB pin must be connected to VDD
VDD
LCD panel
4.7K
COM0~COM3
4.7K
VLCD
SCL
MCU
COM0~COM3
SDA
VDD
SEG0~27
SEG0~27
LED2
LED3
VDD
VSS
0.1uF
VDD
Rev. 1.10
LED1
HT16L21
IFS
RSTB
RLED*4 LED*4
LED0
VLCD
0.1uF
VLCD
26
December 27, 2011
HT16L21
[SP1:SP0]=11
• RSTB pin is connected to a MCU
VDD
LCD panel
4.7K
4.7K
COM0~COM3
SEG0~23
COM0~COM3
SEG0~23
VLCD
RLED*8
SCL
LED*8
LED0
LED1
LED2
SDA
MCU
LED3
HT16L21
VDD
LED4
IFS
LED5
LED6
RSTB
VDD
VSS
VLCD
0.1uF
LED7
0.1uF
VDD
VLCD
• RSTB pin is connected to external resistor and capacitor
VDD
LCD panel
4.7K
4.7K
COM0~COM3
SEG0~23
COM0~COM3
SEG0~23
VLCD
RLED*8
SCL
LED*8
LED0
LED1
LED2
SDA
MCU
LED3
HT16L21
VDD
LED4
IFS
LED5
LED6
RSTB
0.1uF
VDD
100K
VSS
0.1uF
VLCD
LED7
0.1uF
VDD
VLCD
• Use internal power on reset circuit only, the RSTB pin must be connected to VDD
VDD
LCD panel
4.7K
4.7K
COM0~COM3
SEG0~23
COM0~COM3
SEG0~23
VLCD
RLED*8
SCL
LED*8
LED0
LED1
LED2
SDA
MCU
LED3
HT16L21
VDD
LED4
IFS
LED5
LED6
RSTB
VDD
VSS
0.1uF
VDD
Rev. 1.10
VLCD
LED7
0.1uF
VLCD
27
December 27, 2011
HT16L21
SPI Interface
[SP1:SP0]=0x
• RSTB pin is connected to a MCU
LCD panel
CSB
COM0~COM3
SEG0~31
COM0~COM3
SEG0~31
CLK
MCU
HT16L21
DIO
IFS
RSTB
VDD
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
• RSTB pin is connected to external resistor and capacitor
LCD panel
CSB
COM0~COM3
SEG0~31
COM0~COM3
SEG0~31
CLK
MCU
HT16L21
DIO
IFS
RSTB
0.1uF
VDD
100K
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
• Use internal power on reset circuit only, the RSTB pin must be connected to VDD
LCD panel
CSB
COM0~COM3
SEG0~31
COM0~COM3
SEG0~31
CLK
MCU
HT16L21
DIO
IFS
RSTB
VDD
VSS
0.1uF
VDD
Rev. 1.10
28
VLCD
0.1uF
VLCD
December 27, 2011
HT16L21
[SP1:SP0]=10
• RSTB pin is connected to a MCU
LCD panel
COM0~COM3
SEG0~27
COM0~COM3
SEG0~27
VLCD
SCL
RLED*4
CLK
MCU
HT16L21
DIO
LED1
LED2
IFS
RSTB
LED*4
LED0
LED3
VDD
VSS
VLCD
0.1uF
0.1uF
VDD
VLCD
• RSTB pin is connected to external resistor and capacitor
LCD panel
COM0~COM3
SEG0~27
VLCD
CSB
COM0~COM3
SEG0~27
RLED*4
CLK
MCU
HT16L21
DIO
LED1
LED2
IFS
LED3
RSTB
0.1uF
LED*4
LED0
VDD
100K
VSS
0.1uF
VLCD
0.1uF
VDD
VLCD
• Use internal power on reset circuit only, the RSTB pin must be connected to VDD
LCD panel
COM0~COM3
SEG0~27
VLCD
CSB
COM0~COM3
SEG0~27
RLED*4
CLK
MCU
HT16L21
DIO
LED1
LED2
IFS
RSTB
LED3
VDD
VSS
0.1uF
VDD
Rev. 1.10
LED*4
LED0
VLCD
0.1uF
VLCD
29
December 27, 2011
HT16L21
[SP1:SP0]=11
• RSTB pin is connected to a MCU
LCD panel
COM0~COM3
SEG0~23
VLCD
RLED*8
CSB
COM0~COM3
SEG0~23
LED1
CLK
MCU
LED2
DIO
LED3
HT16L21
LED4
LED5
IFS
RSTB
LED*8
LED0
LED6
VDD
VSS
VLCD
0.1uF
LED7
0.1uF
VDD
VLCD
• RSTB pin is connected to external resistor and capacitor
LCD panel
COM0~COM3
SEG0~23
VLCD
RLED*8
CSB
COM0~COM3
LED*8
SEG0~23
LED0
LED1
CLK
LED2
MCU
LED3
HT16L21
DIO
LED4
LED5
IFS
LED6
RSTB
0.1uF
VDD
100K
VSS
0.1uF
VLCD
LED7
0.1uF
VDD
VLCD
• Use internal power on reset circuit only, the RSTB pin must be connected to VDD
LCD panel
COM0~COM3
SEG0~23
VLCD
RLED*8
CSB
COM0~COM3
LED*8
SEG0~23
LED0
LED1
CLK
LED2
MCU
HT16L21
DIO
LED3
LED4
IFS
LED5
LED6
RSTB
VDD
VSS
0.1uF
VDD
Rev. 1.10
VLCD
LED7
0.1uF
VLCD
30
December 27, 2011
HT16L21
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be
updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/
literature/package.pdf) for the latest version of the package information.
44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.469
―
0.476
B
0.390
―
0.398
C
0.469
―
0.476
D
0.390
―
0.398
E
―
0.031
―
F
―
0.012
―
G
0.053
―
0.057
H
―
―
0.063
I
―
0.004
―
J
0.018
―
0.030
K
0.004
―
0.008
α
0°
―
7°
Symbol
A
Rev. 1.10
Dimensions in mm
Min.
Nom.
Max.
11.90
―
12.10
B
9.90
―
10.10
C
11.90
―
12.10
D
9.90
―
10.10
E
―
0.80
―
F
―
0.30
―
G
1.35
―
1.45
H
―
―
1.60
I
―
0.10
―
J
0.45
―
0.75
K
0.10
―
0.20
α
0°
―
7°
31
December 27, 2011
HT16L21
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright© 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication.
However, Holtek assumes no responsibility arising from the use of the specifications described.
The applications mentioned herein are used solely for the purpose of illustration and Holtek makes
no warranty or representation that such applications will be suitable without further modification,
nor recommends the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical components in life
support devices or systems. Holtek reserves the right to alter its products without prior notification. For
the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
32
December 27, 2011