SD60C32/P, SD60C52/P Semiconductor CMOS SINGLE-COMPONENT 8-BIT MICROCOMPUTER Description The AUK 60C32/P 60C52/P is a high-performance micro controller fabricated with AUK high-density CMOS technology. The AUK CMOS technology combines the high speed and density characteristics of MOS with the low power attributes of CMOS. The 60C52 contains a 8K×8 ROM, a 256×8 RAM, 32 I/O lines, three 16bit counter/timers, a six sourc two-priority level nested interrupt structure, a serial I/O port for either multiprocessor communication, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the device has two software selectable modes of power reduction idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator , causing all other chip function to be inoperative. Features • 8-bit CPU optimized for control applications. • • • • • • • Pin-to-pin compatible with intel's 80C52/80C32. 256 Bytes of on-chip data RAM. 60C52 low power CPU only. 32 programmable I/O lines. Three 16bit timer/counters. TTL and CMOS compatible logic levels 64K external program memory space and data memory • MCS-51 fully compatible instruction set • ONCETM (ON-circuit emulation) mode • Power control modes -Idle mode -Power down mode • 6 interrupt source space. Ordering Information Type NO. Marking Package Code Type NO. Marking Package Code SD60C32 SD60C32 PLCC44 SD60C32P SD60C32 DIP40 SD60C52 SD60C52 PLCC44 SD60C52P SD60C52 DIP40 Outline Dimensions (17.653) (17.399) (16.662) (16.510) 20 15.24 0.25 1 0.630 (16.002) 0.590 (14.906) 1.22TYP PLCC44 2.54 1 . 4±0 . 1 4 . 5± 0 . 3 0.5MIN ± 3 . 5± 0 . 3 50.7±0.2 MIN 0.020 (0.508) 0.695 0.685 0.656 0.650 0.180 (4.572) 0.165 (4.191) 0.120 (3.048) 0.090 (2.286) 21 o 0.050 (1.270) BASE PLANE 0.048 (1.219) 0.042(1.067) 45 SEATING PLANE 40 (17.653) (17.399) (16.662) (16.510) 13.4 ±0.2 0.695 0.685 0.656 0.650 XAM51 unit : mm 0 . 5±0 . 1 DIP40 KSI-W015-000 1 SD60C32/P SD60C52/P Absolute Maximum Ratings Characteristic Rating Unit 0 ~ +70 ℃ - 65 ~ + 150 ℃ - 0.5 ~ VCC + 0.5 V Ambient temperature under bias Storage temperature Voltage on any pin to VSS Maximum IOL per I/O pin 15 ㎃ Power dissipation 1.5 W Block Diagram P0.0-P0.7 P2.0-P2.7 PORT 0 DRIVERS PORT 2 DRIVERS PORT 0 LATCH PORT 2 LATCH Vcc Vss RAM ADDR REGISTER RAM B REGISTER ROM/ EPROM STACK POINTER ACC TMP2 TMP1 ALU PSW PROGRAM ADDRESS REGISTER PCON SCON TMOD TCON TH1 T2CON TH0 TL0 TL1 TH2 TL2 RCAP2H RCAP2L SBUF IE IP INTERRUPT SERIAL PORT AND TIMER BLOCKS BUFFER PC INCREMENTER PSEN ALE EA RST TIMING AND CONTROL INSTRUCTION REGISTER PROGRAM COUNTER PD DPTR PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS P1.0-P1.7 P3.0-P3.7 OSCILLATOR XTAL1 XTAL2 KSI-W015-000 2 SD60C32/P SD60C52/P P0.6/AD6 P0.7/AD7 10 TxD/P3.1 INT0/P3.2 INT1/P3.3 11 40DIP 31 EA/VP P 30 ALE/PROG PSEN P2.7/A15 12 29 13 28 T0/P3.4 14 T1/P3.5 15 26 P2.5/A13 WR/P3.6 RD/P3.7 16 25 17 24 P2.4/A12 P2.3/A11 XTAL2 18 23 P2.2/A10 XTAL1 19 22 P2.1/A9 VSS 20 21 P2.0/A8 27 P2.6/A14 38 9 37 10 36 11 35 44PLCC 12 34 13 33 14 32 15 31 16 30 17 29 18 RxD/P3.0 32 39 8 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NC ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS NC A8/P2.0 A9/P2.1 A10/P2.2 A11/P2.3 A12/P2.4 9 40 33 41 8 7 28 P1.7 RST P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 42 P0.5/AD5 27 34 43 7 26 P0.4/AD4 P1.6 25 P0.3/AD3 35 1 36 6 44 5 P1.5 24 P1.4 2 P0.1/AD1 P0.2/AD2 23 37 3 4 22 38 4 3 21 P0.0/AD0 P1.2 P1.3 20 VC C 39 5 40 2 6 1 19 T2/P1.0 T2EX/P1.1 P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 NC VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 Pin Configuration Pin Description VCC : PIN 40 (DIP40), PIN 44 (PLCC44) Supply voltage during normal, Idle and power down operations. VSS : PIN 20 (DIP 40), PIN 22 (PLCC44) Circuit ground. Port 0 : PIN 32~39 (DIP 40), PIN 36~43 (PLCC44) Port 0 is an 8bit open drain bi-directional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1's written to them float, and in that state can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullups when emitting 1's and source and sink several LS TTL inputs. Port 0 outputs the code bytes during program verification on the 60C52 external pullups resistors are required during program verification. Port 1 : PIN 1~8 (DIP 40), PIN 2~9 (PLCC44) Port 1 output buffers can drive LSI TTL inputs. Port 1 is an 8bit bi-directional I/O port with internal pullups. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current because of the internal pullups KSI-W015-000 3 SD60C32/P SD60C52/P Pin Description (Continued) In addition, Port 1 serves the functions of the following special features of the 60C52. Port Pin Alternate Function P1.0 T2(External Count Input to Timer / Counter 2) P1.1 T2EX(Timer / Counter 2 Capture/Reload Trigger and Direction Control) Port 1 receives the low-order address bytes during ROM verification. Port 2 : PIN 21~28 (40DIP), PIN 24~31 (44PLCC) Port 2 is an 8-bit bi-directional I/O port with internal pullups. The port 2 output buffers can drive LS TTL inputs. Port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as input. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8 bit addresses (MOVX @ Ri), port 2 emits the contents of the P2 special function register Port 3 : PIN 10~17 (DIP 40), PIN 13~19 (PLCC44) Port 3 is an 8bit bi-directional I/O port with internal pullups. The port 3 output buffers can drive LS TTL input. Port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current because of the pullups. Port 3 also serves the function of various special feature of the MCS-51 Family, as listed below : Port PIN PIN NO. Alternate Function P3.0 10 RxD (Serial input port) P3.1 11 TxD (Serial output port) P3.2 12 INT0 (External interrupt 0) P3.3 13 INT1 (External interrupt 1) P3.4 14 T0 (Timer 0 external input) P3.5 15 T1 (Timer 1 external input) P3.6 16 WR (External data memory write strobe) P3.7 17 RD (External data memory read strobe) KSI-W015-000 4 SD60C32/P SD60C52/P RST: PIN 9 (DIP40), PIN 10 (PLCC44) Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. An internal pulldown resistor permits a power-on reset with only a capacitor connected to VCC . ALE: PIN 30 (DIP40), PIN 33 (PLCC44) Address latch enable output pulse for latching the low byte of the address during accesses to external memory. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note : However, that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input PROG during EPROM programming. PSEN : PIN 29 (DIP 40), PIN 32 (PLCC44) Program store enable is the read strobe to external program memory. When the 60C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA: PIN 31 (DIP 40), PIN 35 (PLCC44) External access enable. EA must be strapped to VSS in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. If EA is strapped to VCC the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. XTAL1: PIN 19 (DIP 40), PIN 21 (PLCC44) Input to the Inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2: PIN 18 (DIP 40), PIN 20 (PLCC44) Output from the inverting oscillator amplifier 0 Crystal Oscillator XTAL2 NC: PIN1, 12, 23, 34 (PLCC44) Non connection pins. 30pF 30pF XTAL1 VSS KSI-W015-000 5 SD60C32/P SD60C52/P Idle Mode In the Idle mode, the CPU puts itself to sleep while all the on chip peripherals stay active. The instruction that invokes the Idle mode is the last instruction executed in the normal operating mode before Idle mode is activated. The content of the on-chip RAM and all the special function registers remain intact during this mode. The Idle mode can be terminated either by any enabled interrupt, at which time the process is picked up at the interrupt service routine and continued, or by a hardware reset which starts the processor the same as a power on reset. Power Down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and special function register retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The control bits for the reduced power modes are in the special function register PCON. Table. Status of the external pins during Idle and power down modes. Mode Program Memory ALE PSEN Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Internal 0 0 Data Data Data Data External 0 0 Float Data Data Data Power Down Power Down PORT 0 PORT 1 PORT 2 PORT 3 KSI-W015-000 6 SD60C32/P SD60C52/P Electrical Characteristics (DC) (Ta = 0 ℃ ~ 70℃ or -40℃ ~ 85 ℃, VCC = 5V ± 20%, VSS =0V) SYMBOL PARAMETER LIMITS TEST CONDITIONS MIN TYP. MAX VIL Input low voltage, except EA -0.5 0.2VCC0.1 V VIL1 Input low voltage to EA 0 0.2VCC0.3 V VIH Input high voltage, except XTAL1,RST 0.2VCC +0.9 VCC+0.5 V VIH1 Input high voltage to XTAL1, RST 0.7 VCC VCC+0.5 V VOL Output low voltage to ports 1,2,3 IOL=1.6㎃ 0.45 V VOL1 Output low voltage to ports 0, ALE, PSEN IOL=3.2㎃ 0.45 V VOH Output high voltage to ports 1,2,3,ALE,PSEN IOH=-60㎂ IOH=-30㎂ IOH=-10㎂ VCC-0.3 VCC-0.7 VCC-1.5 V VOH1 Output high voltage (port 0 in external bus mode) IOH=-200㎂ IOH=-3.2㎃ IOH=-7.0㎃ VCC-0.3 VCC-0.7 VCC-1.5 V IIL Logical 0 input current to ports 1,2,3 VIN =0.45V -10 -50 ㎂ ITL Logical 1 to 0 transition current to ports 1,2,3 VIN =2V - 265 -650 ㎂ ILI Input leakage current to port 0, EA 0 < VI N < VCC 0.02 ±10 ㎂ ICC Power supply current Active mode @ 12MHz Idle mode @ 12MHz Power-down mode 15 5 5 30 7.5 75 ㎃ ㎃ ㎂ RRST Internal reset pull-down resistor 100 225 kohm C 1O Pin capacitance 40 10 KSI-W015-000 UNIT pF 7 SD60C32/P SD60C52/P Electrical Characteristics (AC) (Ta = 0 ℃ ~ 70℃ or -40℃ ~ 85 ℃, VCC = 5V ± 20%, VSS =0V) SYSBOL FIGURE PARAMETER 12MHz CLOCK MIN MAX Oscillator frequency : Speed Versions 60C32/60C52 1/t CLCL VARIABLE CLOCK MIN MAX 3.5 16 UNIT MHz tLHLL 1 ALE pulse width 127 2tCLCL-40 ㎱ tAVLL 1 Address valid to ALE low 43 tCLCL-40 ㎱ tLLAX 1 Address hold after ALE low 53 tCLCL-30 ㎱ tLLIV 1 ALE low to valid instruction in tLLPL 1 ALE low to PSEN low 53 tCLCL-30 ㎱ tPLPH 1 PSEN pulse with 205 3tCLCL-45 ㎱ tPLIV 1 PSEN low to valid instruction in tPXIX 1 Input instruction hold after PSEN tPXIZ 1 Input instruction float after PSEN 59 tCLCL-25 ㎱ tAVIV 1 Address to valid instruction in 312 5tCLCL-105 ㎱ tPLAZ 1 PSEN low to address float 10 10 ㎱ tRLRH 2, 3 RD pulse width 400 6tCLCL-100 ㎱ tWLWH 2, 3 WR pulse width 400 6tCLCL-100 ㎱ tRLDV 2, 3 RD low to valid data in tRHDX 2, 3 Data hold after RD tRHDZ 2, 3 Data float after RD 107 2tCLCL-70 ㎱ tLLDV 2, 3 ALE low to valid data in 517 8tCLCL-150 ㎱ tAVDV 2, 3 Address to valid data in 585 9tCLCL-165 ㎱ tLLWL 2, 3 ALE low to RD or WR low 200 3tCLCL+50 ㎱ tAVWL 2, 3 Address valid to WR low or RD low 203 4tCLCL-130 ㎱ tQVWX 2, 3 Data valid to WR transition 33 tCLCL-50 ㎱ tWHQX 2, 3 Data hold after WR 33 tCLCL-50 ㎱ tQVWH 2, 3 Data valid to WR High 433 7tCLCL-150 ㎱ tRLAZ 2, 3 RD low to address float tWHLH 2, 3 RD or WR high to ALE high 43 tCHCX 4 High time 20 20 ㎱ tCLCX 4 Low time 20 20 ㎱ tCLCH 4 Rise time 20 20 ㎱ tCHCL 4 Fall time 20 20 ㎱ 234 4tCLCL-100 145 0 3 CLCL-105 0 ㎱ ㎱ ㎱ Data Memory 252 0 5tCLCL-165 0 300 3tCLCL-50 0 123 tCLCL-40 ㎱ ㎱ 0 ㎱ tCLCL-40 ㎱ External Clock KSI-W015-000 8 SD60C32/P SD60C52/P Electrical Characteristics (Continued) (Ta = 0 ℃ ~ 70℃ or -40℃ ~ 85 ℃, VCC = 5V ± 20%, VSS =0V) SYMB FIGUR OL E 1/t CLCL 16MHz CLOCK MIN MAX PARAMETER VARIABLE CLOCK UNI T MIN MAX t LHLL 1 Oscillator frequency : Speed Versions 60C52/60C32 ALE pulse width t AVLL 1 Address valid to ALE low 23 t CLCL-40 ㎱ t LLAX 1 Address hold after ALE low 33 t CLCL-30 ㎱ t LLIV 1 ALE low to valid instruction in t LLPL 1 ALE low to PSEN low 23 t CLCL-40 ㎱ t PLPH 1 PSEN pulse with 143 3t CLCL-45 ㎱ t PLIV 1 PSEN low to valid instruction in t PXIX 1 Input instruction hold after PSEN t PXIZ 1 Input instruction float after PSEN 38 t CLCL-25 ㎱ t AVTV 1 Address to valid instruction in 208 5t CLCL-105 ㎱ t PLAZ 1 PSEN low to address float 10 10 ㎱ 3.5 16 MHz 85 2t CLCL-40 ㎱ 150 4t CLCL-100 83 0 3CLCL-105 0 ㎱ ㎱ ㎱ Data Memory t RLRH 2, 3 RD pulse width 275 6t CLCL-100 ㎱ t WLWH 2, 3 WR pulse width 275 6t CLCL-100 ㎱ t RLDV 2, 3 RD low to valid data in t RHDX 2, 3 Data hold after RD t RHDZ 2, 3 Data float after RD 55 2t CLCL-70 ㎱ t LLDV 2, 3 ALE low to valid data in 350 8t CLCL-150 ㎱ t AVDV 2, 3 Address to valid data in 398 9t CLCL-165 ㎱ t LLWL 2, 3 ALE low to RD or WR low 138 3t CLCL+50 ㎱ t AVWL 2, 3 Address valid to WR low or RD low 120 4t CLCL-130 ㎱ t ZVWX 2, 3 Data valid to WR transition 13 t CLCL-50 ㎱ t WHQX 2, 3 Data hold after WR 13 t CLCL-50 ㎱ t QVWH 2, 3 Data valid to WR High 288 7t CLCL-150 ㎱ t RLAZ 2, 3 RD low to address float t WHLH 2, 3 RD or WR high to ALE high 23 148 0 5t CLCL-165 0 238 3t CLCL-50 0 103 t CLCL-40 ㎱ ㎱ 0 ㎱ t CLCL+40 ㎱ External Clock t CHCX 4 High time 20 20 ㎱ t CLCX 4 Low time 20 20 ㎱ t CLCH 4 Rise time 20 20 ㎱ t CHCL 4 Fall time 20 20 ㎱ KSI-W015-000 9 SD60C32/P SD60C52/P Timing Diagram tLHLL ALE tA V L L tLLPL tPLPH tLLIV PSEN tPLIV tL L A X PORT0 tPXIZ tPLAZ tPXIX A0 - A7 INSTR IN A0 - A7 tAVIV PORT2 A0 - A15 A8 - A15 Figure 1. External Program Memory Read Cycle ALE tWHLH tLLDV PSEN tLLWL tRLRH RD tAVLL tL L A X tRLDV tRLAX PORT0 A0 - A7 FROM RI OR DPL tRHDZ tRHDX DATA IN A0 - A7 FROM PCL INSTR IN tAVWL tAVDV PORT2 P2.0 - P2.7 OR A8 - A15 FROM DPH A0 - A15 FROM PCH Figure 2. External Data Memory Read Cycle KSI-W015-000 10 SD60C32/P SD60C52/P Timing Diagram (Continued) ALE tWHLH PSEN tLLWL tWLWH WR tLLAX tAVLL PORT0 tQVWX A0 - A7 FROM RI OR DPL tWHQX DATA OUT A0 - A7 FROM PCL INSTR IN tAVWL PORT2 P2.0 - P2.7 OR A8 - A15 FROM DPH Figure 3. External Data A0 - A15 FROM PCH Memory Write Cycle - 0.5 VCC 0.7VCC 0.45V 0.2VSS-0.1 tCHCL tCHCX tCLCX tCLCH tCLCL Figure 4. External Clock Drive + 0.1V -0.5 VCC 0.45V VLOAD+ 0.2VCC+0.9 VLOAD - 0.1V VLOAD 0.2VCC-0.1 NOTE : AC Inputs during testing are driven at V CC-0.5 for a logic '1' and 0.45V for a logic '0'. Timing measurements are made at V IH min for a logic '1' and V IL for a logic '0' TIMING REFERENCE POINTS - 0.1V VOH + 0.1V VOL NOTE : For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begings to float when a 100mV change from the loaded V OH /V OL level occurs. I OH/IOL ≥ 20mA Figure 5. AC Testing Input/Output Figure 6. Float Waveform KSI-W015-000 11 SD60C32/P SD60C52/P Timing Diagram (Continued) 45 40 35 30 MAX ACTIVE MODE 25 I CC ㎃ 20 TYP ACTIVE MODE 15 10 MAX IDLE MODE 5 TYP IDLE MODE 4MHz 8MHz 12MHz 16MHz FREQ AT XTAL1 Figure 7. Icc vs. FREQ Valid only within frequency specifications of the device under test VCC VCC ICC ICC RST VCC RST VCC P0 P0 EA (NC) CLOCK SIGNAL VCC VCC EA (NC) XTAL2 XTAL1 CLOCK SIGNAL XTAL2 XTAL1 VSS VSS Figure 8. I C C Test Condition, Active Mode All other pins are disconnected Figure 9. I C C Test Condition, Idle Mode All other pins are disconnected KSI-W015-000 12 SD60C32/P SD60C52/P Timing Diagram (Continued) - 0.5 V CC 0.7VCC 0.45V - 0.1 0.2V SS tCHCL tCHCX tCLCH t CLCX t CLCL F i g u r e 1 0 . C l o c k S i g n a l W a v e f o r m f o r Ic c T e s t s i n A c t i v e a n d I d l e M o d e s t C L C H = t C H C L = 5㎱ V CC I CC RST VCC VCC P0 EA (NC) XTAL2 XTAL1 VSS F i g u r e 1 1 . Ic c T e s t C o n d i t i o n , P o w e r d o w n M o d e A l l o t h e r p i n s a r e d i s c o n n e c t e d , Vc c = 2 V t o 5 . 5 V KSI-W015-000 13