AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider www.azmicrotek.com DESCRIPTION FEATURES The AZP53 is a sine wave/CMOS to LVPECL buffer/divider optimized for very low phase noise (-165dBc/Hz). It is particularly useful in converting crystal or SAW based oscillators into LVPECL outputs for up 800MHz of bandwidth. For greater bandwidth, refer to the AZP63. • • • • • The AZP53 is one of a family of parts that provide options of fixed ÷1, fixed ÷2 and selectable ÷1, ÷2 modes as well as active high enable or active low enable to oscillator designers. Refer to Table 2 for the comparison of parts within the AZP5x and AZP63 family. LVPECL outputs optimized for very low phase noise (-165dBc/Hz) Up to 800MHz bandwidth Selectable ÷1, ÷2 output Selectable Enable logic 3.0V to 3.6V operation BLOCK DIAGRAM APPLICATIONS • Converting crystal or SAW based oscillators to LVPECL output PACKAGE AVAILABILITY • Order Number • • Available in die QFN8 SON8 • Green/RoHS Compliant/Pb-Free Package Marking 1 AZP53PG QFN8 D3 <Date Code>2 AZP53QG1 SON8 D <Date Code>2 1 Tape & Reel - Add 'R1' at end of order number for 7in (1k parts), 'R2' (2.5k) for 13in 2 See www.azmicrotek.com for date code format www.azmicrotek.com +1-480-962-5881 Request a Sample 1630 S Stapley Dr, Suite 127 Mesa, AZ 85204 USA May 2012, Rev 2.1 Arizona Microtek, Inc. AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider PIN DESCRIPTION AND CONFIGURATION Table 1 - Pin Description Pin 1 Name Q Type Output Function LVPECL Output 2 Q Output LVPECL Output 3 4 5 6 7 8 EN GND D EN_SEL DIV_SEL VDD Input Power Input Input Input Power Enable Negative Supply Sine or CMOS Input Enable Select Divide Select Positive Supply VDD Q Q EN 1 2 7 D3 <Date Code> 3 6 5 Q 1 Q 2 EN 3 GND 4 DIV_SEL EN_SEL D 4 D<Date Code> 8 8 VDD 7 DIV_SEL 6 EN_SEL 5 D GND Figure 1 - Pin Configuration for QFN8 & SON8, respectively www.azmicrotek.com +1-480-962-5881 Request a Sample 2 May 2012, Rev 2.1 Arizona Microtek, Inc. AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider ENGINEERING NOTES FUNCTIONALITY The AZP53 is one of a family of parts that provide options of fixed ÷1, fixed ÷2 and selectable ÷1, ÷2 modes as well as active high enable or active low enable to oscillator designers. Table 2 details the differences between the parts to assist designers in selecting the optimal part for their design. Table 3 lists the specific AZP53 functional operation. Figure 2 plots the S-parameters of the D input. S-parameter and IBIS model files for the AZP53 are also available for download. Table 2 - AZP51-54 & AZP63 Family Part Number Divide Ratio EN Logic AZP51 AZP52 AZP53 AZP54 AZP63 ÷1 ÷2 Selectable ÷1 or ÷2 ÷1 Selectable ÷1 or ÷2 active HIGH active HIGH selectable active LOW selectable EN pullup/pull-down Pull-up Pull-up selectable Pull-down selectable Bandwidth > 800MHz > 800MHz > 800MHz > 800MHz ≥ 1GHz Table 3 - AZP53 Functional Operation, ÷1 mode Part Number EN_SEL High, NC1 Inputs EN Low, NC1 High AZP53 Low High, NC1 Low DIV_SEL Low, NC High 1 Not connected 2 Don't care 3 Tri-State www.azmicrotek.com +1-480-962-5881 Request a Sample 1 D Low High X2 Q Low High Z3 Outputs Q High Low Z3 Low Low High High High Low X 2 3 Z3 Z Divide Ratio ÷1 ÷2 3 May 2012, Rev 2.1 Arizona Microtek, Inc. AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider Figure 2- S11, Parameters, D Input INPUT TERMINATION The D input bias is VDD/2 fed through an internal 10kΩ resistor. For clock applications, an input signal of at least 750mVpp ensures the AZP53 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation. Input signal D 10kΩ A/R VDD/2 Figure 3 - Input Termination www.azmicrotek.com +1-480-962-5881 Request a Sample 4 May 2012, Rev 2.1 Arizona Microtek, Inc. AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider OUTPUT TERMINATION TECHNIQUES The LVPECL compatible output stage of the AZP53 uses a current drive topology to maximize switching speed as illustrated below in Figure 4. Two current source PMOS transistors (M1-M2) feed the output pins. M5 is an NMOS current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output current of 5.1mA (low output state). M3 is off, and the entire 21.1mA flows through the output pin. The associated output voltage swings match LVPECL levels when external 50Ω resistors terminate the outputs. Both Q and Q ¯ should always be terminated identically to avoid waveform distortion and circulating current caused by unsymmetrical loads. This rule should be followed even if only one output is in use. VDD (+3.3 V) Output Stage Vbp External Circuitry M2 M1 21.1mA 21.1mA Q Q M4 M3 D Vbn 21.1mA - High 5.1mA - Low M5 50Ω 50Ω VTT = VDD - 2.0V 16mA Figure 4 - Typical Output Termination DUAL SUPPLY LVPECL OUTPUT TERMINATION The standard LVPECL loads are a pair of 50Ω resistors connected between the outputs and VDD-2.0V (Figure 4). The resistors provide both the DC and the AC loads, assuming 50Ω interconnect. If an additional supply is available within the application, a four resistor termination configuration is possible (Figure 5). www.azmicrotek.com +1-480-962-5881 Request a Sample 5 May 2012, Rev 2.1 Arizona Microtek, Inc. AZP53 VDD (+3.3 V) Output Stage VDD (+3.3 V) M2 M1 Vbp Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider 21.1mA External Circuitry 130Ω 130Ω 82Ω 82Ω 21.1mA Q Q M4 M3 D 21.1mA - High 5.1mA - Low M5 Vbn 16mA Figure 5 - Dual Supply Output Termination THREE RESISTOR TERMINATION Another termination variant eliminates the need for the additional supply (Figure 6). Alternately three resistors and one capacitor accomplish the same termination and reduce power consumption. VDD (+3.3 V) Output Stage Vbp External Circuitry M2 M1 21.1mA 21.1mA Q Q M4 M3 D 21.1mA - High 5.1mA - Low 50Ω 0.01µF Vbn M5 50Ω 50Ω 16mA Figure 6 - Three Resistor Termination www.azmicrotek.com +1-480-962-5881 Request a Sample 6 May 2012, Rev 2.1 Arizona Microtek, Inc. AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider EVALUATION BOARD (EBP53) Arizona Microtek’s evaluation board EBP53 provides the most convenient way to test and prototype AZP53 series circuits. Built for the AZP53Q 1.5x1.0 mm package, it is designed to support both dual and single supply operation. Dual supply operation (VDD=+2.0V, VSS=-1.3V) enables direct coupling to 50Ω time domain test equipment (Figure 7). VDD (+2.0 V) Output Stage Vbp Test Equipment Terminations M2 M1 21.1mA 21.1mA Q Q M4 M3 D Vbn 21.1mA - High 5.1mA - Low 50Ω 50Ω M5 16mA VSS (-1.3 V) Figure 7 - Split Supply LVPECL Output Termination AC TERMINATION Clock applications or phase noise/frequency domain testing scenarios typically require AC coupling. Figure 8 below shows the AC coupling technique. The 200Ω resistors form the required DC loads, and the 50Ω resistors provide the AC termination. The parallel combination of the 200Ω and 50Ω resistors results in a net 40Ω AC load termination. In many cases this will work well. If necessary, the 50Ω resistors can be increased to about 56Ω. Alternately, bias tees combined with current setting resistors will eliminate the lowered AC load impedance. The 50Ω resistors are typically connected to ground but can be connected to the bias level needed by the succeeding stage. www.azmicrotek.com +1-480-962-5881 Request a Sample 7 May 2012, Rev 2.1 Arizona Microtek, Inc. AZP53 VDD (+3.3 V) Output Stage Vbp 21.1mA M4 M3 Vbn External Circuitry M2 M1 21.1mA D Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider 21.1mA - High 5.1mA - Low Q 0.01µF Q 0.01µF 200Ω M5 200Ω 50Ω 50Ω GND or VT 16mA Figure 8 - AC Termination www.azmicrotek.com +1-480-962-5881 Request a Sample 8 May 2012, Rev 2.1 Arizona Microtek, Inc. AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider PERFORMANCE DATA Table 4 - Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol Characteristic Rating Unit VDD Power Supply 0 to +5.5 V VI Input Voltage -0.5 to VDD + 0.5 V TA Operating Temperature Range -40 to +85 °C TSTG Storage Temperature Range -65 to +150 °C ESDHBM Human Body Model 2500 V ESDMM Machine Model 200 V ESDCDM Charged Device Model 2500 V Table 5 - DC Characteristics DC Characteristics (VDD = 3.0V to 3.6V unless otherwise specified, TA = -40 to 85 °C) Symbol Characteristic Conditions -40 C VOH Output HIGH Voltage VOL Output LOW Voltage 1 1 Min Typ Max 2.05 2.415 2.05 2.48 85 C 2.05 2.54 -40 C 1.365 1.615 1.43 1.68 1.49 1.74 -10 10 25 C VDD = 3.3V 25 C VDD = 3.3V 85 C Unit V V μA IZ Output Leakage Current, Tri-state2 VIH High Level Input Voltage VIL Low Level Input Voltage EN IPU Pullup Current EN_SEL 2.2 μA IPD Pulldown Current DIV_SEL -2.2 μA IP Pullup/Pulldown Current EN ±2.2 μA RBIAS Bias Resistor D Input to Internal VDD/2 Reference 10k Ω IDD Power Supply Current IDDZ EN=Disable EN_SEL DIV_SEL V 0.8 22 Power Supply Current – D Input ≤ VIL Outputs Tri-state1 EN=Disable 1 Specified with outputs terminated through 50Ω resistors to VDD - 2V or Thevenin equivalent. 2 Measured at Q / Q pins. www.azmicrotek.com +1-480-962-5881 Request a Sample 2 V 35 mA 8 mA 9 May 2012, Rev 2.1 Arizona Microtek, Inc. AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider Table 6 - AC Characteristics AC Characteristics (VDD = 3.0V to 3.6V, TA = -40 to 85 °C) Symbol Characteristic Min Max Unit 80 250 ps ÷1 800 MHz ÷2 1300 VINMAX Maximum Recommended Input Signal VDD VINMIN Minimum Recommended Input Signal 1,2 tr / tf Output Rise/Fall (20% - 80%) Maximum Input Frequency - Sine wave2 fMAX nP 1,2 Phase Noise - 1MHz offset 0.2 V p-p -165 1 Specified with outputs terminated through 50W resistors to VCC - 2V or Thevenin equivalent. 2 1.5 v p-p sine wave input, AC coupled to D pin. www.azmicrotek.com +1-480-962-5881 Request a Sample V p-p dBc/Hz 10 May 2012, Rev 2.1 Arizona Microtek, Inc. AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider PACKAGE DIAGRAM QFN8 (1.5x1.5x0.55mm) Green/RoHS compliant/Pb-Free MSL =1 www.azmicrotek.com +1-480-962-5881 Request a Sample 11 May 2012, Rev 2.1 Arizona Microtek, Inc. AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider PACKAGE DIAGRAM SON8 (1.5x1.0x0.4mm) Green/RoHS compliant/Pb-Free MSL =1 www.azmicrotek.com +1-480-962-5881 Request a Sample 12 May 2012, Rev 2.1 Arizona Microtek, Inc. AZP53 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider DIE SPECIFICATIONS Die Size 754µ x 354µ Pad Size 52.1µ Octagonal Die Coordinates (Center 0,0) D X Coordinate (µm) -273.875 Pad Name Y Coordinate (µm) -106.575 EN_SEL -140.35 -106.65 DIV_SEL -43.625 -106.65 VDD 302.875 -20.45 Q 170.925 105.725 QN 72.55 105.725 EN -175.3 106 GND -296.35 72.325 Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part. www.azmicrotek.com +1-480-962-5881 Request a Sample 13 May 2012, Rev 2.1