VCXO Jitter Attenuator and FemtoClock™ Multiplier ICS810252BI-03 DATA SHEET GENERAL DESCRIPTION FEATURES • Two LVCMOS/LVTTL outputs, 17Ω impedance Each output supports independent frequency selection at 25MHz, 62.5MHz, 125MHz, and 156.25MHz The ICS810252BI-03 is a member of the HiPerClockS™ HiperClockS™ family of high performance clock solutions from IDT. The ICS810252BI-03 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock™ frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-TQFP, E-Pad and 32VFQFN packages and supports industrial temperature range. ICS • Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz • Attenuates the phase jitter of the input clock by using a lowcost pullable fundamental mode VCXO crystal • VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection • FemtoClock frequency multiplier provides low jitter, high frequency output • Absolute pull range: ±50ppm • FemtoClock VCO frequency: 625MHz • RMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz - 20MHz): 1.1ps (typical) • 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package nCLK1 VDD CLK1 CLK0 nCLK0 XTAL_OUT VDDX XTAL_IN PIN ASSIGNMENT 32 31 30 29 28 27 26 25 LF1 1 24 LF0 2 23 VDDO_QB ISET 3 22 QB 21 GND 20 VDDO_QA GND GND 4 CLK_SEL 5 VDD 6 19 QA RESERVED 7 18 GND GND 8 17 ODASEL_0 ICS810252BI-03 ODASEL_1 ODBSEL_0 ODBSEL_1 VDD VDDA PDSEL_0 PDSEL_1 PDSEL_2 9 10 11 12 13 14 15 16 32-Lead TQFP, E-Pad 7mm x 7mm x 1.0mm package body Y package Top View 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View ICS810252BYI-03 REVISION A AUGUST 20, 2009 1 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER BLOCK DIAGRAM VCXO Input Pre-Divider CLK0 PD PU/PD nCLK0 CLK1 PD nCLK1 PU/PD CLK_SEL Pulldown 0 1 000 = 1 001 = 193 010 = 256 011 = 2430 100 = 3125 101 = 9720 110 = 15625 111 = 19440 XTAL_OUT LF1 LF0 3 ISET PDSEL_[2:0] PU XTAL_IN Loop Filter Output Divider 25MHz Phase Detector VCXO Charge Pump VCXO Feedback Divider ÷3125 VCXO Jitter Attenuation PLL FemtoClock PLL 625MHz PD 2 2 ODASEL_[1:0] Output Divider QB 00 = 25 01 = 5 10 = 4 11 = 10 PD ICS810252BYI-03 REVISION A AUGUST 20, 2009 QA 00 = 25 01 = 5 10 = 4 11 = 10 2 ODBSEL_[1:0] ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 1. PIN DESCRIPTIONS Number Name Type Analog Input/Output Analog Input/Output 1, 2 LF1, LF0 3 ISET 4, 8, 18, 21, 24 GND Power 5 CLK_SEL Input Description Loop filter connection node pins. Charge pump current setting pin. Power supply ground. Pulldown Input clock select. When HIGH selects CLK1/nCLK1. When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels. Core power supply pins. 6, 12, 27 VDD Power 7 9, 10, 11 13 14, 15 16, 17 RESERVED PDSEL_2, PDSEL_1, PDSEL_0 VDDA ODBSEL_1, ODBSEL_0 ODASEL_1, ODASEL_0 Reser ved 19 QA Output 20 VDDO_QA Power Output power supply pin for QA clock output. Bank B single-ended clock output. LVCMOS/LVTTL interface levels. 17Ω output impedance. Input Power Input Input 22 QB Output 23 VDDO_QB Power 25 nCLK1 Input 26 CLK1 Input 28 nCLK0 Input 29 30, 31 CLK0 XTAL_OUT, XTAL_IN Input 32 VDDX Input Power Reser ved pin. Do not connect. Pullup Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A. Analog supply pin. Frequency select pins for Bank B output. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Frequency select pins for Bank A output. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Bank A single-ended clock output. LVCMOS/LVTTL interface levels. 17Ω output impedance. Output power supply pin for QB clock output. Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Inver ting differential clock input. VDD/2 bias voltage when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 bias voltage when left floating. Non-inver ting differential clock input. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Power supply pin for VCXO charge pump. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN RPULLUP Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor RPULLDOWN ROUT CPD Test Conditions Minimum Typical Maximum Units 4 pF 10 pF 51 kΩ Input Pulldown Resistor 51 kΩ Output Impedance 17 Ω ICS810252BYI-03 REVISION A AUGUST 20, 2009 VDD, VDDX, VDDO_QA, VDDO_QB = 3.465V 3 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 3A. PRE-DIVIDER FUNCTION TABLE Inputs Pre-Divider Value PDSEL_2 PDSEL_1 PDSEL_0 0 0 0 1 0 0 1 193 0 1 0 256 0 1 1 2430 1 0 0 3125 1 0 1 9720 1 1 0 15625 1 1 1 19440 (default) TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE Inputs Output Divider Value ODxSEL_1 ODxSEL_0 0 0 25 (default) 0 1 5 1 0 4 1 1 10 ICS810252BYI-03 REVISION A AUGUST 20, 2009 4 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 3C. FREQUENCY FUNCTION TABLE Input Frequency (MHz) Pre-Divider Value VCXO Frequency (MHz) Femtoclock VCO Frequency (MHz) Output Divider Value Output Frequency (MHz) 0.008 1 25 625 25 25 0.008 1 25 625 5 125 0.008 1 25 625 4 156.25 0.008 1 25 625 10 62.5 1.544 193 25 625 25 25 1.544 193 25 625 5 125 1.544 193 25 625 4 156.25 1.544 193 25 625 10 62.5 2.048 256 25 625 25 25 2.048 256 25 625 5 125 2.048 256 25 625 4 156.25 2.048 256 25 625 10 62.5 19.44 2430 25 625 25 25 19.44 2430 25 625 5 125 19.44 2430 25 625 4 156.25 19.44 2430 25 625 10 62.5 25 3125 25 625 25 25 25 3125 25 625 5 125 25 3125 25 625 4 156.25 25 3125 25 625 10 62.5 77.76 9720 25 625 25 25 77.76 9720 25 625 5 125 77.76 9720 25 625 4 156.25 77.76 9720 25 625 10 62.5 125 15625 25 625 25 25 125 15625 25 625 5 125 125 15625 25 625 4 156.25 125 15625 25 625 10 62.5 155.52 19440 25 625 25 25 155.52 19440 25 625 5 125 155.52 19440 25 625 4 156.25 155.52 19440 25 625 10 62.5 ICS810252BYI-03 REVISION A AUGUST 20, 2009 5 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 32 Lead VFQFN 37°C/W (0 mps) 32 Lead TQFP 32.2°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage VDDA VDDO_QA, VDDO_QB VDDX Minimum Typical Maximum Units 3.135 3. 3 3.465 V Analog Supply Voltage VDD – 0.13 3.3 VDD V Output Supply Voltage 3.135 3.3 3.465 V Charge Pump Supply Voltage 3.135 3.3 3.465 V 190 mA 13 mA 2 mA Maximum Units IDDA Power and Charge Pump Supply Current Analog Supply Current IDDO_QA + IDDO_QB Output Supply Current IDD + IDDX Test Conditions No Load TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current VDD = VIN = 3.465V 15 0 µA VDD = VIN = 3.465V 5 µA IIL Input Low Current Test Conditions CLK_SEL, ODASEL_[0:1], ODBSEL_[0:1] PDSEL[0:2] CLK_SEL, ODASEL_[0:1], ODBSEL_[0:1] PDSEL[0:2] VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 Minimum Typical VDD = 3.465V, VIN = 0V -5 µA VDD = 3.465V, VIN = 0V -150 µA 2.6 V 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO_QA,_QB/2. ICS810252BYI-03 REVISION A AUGUST 20, 2009 6 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum CLK0/nCLK0, CLK1/nCLK1 CLK0, CLK1 VIN = 0V, VDD = 3.465V -5 nCLK0, nCLK1 VIN = 0V, VDD = 3.465V -150 IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 Typical VIN = VDD = 3.465V VCMR Common Mode Input Voltage; NOTE 1, 2 NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. Maximum Units 150 µA µA µA 0.15 1.3 V GND + 0.5 VDD - 0.85 V TABLE 5. AC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fIN Input Frequency fOUT tsk(o) Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Skew; NOTE 2, 3 odc Output Duty Cycle tjit(Ø) Test Conditions Minimum Maximum Units 0.008 155.52 MHz 25 156.25 MHz 125MHz, 25MHz cr ystal Integration Range: 12kHz - 20MHz Typical 1.1 47 ps 130 ps 53 % t R / tF Output Rise/Fall Time 20% to 80% 20 0 500 ps VCXO & FemtoClock PLL Reference Clock Input is ±50ppm 3 s tLOCK Lock Time; NOTE 4 from Nominal Frequency NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized with outputs at the same frequency using the loop filter components for the high loop bandwidth. Refer to VCXO-PLL Loop Bandwidth Selection Table. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage, same frequency and with equal load conditions. Measured at VDDO/2. NOTE 4: Lock time measured from power-up to stable output frequency. ICS810252BYI-03 REVISION A AUGUST 20, 2009 7 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TYPICAL PHASE NOISE AT 125MHZ 125MHz NOISE POWER dBc Hz RMS Phase Jitter (Random) 12kHz to 20MHz = 1.1ps (typical) OFFSET FREQUENCY (HZ) ICS810252BYI-03 REVISION A AUGUST 20, 2009 8 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.65V±5% VDD SCOPE VDD, VDDO_QA, VDDO_QB, VDDA VDDX LVCMOS nCLK0, nCLK1 Qx V V Cross Points PP CMR CLK0, CLK1 GND GND -1.65V±5% DIFFERENTIAL INPUT LEVEL 3.3V OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot V DDO_Q Noise Power FOUTx 2 V DDO_Q FOUTy Offset Frequency f1 2 tsk(o) f2 RMS Jitter = Area Under Offset Frequency Markers PHASE JITTER OUTPUT SKEW V DDO_Q 2 QA, QB t PW t odc = QA, QB PERIOD t PW 80% 80% tR tF 20% 20% x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD ICS810252BYI-03 REVISION A AUGUST 20, 2009 OUTPUT RISE/FALL TIME 9 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PARAMETER MEASUREMENT INFORMATION, CONTINUED VCXO & FEMTOCLOCK PLL LOCK TIME APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. LVCMOS CONTROL PINS All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS810252BYI-03 REVISION A AUGUST 20, 2009 10 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS810252BI-03 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDX, VDDA, VDDO_QA and VDDO_QB should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF VDDX 10Ω .01µF VDDA .01µF 10µF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT ICS810252BYI-03 REVISION A AUGUST 20, 2009 11 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 2.5V FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50Ω R4 120 Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK HCSL *R4 33 R1 50 R2 50 nCLK HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional – R3 and R4 can be 0Ω FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER ICS810252BYI-03 REVISION A AUGUST 20, 2009 12 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER VFQFN EPAD THERMAL RELEASE PATH are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE SOLDER LAND PATTERN THERMAL VIA PIN PIN PAD (GROUND PAD) FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) ICS810252BYI-03 REVISION A AUGUST 20, 2009 13 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TQFP EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) SOLDER PIN PIN PAD EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER SOLDER PIN LAND PATTERN (GROUND PAD) PIN PAD FIGURE 5. ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) ICS810252BYI-03 REVISION A AUGUST 20, 2009 14 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER LAYOUT GUIDELINE Figure 6 shows an example of the 810252IB-03 application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. An optional 3-pole filter can also be used for additional spur reduction. It is recommended that the loop filter components be laid out for the 3-pole option. This will also allow the 2-pole filter to be used. VDD R11 125 R13 125 CLK1 Zo = 50 nCLK1 Zo = 50 R12 84 LVPECL Driv er R14 84 VDD R7 125 VDD = VDDX = VDDO_QA = VDDO_QB = 3.3V R9 125 CLK0 Zo = 50 C28 and C29 are used for additional capacitance to center VCXO tuning curve. For most layouts, it is recommended to add an additional 3pf. For boards with high parasitics, C28 and 29 might not be required. nCLK0 Zo = 50 R8 84 XTAL_OUT R10 85 LVPECL Driv er C28 3pf 25MHz, CL =10pf XTAL_IN VDD C29 3pf R26 CLK0 nCLK0 VDD 10 VDDX 2-pole loop filter example Rs 221k LF1 LF0 GND CLK_SEL VDD Cp 0.001uF Cs 0.1uF C12 0.1u 1 2 3 4 5 6 7 8 LF1 LF0 ISET GND CLK_SEL VDD nc GND R20 2.21K ICS810252Bi-03 35 Receiv er GND VDDO_QB QB GND VDDO_QA QA GND ODASEL_0 GND 24 23 22 21 20 19 18 17 GND R2 GND ODASEL_0 VDDO_QB 820k Rs 200k Cs 1.0uF VDD Cp 0.01uF C17 0.1u ODBSEL_1 ODBSEL_0 ODASEL_1 LF1 PDSEL_2 PDSEL_1 PDSEL_0 R3 C3 220pF R25 VDDA Zo = 50 35 Receiv er 3-pole loop filter example - (optional) LF0 Zo = 50 VDDO_QA PDSEL_2 PDSEL_1 PDSEL_0 VDD VDDA ODBSEL_1 ODBSEL_0 ODASEL_1 LF1 LF0 LF1 R1 VDDO_QB VDDX XTAL_IN XTAL_OUT CLK0 nCLK0 VDD CLK1 nCLK1 U1 LF0 0.1u 32 31 30 29 28 27 26 25 C46 10u 9 10 11 12 13 14 15 16 C47 0.01u C15 VDDO_QA C18 0.1u 10 VDD C14 0.1u C30 0.01u C45 10u FIGURE 6. SCHEMATIC OF RECOMMENDED LAYOUT ICS810252BYI-03 REVISION A AUGUST 20, 2009 15 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER VCXO-PLL EXTERNAL COMPONENTS the crystal specification. In either case, the absolute tuning range is reduced. The correct value of CL is dependant on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (CL). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The frequency of oscillation in the third overtone mode is not necessarily at exactly three times the fundamental frequency. The mechanical properties of the quartz element dictate the position of the overtones relative to the fundamental. The oscillator circuit may excite both the fundamental and overtone modes simultaneously. This will LF0 cause a nonlinearity in the LF1 tuning curve. This potential ISET problem is the reason VCXO RS RSET crystals are required to be CP CS tested for absence of any activity inside a ±200ppm window at three times the XTAL_IN fundamental frequency. Refer to CTUNE FL_30VT and FL_30VT_SPURS in the Crystal 25MHz Characterization Table. The crystal’s load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). If the crystal CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal CL is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than XTAL_OUT CTUNE The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. VCXO CHARACTERISTICS TABLE Symbol Parameter Typical Unit kVCXO VCXO Gain 8000 Hz/V CV_LOW Low Varactor Capacitance 8 pF CV_HIGH High Varactor Capacitance 17 pF VCXO-PLL LOOP BANDWIDTH SELECTION TABLE Bandwidth Crystal Frequency (MHz) RS (kΩ ) CS (µF) CP (µF) RSET (kΩ ) 10Hz (Low) 25MHz 120 1.0 0.01 8.8 50Hz (Mid) 25MHz 221 0.1 0.001 2.21 125Hz (High) 25MHz 620 0.022 0.0004 2.21 CRYSTAL CHARACTERISTICS Symbol Parameter Minimum Mode of Operation fN Typical Maximum Units Fundamental Frequency 25 MHz fT Frequency Tolerance ±20 ppm fS Frequency Stability ±20 ppm CL Load Capacitance Operating Temperature Range -40 85 10 CO Shunt Capacitance CO /C1 Pullability Ratio FL_30VT 3rd Over tone FL 200 FL_30VT_SPURS 3rd Over tone FL Spurs 200 ESR Equivalent Series Resistance 4 pF 220 240 40 Drive Level Aging @ 25°C ICS810252BYI-03 REVISION A AUGUST 20, 2009 °C pF 16 Ω 1 mW ±3 per year ppm ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS810252BI-03. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS810252BI-03 is the sum of the core power plus the analog plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core Power Dissipation • Power (core)MAX = VDD_MAX * ((IDD + IDDX) + IDDA) = 3.465V * (190mA + 13mA) = 703.4mW Output Power Dissipation • Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 17Ω)] = 25.9mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 17Ω * (25.9mA)2 = 11.4mW per output • Total Power Dissipation on the ROUT Total Power (ROUT) = 11.4mW * 2 = 22.8mW Dynamic Power Dissipation at 125MHz Power (125MHz) = CPD * Frequency * (VDDO)2 = 10pF * 125MHz * (3.465V)2 = 15mW per output Total Dynamic Power (125MHz) = 15mW * 2 = 30mW Total Power Dissipation • Total Power = Power (core)MAX + Total Power (ROUT) + Total Dynamic Power (125MHz) = 703.4mW + 22.8mW + 30mW = 756.2mW 2. Junction Temperature. Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.756W * 37°C/W = 113°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of terminated outputs, supply voltage, air flow, and the6A. number of board layers. θ FOR 32 LEAD VFQFN, FORCED CONVECTION TABLE THERMAL RESISTANCE JA θJA vs. 0 Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards TABLE 6B. θJA VS. AIR FLOW TABLE FOR 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W 32 LEAD TQFP, E-PAD θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards ICS810252BYI-03 REVISION A AUGUST 20, 2009 17 0 1 2.5 32.2°C/W 26.3°C/W 24.7°C/W ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER 3. Case Temperature calculated from Junction Temperature θJC Calculations In applications where there is a heatsink present, and the majority of the power is dissipated through the top of the device, the junction temperature can be calculated from the case temperature, TC, using the junction-to-case thermal resistance value θJC. In practical application is it the average of the case temperature of the surface of the device on which the heatsink is attached. The equation for calculating the junction temperature is as follows: Tj = θJC * Pd_case + TC Tj = Junction Temperature θJC= Junction-to-Case Thermal Resistance Pd_case = Total Device Power Dissipation through the case TC = Average Case Temperature It is important to emphasize that case temperature calculations using θJC do not use Pd_total, rather they use Pd_case, which is the portion of power dissipated through the case. In real applications it is difficult to quantify the power dissipated through the case, so the value of θJC is best used for a package-to-package comparison, rather than a junction temperature calculation. As such, the JEDEC standard (JESD51-2) uses another parameter, ψJT (PsiJT), which can be used to calculate junction temperature from a measured case temperature. ψJT Calculations ψJT is the thermal characterization parameter which reports the differences between junction temperature and the temperature at the top dead center of the outside surface of the component package, divided by the power applied to the component. This requires knowing the total power dissipation and a measured case temperature in order to calculate the junction temperature. It can also be calculated using an estimated case temperature for a given junction temperature. In the following equation, TT, is used to indicate the single-point temperature measurement at the top-center of the case. The change in the naming convention from TC to TT is to differentiate the use between the θJC and ψJT calculations. The equation for TJ is as follows: Solving for TT yields: TJ = TT + ψJT * Pd_total TT = TJ - ψJT * Pd_total TJ = Junction Temperature ψJT = (PsiJT) Junction-to-Top of Package Parameter Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TT = Temperature at the top-center of the package The advantage of this method is that it allows for the calculation of the junction temperature or case temperature using total power dissipation and eliminates the need to quantify power dissipation through the top of the device. In order to calculate TT, the appropriate ψJT factor must be used. Assuming no air flow, a multi-layer board, and E-Pad soldered to the board, the appropriate value is 0.3°C/W per Table 7 below. Therefore, TT for a TJ value of 113°C (from the example in section 2) with all outputs switching is: TT = 113.0°C – 0.756W * 0.3°C/W = 112.8°C. This calculation is only an example. TJ will vary depending on the number of terminated outputs, supply voltage, air flow and the number of board layers. Table 7. ψJT for 32 Lead VFQFN, Forced Convection ψJT by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards ICS810252BYI-03 REVISION A AUGUST 20, 2009 18 0.3°C/W ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER RELIABILITY INFORMATION TABLE 8A. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN θJA vs. 0 Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards TABLE 8B. θJAVS. AIR FLOW TABLE FOR 0 1 2.5 37.0°C/W 32.4°C/W 29.0°C/W 32 LEAD TQFP, E-PAD θ by Velocity (Meters per Second) JA Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 32.2°C/W 26.3°C/W 24.7°C/W TRANSISTOR COUNT The transistor count for ICS810252BI-03 is: 6597 ICS810252BYI-03 REVISION A AUGUST 20, 2009 19 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP, E-PAD -HD VERSION EXPOSED PAD DOWN TABLE 9A. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS ABA-HD SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.20 A1 0.05 0.10 0.15 A2 0.95 1.0 1.05 b 0.30 0.35 0.40 c 0.09 -- 0.20 D, E 9.00 BASIC D1, E1 7.00 BASIC D2, E2 5.60 Ref. 0.80 BASIC e L 0.45 θ 0° 0.75 -- 7° ccc -- -- 0.10 D3 & D3 3.0 3.5 4.0 Reference Document: JEDEC Publication 95, MS-026 ICS810252BYI-03 REVISION A AUGUST 20, 2009 20 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area L A3 N N e (Ty p.) 2 If N & N 1 Anvil Singula tion are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D e N &N Odd 0. 08 Chamfer 4x 0.6 x 0.6 max OPTIONAL C D2 2 Th er mal Ba se D2 C NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9B below. TABLE 9B. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A 0.80 -- 1.00 A1 0 -- 0.05 0.25 Ref. A3 b 0.18 0.25 8 NE 5.00 BASIC D D2 3.0 3.15 3.0 3.15 3.3 0.50 BASIC e L 3.3 5.00 BASIC E E2 0.30 8 ND 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS810252BYI-03 REVISION A AUGUST 20, 2009 21 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 810252BKI-03LF ICS252BI03L 32 Lead "Lead-Free" VFQFN tray -40°C to 85°C 810252BKI-03LFT ICS252BI03L 32 Lead "Lead-Free" VFQFN 2500 tape & reel -40°C to 85°C 810252BYI-03LF ICS0252BI03L 32 lead "Lead-Free" TQFP, E-Pad tray -40°C to 85°C 810252BYI-03LFT ICS0252BI03L 32 lead "Lead-Free" TQFP, E-Pad 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS810252BYI-03 REVISION A AUGUST 20, 2009 22 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER REVISION HISTORY SHEET Rev Table Page 16 T9B 21 A Description of Change VCXO-PLL External Components - replace 2nd to last paragraph. Cr ystal Characteristics Table - add 3rd Over tone specs. VFQFN Package Dimensions - corrected D2/E2 dimensions. ICS810252BYI-03 REVISION A AUGUST 20, 2009 23 Date 8/20/09 ©2009 Integrated Device Technology, Inc. ICS810252BI-03 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER www.IDT.com 6024 Silver Creek Valley Road San Jose, CA 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Techical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitablity of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Techology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.