CED71A3/CEU71A3 Dec. 2002 N-Channel Logic Level Enhancement Mode Field Effect Transistor FEATURES 30V , 65A , RDS(ON)=10m Ω @VGS=10V. RDS(ON)=14m Ω @VGS=5.0V. Super high dense cell design for extremely low RDS(ON). D 6 High power and current handling capability. TO-252 & TO-251 package. G D G S CEU SERIES TO-252AA(D-PAK) G D S S CED SERIES TO-251(l-PAK) ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted) Symbol Limit Unit Drain-Source Voltage VDS 30 V Gate-Source Voltage VGS Ć20 V ID 65 A -Pulsed IDM 100 A Drain-Source Diode Forward Current IS 65 A Maximum Power Dissipation @Tc=25 C Derate above 25 C PD 69 0.56 W W/ C TJ, TSTG -55 to 150 C Thermal Resistance, Junction-to-Case RįJC 1.8 C/W Thermal Resistance, Junction-to-Ambient RįJA 40 C/W Parameter Drain Current-Continuous Operating and Storage Temperature Range THERMAL CHARACTERISTICS 6-67 CED71A3/CEU71A3 ELECTRICAL CHARACTERISTICS (TC=25 C unless otherwise noted) Parameter Symbol Condition Drain-Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA Zero Gate Voltage Drain Current IDSS VDS = 30V, VGS = 0V Gate-Body Leakage IGSS VGS =Ć20V, VDS = 0V Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250µA Drain-Source On-State Resistance RDS(ON) Min Typ Max Unit OFF CHARACTERISTICS 6 30 V 1 µA Ć100 nA ON CHARACTERISTICS a ID(ON) gFS On-State Drain Current Forward Transconductance 1 3 V VGS = 10V, ID = 15A 8.5 10 mΩ VGS = 5.0V, ID = 13A 11.5 14 mΩ VGS = 10V, VDS = 5V VDS = 5V, ID = 12A A 65 26 S 2152 PF 965 PF 234 PF b DYNAMIC CHARACTERISTICS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS =15V, VGS = 0V f =1.0MHZ b SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time Turn-Off Delay Time tD(ON) tr tD(OFF) VDD = 15V, ID =1A, VGS = 10V, RGEN =6Ω 30 60 ns 63 110 ns 73 130 ns Fall Time tf 59 100 ns Total Gate Charge Qg 55 67 nC Gate-Source Charge Qgs Gate-Drain Charge Qgd VDS =10V, ID = 15A, VGS =10V 6-68 9 nC 18 nC CED71A3/CEU71A3 ELECTRICAL CHARACTERISTICS (TC=25 C unless otherwise noted) Parameter Min Typ Max Unit Condition Symbol DRAIN-SOURCE DIODE CHARACTERISTICS a Diode Forward Voltage VGS = 0V, Is = 2.3A VSD 0.9 1.3 6 Notes a.Pulse Test:Pulse Width ś 300ijs, Duty Cycle ś 2%. b.Guaranteed by design, not subject to production testing. 60 60 VGS=10,8,6,4V 50 ID, Drain Current (A) ID, Drain Current (A) 50 40 30 VGS=3V 20 10 0 2 1 4 3 30 -55 C 20 25 C 10 Tj=125 C 1 5 2 3 4 VDS, Drain-to-Source Voltage (V) VGS, Gate-to-Source Voltage (V) Figure 1. Output Characteristics Figure 2. Transfer Characteristics 1.80 RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) 3000 2500 C, Capacitance (pF) 40 0 0 Ciss 2000 1500 Coss 1000 500 Crss 0 0 5 10 15 20 25 V 30 VDS, Drain-to Source Voltage (V) 1.60 ID=15A VGS=10V 1.40 1.20 1.00 0.80 0.60 -50 -25 0 25 50 75 100 125 150 TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature Figure 3. Capacitance 6-69 BVDSS, Normalized Drain-Source Breakdown Voltage 1.30 VDS=VGS ID=250ijA 1.20 1.10 1.00 0.90 0.80 0.70 0.60 -50 -25 0 25 50 75 100 125 150 1.15 ID=250ijA 1.10 1.05 1.00 0.95 0.90 0.85 -50 -25 Figure 5. Gate Threshold Variation with Temperature 25 50 75 100 125 150 Figure 6. Breakdown Voltage Variation with Temperature 50 50 40 Is, Source-drain current (A) gFS, Transconductance (S) 0 Tj, Junction Temperature ( C) Tj, Junction Temperature ( C) 30 20 10 VDS=5V 10 1.0 0.1 0 0 10 20 30 0.4 40 IDS, Drain-Source Current (A) 10 1.4 2 ID, Drain Current (A) Qg, Total Gate Charge (nC) s -1 10 10 60 s 45 0m C 30 1s 10 0 -2 0 s m RD O S( it 10 1 im D 2 10 1m L N) 10 4 15 1.2 1.0 10 6 0 0.8 Figure 8. Body Diode Forward Voltage Variation with Source Current VDS=15V ID=15A 8 0.6 VSD, Body Diode Forward Voltage (V) Figure 7. Transconductance Variation with Drain Current VGS, Gate to Source Voltage (V) 6 Vth, Normalized Gate-Source Threshold Voltage CED71A3/CEU71A3 TA=25 C RįJA=40 C/W Single Pulse 10 -2 10 -1 10 0 10 1 VDS, Drain-Source Voltage (V) Figure 10. Maximum Safe Operating Area Figure 9. Gate Charge 6-70 10 2 CED71A3/CEU71A3 4 VDD t on RL V IN D td(off) tf 90% 90% VOUT VOUT VGS RGEN toff tr td(on) 10% INVERTED 10% 6 G 90% S VIN 50% 50% 10% PULSE WIDTH Figure 12. Switching Waveforms Figure 11. Switching Test Circuit 0 r(t),Normalized Effective Transient Thermal Impedance 10 D=0.5 0.2 10 -1 0.1 0.05 PDM 0.02 10 t1 -2 t2 0.01 1. RįJA (t)=r (t) * RįJA 2. RįJA=See Datasheet 3. TJM-TA = P* RįJA (t) 4. Duty Cycle, D=t1/t2 Single Pulse 10 -3 10 -4 10 -3 10 -2 10 -1 10 0 10 1 Square Wave Pulse Duration (sec) Figure 13. Normalized Thermal Transient Impedance Curve 6-71 10 2