CLARE M-8880

M-8880 DTMF Transceiver
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Advanced CMOS technology for low power consumption and increased noise immunity
Complete DTMF transmitter/receiver in a single chip
Standard 6500/6800 series microprocessor port
Central office quality and performance
Adjustable guard time
Automatic tone burst mode
Call progress mode
Single +5 Volt power supply
20-pin DIP and SOIC packages
2 MHz microprocessor port operation
Inexpensive 3.58 MHz crystal
No continuous f2 clock required, only strobe
Figure 1 Pin Diagram
Applications include: paging systems, repeater systems/mobile radio, interconnect dialers, PBX systems,
computer systems, fax machines, pay telephones,
credit card verification
The M-8880 is a complete DTMF Transmitter/Receiver that features adjustable guard time, automatic tone burst mode, call
progress mode, and a fully compatible 6500/6800 microprocessor interface. The receiver portion is based on the industry standard M-8870 DTMF Receiver, while the transmitter uses a
switched-capacitor digital-to-analog converter for
low-distortion, highly accurate DTMF signaling. Tone bursts can
be transmitted with precise timing by making use of the automatic tone burst mode. To analyze call progress tones, a call
progress filter can be selected by an external microprocessor.
Functional Description
M-8880 functions consist of a high-performance DTMF receiver
with an internal gain setting amplifier and a DTMF generator that
contains a tone burst counter for generating precise tone bursts
and pauses. The call progress mode, when selected, allows the
detection of call progress tones. A standard 6500/6800 series
microprocessor interface allows access to an internal status
register, two control registers, and two data registers.
Input Configuration
The input arrangement consists of a differential input operational amplifier and bias sources (VREF) for biasing the amplifier
inputs at VDD/2. Provisions are made for the connection of a
feedback resistor to the op-amp output (GS) for gain adjust-
Figure 2 Block Diagram
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M-8880
Figure 3 Single-Ended Input Configuration
Figure 4 Differential Input Configuration
ment. In a single-ended configuration, the input pins should be
connected as shown in Figure 3. Figure 4 shows the necessary
connections for a differential input configuration.
A decoder employs digital counting techniques to determine the
frequencies of the incoming tones, and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals
(such as voice), while tolerating small deviations in frequency.
The algorithm provides an optimum combination of immunity to
talkoff with tolerance to interfering frequencies (third tones) and
noise. When the detector recognizes the presence of two valid
tones (referred to as “signal condition”), the early steering (ESt)
output goes to an active state. Any subsequent loss of signal
condition will cause ESt to assume an inactive state.
Receiver Section
The low and high group tones are separated by applying the
DTMF signal to the inputs of two sixth-order switched capacitor
bandpass filters with bandwidths that correspond to the low and
high group frequencies listed in Table 2. The low group filter incorporates notches at 350 and 440 Hz, providing excellent dial
tone rejection. Each filter output is followed by a single-order
switched capacitor filter that smooths the signals prior to limiting.
Limiting is performed by high-gain comparators with hysteresis
to prevent detection of unwanted low-level signals. The comparator outputs provide full-rail logic swings at the incoming
DTMF signal frequencies.
Steering Circuit: Before a decoded tone pair is registered, the
receiver checks for a valid signal duration (referred to as “character recognition condition”). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
Table 1 Pin Functions
Name
IN+
INGS
VREF
VSS
OSC1
OSC2
TONE
R/W
CS
RS0
φ2
IRQ/CP
D0 - D3
ESt
St/GT
VDD
Description
Noninverting op-amp input.
Inverting op-amp input.
Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor.
Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail.
Negative power supply input.
DTMF clock/oscillator input.
Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit.
Dual tone multifrequency (DTMF) output.
Read/write input. Controls the direction of data transfer to and from the microprocessor and the receiver/transmitter. TTL
compatible.
Chip select. TTL input (CS = 0 to select the chip).
Register select input. See Table 6. TTL compatible.
System clock input. May be continuous or strobed only during read or write. TTL compatible.
Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and interrupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Figure 11
Microprocessor data bus. TTL compatible.
Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any
momentary loss of signal condition will cause ESt to return to a logic low.
Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the
detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The
GT output acts to reset the external steering time-constant; its state is a funciton of ESt and the voltage on St.
Positive power supply input.
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M-8880
causes VC (see Figure 5) to rise as the capacitor discharges.
Provided that the signal condition is maintained (ESt remains
high) for the validation period (tGTP), VC reaches the threshold
(VTSt) of the steering logic to register the tone pair, latching its
corresponding 4-bit code (see Table 2) into the receive data register.
The steering circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause.
This capability, together with the ability to select the steering
time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.
Table 2 Tone Encoding/Decoding
Guard Time Adjustment: The simple steering circuit shown in
Figure 5 is adequate for most applications. Component values
are chosen according to the formula:
FLOW
FHIGH
Digit
D3
D2
D1
D0
697
697
697
770
770
770
852
852
852
941
941
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
*
941
1477
#
697
1633
A
770
1633
B
852
1633
C
941
1633
D
0 = logic low, 1 = logic high
tREC = tDP + tGTP
TID = tDA + tGTA
The value of tDP is a device parameter and tREC is the minimum
signal duration to be recognized by the receiver. A value for C1
of 0.1 µF is recommended for most applications, leaving R1 to
be selected by the designer. Different steering arrangements
may be used to select independently the guard times for tone
present (tGTP) and tone absent (tGTA). This may be necessary to
meet system specifications that place both accept and reject
limits on both tone duration and interdigit pause. Guard time adjustment also allows the designer to tailor system parameters
such as talkoff and noise immunity. Increasing tREC improves
talkoff performance since it reduces the probability that tones
simulated by speech will maintain signal condition long enough
to be registered. Alternatively, a relatively short tREC with a long
tDO would be appropriate for extremely noisy environments
where fast acquisition time and immunity to tone dropouts are
required. Design information for guard time adjustment is shown
in Figure 6.
At this point the StGT output is activated and drives VC to VDD.
StGT continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to settle, the
delayed steering output flag goes high, signaling that a received
tone pair has been registered. It is possible to monitor the status
of the delayed steering flag by checking the appropriate bit in the
status register. If interrupt mode has been selected, the IRQ/CP
pin will pull low when the delayed steering flag is active.
Figure 6 Guard Time Adjustment
Figure 5 Basic Steering Circuit
The contents of the output latch are updated on an active delayed steering transition. This data is presented to the 4-bit
bidirectional data bus when the receive data register is read.
Call Progress Filter
A call progress (CP) mode can be selected, allowing the detection of various tones that identify the progress of a telephone call
on the network. The call progress tone input and DTMF input are
common; however, call progress tones can only be detected
when the CP mode has been selected. DTMF signals cannot be
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M-8880
detected if the CP mode has been selected (see Table 3). Figure 7 indicates the useful detect bandwidth of the call progress
filter. Frequencies presented to the input (IN+ and IN-) that are
within the “accept” bandwidth limits of the filter are hard-limited
by a high-gain comparator with the IRQ /CP pin serving as the
output. The square wave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being
detected. Frequencies in the “reject” area will not be detected,
and consequently there will be no activity on IRQ /CP as a result
of these frequencies.
accuracy. When there is no tone output signal, the TONE pin
assumes a DC level of 2.5 volts (typically). A bandwidth limiting
filter is incorporated to attenuate distortion products above 4
KHz.
Burst Mode: Certain telephony applications require that generated DTMF signals be of a specific duration, determined either
by the application or by any of the existing exchange transmitter
specifications. Standard DTMF signal timing can be accomplished by making use of the burst mode. The transmitter is capable of issuing symmetric bursts/pauses of predetermined
duration. This burst/pause duration is 51 ms ± 1 ms, a standard
interval for autodialer and central office applications. After the
burst/pause has been issued, the appropriate bit is set in the status register, indicating that the transmitter is ready for more data.
The timing described is available when the DTMF mode has
been selected. However, when call progress (CP) mode is selected, a secondary burst/pause time is available that extends
this interval to 102 ms ± 2 ms. The extended interval is useful
when precise tone bursts of longer than 51 ms duration and 51
ms pause are desired. Note that when CP mode and burst mode
have been selected, DTMF tones may be transmitted only and
not received. In applications requiring a nonstandard
burst/pause time, use a software timing loop or external timer.
This provides the timing pulses when the burst mode is disabled
by enabling and disabling the transmitter.
Figure 7 Call Progress Response
The M-8880 is initialized on powerup sequence with DTMF
mode and burst mode selected.
DTMF Generator
The DTMF transmitter used in the M-8880 is capable of generating all 16 standard DTMF tone pairs with low distortion and high
accuracy. All frequencies are derived from an external 3.58
MHz crystal. The sinusoidal waveforms for the individual tones
are digitally synthesized using row and column programmable
dividers and switched capacitor digital-to-analog converters.
The row and column tones are mixed and filtered, providing a
DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format shown in Table 2 must be written to the transmit data
register. Note that this is the same as the receiver output code.
The individual tones that are generated (fLOW and fHIGH) are referred to as low-group and high-group tones. Typically, the
high-group to low-group amplitude ratio (twist) is 2 dB to compensate for high-group attenuation on long loops.
Operation: During write operations to the transmit data register,
4-bit data on the bus is latched and converted to a 2 of 8 code for
use by the programmable divider circuitry to specify a time segment length that will ultimately determine the tone frequency.
The number of time segments is fixed at 32, but the frequency is
varied by varying the segment length. When the divider reaches
the appropriate count as determined by the input code, a reset
pulse is issued and the counter starts again. The divider output
clocks another counter that addresses the sinewave lookup
ROM. The lookup table contains codes used by the switched
capacitor D/A converter to obtain discrete and highly accurate
DC voltage levels. Two identical circuits are used to produce
row and column tones, which are then mixed using a low-noise
summing amplifier. The oscillator described needs no “startup”
time as in other DTMF generators, since the crystal oscillator is
running continuously, thus providing a high degree of tone burst
Single-Tone Generation: A single-tone mode is available
whereby individual tones from the low group or high group can
be generated. This mode can be used for DTMF test equipment
applications, acknowledgment tone generation, and distortion
measurements. Refer to Table 4 for details.
Distortion Calculations: The M-8880 is capable of producing
precise tone bursts with minimal error in frequency (see Table
3). The internal summing amplifier is followed by a first-order
low-pass switched capacitor filter to minimize harmonic components and intermodulation products. The total harmonic distortion for a single tone can be calculated using Equation 1, (see
Figure 9) which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage. The Fourier components of the tone
output correspond to V2f... Vnf as measured on the output
waveform. The total harmonic distortion for a dual tone can be
calculated using Equation 2 (see Figure 9).
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Table 3 Actual Frequencies vs. Standard
Requirements
Active
Cell
L1
L2
L3
L4
H1
H2
H3
H4
Output Frequency (Hz)
Specified
Actual
697
770
852
941
1209
1336
1447
1633
699.1
766.2
847.4
948.0
1215.9
1331.7
1471.9
1645.0
% Error
+ 0.30
- 0.49
- 0.54
+ 0.74
+ 0.57
- 0.32
- 0.35
+ 0.73
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M-8880
Table 4 Control Register A Description
Bit
Name
Function
b0
TOUT
Tone output
b1
CP/DTMF
b2
IRQ
b3
RSET
Description
A logic 1 enables the tone output. This function can be implemented in either the burst mode or
nonburst mode.
Mode control In DTMF mode (logic 0), the device is capable of generating and receiving DTMF signals. When
the call progress (CP) mode is selected (logic 1), a 6th-order bandpass filter is enabled to allow
call progress tones to be detected. Call progress tones within the specified bandwidth will be presented at the IRQ/CP pin in rectangular wave format if the IRQ bit has been enabled (b2 =1). Also,
when the CP mode and burst mode have both been selected, the transmitter will issue DTMF signals with a burst and pause of 102 ms (typ) duration. This signal duration is twice that obtained
from the DTMF transmitter, if DTMF mode had been selected. Note that DTMF signals cannot be
decoded when the CP mode has been selected.
Interrupt enable A logic 1 enables the interrupt mode. When this mode is active and the DTMF mode has been selected (b1 = 0), the IRQ/CP pin will pull to a logic 0 condition when either (1) a valid DTMF signal
has been received and has been present for the guard time or (2) the transmitter is ready for more
data (burst mode only).
Register select A logic 1 selects control register B on the next write cycle to the control register address. Subsequent write cycles to the control register are directed back to control register A.
Table 5 Control Register B Description
Bit
Name
Function
b0
BURST
Burst mode
b1
TEST
b2
S/D
b3
C/R
Description
A logic 0 enables the burst mode. When this mode is selected, data corresponding to the desired
DTMF tone pair can be written to the transmit data register, resulting in a tone burst of a specific
duration (see Table 12). Subsequently, a pause of the same duration is induced. Immediately following the pause, the status register is updated indicating that the transmit data register is ready
for further instructions, and an interrupt will be generated if the interrupt mode has been enabled.
Additionally, if call progress (CP) mode has been enabled, the burst and pause duration is increed
by a factor of two. When the burst mode is not selected (logic 1), tone bursts of any desired duration may be generated.
Test mode
By enabling the test mode (logic 1), the IRQ/CP pin will present the delayed steering (inverted)
signal from the DTMF receiver. Refer to Figure 11 (b3 waveform) for details concerning the output
waveform. DTMF mode must be selected (CRA b1 = 0) before test mode can be implemented.
Single/dual tone A logic 0 will allow DTMF signals to be produced. If single-tone generation is enabled (logic 1), eigeneration
ther now or column tones (low or high group) can be generated depending on the state of b3 in
control register B.
Column/row
When used in conjunction with b2 (above), the transmitter can be made to generate single-row or
tones
single-column frequencies. A logic0 will select row frequencies and a logic 1 will select column frequencies.
VL and VH correspond to the low-group and high-group amplitude, respectively, and V2IMD is the sum of all the intermodulation
components. The internal switched capacitor filter following the
D/A converter keeps distortion products down to a very low
level.
DTMF Clock Circuit
The internal clock circuit is completed with the addition of a standard 3.579545 MHz television color burst crystal. A number of
M-8880 devices can be connected as shown in Figure 8 using
only one crystal.
Microprocessor Interface
The M-8880 uses a microprocessor interface that allows precise control of transmitter and receiver functions. Five internal
registers are associated with the microprocessor interface,
which can be subdivided into three categories: data transfer,
transceiver control, and transceiver status. Two registers are
associated with data transfer operations. The receive data,
read-only, contains the output code of the last valid DTMF tone
pair to be decoded. The data entered in the transmit data register determines which tone pair is to be generated (see Table 2).
Figure 8 Common Crystal Connection
Data can only be written to the transmit data register. Transceiver control is accomplished with two control registers (CRA
and CRB), occupying the same address space. A write operation to CRB can be executed by setting the appropriate bit in
CRA. The following write operation to the same address will
then be directed to CRB, and subsequent write cycles will then
be redirected to CRA. Internal reset circuitry clears the control
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M-8880
registers on powerup; however, as a precautionary measure the
initialization software should include a routine to clear the registers. Refer to Tables 3 and 4 for details on the control registers.
The IRQ/CP pin can be programmed to provide an interrupt request signal on validation of DTMF signals, or when the transmitter is ready for more data (burst mode only). The IRQ/CP pin
is configured as an open-drain output device and as such requires a pullup resistor (see Figure 10).
Ordering Information
M-888001P
20-pin plastic DIP
M-8880-01SM
20-pin plastic SOIC
M-8880-01T
20-pin plastic SOIC,Tape and Reel
Figure 9 Equations
Table 7 CRA Bit Postions
Table 6 Internal Register Functions
RS0
R/W
Function
0
0
1
1
0
1
0
1
Write to transmitter
Read from receiver
Write to control register
Read from status register
b3
b2
b1
b0
RSEL
IRQ
CP/DTMF
TOUT
Table 8 CRB Bit Positions
b3
b2
b1
b0
C/R
S/D
TEST
BURST
Figure 10 Application Circuit (Single-Ended Input)
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M-8880
Table 9 Status Register Description
BIT
b0
b1
b2
b3
Name
Status Flag Set
Status Flag Cleared
IRQ
Interrupt has occurred. Bi tone (b1) and/or bit 2 (b2)
is set.
Transmit data register
Pause duration has terminated and transmitter is
empty (burst mode only) ready for new data.
Receive data register
Valid data is in the receive data register.
full
Set on valid detection of the absence of a DTMF sigDelayed steering
nal.
Interrupt is inactive. Cleared after status register is
read.
Cleared after status register is read or when not in
burst mode.
Cleared after status register is read.
Cleared on detection of a valid DTMF signal.
Table 10 Absolute Maximum Ratings
Parameter
Symbol
Value
+ 6.0 V max
VDD
Power supply voltage (VDD - VSS)
Vdc
VSS -0.3 V to VDD + 0.3 V
Voltage on any pin
10 mA max
IDD
Current on any pin
TA
-40°C to +85°C
Operating temperature
TS
-65°C to +150°C
Storage temperature
Note: Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied.
Table 11 DC Characteristics
Symbol
Min
Typ*
Max
Units
Operating supply voltage
Operating supply current
Power consumption
Parameter
VDD
IDD
PO
4.75
—
—
5.0
10
50
5.25
15
78.75
V
mA
mW
Inputs
High-level input voltage, OSC1
Low-level input voltage, OSC1
Input impedance (@ 1 kHz), IN+, IN-
VIHO
VILO
RIN
3.5
—
—
—
—
10
—
1.5
—
V
V
Steering threshold voltage
VTSt
2.2
2.3
2.5
Outputs
High-level output voltage (no load), OSC2
Low-level output voltage (no load), OSC2
Output leakage current (VOH = 2.4V), IRQ
VOHO
VOLO
IOZ
VDD - 0.1V
—
—
—
—
1.0
—
0.1
10.0
VREF output voltage (no load)
VREF output resistance
VREF
ROR
2.4
—
—
2.7
1.0
kΩ
VIL
VIH
VOL
VOH
—
2.0
—
2.4
—
—
—
—
0.8
—
0.4
—
V
V
V
V
IIZ
—
—
10.0
µA
Data Bus
Low-level input voltage
High-level input voltage
Low-level output voltage (IOL = 1.6 mA)
High-level output voltage (IOH = 400 µA)
Input leakage current (VIN = 0.4 to 2.4 V)
MΩ
V
V
V
µA
V
All voltages referenced to VSS unless otherwise noted. VDD = 5.0 V ± 5%; fC = 3.579545 MHz; ΤA = -40°C to +85°C, unless otherwise
noted. *Typical values are for use as design aids only, and are not guaranteed or subject to production testing.
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M-8880
Table 12 AC Characteristics
PARAMETER
SYMBOL
MIN
TYP*
MAX
UNITS
-29
27.5
—
—
+1
869
dBm
mVRMS
6
dB
Receive signal conditions
Valid input signal levels
(each tone of composite signal; Notes 1, 2, 3, 5, 6, 9)
—
Positive twist accept (Notes 2, 3, 6, 9)
—
Negative twist accept (Notes 2, 3, 6, 9)
± 1.5% ± 2 Hz
Frequency deviation accept (Notes 2, 3, 5, 9)
6
dB
—
—
Nom.
± 3.5%
—
—
Nom.
Third tone tolerance (Notes 2, 3, 4, 5, 9, 10)
—
-16
—
dB
Noise tolerance (Notes 2, 3, 4, 5, 7, 9, 10)
—
-12
—
dB
Dial tone tolerance (Notes 2, 3, 4, 5, 8, 9, 11)
—
+22
—
dB
Frequency deviation reject (Notes 2, 3, 5)
Call progress
Lower frequency (@ -25 dBm) accept
fLA
—
320
—
Hz
Upper frequency (@ -25 dBm) accept
fHA
—
510
—
Hz
Lower frequency (@ -25 dBm) reject
fLR
—
290
—
Hz
Upper frequency (@ -25 dBm) reject
fHR
—
540
—
Hz
Receive timing
Tone present detect time
tDP
5
11
14
ms
Tone absent detect time
tDA
0.5
4
8.5
ms
Tone duration accept (ref. Figure 12)
tREC
—
—
40
ms
Tone duration reject (ref. Figure 12)
tREC
20
—
—
ms
Interdigit pause accept (ref. Figure 12)
tID
—
—
40
ms
Interdigit pause reject (ref. Figure 12)
tDO
20
—
—
ms
Delay St to b3
tPStb3
—
13
—
µs
Delay St to RXO—RX3
tPStRX
—
8
—
µs
Tone burst duration (DTMF mode)
tBST
50
—
52
ms
Tone pause duration (DTMF mode)
tPS
50
—
52
ms
Tone burst duration (extended, call progress mode)
tBSTE
100
—
104
ms
Tone pause duration (extended, call progress mode)
tPSE
100
—
104
ms
High group output level (RL = 10 kΩ)
VHOUT
-6.1
—
-2.1
dBm
Low group output level (RL = 10 kW)
VLOUT
-8.1
—
-4.1
dBm
Transmit timing
Tone output
Pre-emphasis (RL = 10 kW)
dBP
0
2
3
dB
Output distortion (RL = 10 kΩ, 3.4 kHz bandwidth)
THD
—
-25
—
dB
fD
—
± 0.7
± 1.5
%
RLT
10
—
50
kΩ
Frequency deviation (f = 3.5795 MHz)
Output load resistance
Microprocessor interface
φ 2 cycle period
tCYC
0.5
—
—
µs
φ2 high pulse width
tCH
200
—
—
ns
φ2 low pulse width
tCL
180
—
φ2 rise and fall time
t R, t F
—
—
25
ns
Address, R/W hold time
tAH, tRWH
10
—
—
ns
Address, R/W setup time (prior to φ2)
tAS, tRWS
23
—
—
ns
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ns
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M-8880
Table 12 AC Characteristics (continued)
Parameter
Symbol
Min
Typ*
Max
Units
Data hold time (read)
tDHR
22
—
—
ns
f2 to valid data delay (read) (200 pF load)
tDDR
—
—
150
ns
Data setup time (write)
tDSW
45
—
—
ns
Data hold time (write)
tDHW
10
—
—
ns
Microprocessor interface (continued)
Input capacitance, D0—D3
Output capacitance, IRQ/CP
CIN
—
5
—
pF
C/OUT
—
5
—
pF
fC
3.5759
3.5795
3.5831
MHz
tLHCL
—
—
110
ns
ns
DTMF clock
Crystal clock frequency
Clock input rise time (external clock)
Clock input fall time (external clock)
tHLCL
—
—
110
Clock input duty cycle (external clock)
DCCL
40
50
60
%
CLO
—
—
30
pF
Capacitive load, OSC2
All voltages referenced to unless otherwise noted. VDD = 5.0 V ± 5%; VSS = 0 V; fC = 3.579545 MHz; TA = -40°C to +85°C
*Typical values are for use as design aids only, and are not guaranteed or subject to production testing.
Notes:
1. dBm = decibels above or below a reference power of 1 mW into a 600 W load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40 ms. Tone pause = 40 ms.
4. Nominal DTMF frequencies are used.
5. Both tones in the composite signal have an equal amplitude.
6. The tone pair is deviated by ± 1.5% ± 2 Hz.
7. Bandwidth limited (3 kHz) Gaussian noise.
8. The precise dial tone frequencies are 350 and 440 Hz (± 2%).
9. For an error rate of less than 1 in 10,000.
10. Referenced to the lowest amplitude tone in the DTMF signal.
11. Referenced to the minimum valid accept level.
Table 13 Electrical Characteristics - Gain Setting Amplifier
Parameter
Input leakage current (VSS £ VIN £ VDD)
Input resistance
Input offset voltage
Power supply rejection (1 KHz)
Common mode rejection (-3.0 V £ VIN £ 3.0 V)
DC open-loop voltage gain
Unity gain bandwidth
Output voltage swing (RL ³ 100 KΩ to VSS)
Maximum capacitive load, GS
Maximum resistive load, GS
Common mode range (no load)
Symbol
Min
Typ*
Max
IIN
—
100
—
Units
nA
RIN
—
10
—
VOS
PSRR
CMRR
—
—
—
25
60
60
—
—
—
MΩ
mV
dB
dB
AVOL
BW
VO
—
—
—
65
1.5
4.5
—
—
—
dB
MHz
VPP
CL
RL
—
—
100
50
—
—
VCM
—
3.0
—
pF
KΩ
VPP
All voltages referenced to unless otherwise noted. VDD = 5.0 V; VSS = 0 V; TA = 25°C
*Typical values are for use as design aids only, and are not guaranteed or subject to production testing.
40-406-00012, Rev. G
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Page 9
M-8880
Figure 11 Timing Diagrams
Figure 12 Test Loads
40-406-00012, Rev. G
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Page 10
M-8880
Explanation of Events
(A) Tone bursts detected, tone duration invalid, RX Data Register not updated.
(B) Tone #n detected, tone duration valid, tone decoded and latched in RX Data Register.
(C) End of tone #n detected, tone absent duration valid, RX Data Register remain latched until next valid tone.
(D) Tone #n + 1 detected, tone duration valid, tone decoded and latched in RX Data Register.
(E) Acceptable dropout of tone #n + 1, tone absent duration invalid, RX Data Register remain latched.
(F) End of tone #n + 1 detected, tone absent duration valid, RX Data Register remain latched until next valid tone.
Explanation of Symbols
VIN
ESt
St/GT
RX0-RX3
b3
b2
IRQ/CP
tREC
tREC
tID
tDO
tDP
tDA
TGTP
tGTA
DTMF composite input signal.
Early steering output. Indicates detection of valid tone frequencies.
Steering input/guard time output. Drives external RC timing circuit.
4-bit decoded data in receive data register.
Delayed steering output. Indicates that valid frequencies have been present/absent for the
required guard time, thus constituting a valid DTMF signal.
Output enable (input). A low level shifts Q1 - Q4 to its high impedance state.
Interrupt is active indicating that new data is in the RX data register. The interrupt is cleared
after the status register is ready.
Maximum DTMF signal duration not detected as valid.
Minimum DTMF signal duration required for valid recognition.
Minimum time between valid DTMF signals.
Maximum allowable dropout during valid DTMF signal.
Time to detect the presence of valid DTMF signals.
Time to detect the absence of valid DTMF signals.
Guard time, tone present.
Guard time, tone absent.
Figure 13 Timing Diagrams
40-406-00012, Rev. G
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Page 11
M-8880
A
A1
b
b2
C
D
E
E1
e
ec
L
Tolerances
Inches
Metric (mm)
Min
Max
Min
Max
.210
5.33
.015
.38
.014
.022
.36
.56
.045
.070
1.14
1.78
.008
.014
.20
.36
.980
1.060
24.89
26.92
.300
.325
7.62
8.26
.240
.280
6.10
7.11
.100 BSC
2.54 BSC
15°
0°
15°
0°
.115
.150
2.92
3.81
A
A1
b
D
E
e
H
L
Tolerances
Inches
Min
Max
.093
.104
.004
.012
.013
.020
.496
.512
.291
.299
.050 BSC
.394
.419
.016
.050
Metric (mm)
Min
Max
2.35
2.65
.10
.30
.33
.51
12.60
13.00
7.39
7.59
1.27 BSC
10.00
10.65
.40
1.27
Figure 14 Package Dimensions
40-406-00012, Rev. G
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Page 12
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Clare cannot assume responsibility for use of any circuitry other then circuitry entirely embodied in this Clare product. No circuit patent licenses nor
indemnity are expressed or implied. Clare reserves the right to change the
specification and circuitry, without notice at an y time. The products described in this document are not intended for use in medical implantation
or other direct life support applications where malfunction may result in
direct physical harm, injury or death to a person.
Specification: 40-406-00012, Rev. G
© Copyright 2000, CP Clare Corporation d/b/a Clare
All rights reserved. Printed in USA.
07/28/00