MT8885AN1 - Microsemi

MT8885
Integrated DTMF Transceiver with Power
Down and Adaptive Micro Interface
Data Sheet
Features
September 2005
•
Central office quality DTMF transmitter/receiver
•
Single 5 Volt power supply
•
Adaptive micro interface enables compatibility
with Intel and Motorola processors
•
DTMF transmitter/receiver power-down via
register control or power-down pin
•
Adjustable guard time
•
Automatic tone burst mode
•
Call progress tone detection to -30 dBm
Ordering Information
MT8885AN
24 Pin SSOP
Tubes
MT8885AP
28 Pin PLCC
Tubes
MT8885AE
24 Pin PDIP
Tubes
MT8885AN1
24 Pin SSOP*
Tubes
MT8885AE1
24 Pin PDIP*
Tubes
MT8885ANR
24 Pin SSOP
Tape & Reel
MT8885ANR1
24 Pin SSOP*
Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
Description
The MT8885 is a monolithic DTMF transceiver with call
progress filter. It is fabricated in CMOS technology
offering low power consumption and high reliability.
Applications
•
Credit card systems
•
Paging systems
•
Repeater systems/mobile radio
•
Interconnect dialers
•
Pay phones
•
Remote monitor/Control systems
The receiver section is based upon the industry
standard MT8870 DTMF receiver. The transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones.
The MT8885 utilizes an adaptive micro interface, which
allows the device to be connected to a number of
popular microcontrollers with minimal external logic.
D/A
Converters
∑
TONE
Tone Burst
Gating Cct.
IN+
+
IN-
-
OSC2
Dial
Tone
Filter
High Group
Filter
Low Group
Filter
Oscillator
Circuit
Control
Logic
Bias
Circuit
VDD VRef
VSS
Transmit Data
Register
Status
Register
Control
Logic
GS
OSC1
Row and
Column
Counters
PWDN
Data
Bus
Buffer
D0
D1
D2
D3
Interrupt
Logic
IRQ/CP
Digital
Algorithm
and Code
Converter
Steering
Logic
ESt
Control
Register
A
Control
Register
B
DS/RD
I/O
Control
Receive Data
Register
St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1996-2005, Zarlink Semiconductor Inc. All Rights Reserved.
CS
R/W/WR
RS0
MT8885
Data Sheet
ESt
VDD
St/GT
ESt
D3
D2
D1
D0
NC
PWDN
IRQ/CP
DS/RD
RS0
4
3
2
1
28
27
26
24
23
22
21
20
19
18
17
16
15
14
13
•
NC
VRef
VSS
OSC1
OSC2
NC
NC
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
25
24
23
22
21
20
19
NC
D3
D2
D1
D0
NC
PWDN
TONE
R/W/WR
CS
RS0
NC
DS/RD
IRQ/CP
IN+
INGS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W/WR
CS
GS
NC
ININ+
VDD
The MT8885 provides enhanced power-down features. The transmitter and receiver may independently be
powered down via register control.
24 PIN DIP/SSOP
28 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
24
28
1
1
IN+
Non-inverting op-amp input.
2
2
IN-
Inverting op-amp input.
3
4
GS
Gain Select. Gives access to output of front end differential amplifier for connection
of feedback resistor.
4
6
VRef
Reference Voltage output (VDD/2).
5
7
VSS
Ground (0 V).
6
8
OSC1
Oscillator input. This pin can also be driven directly by an external clock.
7
9
OSC2
Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
10
12
TONE
Output from internal DTMF transmitter.
11
13
12
14
CS
Chip Select input must be gated externally by either address strobe (AS), valid
memory address (VMA) or address latch enable (ALE) signal, depending on
processor used. See Figure 12. Must not be tied low. CMOS compatible.
13
15
RS0
Register Select input. Refer to Table 3 for bit interpretation. CMOS compatible.
14
17
DS (RD)
R/W(WR) (Motorola) Read/Write or (Intel) Write microprocessor input. CMOS compatible.
(Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is
only required when the device is being accessed. CMOS compatible.
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Zarlink Semiconductor Inc.
MT8885
Data Sheet
Pin Description
Pin #
Name
Description
18
IRQ/CP
Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output
goes low when a valid DTMF tone burst has been transmitted or received. In call
progress mode, this pin will output a rectangular signal representative of the input
signal applied at the input op-amp. The input signal must be within the bandwidth
limits of the call progress filter, see Figure 8.
16
19
PWDN
Power-Down (input). Active High. Powers down the device and inhibits the oscillator.
IRQ and TONE output are high impedance. Data bus is held in tri-state. This pin has
no internal pulldown resistor. Therefore, must be tied to logic low when not used.
18-21
21-24
D0-D3
Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD =
1 (Intel). TTL compatible.
22
26
ESt
Early Steering output. Presents a logic high once the digital algorithm has detected
a valid tone pair (signal condition). Any momentary loss of signal condition will cause
ESt to return to a logic low.
23
27
St/GT
Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt
detected at St causes the device to register the detected tone pair and update the
output latch. A voltage less than VTSt frees the device to accept a new tone pair. The
GT output acts to reset the external steering time-constant; its state is a function of
ESt and the voltage on St.
24
28
VDD
Positive power supply (5 V typ.).
3, 5,
10,11
16, 20,
25
NC
No Connection.
24
28
15
8, 9
17
1.0
Functional Description
The MT8885 Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain
setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and
pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected.
The adaptive micro interface allows various microcontrollers to access the MT8885 internal registers.
1.1
Power-Down
The MT8885 provides enhanced power-down functionality to facilitate minimization of supply current consumption.
DTMF transmitter and receiver circuit blocks may be independently powered down via register control. When
asserted, the RxEN control bit powers down all analog and digital circuitry associated solely with the DTMF and
Call Progress receiver. The TOUT control bit is used to disable the transmitter and put all circuitry associated only
with the DTMF transmitter in power-down mode. With the TOUT control bit asserted, the TONE output pin is held in
a high impedance (floating) state. When both power-down control bits are asserted, circuits utilized by both the
DTMF transmitter and receiver are also powered down. This power-down control disables the crystal oscillators,
and the VRef generator. In addition, the IRQ, TONE output and DATA pins are held in a high impedance state.
Finally, the whole device is put in a power-down state when the PWDN pin is asserted.
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Zarlink Semiconductor Inc.
MT8885
1.2
Data Sheet
Input Configuration
The input arrangement of the MT8885 provides a differential-input operational amplifier as well as a bias source
(VRef), which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the opamp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in
Figure 3.
Figure 4 shows the necessary connections for a differential input configuration.
1.3
Receiver Section
Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order
switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies
(see Table 1). The filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each
filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of
unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the
incoming DTMF signals.
MT8885
IN+
C
IN-
RIN
RF
VOLTAGE GAIN
(AV) = RF / RIN
GS
VRef
Figure 3 - Single-Ended Input Configuration
MT8885
C1
IN+
R1
INC2
R4
R5
GS
R2
R3
VRef
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60 kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
INPUT IMPEDANCE
(AV diff) - R5/R1
(Z diff) = 2 R12 + (1/ωC)2
IN
Figure 4 - Differential Input Configuration
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Zarlink Semiconductor Inc.
MT8885
Data Sheet
FLOW
FHIGH
Digit
D3
D2
D1
D0
697
1209
1
0
0
0
1
697
1336
2
0
0
1
0
697
1477
3
0
0
1
1
770
1209
4
0
1
0
0
770
1336
5
0
1
0
1
770
1477
6
0
1
1
0
852
1209
7
0
1
1
1
852
1336
8
1
0
0
0
852
1477
9
1
0
0
1
941
1336
0
1
0
1
0
941
1209
*
1
0
1
1
941
1477
#
1
1
0
0
697
1633
A
1
1
0
1
770
1633
B
1
1
1
0
852
1633
C
1
1
1
1
941
1633
D
0
0
0
0
Table 1 - Functional Encode/Decode Table
0= LOGIC LOW, 1= LOGIC HIGH
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state.
1.4
Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes vc (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt
remains high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the tone
pair, latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT output is
activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to
allow the output latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has
been registered. The status of the delayed steering flag can be monitored by checking the appropriate bit in the
status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering flag is
active.
The contents of the output latch are updated on an active delayed steering transition. This data is presented to the
four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to
validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together
with the capability of selecting the steering time constants externally, allows the designer to tailor performance to
meet a wide variety of system requirements.
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Zarlink Semiconductor Inc.
MT8885
Data Sheet
VDD
MT8885
C1
VDD
Vc
St/GT
ESt
R1
tGTA = (R1C1) In (VDD / VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
Figure 5 - Basic Steering Circuit
1.5
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen
according to the following inequalities (see Figure 7):
t REC ≥ t DPmax + t GTPmax - t DAmin
t REC ≤ t DPmin + t GTPmin - t DAmax
t ID ≥ t DAmax + t GTAmax - t DPmin
t DO ≤ t DAmin + t GTAmin - t DPmax
The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum signal duration
to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most applications, leaving R1 to be
selected by the designer. Different steering arrangements may be used to select independent tone present (tGTP)
and tone absent (tGTA) guard times. This may be necessary to meet system specifications which place both accept
and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor
system parameters such as talk-off and noise immunity.
Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will
maintain a valid signal condition long enough to be registered. Alternatively, a relatively short tREC with a long tDO
would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs
are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.
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Zarlink Semiconductor Inc.
MT8885
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
tGTA = (R1C1) In (VDD/VTSt)
RP = (R1R2) / (R1 + R2)
VDD
C1
St/GT
R1
ESt
R2
a) decreasing tGTP; (tGTP < tGTA)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
tGTA = (RpC1) In (VDD/VTSt)
RP = (R1R2) / (R1 + R2)
VDD
C1
St/GT
R1
R2
ESt
b) decreasing tGTA; (tGTP > tGTA)
Figure 6 - Guard Time Adjustment
7
Zarlink Semiconductor Inc.
Data Sheet
MT8885
2.0
Data Sheet
Call Progress Filter
A call progress mode, using the MT8885, can be selected to allow the detection of various tones, which identify the
progress of a telephone call on the network. The call progress tone input and DTMF input are common, however,
call progress tones can only be detected when CP mode has been selected.
EVENTS
A
B
C
tREC
tREC
D
F
tDO
tID
TONE
#n + 1
TONE #n
Vin
E
TONE
#n + 1
tDA
tDP
ESt
tGTP
tGTA
VTSt
St/GT
tPStRX
RX0-RX3
DECODED TONE # (n-1)
# (n + 1)
#n
tPStb3
b3
b2
Read
Status
Register
IRQ/CP
Figure 7 - Receiver Timing Diagram
LEVEL
(dBm)
-25
0
250
500
750
FREQUENCY (Hz)
= Reject
= May Accept
= Accept
Figure 8 - Call Progress Response
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Zarlink Semiconductor Inc.
MT8885
Data Sheet
EXPLANATION OF EVENTS
A)
TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.
B)
TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
C)
END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
D)
TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
E)
ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.
F)
END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
EXPLANATION OF SYMBOLS
Vin
DTMF COMPOSITE INPUT SIGNAL.
ESt
EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT
STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
RX 0 -RX3 4-BIT DECODED DATA IN RECEIVE DATA REGISTER
b3
DELAYED STEERING IN STATUS REGISTER (BIT 3) INDICATES THAT VALID FREQUENCIES HAVE BEEN
PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW
FOR THE DURATION OF A VALID DTMF SIGNAL.
b2
RECEIVE DATA REGISTER FULL (BIT 2) IN STATUS REGISTER INDICATES THAT VALID DATA IS IN THE
RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS REGISTER IS READ.
INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS
IRQ/CP
CLEARED AFTER THE STATUS REGISTER IS READ.
tREC
MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID. TYPICALLY 20 MS.
tREC
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION. TYPICALLY 40 MS.
tID
MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS. TYPICALLY 40 MS.
tDO
MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL. TYPICALLY 20 MS.
tDP
TIME TO DETECT VALID FREQUENCIES PRESENT.
tDA
TIME TO DETECT VALID FREQUENCIES ABSENT.
tGTP
GUARD TIME, TONE PRESENT.
tGTA
GUARD TIME, TONE ABSENT.
Figure 9 - Description of Timing Events
DTMF signals cannot be detected if CP mode has been selected (see Table 7). Figure 8 indicates the useful detect
bandwidth of the call progress filter. Frequencies presented to the input, which are within the ‘accept’ bandwidth
limits of the filter, are hard-limited by a high gain comparator with the IRQ/CP pin serving as the output. The
squarewave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement
to determine the nature of the call progress tone being detected. Frequencies which are in the ‘reject’ area will not
be detected and consequently the IRQ/CP pin will remain low.
3.0
DTMF Generator
The DTMF transmitter employed in the MT8885 is capable of generating all sixteen standard DTMF tone pairs with
low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The sinusoidal
waveforms for the individual tones are digitally synthesized by using row and column programmable dividers and
switched capacitor D/A converters. The row and column tones are mixed and filtered to provide a DTMF signal with
low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format
shown in Table 1 must be written to the transmit Data Register. Note that Table 1 is the same as the receiver
output code. The individual tones which are generated (fLOW and fHIGH) are referred to as Low Group and High
Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group
frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB
to compensate for high group attenuation on long loops.
The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length
of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched
and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time
segment length which will ultimately determine the frequency of the tone. When the divider reaches the appropriate
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Zarlink Semiconductor Inc.
MT8885
Data Sheet
count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time
segments is fixed at 32, however, by varying the segment length as described above, the frequency can also be
varied. The divider output clocks another counter, which addresses the sinewave lookup ROM.
The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and
highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which
are then mixed by using a low noise summing amplifier. A bandwidth limiting filter is incorporated and serves to
attenuate distortion products above 8 kHz. Figure 10 shows that the distortion products are very low in amplitude.
Scaling Information
10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz
Figure 10 - Spectrum Plot
4.0
Burst Mode
In certain telephony applications it is required that DTMF signals being generated are of a specific duration
determined either by the particular application or by any one of the exchange transmitter specifications currently
existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is
capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms±1 ms
which is a standard interval for autodialer and central office applications. After the burst/pause has been issued, the
appropriate bit is set in the Status Register to indicate that the transmitter is ready for more data. The timing
described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode)
is selected, the burst/pause duration is doubled to 102 ms ±2 ms. Note that when CP mode and Burst mode have
been selected, DTMF tones may only be transmitted and not received. In applications where a non-standard
burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses
when the burst mode is disabled by enabling and disabling the transmitter.
5.0
Single Tone Generation
A single tone mode is available whereby individual tones from the low group or high group can be generated. This
mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion
measurements. Refer to Control Register B description for details.
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Zarlink Semiconductor Inc.
MT8885
Data Sheet
Output Frequency (Hz)
Active
Input
Specified
Actual
L1
697
699.1
+0.30
L2
770
766.2
-0.49
L3
852
847.4
-0.54
L4
941
948.0
+0.74
H1
1209
1215.9
+0.57
H2
1336
1331.7
-0.32
H3
1477
1471.9
-0.35
%Error
H4
1633
1645.0
+0.73
Table 2 - Actual Frequencies Versus Standard Requirements
6.0
Distortion Calculations
The MT8885 is capable of producing precise tone bursts with minimal error in frequency (see Table 2). The internal
summing amplifier is followed by a first-order lowpass switched capacitor filter to minimize harmonic components
and intermodulation products. The total harmonic distortion for a single tone can be calculated by using Equation 1,
which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency
expressed as a percentage.
V22f + V23f + V24f + .... V2nf
THD (%) = 100
V2fundamental
Equation 1. THD (%) For a Single Tone
The Fourier components of the tone output correspond to V2f.... Vnf as measured on the output waveform. The total
harmonic distortion for a dual tone can be calculated by using Equation 2. VL and VH correspond to the low group
amplitude and high group amplitude, respectively and V2IMD is the sum of all the intermodulation components. The
internal switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as
shown in Figure 10.
V22L + V23L + .... V2nL + V22H +
V23H + .. V2nH + V2IMD
THD (%) = 100
V2L + V2H
Equation 2. THD (%) For a Dual Tone
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Zarlink Semiconductor Inc.
MT8885
7.0
Data Sheet
DTMF Clock Circuit
The internal clock circuit is completed with the additions of a standard television colour burst crystal. The crystal
specification is as follows:
Frequency:
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
Maximum Series Resistance:
Maximum Drive Level:
3.579545 MHz
±0.1%
Parallel
18 pF
150 ohms
2 mW
e.g.CTS Knights MP036S
Toyocom TQC-203-A-9S
A number of MT8885 devices can be connected as shown in Figure 11 such that only one crystal is required.
Alternatively, the OSC1 inputs on all devices can be driven from a CMOS buffer with the OSC2 outputs left
unconnected.
MT8885
OSC1 OSC2
MT8885
MT8885
OSC1 OSC2
OSC1 OSC2
3.579545 MHz
Figure 11 - Common Crystal Connection
8.0
Microprocessor Interface
The MT8885 design incorporates an adaptive interface, which allows it to be connected to various kinds of
microprocessors. Key functions of this interface include the following:
•
Continuous activity on DS/RD is not necessary to update the internal status registers.
•
Compatible with Motorola and Intel processors. Determines whether input timing is that of an Intel or
Motorola controller by monitoring
DS/RD, on the CS falling edge.
•
Differentiates between multiplexed and non-multiplexed microprocessor buses. Address and data are
latched in accordingly.
Figure 16 shows the timing diagram for the Motorola microcontrollers. The chip select (CS) input is formed by
NANDing address strobe (AS) and address decode output. The MT8885 examines the state of DS/RD on the falling
edge of CS. For Motorola bus timing DS/RD must be low on the falling edge of CS. Figure 12(a) shows the
connection of the MC68HC11 Motorola processor to the MT8885 DTMF transceiver.
Figures 17 and 18 are the timing diagrams for Intel micro-controllers with multiplexed address and data buses. The
MT8885 latches in the state of DS/RD on the falling edge of CS. When DS/RD is high, Intel processor operation is
selected. By NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS
can be generated. Figure 12(b) shows the connection of these Intel processors to the MT8885 transceiver.
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Zarlink Semiconductor Inc.
MT8885
Data Sheet
NOTE: The adaptive micro interface relies on high-to-low transition on CS to recognize the microcontroller
interface. This pin must not be tied permanently low. Only one register access is allowed on any CS assertion.
The adaptive micro interface provides access to five internal registers. The read-only Receive Data Register
contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data
Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is
accomplished with two control registers (see Tables 6 and 7), CRA and CRB, which have the same address. A write
operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation to the
same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The readonly status register indicates the current transceiver state (see Table 8).
A software reset must be included at the beginning of all programs to initialize the control registers upon power-up
or power reset (see Figure 14). Refer to Tables 4-7 for bit descriptions of the two control registers.
The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when
the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a
square-wave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external
pull-up resistor (see Figure 13).
Motorola
Intel
RS0
R/W
WR
RD
Function
0
0
0
1
Write to Transmit
Data Register
0
1
1
0
Read from Receive
Data Register
1
0
0
1
Write to Control Register
1
1
1
0
Read from Status Register
Table 3 - Internal Register Functions
b3
b2
b1
b0
RSEL
IRQ
CP/DTMF
TOUT
Table 4 - CRA Bit Positions
b3
b2
b1
b0
C/R
S/D
RxEN
BURST
ENABLE
Table 5 - CRB Bit Positions
13
Zarlink Semiconductor Inc.
MT8885
8031/8051/
8080/8085
MT8885
MC68HC11
CS
A8-A15
Data Sheet
MT8885
CS
A8-A15
D0-D3
AS
D0-D3
ALE
AD0-AD3
RS0
DS/RD
E
R/W/WR
RW
P0
RS0
RD
DS/RD
R/W/WR
WR
12 (a) Motorola
12 (b) Intel
Figure 12 a) & b) - MT8885 Interface Connections for Various Intel and Motorola Micros
Bit
Name
Description
b0
TOUT
Tone Output Control. A logic high enables the tone output; a logic low puts the DTMF
transmitter in power-down mode. The TONE output pin is held in high impedance and the
transmit register is cleared. See Note 1 below.
b1
CP/DTMF
Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;
a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and
transmitting DTMF signals. In CP mode a rectangular wave representation of the received
tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control
register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristics for Call Progress.
Note: DTMF signals cannot be detected when CP mode is selected.
b2
IRQ
Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the
interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,
b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been
received for a valid guard time duration, or 2) the transmitter is ready for more data (burst
mode only).
b3
RSEL
Register Select. A logic high selects control register B for the next write cycle to the control
register address. After writing to control register B, the following control register write cycle
will be directed to control register A.
Table 6 - Control Register A Description
14
Zarlink Semiconductor Inc.
MT8885
Data Sheet
Bit
Name
Description
b0
BURST
Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.
When activated, the digital code representing a DTMF signal (see Table 1) can be written to
the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the pause, the status register will be updated (b1 Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (de-activated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).
b1
RxEN
This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both
circuits. A logic high deactivates and puts both receiver circuits into power-down mode. See
Note 1 below.
b2
S/D
Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) through the C/R bit (control
register B, b3).
b3
C/R
Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone output. This function is used in conjunction with the S/D bit (control register B,
b2).
Table 7 - Control Register B Description
Note 1:
When both TOUT and RxEN are asserted to power-down, the crystal oscillator and the Vref circuits are powered down.
Bit
Name
b0
IRQ
Status Flag Set
Status Flag Cleared
Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.
Interrupt is inactive. Cleared after
Status Register is read.
b1
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2
RECEIVE DATA REGISTER
FULL
Valid data is in the Receive Data
Register.
Cleared after Status Register is
read.
b3
DELAYED STEERING
Set upon the valid detection of the
absence of a DTMF signal.
Cleared upon the detection of a
valid DTMF signal.
Table 8 - Status Register Description
15
Zarlink Semiconductor Inc.
MT8885
Data Sheet
VDD
MT8885
C1
R1
DTMF/CP
INPUT
R2
VDD
IN-
St/GT
GS
ESt
DTMF
OUTPUT
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 kΩ 1%
R4 = 3.3 kΩ 10%
R5 = 4.7 MΩ 10%
RL = 10 k Ω (min.)
C1 = 100 nF 5%
C2 = 100 nF 5%
C3 = 100 nF 10%*
C4 = 10 nF 10%
X-tal = 3.579545 MHz
C4
RL
C2
R4
VRef
D3
VSS
D2
OSC1
D1
OSC2
D0
TONE
IRQ/CP
R5
X-tal
C3
IN+
WR
RD
CS
RS0
R3
To µP
or µC
* Microprocessor based systems can inject undesirable noise into the supply rails.
The performance of the MT8885 can be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.
Figure 13 - Application Circuit (Single-Ended Input)
16
Zarlink Semiconductor Inc.
MT8885
Data Sheet
INITIALIZATION PROCEDURE
A software reset must be included at the beginning of all programs to initialize the control registers after
power up.
Description:
1)
2)
3)
4)
5)
6)
Read Status Register
Write to Control Register
Write to Control Register
Write to Control Register
Write to Control Register
Read Status Register
RS0
1
1
1
1
1
1
Motorola
Intel
WR RD
R/W
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
0
b3
X
0
0
1
0
X
Data
b2
X
0
0
0
0
X
b1
X
0
0
0
0
X
b0
X
0
0
0
0
X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS
Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.
Sequence:
RS0
1) Write to Control Register A
1
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B
1
(burst mode)
3) Write to Transmit Data Register
0
(send a digit 7)
4) Wait for an Interrupt or Poll Status Register
5) Read the Status Register
1
R/W
0
WR RD
0
1
b3
1
b2
1
b1
0
b0
1
0
0
1
0
0
0
0
0
0
1
0
1
1
1
1
1
0
X
X
X
X
-if bit 1 is set, the Tx is ready for the next tone, in which case...
Write to Transmit Register
0
0
0
(send a digit 5)
1
0
1
0
1
-if bit 2 is set, a DTMF tone has been received, in which case....
Read the Receive Data Register
0
1
1
0
X
X
X
X
-if both bits are set...
Read the Receive Data Register
Write to Transmit Data Register
0
1
X
0
X
1
X
0
X
1
0
0
1
0
1
0
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)
Figure 14 - Application Notes
17
Zarlink Semiconductor Inc.
MT8885
Data Sheet
Absolute Maximum Ratings*
Parameter
Symbol
1
Power supply voltage VDD-VSS
2
Voltage on any pin
3
Current at any pin (Except VDD
4
Storage temperature
TST
5
Package power dissipation
PD
Min.
Max.
Units
6.0
V
VDD+0.3
V
10
mA
+150
°C
1000
mW
VDD -VSS
VSS-0.3
VI
and VSS)
-65
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter
Sym
Min.
Typ.‡
Max.
Units
5.0
5.25
V
+85
°C
3.583124
MHz
1
Positive power supply
VDD
4.75
2
Operating temperature
TO
-40
3
Crystal clock frequency
fCLK
3.575965
3.579545
Test Conditions
‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics † - VSS=0 V.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
Standby supply current
IDDQ
3.0
15.0
µA
TOUT and RxEN bits
asserted to powerdown mode
Transmitter supply
current
IDDTX
5.5
9.0
mA
Transmitter fully
enabled and RxEN bit
asserted to powerdown mode
Receiver supply current
IDDRX
4.5
8.0
mA
Receiver fully enabled
and TOUT bit
asserted to powerdown mode
4
Operating supply current
IDD
7.0
11.0
mA
Device fully enabled
5
High level input voltage
(OSC1)
VIHO
Low level input voltage
(OSC1)
VILO
Steering threshold
voltage
VTSt
1
2
3
6
7
S
U
P
P
L
Y
I
N
P
U
T
S
0.7
VDD
0.43
VDD
V
0.46
VDD
18
Zarlink Semiconductor Inc.
0.3 VDD
V
0.51
VDD
V
VDD = 5 V
MT8885
Data Sheet
DC Electrical Characteristics (continued)† - VSS=0 V.
Characteristics
8
9
10
11
O
U
T
P
U
T
S
12
13
14
15
16
17
18
19
20
21
D
i
g
i
t
a
l
Data
Bus
ESt
and
St/G
T
IRQ/
CP
Sym.
Low level output voltage
(OSC2)
VOLO
High level output voltage
(OSC2)
VOHO
Output leakage current
(IRQ) (Tone)
IOZT
VRef output voltage
VRef
VRef output resistance
Min.
Typ.‡
Max.
Units
0.1 VDD
V
No load
V
No load
0.9
VDD
Test Conditions
10
µA
0.53
VDD
V
No load
ROR
2.5
kΩ
Note 9
Low level input voltage
VIL
0.3 VDD
V
High level input voltage
VIH
Input leakage current
IIZ
10
µA
VIN=VSS to VDD
Output high impedance
IOZD
10
µA
VIN=VSS to VDD
Source current
IOHD
1.4
6.6
mA
VOH=0.9VDD
Sink current
IOLD
2.0
4.0
mA
VOL=0.1VDD
Source current
IOHE
0.5
3.0
mA
VOH=0.9VDD
Sink current
IOLE
2.0
4
mA
VOL=0.1VDD
Sink current
IOLI
4.0
16.0
mA
VOL=0.1VDD
1
0.47
VDD
0.7
VDD
V
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25 °C, VDD =5 V and for design aid only: not guaranteed and not subject to production testing.
* See “Notes” following AC Electrical Characteristics Tables.
Electrical Characteristics
Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V, VDD=5 V, TO=25°C.
Characteristics
Sym.
Typ.‡
Min.
Max.
Units
Test Conditions
100
nA
VSS ≤ VIN ≤ VDD
Note 9
MΩ
Note 9
mV
Note 9
1
Input leakage current
IIN
2
Input resistance
RIN
3
Input offset voltage
VOS
4
Power supply rejection
PSRR
50
dB
1 kHz, See Note 9
5
Common mode rejection
CMRR
40
dB
VSS + 0.75V ≤ VIN ≤ VDD 0.75V biased at VREF =
1.5 V
Note 9
6
DC open loop voltage gain
AVOL
32
dB
Note 9
7
Unity gain bandwidth
fc
0.3
MHz
Note 9
10
25
19
Zarlink Semiconductor Inc.
MT8885
Data Sheet
Electrical Characteristics
Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V, VDD=5 V, TO=25°C.
Characteristics
Sym.
Min.
VO
2.2
8
Output voltage swing
9
Allowable capacitive load
(GS)
CLGS
10
Allowable resistive load (GS)
RLGS
11
Common mode range
VCM
Typ.‡
Max.
Units
Test Conditions
Vpp
RLGS ≥ 100 kΩ to VSS at
GS, 3 KHz
Note 9
pF
Note 9
kΩ
Note 9
Vpp
VDD = 5 V, No Load
Note 9
100
50
1.5
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
MT8885 AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
1
R
X
Sym.
Valid input signal levels
(each tone of composite
signal)
Typ.
Min.
Max.
Units
-29
1
dBm
1, 2, 3, 5, 6
27.5
869
mVRMS
1, 2, 3, 5, 6
‡
Notes*
2
Positive twist accept
8
dB
2, 3, 6, 9
3
Negative twist accept
8
dB
2, 3, 6, 9
4
5
R
X
Freq. deviation accept
±1.5%± 2 Hz
2, 3, 5
Freq. deviation reject
±3.5%
2, 3, 5
6
Third tone tolerance
-16
dB
2, 3, 4, 5, 9, 10
7
Noise tolerance
-12
dB
2, 3, 4, 5, 7, 9, 10
8
Dial tone tolerance
dB
2, 3, 4, 5, 8, 9
22
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD = 5 V, and for design aid only: not guaranteed and not subject to production testing.
* *See “Notes” following AC Electrical Characteristics Tables.
AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics
Sym.
Min.
320
1
Accept Bandwidth
fA
2
Lower freq. (REJECT)
fLR
3
Upper freq. (REJECT)
fHR
4
Call progress tone detect level (total
power)
Typ.‡
Max.
Units
500
Hz
@ -25 dBm
Note 9
290
Hz
@ -25 dBm
Note 9
540
Hz
@ -25 dBm
Note 9
-30
dBm
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD=5 V, and for design aid only: not guaranteed and not subject to production testing.
20
Zarlink Semiconductor Inc.
Conditions
MT8885
Data Sheet
AC Electrical Characteristics † - Voltages are with respect to ground (VSS), unless otherwise stated.
Sym.
Min.
Typ.‡
Max.
Units
Tone present detect time
tDP
4
11
14
ms
Note 11
Tone absent detect time
tDA
0.5
4
8.5
ms
Note 11
Characteristics
1
2
T
O
N
E
Conditions
Delay St to b3
tPStb3
20
µs
Figure 7, Note 9
Delay St to RX0-RX3
tPStRX
11
µs
Figure 7, Note 9
5
Tone burst duration
tBST
50
52
ms
DTMF mode
6
Tone pause duration
tPS
50
52
ms
DTMF mode
7
Tone burst duration (extended)
tBSTE
100
104
ms
Call Progress mode
tPSE
100
104
ms
Call Progress mode
High group output level
VHOUT
-6.1
-2.1
dBm
RLT=10 kΩ
Low group output level
VLOUT
-8.1
-4.1
dBm
RLT=10 kΩ
3
dB
RLT=10 kΩ
-35
dB
25 kHz Bandwidth
3
4
8
9
I
N
T
O
N
E
10
11
12
O
U
T
Tone pause duration
(extended)
Pre-emphasis
dBP
Output distortion (Single Tone)
THD
2
RLT=10 kΩ, Note 9
13
±0.7
14
Frequency deviation
15
Output load resistance
RLT
10
16
Crystal/clock frequency
fC
3.575
9
17
18
X
T
A
L
fD
Clock input rise and fall time
tCLRF
Clock input duty cycle
DCCL
40
3.579
5
±1.5
%
fC=3.579545 MHz
50
kΩ
Note 9
3.583
1
MHz
Note 9
110
ns
Ext. clock, Note 9
60
%
Ext. clock, Note 9
50
19
OSC2 load capacitance
CLO
30
pF
20
Oscillator start-up time
tOST
10
ms
Note 9
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Conditions
1
RD/WR low pulse width
tCL
200
400
ns
Figure 15, Note 12
tCL + tCH ≥ 1000 ns
2
DS high pulse width
tCH
200
400
ns
Figure 15, Note 12
tCL + tCH ≥ 1000 ns
3
Rise and fall time all digital inputs
tR,tF
ns
Figure 15
4
R/W setup time
tRWS
23
ns
Figures 16
5
R/W hold time
tRWH
20
ns
Figures 16
6
Address setup time (RS0)
tAS
0
ns
Figures 16 - 18
7
Address hold time (RS0)
tAH
40
ns
Figures 16 - 18
20
21
Zarlink Semiconductor Inc.
MT8885
Data Sheet
AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics
Sym.
Min.
22
8
Data hold time (read)
tDHR
9
DS/RD to valid data delay (read)
tDDR
10
Data setup time (write)
tDSW
11
Data hold time (write)
12
Typ.‡
Max.
Units
Conditions
ns
Figures 16 - 17
ns
Figures 16 - 17
45
ns
Figures 16, 18
tDHW
10
ns
Figures 16, 18
Chip select setup time
tCSS
45
ns
Figures 16 - 18
13
Chip select hold time
tCSH
40
ns
Figures 16 - 18
14
DS/RD set up time prior to CS
assertion
tRDS,tDSS
20
ns
Figures 16, 17
100
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD=5 V, and for design aid only: not guaranteed and not subject to production testing
NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
2) Digit sequence consists of all 16 DTMF tones.
3) Tone duration=40 ms. Tone pause = 40 ms.
4) Nominal DTMF frequencies are used.
5) Both tones in the composite signal have an equal amplitude.
6) The tone pair is deviated by ± 1.5% ±2 Hz.
7) Bandwidth limited (3 kHz) Gaussian noise.
8) The precise dial tone frequencies are 350 and 440 Hz (±2%).
9) Guaranteed by design and characterization. Not subject to production testing.
10) Referenced to the lowest amplitude tone in the DTMF signal.
11) For guard time calculation purposes.
12) Operation of microprocessor interface requires that tCL + t CH ≥ 1000 ns
tR
tF
VHM
All Digital Inputs
VLM
*V HM = 0.7V DD, VLM = 0.3V DD
Figure 15 - Digital Signal Input Rise/Fall Times
22
Zarlink Semiconductor Inc.
MT8885
Data Sheet
tCL
tCH
tRWS
DS (E)
tDSS
tRWH
R/W
Read
AD3-AD0
(RS0, D0-D3)
Write
AD3-AD0
(RS0-D0-D3)
Addr
Data
Addr
Data
tDSW
tAH
Addr *
non-mux
tDHR
tDDR
tAS
tCSH
High Byte of Addr
AS *
CS = AS.Addr
tCSS
* microprocessor pins
Figure 16 - Motorola BUS Timing Diagram
23
Zarlink Semiconductor Inc.
tDHW
MT8885
Data Sheet
tCSS
ALE*
tRDS
RD
tCH
tCL
WR
P0*
(RS0,
D0-D3)
tAS
tDHR
tDDR
tAH
Data
A0-A7
P2 *
(Addr)
A8-A15 Address
tCSH
CS = ALE.Addr
* microprocessor pins
Figure 17 - Intel Read Timing Diagram
ALE*
tCSS
RD**
tCL
tCH
WR
tAS
P0*
(RS0,
D0-D3)
tDSW
tAH
tDHW
Data
A0-A7
P2 *
(Addr)
A8-A15 Address
tCSH
CS = ALE.Addr
* microprocessor pins
** RD must be high on the falling edge of CS for Intel Bus Timing
Figure 18 - Intel Write Timing Diagram
24
Zarlink Semiconductor Inc.
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However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
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This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
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Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
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