TI TLK3131

TLK3131
Single Channel Multi-Rate Transceiver
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLLS957
December 2008
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
www.ti.com
Contents
1
Introduction......................................................................................................................... 9
1.1
1.2
1.3
2
Detailed Description ........................................................................................................... 11
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
11
12
12
12
12
16
17
17
18
19
20
21
22
23
24
25
26
27
28
28
28
30
30
30
30
31
31
33
38
................................................................................ 53
Gigabit Ethernet Mode (RGMII) ..........................................................................................
JITTER TEST PATTERN GENERATION AND VERIFICATION PROCEDURES .................................
PRBS Test Generation and Verification Procedures .................................................................
Signal Pin Description .....................................................................................................
53
56
58
60
Electrical Specifications ...................................................................................................... 66
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
2
Clocking Modes.............................................................................................................
Operating Frequency Range..............................................................................................
CPRI Latency Support .....................................................................................................
Powerdown Mode ..........................................................................................................
Application Examples ......................................................................................................
Device Operation Modes ..................................................................................................
Parallel Interface Modes - Detailed Description ........................................................................
2.7.1
RGMII Mode (Reduced Gigabit Media Independent Interface) ............................................
2.7.2
RTBI Mode (Reduced Ten Bit Interface) .....................................................................
2.7.3
TBI Mode (Ten Bit Interface) ...................................................................................
2.7.4
GMII Mode (Gigabit Media Independent Interface) .........................................................
2.7.5
EBI Mode (Eight Bit Interface) .................................................................................
2.7.6
REBI Mode (Reduced Eight Bit Interface) ...................................................................
2.7.7
NBI Mode (Nine Bit Interface Mode) ..........................................................................
2.7.8
RNBI Mode (Reduced Nine Bit Interface) ....................................................................
2.7.9
TBID Mode (Ten Bit Interface DDR) ..........................................................................
2.7.10 NBID Mode (Nine Bit Interface DDR) .........................................................................
2.7.11 Parallel Interface Clocking Modes.............................................................................
2.7.12 Parallel to Serial .................................................................................................
2.7.13 Serial to Parallel .................................................................................................
2.7.14 High Speed CML Output .......................................................................................
2.7.15 High Speed Receiver ...........................................................................................
2.7.16 Loopback .........................................................................................................
2.7.17 Link Test Functions .............................................................................................
2.7.18 MDIO Management Interface ..................................................................................
2.7.19 MDIO Protocol Timing ..........................................................................................
2.7.20 Clause 22 Indirect Addressing .................................................................................
PROGRAMMERS REFERENCE.........................................................................................
Top Level Programmers Reference .....................................................................................
Device Reset Requirements/Procedure
3.1
3.2
3.3
3.4
4
Features ....................................................................................................................... 9
Pin Out ........................................................................................................................ 9
Description .................................................................................................................. 10
ABSOLUTE MAXIMUM RATINGS .......................................................................................
RECOMMENDED OPERATING CONDITIONS........................................................................
REFERENCE CLOCK TIMING REQUIREMENTS (REFCLKP/N) ..................................................
REFERENCE CLOCK ELECTRICAL CHARACTERISTICS (REFCLKP/N)........................................
SINGLE ENDED REFERENCE CLOCK ELECTRICAL CHARACTERISTICS (REFCLK) .......................
JITTER CLEANER TIMING PARAMETERS ...........................................................................
LVCMOS ELECTRICAL CHARACTERISTICS .........................................................................
MDIO ELECTRICAL CHARACTERISTICS .............................................................................
HSTL SIGNALS (VDDQ = 1.5/1.8 V) ...................................................................................
SERIAL TRANSMITTER/RECEIVER CHARACTERISTICS .........................................................
Contents
66
66
67
67
67
67
68
68
68
69
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Single Channel Multi-Rate Transceiver
www.ti.com
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
SLLS957 – DECEMBER 2008
DRIVER TEMPLATE PARAMETERS ...................................................................................
TIMING DEFINITION ......................................................................................................
APPLICATION MODES ...................................................................................................
HSTL Output Switching Characteristics (DDR Timing Mode Only) ..................................................
HSTL Output Switching Characteristics (SDR Timing Mode Only) ..................................................
HSTL (DDR Timing Mode Only) Input Timing Requirements ........................................................
HSTL (SDR Timing Mode Only) Input Timing Requirements ........................................................
MDIO Timing Requirements Over Recommended Operating Conditions ..........................................
JTAG Timing Requirements Over Recommended Operating Conditions ..........................................
PACKAGE DISSIPATION RATING ......................................................................................
70
70
71
73
74
75
76
77
78
81
A
APPENDIX A – Frequency Ranges Supported ........................................................................ 82
B
C
APPENDIX B – Jitter Cleaner PLL External Loop Filter............................................................ 97
APPENDIX C – Device Test Mode ......................................................................................... 98
A.1
Recovered Byte Clock Jitter Cleaner Mode: ............................................................................ 95
Contents
3
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
www.ti.com
List of Figures
1-1
System Block Diagram – PCS................................................................................................... 10
1-2
Block Diagram – TLK3131 Clocking Architecture............................................................................. 11
2-1
Single 10-Bit SERDES Application ............................................................................................. 13
2-2
1000Base-X – Remote (Serial) Loopback Application ....................................................................... 13
2-3
1000Base-X – Local (Parallel ) Loopback Application ....................................................................... 13
2-4
TLK3131 Block Diagram ......................................................................................................... 14
2-5
Detailed 1000Base-X Core Block Diagram .................................................................................... 14
2-6
Block Diagram of SERDES Core
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4
...............................................................................................
RGMII – Individual Channel Byte Ordering – Channel 0 Example .........................................................
RTBI – Individual Channel Byte Ordering – Channel 0 Example ...........................................................
TBI – Individual Channel Byte Ordering – Channel 0 Example .............................................................
GMII – Individual Channel Byte Ordering – Channel 0 Example ...........................................................
EBI – Individual Channel Byte Ordering – Channel 0 Example.............................................................
REBI – Individual Channel Byte Ordering – Channel 0 Example ...........................................................
NBI – Individual Channel Byte Ordering – Channel 0 Example ............................................................
RNBI – Individual Channel Byte Ordering – Channel 0 Example ..........................................................
TBID – Individual Channel Byte Ordering – Channel 0 Example ...........................................................
NBID – Individual Channel Byte Ordering – Channel 0 Example ..........................................................
Receive Interface Timing – Source Centered/Aligned .......................................................................
Transmit Interface Timing ........................................................................................................
Example High Speed I/O AC Coupled Mode ..................................................................................
Output Differential Voltage With 1-Tap FIR De-emphasis ...................................................................
CL22 – Management Interface Read Timing(1) ................................................................................
CL22 - Management Interface Write Timing...................................................................................
CL22 – Indirect Address Method – Address Write............................................................................
CL22 – Indirect Address Method – Data Write ................................................................................
CL22 – Indirect Address Method – Address Write............................................................................
CL22 – Indirect Address Method – Data Read(1) .............................................................................
Device Pinout Diagram – (Top View) ...........................................................................................
Transmit Output Waveform Parameter Definitions ...........................................................................
Transmit Template ................................................................................................................
Receive Template .................................................................................................................
Input Jitter ..........................................................................................................................
HSTL (DDR Timing Mode Only) Source Centered Output Timing Requirements ........................................
HSTL (DDR Timing Mode Only) Source Aligned Output Timing Requirements ..........................................
HSTL (SDR Timing Mode Only) Rising Edge Aligned Output Timing Requirements ....................................
HSTL (SDR Timing Mode Only) Falling Edge Aligned Output Timing Requirements....................................
HSTL (DDR Timing Mode Only) Source Centered Data Input Timing Requirements ...................................
HSTL (DDR Timing Mode Only) Source Aligned Data Input Timing Requirements .....................................
List of Figures
15
17
18
19
20
21
22
23
24
25
26
27
28
29
29
31
31
31
32
32
32
65
70
70
71
71
73
73
74
74
75
75
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TLK3131
Single Channel Multi-Rate Transceiver
www.ti.com
4-11
4-12
4-13
4-14
4-15
4-16
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
B-1
SLLS957 – DECEMBER 2008
..
HSTL (SDR Timing Mode Only) Rising Edge Aligned (Falling Edge Sampled) Data Input Timing Requirements ..
MDIO Read/Write Timing ........................................................................................................
JTAG Timing .......................................................................................................................
HSTL I/O Schematic ..............................................................................................................
PACKAGE Information (Package Designator = ZWQ) .......................................................................
Standard Based Jitter Cleaner/SERDES Provisioning .......................................................................
9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (2x) Provisioning .....................................................
9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (1x) Provisioning .....................................................
9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (0.5x) Provisioning...................................................
9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (0.25x) Provisioning .................................................
8 BIT SERDES Mode – Jitter Cleaner/SERDES (2x) Provisioning(A) ......................................................
8 BIT SERDES Mode – Jitter Cleaner/SERDES (1x) Provisioning(A) ......................................................
8 BIT SERDES Mode – Jitter Cleaner/SERDES (0.5x) Provisioning ......................................................
Recovered Byte Clock Jitter Cleaner Mode ...................................................................................
Jitter Cleaner External Loop Filter ..............................................................................................
HSTL (SDR Timing Mode Only) Falling Edge Aligned (Rising Edge Sampled) Data Input Timing Requirements
List of Figures
76
76
77
78
78
80
87
88
89
90
91
92
93
94
96
97
5
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
www.ti.com
List of Tables
2-1
Supported Protocol Rates and REFCLK Values .............................................................................. 12
2-2
Device Operation Modes ......................................................................................................... 16
2-3
RGMII – Lane To Functional Pin Mapping..................................................................................... 17
2-4
RTBI – Lane To Functional Pin Mapping ...................................................................................... 18
2-5
TBI – Lane To Functional Pin Mapping ........................................................................................ 19
2-6
GMII – Lane To Functional Pin Mapping....................................................................................... 20
2-7
EBI – Lane To Functional Pin Mapping ........................................................................................ 21
2-8
REBI – Lane To Functional Pin Mapping ...................................................................................... 22
2-9
NBI – Lane To Functional Pin Mapping ........................................................................................ 23
2-10
RNBI – Lane To Functional Pin Mapping ...................................................................................... 24
2-11
TBID – Lane To Functional Pin Mapping ...................................................................................... 25
2-12
NBID – Lane To Functional Pin Mapping ...................................................................................... 26
2-13
PHY_CONTROL_1
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
2-32
2-33
2-34
2-35
2-36
2-37
2-38
2-39
6
...............................................................................................................
PHY_STATUS_1 ..................................................................................................................
PHY_IDENTIFIER_1..............................................................................................................
PHY_IDENTIFIER_2..............................................................................................................
PHY_EXT_STATUS ..............................................................................................................
PHY_CH_CONTROL_1 ..........................................................................................................
PHY_CH_CONTROL_2 ..........................................................................................................
PHY_RX_CTC_FIFO_STATUS .................................................................................................
PHY_TX_CTC_FIFO_STATUS .................................................................................................
PHY_TX_WIDE_FIFO _STATUS ...............................................................................................
PHY_TEST_PATTERN_SYNC_STATUS .....................................................................................
PHY_TEST_PATTERN_COUNTER ............................................................................................
PHY_CRPAT_PATTERN_COUNTER_1 ......................................................................................
PHY_CRPAT_PATTERN_COUNTER_2 ......................................................................................
PHY_TEST_MODE_CONTROL ................................................................................................
PHY_CHANNEL_STATUS.......................................................................................................
PHY_PRBS_HIGH_SPEED_TEST_COUNTER ..............................................................................
PHY_EXT_ADDRESS_CONTROL .............................................................................................
PHY_EXT_ADDRESS_DATA ...................................................................................................
SERDES_PLL_CONFIG .........................................................................................................
PLL Multiplier Control .............................................................................................................
SERDES_RATE_CONFIG_TX_RX .............................................................................................
SERDES_RX0_CONFIG .........................................................................................................
SERDES_RX1_CONFIG .........................................................................................................
SERDES_TX0_CONFIG .........................................................................................................
SERDES_TX1_CONFIG .........................................................................................................
Transmit De-emphasis Control ..................................................................................................
List of Tables
33
33
34
34
34
34
35
36
36
36
36
36
37
37
37
37
37
37
37
38
38
38
39
39
39
40
40
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Single Channel Multi-Rate Transceiver
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SLLS957 – DECEMBER 2008
2-40
Output Swing Control ............................................................................................................. 40
2-41
SERDES_TEST_CONFIG_TX .................................................................................................. 41
2-42
SERDES_TEST_CONFIG_RX .................................................................................................. 41
2-43
SERDES_RX0_STATUS ......................................................................................................... 41
2-44
SERDES_RX1_STATUS......................................................................................................... 42
2-45
SERDES_TX0_STATUS ......................................................................................................... 42
2-46
SERDES_TX1_STATUS ......................................................................................................... 42
2-47
SERDES_PLL_STATUS ......................................................................................................... 42
2-48
JC_CLOCK_MUX_CONTROL .................................................................................................. 43
2-49
JC_VTP_CLK_DIV_CONTROL ................................................................................................. 43
2-50
JC_DELAY_STOPWATCH_CLK_DIV_CONTROL ........................................................................... 44
2-51
JC_DELAY_STOPWATCH_COUNTER
2-52
2-53
2-54
2-55
2-56
2-57
2-58
2-59
2-60
2-61
2-62
2-63
2-64
2-65
2-66
2-67
2-68
2-69
2-70
2-71
2-72
2-73
2-74
2-75
2-76
2-77
2-78
2-79
2-80
.......................................................................................
JC_REFCLK_FB_DIV_CONTROL..............................................................................................
JC_RXB_OUTPUT_CLK_DIV_CONTROL ....................................................................................
JC_CHARGE_PUMP_CONTROL ..............................................................................................
Charge Pump Control Setting (CP_CTRL) ....................................................................................
JC_PLL_CONTROL ..............................................................................................................
JC_TEST_CONTROL_1 .........................................................................................................
JC_TEST_CONTROL_2 .........................................................................................................
JC_TI_TEST_CONTROL_1 .....................................................................................................
JC_TI_TEST_CONTROL_2 .....................................................................................................
JC_TRIM_STATUS ...............................................................................................................
DIE_ID_7 ...........................................................................................................................
DIE_ID_6 ...........................................................................................................................
DIE_ID_5 ...........................................................................................................................
DIE_ID_4 ...........................................................................................................................
DIE_ID_3 ...........................................................................................................................
DIE_ID_2 ...........................................................................................................................
DIE_ID_1 ...........................................................................................................................
DIE_ID_0 ...........................................................................................................................
EFUSE_STATUS .................................................................................................................
EFUSE_CONTROL ...............................................................................................................
HSTL_INPUT_TERMINATION_CONTROL ...................................................................................
HSTL_OUTPUT_SLEWRATE_CONTROL ....................................................................................
HSTL_INPUT_VTP_CONTROL .................................................................................................
HSTL_OUTPUT_VTP_CONTROL ..............................................................................................
HSTL_GLOBAL_CONTROL .....................................................................................................
TX0_DLL_CONTROL.............................................................................................................
TX1_DLL_CONTROL.............................................................................................................
RX0_DLL_CONTROL ............................................................................................................
RX1_DLL_CONTROL ............................................................................................................
List of Tables
44
44
44
45
45
45
46
46
46
46
46
46
47
47
47
47
47
47
47
47
48
48
48
48
49
49
50
50
50
50
7
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
www.ti.com
2-81
DLL Offset Control ................................................................................................................ 51
2-82
TX0_DLL_STATUS ............................................................................................................... 51
2-83
TX1_DLL_STATUS ............................................................................................................... 51
2-84
RX0_DLL_STATUS ............................................................................................................... 51
2-85
RX1_DLL_STATUS ............................................................................................................... 51
2-86
CH0_TESTFAIL_ERR_COUNTER ............................................................................................. 51
2-87
CH1_TESTFAIL_ERR_COUNTER ............................................................................................. 51
2-88
STCI_CONTROL_STATUS ...................................................................................................... 52
2-89
TESTCLK_CONTROL ............................................................................................................ 52
2-90
BIDI_CMOS_CONTROL ......................................................................................................... 52
2-91
DEBUG_CONTROL .............................................................................................................. 52
2-92
DUTY_CYCLE_CONTROL ...................................................................................................... 52
3-1
Global Signals ..................................................................................................................... 60
3-2
JTAG Signals ...................................................................................................................... 61
3-3
MDIO Related Signals ............................................................................................................ 61
3-4
Parallel Data Pins ................................................................................................................. 62
3-5
.....................................................................................................
Miscellaneous Pins ...............................................................................................................
Voltage Supply and Reference Pins ............................................................................................
Jitter Cleaner Related Pins ......................................................................................................
Parallel Interface – Valid Signal Operational Mode Definitions .............................................................
TLK3131 Application Mode –vs– Interface Timing Mode Support..........................................................
Worst Case Device Power Dissipation .........................................................................................
Reference Clock Selection – Gigabit Ethernet Mode ........................................................................
Reference Clock Selection – 1X/2X Fibre Channel Mode ...................................................................
Reference Clock Selection – OBSAI Mode ....................................................................................
Reference Clock Selection – CPRI Mode......................................................................................
Reference Clock Selection – 9/10 Bit SERDES Mode – Full Rate (SPEED[1:0] = 00) ..................................
Reference Clock Selection – 9/10 Bit SERDES Mode – Half Rate (SPEED[1:0] = 01) .................................
Reference Clock Selection – 9/10 Bit SERDES Mode – Quarter Rate (SPEED[1:0] = 10) .............................
Reference Clock Selection – 8 Bit SERDES Mode – Full Rate (SPEED[1:0] = 00) .....................................
Reference Clock Selection – 8 Bit SERDES Mode – Half Rate (SPEED[1:0] = 01) .....................................
Reference Clock Selection – 8 Bit SERDES Mode – Quarter Rate (SPEED[1:0] = 10) .................................
Device Mode Configuration ......................................................................................................
Device Test Mode Pin Configuration ...........................................................................................
3-6
3-7
3-8
4-1
4-2
4-3
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
C-1
C-2
8
Serial Side Data/Clock Pins
List of Tables
63
63
64
65
72
79
81
82
83
83
84
84
85
85
86
86
86
98
98
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Single Channel Multi-Rate Transceiver
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1
Introduction
1.1
Features
•
•
•
•
•
•
•
•
•
SLLS957 – DECEMBER 2008
Single Channel 600Mbps to 3.75Gbps
Multi-Rate Transceiver
Supports 1X/2X Fibre Channel (FC), CPRI
(x1/x2/x4), OBSAI (x1/x2/x4), and 1GbE
(1000Base-X) Data Rates
IEEE Compliant 1000Base-X PCS Support
Supports SERDES Operation Modes in 8/10 Bit
Data Modes (TBI and 8 Bit + Control)
Serial Side Transmit De-Emphasis and Receive
Adaptive Equalization to Allow Extended
Backplane Reach
Low Jitter LC Oscillator Jitter-Cleaner Allows
use of Poor Quality REFCLK
Full Datapath Loopback Capability
(Serial/Parallel Side)
Support PRBS 27-1 and 223 – 1 Gen/Verify.
Support standard defined CRPAT, High and
Low Frequency, and Mixed Freq Testing.
GMII/RGMII: HSTL Class 1 I/O With On-Chip
Termination: Programmable Input and 50Ω
Output (1.5 and 1.8V Power Supply)
1.2
•
GMII/RGMII: Source And Data Centered I/O
Timing Modes
Supports Jumbo Packet (9600 byte maximum)
Operation.
MDIO: IEEE 802.3 Clause 22 Compliant
Management Data Input / Output Interface
Modes (Either 1.2V or 2.5V MDIO I/O)
1.2V Core, 1.5V/1.8V HSTL I/O Supply, and 2.5V
LVCMOS I/O Supply
JTAG: IEEE 1149.1/1149.6 Test Interface
±200 ppm Clock Tolerance in 1000Base-X
Receive Datapaths
90 nm Advanced CMOS Technology
Package: PBGA, 13×13mm, 144 Ball, 1mm
Pitch
700mW Maximum Power Dissipation at 1CH
3.75 Gbps (1.5V HSTL Mode, Input HSTL
Termination Disabled)
Asymmetric RX/TX Rates Supported
Industrial Ambient Operating Temperature
(–40°C to 85°C) at Full Rate
•
•
•
•
•
•
•
•
•
•
Pin Out
TLK3131
(R)GMII
TXD (7..0)
TXC (4,0)
TDP /N
RXCLK
RDP /N
RXD (7..0)
1
1
Serial I/F
TXCLK
RXC (4,0)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
1.3
www.ti.com
Description
The TLK3131 is a flexible single channel configurable serial transceiver. It can be configured to be
compliant with the 1000Base-X 1Gbps Ethernet Specification (Auto-Negotiation not supported). The
TLK3131 provides high-speed bi-directional point-to-point data transmissions with up to 7.5 Gbps of raw
data transmission capacity. The primary application of this device is in backplanes and front panel
connections requiring 3.75Gbps connections over controlled impedance media of approximately 50Ω. The
transmission media can be printed circuit board (PCB) traces, copper cables or fiber-optical media. The
ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media
and the noise coupling into the lines.
The TLK3131 performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions
for a physical layer interface. The TLK3131 also provides 1000Base-X (PCS) layer functionality described
in Clause 36 of 802.3-2002. The serial transmitter is implemented using differential Current Mode Logic
(CML) with integrated termination resistors.
Figure 1-1 shows an example system block diagram for TLK3131 used to provide the Physical Coding
Sublayer to Coarse Wave-length Division Multiplexed optical transceiver or parallel optics.
Many common applications may be enabled by way of externally available control pins. Detailed control of
the TLK3131 is available by way of accessing a register space of control bits available through a two-wire
access port called the Management Data Input/Output (MDIO) interface.
The PCS (Physical Coding Sublayer) functions such as the CTC FIFO are designed to be compliant for an
1000Base-X PCS link. However, each of the PCS functions may be disabled or bypassed until the
TLK3131 is operating at its most basic state, that of a simple single channel 10-bit SERDES suitable for a
wide range of applications such as CPRI or OBSAI wireless infrastructure links.
The differential output swing for the TLK3131 is suitable for compliance with IEEE 802.3 Gigabit Ethernet
links, which is also suitable for CPRI LV serial links. The TLK3131 provides for setting larger output signal
swing suitable for CPRI HV links by setting an appropriate register bit available though MDIO.
1
TCLK
TD(7:0)
1
1
TC(4,0)
TLK3131
Parallel I/F
Serial I/F
Backplane
1
Serial I/F
Parallel I/F
Line Card
MAC/
Packet
Processor
CWDM or
Parallel
Optics
TLK3131
RC(4,0)
RCLK
RD(7:0)
Figure 1-1. System Block Diagram – PCS
10
Introduction
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Single Channel Multi-Rate Transceiver
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SLLS957 – DECEMBER 2008
REF_SEL[1:0]
REFCLK_P
00
REFCLK_N
01
1X
REFCLK
REFCLK
Divider
REF_DIV[6:0]
Jitter Cleaner
PLL Core
PLL
Feedback
Divider
FB_DIV[6:0]
RXBCLK[0]
TX_SEL[1:0]
First PLL Output
Divider
RXTX_DIV[6:0]
SERDES TX
00
01
REFCLK_TX
PLL
10
P2S
11
TX0P/N
SERDES RX
00
01
REFCLK_RX
PLL
10
S2P
11
00
RXBYTE_CLK
01
10
11
Second PLL
Output
Divider
RXB_DIV[6:0]
RXB_SEL[1:0]
00
DELAY_CLK
01
10
11
Third PLL
Output
Divider
DEL_DIV[6:0]
RX0P/N
RX_SEL[1:0]
(2.875 Ghz Min., 3 Ghz Typ., 3.125 Ghz Max.)
DEL_SEL[1:0]
HSTL_2X_CLK
HSTL Output
Divider
HSTL_DIV2[6:0]
10
Fourth PLL
Output
Divider
11
HSTL_DIV1[6:0]
00
01
Note: Default Mux Selects are Underlined.
HSTL_SEL[1:0]
Figure 1-2. Block Diagram – TLK3131 Clocking Architecture
2
Detailed Description
2.1
Clocking Modes
The TLK3131 contains an internal low-bandwidth, low-jitter high quality LC oscillator that may be
configured as a jitter cleaner. The jitter cleaner oscillator has a high frequency narrow band of operation
that may be used to generate all common reference clock frequencies by way of programmable pre-scaler
and post-scaler registers. In this manner a poor quality input reference clock can be input to the jitter
cleaner which will lock to the reference clock and provide a clean reference to the internal SERDES PLLs.
Appendix A defines in detail the clocking possibilities, and device settings.
Alternatively, the jitter cleaner may be used to lock to a recovered byte clock from the RX channel and
remove jitter that may have transferred through the clock/data recovery circuit from the serial data stream
to the recovered byte clock (including parallel output data timing). In this way the recovered byte clock
may be extracted from the serial data stream yet be suitable for use in applications that require a clean
clock source derived from the serial data stream. If the jitter cleaner is used to clean the recovered byte
clock, it may not also be used to clean the input reference clock, and the PLL at the center of the
deserializer core must have a clean low-jitter reference clock from an external clock source, preferably a
low-jitter crystal based oscillator. Also note that the Transmit SERDES macro can run from the cleaned
recovered RX byte clock which allows for the outgoing TX serial data rate to exactly match the incoming
data rate of RX Channel.
The TLK3131 clocking architecture allows for bypass of the JC PLL in cases where power or application
board area is critical.
See Figure 1-2 for a representation of the use of the jitter cleaner in the TLK3131.
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Single Channel Multi-Rate Transceiver
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Operating Frequency Range
The TLK3131 is optimized for operation at a serial data rate of 600 Mbit/s through 3.75 Gbit/s. The
external differential (optionally single ended) reference clock has a large operating frequency range
allowing support for many different applications. The reference clock frequency must be within ±200 PPM
of the incoming serial data rate, and have less than 40ps of jitter. The following table shows a summary of
frequency ranges supported. For more details, see Appendix A. The transmit parallel input clock must be
frequency locked (0 ppm) to the supplied REFCLK frequency.
Table 2-1. Supported Protocol Rates and REFCLK Values
2.3
PROTOCOL
Refclk (MHz)
LINE RATE (Gbps)
1G Ethernet
62.5/125/250
1.25
1X/2X Fibre Channel
53.125/106.25/212.5
2.125
1.0625
OBSAI
76.8/153.6/307.2
3.072
1.536
0.768
CPRI
61.44/122.88/245.76
2.4576
1.2288
0.6144
Generic TBI
50 → 375 MHz
0.600 → 3.75
Generic RTBI
50 → 375 MHz
0.600 → 1.6
Generic NBID/TBID
50 → 375 MHz
0.600 → 3.2
CPRI Latency Support
The TLK3131 has a round trip latency measurement capability to support its use in CPRI applications.
When enabled, the TLK3131 will measure the elapsed time from the transmission of a K28.5 code in a
CPRI frame until the reception of a K28.5 code in the receive path. This measurement result may be read
through an MDIO readable register. The measurement has an accuracy of ±4 ns with the Jitter Cleaner
PLL enabled, and an accuracy of ± two parallel byte clock periods if the Jitter Cleaner PLL is disabled.
2.4
Powerdown Mode
The TLK3131 (through the ENABLE pin and through register control) is capable of going into a low power
quiescent state. In this state, all analog and digital circuitry is disabled.
2.5
Application Examples
TLK3131 supports many different application modes. Detailed register settings per application mode are
shown in Table 2-2. The following application diagrams do not show all possible applications, and are
intended only to illustrate the flexibility of the device.
Figure 2-1 shows the TLK3131 in a single channel SERDES Application. The 1000Base-X PCS layer can
be enabled or disabled. Note that the 8B/10B encoder/decoder functions can either be turned on or turned
off. When turned off, either 5 or 10 bits (DDR/SDR) of data is accepted from and presented to the parallel
side. When the 8B/10B encoder/decoder functions are enabled, 1 bit of control and 8 bits of data are
accepted from and presented to the parallel side using the standardized (R)GMII control characters.
12
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TLK3131
10
10
1
1
P
A
R
A
L
L
E
L
S
E
R
I
A
L
Figure 2-1. Single 10-Bit SERDES Application
Figure 2-2 shows the TLK3131 in a 1000Base-X Remote Loopback Application. It is possible to configure
serial side loopback in SERDES mode.
5/10
P
A
R
A
L
L
E
L
TLK3131
1
S
E
R
I
A
L
PCS CORE
1
Figure 2-2. 1000Base-X – Remote (Serial) Loopback Application
Figure 2-3 shows the TLK3131 in a Local Loopback Application.
5/10
P
A
R
A
L
L
E
L
TLK3131
PCS CORE
S
E
R
I
A
L
1
Figure 2-3. 1000Base-X – Local (Parallel ) Loopback Application
The TLK3131 supports the IEEE 802.3 defined Management Data Input/Output (MDIO) Interface to allow
ease in configuration and status monitoring of the link. The bi-directional data pin (MDIO) must be
externally pulled up to 1.2V or 2.5V (VDDM) per the standard for MDIO.
The TLK3131 supports the IEEE 1149.1/1149.6 defined JTAG test port for ease in board manufacturing
test. It also supports a comprehensive series of built-in tests for self-test purposes including PRBS
generation and verification, CRPAT, Mixed/High/Low Frequency testing.
The TLK3131 operates with a 1.2V core voltage supply, a 1.5/1.8V HSTL I/O voltage supply and a 2.5V
LVCMOS/bias supply.
The TLK3131 is packaged in a 13×13mm, 144-ball, 1mm ball pitch Plastic Ball Grid Array (PBGA)
package and is characterized for operation from –40°C to 85°C Ambient, 105°C Junction, and 5% power
supply variation at the balls of the device unless noted otherwise.
The following block diagram provides a high level description of the TLK3131.
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TXCLK
TXD(7:0)
GMII/
RGMII/
TBI/
RTBI
TX
Serial
I/F
Core
TXC(4,0)
1
TDP
TDN
1000Base-X PCS
1
RDP
RDN
GMII/
RGMII/
RXD(7:0) TBI/
RTBI
RX
RXC(4,0)
RXCLK
TCK
TDI
TMS
JTAG
Jitter
Cleaner
PLL
TRSTN
TDO
PRTAD[4:0]
MDIO
MDIO
MDC
Figure 2-4. TLK3131 Block Diagram
Following is a more detailed block diagram description of the core.
Test
mode
Channel 0
Self
Test
TXCLK
8 Bit
TX
FIFO
TXD[7:0]
8b/
10b
enc
10-bits
TDP0
TDN0
RCLK
RXCLK
8-bits
RXD(7:0)
8b/10b
Decoding
&
Self Test
Verification/
Reporting
RX
FIFO
/
CTC
10-bits
SERDES
Core
RDP0
RDN0
RCLK
REFCLKP
REFCLKN
Figure 2-5. Detailed 1000Base-X Core Block Diagram
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Parallel
to Serial
Parallel Data In
Multiplying
Clock
Synthesizer
REFCLKP
N/
TDP
D Q
TDN
Baud
Clock
Interpolator
and Clock
Recovery
Recovered
Clock
RCLK
Parallel Data Out
Serial to
Parallel
and
Comma
Detect
RDP
RDN
Figure 2-6. Block Diagram of SERDES Core
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Device Operation Modes
Table 2-2. Device Operation Modes
DEVICE MODE
RGMII
(DDR)
GMII
(SDR)
RTBI
(DDR)
TBI
(SDR)
REBI
(DDR)
NIBBLE_ORDER 17.4
RNBI
(DDR)
NBI
(SDR)
0
TBID
(DDR)
NBID
(DDR)
Clause 22 (1)
MDIO Access Method
DDR_SDR 17.5
EBI
(SDR)
1
0
1
0
1
0
1
0/1
X
0/1
X
0/1
X
0/1
TX_EDGE_MODE 17.1
0/1
RX_EDGE_MODE 17.0
FC_ENC_MODE 17.6
0
COMMA_DET_EN 17.7
PCS_EN 17.3 Logical OR w/CODE pin
0/1
FULL_DDR 17.9
0
1
0/1
0
0/1
1
0/1
1
0
1
0
ENC_DEC_EN 17.2
BUSWIDTH 36864.7
X
X
0
0
1
1
0
0
1
Legend : (X = Don’t Care) — (0 = Must Be Zero) — (1 = Must Be One) — (0/1 = Can Be Either Zero-or-One)
(1)
16
All Clause 22 Registers are per device channel.
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Parallel Interface Modes - Detailed Description
The TLK3131 has several parallel interface modes. The major parallel interface modes of operation are
presented below:
2.7.1
RGMII Mode (Reduced Gigabit Media Independent Interface)
Table 2-3. RGMII – Lane To Functional Pin Mapping
DATA
CHANNEL
NUMBER
TX_EN/TX_ER
CONTROL BIT
(INPUT)
TRANSMIT
DATA NIBBLE
(INPUT)
RX_DV/RX_ER
CONTROL BIT
(OUTPUT)
RECEIVE
CONTROL
NIBBLE
(OUTPUT)
TRANSMIT
CLOCK
(INPUT)
RECEIVE
CLOCK
(OUTPUT)
Channel 0
TXC_[4]
TXD_[3:0]
RXD_[4]
RXD_[3:0]
TXCLK_[0]
RXCLK_[0]
DDR Source Centered Timing
Nibble Order = 1 (Default)
TXCLK_[0]
TXD_[4:0]
{TX_EN,Data0[3:0]}
{TX_EN^TX_ER,
Data0[7:4]}
{TX_EN,Data1[3:0]}
{TX_EN^TX_ER,
Data1[7:4]}
RXCLK_[0]
RXD_[4:0]
{RX_DV,Data0[3:0]}
{RX_DV^RX_ER,
Data0[7:4]}
{RX_DV,Data1[3:0]}
{RX_DV^RX_ER,
Data1[7:4]}
Note: If Nibble Order = 0, the picture is
the same except that
{TX_EN,DataN[3:0]} and
{TX_EN^TX_ER,DataN[7:4]} swap
locations.
Note: If Nibble Order = 0, the picture is
the same except that
{RX_DV,DataN[3:0]} and
{RX_DV^RX_ER,DataN[7:4]} swap
locations.
DDR Source Aligned Timing
Nibble Order = 1 (Default)
TXCLK_[0]
TXD_[4:0]
{TX_EN,Data0[3:0]}
{TX_EN^TX_ER,
Data0[7:4]}
{TX_EN,Data1[3:0]}
{TX_EN^TX_ER,
Data1[7:4]}
RXCLK_[0]
RXD_[4:0]
{RX_DV,Data0[3:0]}
{RX_DV^RX_ER,
Data0[7:4]}
{RX_DV,Data1[3:0]}
{RX_DV^RX_ER,
Data1[7:4]}
Note: If Nibble Order = 0, the picture is
the same except that
{TX_EN,DataN[3:0]} and
{TX_EN^TX_ER,DataN[7:4]} swap
locations.
Note: If Nibble Order = 0, the picture is
the same except that
{RX_DV,DataN[3:0]} and
{RX_DV^RX_ER,DataN[7:4]} swap
locations.
Figure 2-7. RGMII – Individual Channel Byte Ordering – Channel 0 Example
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RTBI Mode (Reduced Ten Bit Interface)
Table 2-4. RTBI – Lane To Functional Pin Mapping
DATA CHANNEL
NUMBER
TRANSMIT DATA 5 BITS
(INPUT)
RECEIVE DATA 5 BITS
(OUTPUT)
TRANSMIT CLOCK
(INPUT)
RECEIVE CLOCK
(OUTPUT)
Channel 0
TXC_[4:0]
RXD_[4:0]
TXCLK_[0]
RXCLK_[0]
DDR Source Centered Timing
(Nibble Order = 0)
DDR Source Centered Timing
(Nibble Order = 1 Default)
TXCLK_[0]
TXCLK_[0]
TXD_[4:0]
Data0[4:0]
Data0[9:5]
RXCLK_[0]
TXD_[4:0]
Data0[9:5]
Data0[4:0]
Data0[9:5]
Data0[4:0]
RXCLK_[0]
RXD_[4:0]
Data0[4:0]
Data0[9:5]
RXD_[4:0]
DDR Source Aligned Timing
(Nibble Order = 0)
DDR Source Aligned Timing
(Nibble Order = 1 Default)
TXCLK_[0]
TXCLK_[0]
TXD_[4:0]
Data0[4:0]
Data0[9:5]
RXCLK_[0]
RXD_[4:0]
TXD_[4:0]
Data0[9:5]
Data0[4:0]
Data0[9:5]
Data0[4:0]
RXCLK_[0]
Data0[4:0]
Data0[9:5]
RXD_[4:0]
Figure 2-8. RTBI – Individual Channel Byte Ordering – Channel 0 Example
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TBI Mode (Ten Bit Interface)
Table 2-5. TBI – Lane To Functional Pin Mapping
DATA CHANNEL
NUMBER
TRANSMIT DATA 10 BITS
(INPUT)
RECEIVE DATA 10 BITS
(OUTPUT)
TRANSMIT CLOCK
(INPUT)
RECEIVE CLOCK
(OUTPUT)
Channel 0
{TXC_[4], TXC_[0],TXD_[7:0]}
{RXC_[4], RXC_[0],RXD_[7:0]}
TXCLK_[0]
RXCLK_ [0]
SDR Rising Edge Aligned Timing
TXCLK_[0]
TXC_[4],TXC_[0],TXD_[7:0]
Data0[9:0]
Data1[9:0]
Data0[9:0]
Data1[9:0]
RXCLK_[0]
RXC_[4],RXC_[0],RXD_[7:0]
SDR Falling Edge Aligned Timing
TXCLK_[0]
TXC_[4],TXC_[0],TXD_[7:0]
Data0[9:0]
Data1[9:0]
Data0[9:0]
Data1[9:0]
RXCLK_[0]
RXC_[4],RXC_[0],RXD_[7:0]
Figure 2-9. TBI – Individual Channel Byte Ordering – Channel 0 Example
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GMII Mode (Gigabit Media Independent Interface)
Table 2-6. GMII – Lane To Functional Pin Mapping
DATA
CHANNEL
NUMBER
TX_EN
CONTROL
BIT
(INPUT)
TX_ER
CONTROL
BIT
(INPUT)
TRANSMIT
DATA BYTE
(INPUT)
RX_DV
CONTROL
BIT
(OUTPUT)
RX_ER
CONTROL BIT
(OUTPUT)
RECEIVE
DATA BYTE
(OUTPUT)
TRANSMIT
CLOCK
(INPUT)
RECEIVE
CLOCK
(OUTPUT)
Channel 0
TXC_[0]
TXC_[4]
TXD_[7:0]
RXC_[0]
RXC_[4]
RXD_[7:0]
TXCLK_[0]
RXCLK_[0]
SDR Rising Edge Aligned Timing
TXCLK_[0]
TXC_[0],TXC_[4],TXD_[7:0]
{TX_EN,TX_ER,Data0[7:0]}
{TX_EN,TX_ER,Data1[7:0]}
{RX_DV,RX_ER,Data0[7:0]}
{RX_DV,RX_ER,Data1[7:0]}
RXCLK_[0]
RXC_[0],RXC_[4],RXD_[7:0]
SDR Falling Edge Aligned Timing
TXCLK_[0]
TXC_[0],TXC_[4],TXD_[7:0]
{TX_EN,TX_ER,Data0[7:0]}
{TX_EN,TX_ER,Data1[7:0]}
{RX_DV,RX_ER,Data0[7:0]}
{RX_DV,RX_ER,Data1[7:0]}
RXCLK_[0]
RXC_[0],RXC_[4],RXD_[7:0]
Figure 2-10. GMII – Individual Channel Byte Ordering – Channel 0 Example
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EBI Mode (Eight Bit Interface)
Table 2-7. EBI – Lane To Functional Pin Mapping
DATA CHANNEL
NUMBER
TRANSMIT DATA 8 BITS
(INPUT)
RECEIVE DATA 8 BITS
(OUTPUT)
TRANSMIT CLOCK
(INPUT)
RECEIVE CLOCK
(OUTPUT)
Channel 0
TXD_[7:0]
RXD_[7:0]
TXCLK_[0]
RXCLK_[0]
SDR Rising Edge Aligned Timing
TXCLK_[0]
TXD_[7:0]
Data0[7:0]
Data1[7:0]
Data0[7:0]
Data1[7:0]
RXCLK_[0]
RXD_[7:0]
SDR Falling Edge Aligned Timing
TXCLK_[0]
TXD_[7:0]
Data0[7:0]
Data1[7:0]
Data0[7:0]
Data1[7:0]
RXCLK_[0]
RXD_[7:0]
Figure 2-11. EBI – Individual Channel Byte Ordering – Channel 0 Example
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REBI Mode (Reduced Eight Bit Interface)
Table 2-8. REBI – Lane To Functional Pin Mapping
DATA CHANNEL
NUMBER
TRANSMIT DATA 4 BITS
(INPUT)
RECEIVE DATA 4 BITS
(OUTPUT)
TRANSMIT CLOCK
(INPUT)
RECEIVE CLOCK
(OUTPUT)
Channel 0
TXD_[3:0]
RXD_[3:0]
TXCLK_[0]
RXCLK_[0]
DDR Source Centered Timing
(Nibble Order = 0)
DDR Source Centered Timing
(Nibble Order = 1 Default)
TXCLK_[0]
TXD_[3:0]
TXCLK_[0]
Data0[3:0]
Data0[7:4]
RXCLK_[0]
RXD_[3:0]
TXD_[3:0]
Data0[3:0]
Data0[7:4]
TXCLK_[0]
RXD_[3:0]
Data0[7:4]
Data0[3:0]
DDR Source Aligned Timing
(Nibble Order = 0)
TXCLK_[0]
Data0[3:0]
Data0[7:4]
RXCLK_[0]
RXD_[3:0]
Data0[3:0]
RXCLK_[0]
DDR Source Aligned Timing
(Nibble Order = 1 Default)
TXD_[3:0]
Data0[7:4]
TXD_[3:0]
Data0[7:4]
Data0[3:0]
Data0[7:4]
Data0[3:0]
RXCLK_[0]
Data0[3:0]
Data0[7:4]
RXD_[3:0]
Figure 2-12. REBI – Individual Channel Byte Ordering – Channel 0 Example
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NBI Mode (Nine Bit Interface Mode)
Table 2-9. NBI – Lane To Functional Pin Mapping
DATA CHANNEL
NUMBER
TRANSMIT DATA 9 BITS
(INPUT)
RECEIVE DATA 9 BITS
(OUTPUT)
TRANSMIT CLOCK
(INPUT)
RECEIVE CLOCK
(OUTPUT)
Channel 0
{TXC_[0],TXD_[7:0]}
{RXC_[0],RXD_[7:0]}
TXCLK_[0]
RXCLK_[0]
SDR Rising Edge Aligned Timing
TXCLK_[0]
TXC_[0],TXD_[7:0]
Data0[8:0] = {Control Bit, Data Byte}
Data1[8:0] = {Control Bit, Data Byte}
Data0[8:0] = {Control Bit, Data Byte}
Data1[8:0] = {Control Bit, Data Byte}
RXCLK_[0]
RXC_[0],RXD_[7:0]
SDR Falling Edge Aligned Timing
TXCLK_[0]
TXC_[0],TXD_[7:0]
Data0[8:0] = {Control Bit, Data Byte}
Data1[8:0] = {Control Bit, Data Byte}
Data0[8:0] = {Control Bit, Data Byte}
Data1[8:0] = {Control Bit, Data Byte}
RXCLK_[0]
RXC_[0],RXD_[7:0]
Figure 2-13. NBI – Individual Channel Byte Ordering – Channel 0 Example
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RNBI Mode (Reduced Nine Bit Interface)
Table 2-10. RNBI – Lane To Functional Pin Mapping
DATA CHANNEL
NUMBER
TRANSMIT DATA 5 BITS
(INPUT)
RECEIVE DATA 5 BITS
(OUTPUT)
TRANSMIT CLOCK
(INPUT)
RECEIVE CLOCK
(OUTPUT)
Channel 0
TXD_[4:0]
RXD_[4:0]
TXCLK_[0]
RXCLK_[0]
DDR Source Centered Timing
(Nibble Order = 0)
DDR Source Centered Timing
(Nibble Order = 1 Default)
TXCLK_[0]
TXD_[4:0]
TXCLK_[0]
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
RXCLK_[0]
RXD_[4:0]
TXD_[4:0]
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
RXD_[4:0]
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
DDR Source Aligned Timing
(Nibble Order = 0)
TXCLK_[0]
TXCLK_[0]
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
RXCLK_[0]
RXD_[4:0]
Data0[4:0] =
{Data Byte[4:0]}
RXCLK_[0]
DDR Source Aligned Timing
(Nibble Order = 1 Default)
TXD_[4:0]
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
TXD_[4:0]
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
RXCLK_[0]
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
RXD_[4:0]
Figure 2-14. RNBI – Individual Channel Byte Ordering – Channel 0 Example
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TBID Mode (Ten Bit Interface DDR)
Table 2-11. TBID – Lane To Functional Pin Mapping
DATA CHANNEL
NUMBER
TRANSMIT DATA 10 BITS
(INPUT)
RECEIVE DATA 10 BITS
(OUTPUT)
TRANSMIT CLOCK
(INPUT)
RECEIVE CLOCK
(OUTPUT)
Channel 0
{TXC_[4], TXC_[0],TXD_[7:0]}
{RXC_[4], RXC_[0],RXD_[7:0]}
TXCLK_[0]
RXCLK_ [0]
DDR Source Centered Timing
TXCLK_[0]
TXC_[4], TXC_[0],
TXD_[7:0]
Data0[9:0]
Data1[9:0]
Data0[9:0]
Data1[9:0]
RXCLK_[0]
RXC_[4], RXC_[0],
RXD_[7:0]
DDR Source Aligned Timing
TXCLK_[0]
TXC_[4], TXC_[0],
TXD_[7:0]
Data0[9:0]
Data1[9:0]
Data0[9:0]
Data1[9:0]
RXCLK_[0]
RXC_[4], RXC_[0],
RXD_[7:0]
Figure 2-15. TBID – Individual Channel Byte Ordering – Channel 0 Example
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2.7.10 NBID Mode (Nine Bit Interface DDR)
Table 2-12. NBID – Lane To Functional Pin Mapping
DATA CHANNEL
NUMBER
TRANSMIT DATA 9 BITS
(INPUT)
RECEIVE DATA 9 BITS
(OUTPUT)
TRANSMIT CLOCK
(INPUT)
RECEIVE CLOCK
(OUTPUT)
Channel 0
{TXC_[0],TXD_[7:0]}
{RXC_[0],RXD_[7:0]}
TXCLK_[0]
RXCLK_ [0]
DDR Source Centered Timing
TXCLK_[0]
TXC_[0], TXD_[7:0]
Data0[8:0] = {Control
Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte}
Data0[8:0] = {Control
Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte}
RXCLK_[0]
RXC_[0], RXD_[7:0]
DDR Source Aligned Timing
TXCLK_[0]
TXC_[0], TXD_[7:0]
Data0[8:0] = {Control
Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte}
Data0[8:0] = {Control
Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte}
RXCLK_[0]
RXC_[0], RXD_[7:0]
Figure 2-16. NBID – Individual Channel Byte Ordering – Channel 0 Example
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2.7.11 Parallel Interface Clocking Modes
The TLK3131 supports source centered timing and source aligned DDR timing on the parallel receive
output bus. TLK3131 also supports rising edge aligned and falling edge aligned SDR timing on the parallel
receive output bus. See Figure 2-17 for more details.
RXCLK
tSETUP
Source Centered (DDR)
RXD
RXC
tHOLD
tHOLD
tSETUP
Data
Data
Source Aligned (DDR)
RXD
RXC
Data
Data
Data
Falling Edge Aligned (SDR)
RXD
RXC
Data
Data
Rising Edge Aligned (SDR)
Data
RXD
RXC
Data
Figure 2-17. Receive Interface Timing – Source Centered/Aligned
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The transmit input timing modes are shown in Figure 2-18. SDR/DDR input timing modes supported are
similar to those supported in the receive direction.
TXCLK
tSETUP
Source Centered (DDR)
TXD
TXC
tSETUP
tHOLD
tHOLD
Data
Data
Source Aligned (DDR)
TXD
TXC
Data
Data
Data
Falling Edge Aligned (Rising Edge Sampled) (SDR)
TXD
TXC
Data
Data
Rising Edge Aligned (Falling Edge Sampled) (SDR)
Data
TXD
TXC
Data
Figure 2-18. Transmit Interface Timing
2.7.12 Parallel to Serial
The parallel-to-serial shift register takes in data and converts it to a serial stream. The shift register is
clocked by the internally generated bit clock, which is 10 times the reference clock (REFCLKP/REFCLKN)
frequency. The least significant bit (LSB) is transmitted first.
2.7.13 Serial to Parallel
Serial data is received on the RDP/RDN pins. The interpolator and clock recovery circuit will lock to the
data stream if the clock to be recovered is within ±200 PPM of the internally generated bit rate clock. The
recovered clock is used to retime the input data stream. The serial data is then clocked into the
serial-to-parallel shift registers. If enabled, the 10-bit wide parallel data is then fed into 8b/10b decoders.
2.7.14 High Speed CML Output
The high speed data output driver is implemented using Current Mode Logic (CML) with integrated pull up
resistors, requiring no external components. The line can be directly coupled or AC coupled. Under many
circumstances, AC coupling is desirable.
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TDP
RDP
50 W transmission line
VDDT 0.8*VDDT
DIR
COUP
50
GND
AC
COUP
50
50 W transmission line
RDN
TDN
MEDIA
TRANSMITTER
RECEIVER
Figure 2-19. Example High Speed I/O AC Coupled Mode
Current Mode Logic (CML) drivers often require external components. The disadvantage of the external
component is a limited edge rate due to package and line parasitic. The CML driver on TLK3131 has
on-chip 50Ω termination resistors terminated to VDDT, providing optimum performance for increased
speed requirements. The transmitter output driver is highly configurable allowing output amplitude and
de-emphasis to be tuned to a channel's individual requirements. Software programmability allows for
flexible output amplitude control. AC Coupled and Direct Coupled modes are supported. When AC
coupling is selected, the receiver input is internally biased 0.8×VDDT which is the optimum voltage for
input sensitivity. As the input and output references are derived from VDDT, the tolerance of this supply
will dominate the accuracy of the internal reference.
When transmitting data across long lengths of PCB trace or cable, the high frequency content of the signal
is attenuated due to the skin effect of the media. This causes a “smearing” of the data eye when viewed
on an oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In
order to provide equalization for the high frequency loss, 1-tap finite impulse response (FIR) transmit
de-emphasis is implemented. A highly configurable output driver maximizes flexibility in the end system by
allowing de-emphasis and output amplitude to be tuned to a channel’s individual requirements. A total of
15 de-emphasis settings and 8 output amplitude settings can be independently selected.
VOD (p)
VOD(d)
VCMT
VOD (pd) VOD(pp)
VOD (d)
bit
time
bit
time
VOD(p)
Figure 2-20. Output Differential Voltage With 1-Tap FIR De-emphasis
The level of de-emphasis is programmable via MDIO Register bits. Users can control the strength of the
de-emphasis to optimize for a specific system requirement.
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2.7.15 High Speed Receiver
The high speed receiver conforms to the physical layer requirements of IEEE 802.3ae Clause 47(XAUI),
Gigabit Ethernet, and FibreChannel 1 and 2. Register control gives selection between AC and DC
coupling at the receiver. When the receiver is AC coupled, the termination impedances of the receivers
are configured as 100 Ω with the center tap weakly tied to 0.8×VDDT with a capacitor to create an AC
ground. When the receiver is DC coupled, the common mode will be determined by both receiver and
transmitter characteristics.
The receive channel incorporates an adaptive equalizer. This circuit compensates for channel insertion
loss by amplifying the high frequency components of the signal, reducing inter-symbol interference.
Equalization can be enabled or disabled per register settings. Both the gain and bandwidth of the
equalizer are controlled by the receiver equalization logic. There are ten available equalization settings.
2.7.16 Loopback
Configuration for parallel or serial side loopback is possible.
An external loopback (requiring external connection) is also supported, which can be used with the PRBS
patterns, as well as the CRPAT, Mixed/High/Low Frequency tests.
2.7.17 Link Test Functions
The TLK3131 has an extensive suite of built in test functions to support system diagnostic requirements.
There is a built-in link test generator and verification logic. Several patterns can be selected via the MDIO
that offer extensive test coverage. The patterns are: 27-1 or 223-1 PRBS (Pseudo Random Bit Stream),
CRPAT, high and low and mixed frequency patterns.
2.7.18 MDIO Management Interface
The TLK3131 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of
the IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the
serial links. Normal operation of the TLK3131 is possible without use of this interface. However, some
additional features are accessible only through the MDIO.
The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference
(MDC). The device id and port address are determined by control pins (see Table 3-3).
TLK3131 will respond to MDIO accesses for two channels (channel 0 and channel 1), although there is no
datapath for channel 1.
In Clause 22, the top 4 control pins PRTAD[4:1] determine the device port address. In this mode the 2
individual channels (channel one datapath unusable) in TLK3131 are classified as 2 different ports. So for
any PRTAD[4:1] value there will be 2 ports per TLK3131.
TLK3131 will respond if the 4 MSB’s of PHY address field on MDIO protocol (PA[4:1]) matches
PRTAD[4:1]. The LSB of PHY address field (PA[0]) will determine which channel/port within TLK3131 to
respond to.
If PA[0] = 1b0, TLK3131 Channel 0 will respond.
If PA[0] = 1b1, TLK3131 Channel 1 will respond. (This channel does not have a datapath pinned out, and
is not usable).
Write transactions which address an invalid register or device or a read only register will be ignored. Read
transactions which address an invalid register will return a 0.
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2.7.19 MDIO Protocol Timing
The Clause 22 timing required to read from the internal registers is shown in Figure 2-21. The Clause 22
timing required to write to the internal registers is shown in Figure 2-22.
MDC
Pu1
MDIO
1
0
1
0
PA4
PA0
RA4
32 "1's"
(1)
Read
Code
Start
Preamble
PHY
Addr
0
RA0
REG
Addr
D15
1
D0
Turn
Around
Data
Idle
Note that the 1 in the Turn Around section is externally pulled up, and driven to Z by TLK3131
Figure 2-21. CL22 – Management Interface Read Timing(1)
MDC
MDIO
0
1
0
1
PA [4:0]
RA 4
RA 0
1
0
D15
D0
1
32 "1's"
Write
Code
Start
Preamble
PHY
Addr
REG
Addr
Turn
Around
Data
Idle
Figure 2-22. CL22 - Management Interface Write Timing
The IEEE 802.3 Clause 22 specification defines many of the registers, and additional registers have been
implemented for expanded functionality.
2.7.20 Clause 22 Indirect Addressing
The TLK3131 Register space is divided into two register groups. One register group can be addressed
directly through Clause 22, and one register group can be addressed indirectly through Clause 22. The
register group which can be addressed through Clause 22 indirectly is implemented in vendor specific
register space (16’h9000 onwards). Due to clause 22 register space limitations, an indirect addressing
method is implemented so that this extended register space can be accessed through clause 22. To
access this register space (16’h9000 onwards), an address control register (Reg 30, 5’h1E) should be
written with the register address followed by a read/write transaction to address data register (Reg 31,
5’h1F) to access the contents of the address specified in address control register. Following timing
diagrams illustrate an example write transaction to Register 16’h9000 using indirect addressing in Clause
22.
MDC
MDIO
0
1
0
1
PA [4:0]
5'h1E
PHY
Addr
REG
Addr
1
0
16 'h9000
1
32 "1's"
Preamble
Start
Write
Code
Turn
Around
Data
Idle
Figure 2-23. CL22 – Indirect Address Method – Address Write
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MDC
MDIO
0
1
0
1
PA [4:0]
5'h1F
PHY
Addr
REG
Addr
1
0
DATA
Turn
Around
Data
1
32 "1's"
Write
Code
Start
Preamble
Idle
Figure 2-24. CL22 – Indirect Address Method – Data Write
Following timing diagrams illustrate an example read transaction to read contents of Register 16’h9000
using indirect addressing in Clause 22.
MDC
MDIO
0
1
0
1
PA [4:0]
5'h1E
PHY
Addr
REG
Addr
1
0
1
16 'h9000
32 "1's"
Write
Code
Start
Preamble
Turn
Around
Data
Idle
Figure 2-25. CL22 – Indirect Address Method – Address Write
MDC
Pu1
MDIO
1
0
1
0
PA4
PA0
5’h1F
32 "1's"
Preamble
(1)
Start
Read
Code
PHY
Addr
REG
Addr
0
D15
D0
1
Turn
Around
Data
Idle
Note that the 1 in the Turn Around section is externally pulled up, and driven to Z by TLK3131.
Figure 2-26. CL22 – Indirect Address Method – Data Read(1)
The IEEE 802.3 Clause 22/45 specification defines many of the registers, and additional registers have
been implemented for expanded functionality.
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PROGRAMMERS REFERENCE
Following registers can be addressed directly only through Clause 22. These bits are per channel basis.
Channel identification is based on PHY (Port) address field.
Channel 0 can be accessed by setting LSB of PHY address to 0.
Channel 1 can be accessed by setting LSB of PHY address to 1 (access is only required during device
initialization per the software bring up procedure).
Table 2-13. PHY_CONTROL_1
ADDRESS: 0x00
BIT(s)
DESCRIPTION
ACCESS
Reset
1 = PHY reset (including all registers and Tx/Rx datapath)
0 = Normal operation (Default 1’b0)
0.14
Loopback
Logically OR’ed with PLOOP
1 = Enable loop back mode. In this mode, serial output of the channel is looped
back onto serial input.
0 = Disable loop back mode (Default 1’b0)
RW
0.13
Speed Selection(LSB)
This is the least significant bit of the speed selection bits (MSB is 0.6). {0.6,0.13} =
2’b10 1000Base-X Rate This bit always reads 0.
RO
0.12
Auto-Negotiation Enable
Always reads 0. (Auto-Negotiation not supported)
RO
0.11
Power Down
Setting this bit high powers down the channel, with exception that MDIO interface
stays active. Serdes PLL’s can be shut down by de-asserting bits 36864.12 and
36864.4. Jitter cleaner PLL can be shut down by de-asserting 37127.15
1 = Power Down mode is enabled.
0 = Normal operation (Default 1’b0)
RW
0.10
Isolate
Setting this bit high isolates the channel from the parallel interface. Inputs are
ignored; Outputs are set to high impedance. 1 = Isolate is enabled 0 = Normal
operation (Default 1’b0)
RW
0.9
Restart Auto-Negotiation
Always reads 0. (Auto-Negotiation not supported)
RO
0.8
Duplex Mode
Always reads 1. (Only Full duplex supported)
RO
0.7
Collision Test
Not Applicable. Read will return a 0.
RO
Speed Selection (MSB)
This is the most significant bit of the speed selection bits (LSB is 0.13).
{0.6,0.13} = 2’b10 1000Base-X Rate. This bit always reads 1
RO
0.15
0.6
(1)
DEFAULT: 0x0140
NAME
RW
SC (1)
After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.
Table 2-14. PHY_STATUS_1
ADDRESS: 0x01
BIT(s)
NAME
DEFAULT: 0x0101
DESCRIPTION
ACCESS
1.15
1000Base-T4
Always reads 0
RO
1.14
100Base-X FD
Always reads 0
RO
1.13
100Base-X HD
Always reads 0
RO
1.12
10Mb/s FD
Always reads 0
RO
1.11
10Mb/s HD
Always reads 0
RO
1.10
100Base-T2 FD
Always reads 0
RO
1.9
100Base-T2 HD
Always reads 0
RO
1.8
Extended Status
Read will return 1 indicating extended status information is held in register 0x0F.
RO
1.6
MF Prea Supp
Read will return 0 indicating MDIO doesn’t accept command without preceding preamble
(minimum 32 1’s). Writes will be ignored
RO
1.5
AN Complete
Always reads 0 (AN not supported)
RO
1.4
Remote Fault
Always reads 0
RO
1.3
AN Ability
Read will return 0, indicating that Auto negotiation is not supported
RO
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Table 2-14. PHY_STATUS_1 (continued)
ADDRESS: 0x01
BIT(s)
DEFAULT: 0x0101
NAME
DESCRIPTION
ACCESS
1.2
Link Status
Read will return the Link Status and is valid only when device is in GMII/RGMII mode or
when bit 17.7 is set in Non-GMII/RGMII modes. Note: Link status will always indicate high
when in loopback. In remote loopback mode, the bit represents the normal bit function.
1 = Link UP
0 = Link DOWN
1.1
Jabber Detect
Always reads 0
RO
1.0
Extended Capability
Read will return 1 indicating extended register capability
RO
RO/LL
Table 2-15. PHY_IDENTIFIER_1
ADDRESS: 0x02
BIT(s)
2.15.0
NAME
OUI c:r
DEFAULT: 0x4000
DESCRIPTION
ACCESS
Organizationally unique identifier.
RO
Table 2-16. PHY_IDENTIFIER_2
ADDRESS: 0x03
BIT(s)
3.15:0
NAME
OUI c:r
DEFAULT: 0x50E0
DESCRIPTION
ACCESS
Device identifier. Manufacturer model and revision number
RO
Table 2-17. PHY_EXT_STATUS
ADDRESS: 0x0F
BIT(s)
NAME
DEFAULT: 0x8000
DESCRIPTION
ACCESS
15.15
1000Base-X FD
Always reads 1, indicating device supports Full Duplex mode.
RO
15.14
1000Base-X HD
Read will return 0, writes will be ignored.
RO
15.13
1000Base-T FD
Read will return 0, writes will be ignored.
RO
15.12
1000Base-T HD
Read will return 0, writes will be ignored.
RO
Table 2-18. PHY_CH_CONTROL_1
ADDRESS: 0x10
BIT(s)
DEFAULT: 0x0000
DESCRIPTION
ACCESS
16.15
Reserved
Reserved, This value always reads zero.
RW/SC
16.11
Datapath reset control
1 = Resets channel logic excluding MDIO registers (Resets Tx and Rx datapath)
RW/SC
Receive Parallel Output clock
select
00 = Selects SERDES TX clock (Default 2’b00)
01 = Selects Jitter cleaned clock(Selecting the jitter cleaned clock while the jitter
cleaner PLL is disabled is not recommended)
10 = Selects SERDES RX clock
11 = Reserved
RW
16.8
Farend Loopback
Logically OR’ed with SLOOP
When asserted high the data presented at the serial receive interface is looped
back to the serial transmit interface of the channel via the deserializer, the
serializer and if enabled the PCS function. If 1GX PCS is not enabled, the
incoming datarate must be frequency locked (ppm 0) with REFCLK.
Also referred to as remote loopback.
0 = Farend Loopback is disabled. (Default 1’b0)
1 = Farend loopback is enabled.
RW
16.7
PRBS Verifier Enable
A logic 1 enables the PRBS (2^7) verifier in the receive datapath.
Logically OR'ed with the PRBSEN pin. (Default 1’b0)
RW
16.6
PRBS Generator Enable
A logic 1 enables the PRBS (2^7) generator in the transmit datapath. Logically
OR'ed with the PRBSEN pin. (Default 1’b0)
RW
16.5
Channel sync freeze control
When set, freezes last acquired word alignment. (Default 1’b0)
RW
16.4
Test Pattern Generator Enable When high activates the generator selected by bits 16.2:0. (Default 1’b0)
16.10:9
34
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Detailed Description
RW
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Table 2-18. PHY_CH_CONTROL_1 (continued)
ADDRESS: 0x10
BIT(s)
16.3
16.2:0
NAME
DEFAULT: 0x0000
DESCRIPTION
ACCESS
Test Pattern Verifier Enable
When high activates the verifier selected by bits 16.2:0. (Default 1’b0)
RW
Pattern Select
Test Pattern Selection
000 = High Frequency Test Pattern (Default 3’b000)
001 = Low Frequency Test Pattern
010 = Mixed Frequency Test Pattern
011 = CRPAT Long
100 = CRPAT Short
Others = Reserved
RW
Table 2-19. PHY_CH_CONTROL_2
ADDRESS: 0x11
BIT(s)
17.15
NAME
DEFAULT: 0x3590
DESCRIPTION
ACCESS
Reserved
Reserved, This value always reads zero.
17.14
Sync Status Override
1 = Causes an override of the sync state of 1000Base-X synchronization state
machine to reflect a “1” in the sync_status (1.2) bit.
0 = Original (normal operation) sync_status value is represented in bit 1.2. (Default
1’b0)
RW
17.13
TX PMA Bit Order
When asserted, allows the ten bits of data given to the parallel side of the
SERDES TX macro to be flipped. This is normally set since the SERDES transmits
MSB first, and the 1000Base-X standard requires LSB to be transmitted first. For
standard based operation, the customer may leave this bit alone. (Default 1’b1)
RW
17.12
RX PMA Bit Order
When asserted, allows the ten bits of data received from the parallel side of the
SERDES RX macro to be flipped. This is normally set since the SERDES receives
MSB first, and the 1000Base-X standard requires LSB to be received first. For
standard based operation, the customer may leave this bit alone. (Default 1’b1)
RW
17.11
LOS Override
1 = Overrides Loss of signal (LOS) status coming from SERDES. Synchronization
turned on irrespective of LOS status
0 = Synchronization depends on LOS status. (Default 1’b0)
RW
17.10
CTC enable
1 = Clock Tolerance Compensation on receive datapath is enabled (Default 1’b1)
0 = Clock Tolerance Compensation on receive datapath is disabled
RW
17.9
Full DDR mode
1 = Sets the device in full DDR mode (NBID/TBID modes)
0 = Disables full DDR mode (Default)
RW
17.8
RCLK out enable
1 = Enables RX_CLK out (Default 1’b1)
0 = Disables RX_CLK out.
RX_CLK will be low when this bit is de-asserted
RW
17.7
Comma enable
1 = Enables comma detection (Default 1’b1)
0 = Disables comma detection
RW
17.6
FC enable
1 = Enables FC_PH overlay detection. This is needed in 1x/2x Fiber channel mode
to allow proper detection of EOF 8B/10B disparity
0 = Disables FC_PH overlay detection (Default 1’b0)
RW
17.5
Data mode
Valid only when 17.9 (Full DDR mode) is LOW.
1 = Enables DDR data mode on parallel Transmit and Receive directions (data
clocked on both rising and falling edge)
0 = Enables SDR data mode on parallel Transmit and Receive directions (data is
clocked only on rising edge or only on falling edge) (Default 1’b0)
RW
17.4
Nibble order
Applicable only in non FULL DDR modes
1 = LSB on rising edge followed by MSB on falling edge (Default 1’b1)
0 = MSB on rising edge followed by LSB on falling edge
RW
17.3
PCS TX_RX Enable
1 = Enables 1000Base-X PCS Tx and PCS Rx functions
0 = Disables 1000Base-X PCS Tx Function (Default 1’b0)
RW
17.2
Encode Decode Enable
0 = 8B/10B encode decode functions are disabled (Default 1’b0)
1 = 8B/10B encode decode functions are enabled
RW
TX Edge Mode
When channel is in DDR mode
1 = Source aligned timing on transmit parallel interface.
0 = Source centered timing on transmit parallel interface. Data is latched on both
rising and falling clock edges.
RW
17.1
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Table 2-19. PHY_CH_CONTROL_2 (continued)
ADDRESS: 0x11
BIT(s)
DEFAULT: 0x3590
NAME
DESCRIPTION
ACCESS
When channel is in SDR mode
1 = Rising edge align mode. Incoming parallel data is aligned to rising edge of
parallel input clock. Internally data is latched at the falling edge of the clock.
0 = Falling edge align mode. Incoming data is aligned to falling edge of parallel
input clock. Internally data is latched at the rising edge of the clock
17.0
When channel is in DDR mode
1 = Source aligned timing on receive parallel interface. Data changes at clock
edge.
0 = Source centered timing on receive parallel interface.
RX Edge Mode
RW
When channel is in SDR mode
1 = Rising edge align mode. Outgoing parallel data is aligned to the rising edge of
the parallel output clock
0 = Falling edge align mode. Outgoing parallel data is aligned to the falling edge of
the parallel output clock
Table 2-20. PHY_RX_CTC_FIFO_STATUS
ADDRESS: 0x12
BIT(s)
NAME
DEFAULT: 0x0000
DESCRIPTION
ACCESS
18.15
RX_CTC_Reset
When high indicates overflow or underflow has occurred in CTC FIFO and FIFO
has been reset.
18.14
RX_CTC_Insert
When high indicates RX CTC has inserted at least one ordered set.
18.13
RX_CTC_Delete
When high indicates RX CTC has deleted at least one ordered set.
RO/LH
Table 2-21. PHY_TX_CTC_FIFO_STATUS
ADDRESS: 0x13
BIT(s)
19.15
NAME
TX_FIFO_Reset_1Gx
DEFAULT: 0x0000
DESCRIPTION
ACCESS
When high indicates collision has occurred in TX FIFO and the FIFO is reset in 1gx
mode. Valid in Non-NBID, Non-TBID modes.
RO/LH
Table 2-22. PHY_TX_WIDE_FIFO _STATUS
ADDRESS: 0x14
BIT(s)
NAME
DEFAULT: 0x0000
DESCRIPTION
ACCESS
20.15
TX_WIDE_FIFO_Overflow
When high indicates Overflow condition has occurred in TX WIDE FIFO. Valid
only when device is in NBID/TBID modes.
20.14
TX_WIDE_FIFO_Underflow
When high indicates Underflow condition has occurred in TX WIDE FIFO. Valid
only when device is in NBID/TBID modes.
RO/LH
Table 2-23. PHY_TEST_PATTERN_SYNC_STATUS
ADDRESS: 0x15
BIT(s)
NAME
DEFAULT: 0x0000
DESCRIPTION
ACCESS
21.1
Test Pattern Sync
When high indicates alignment has been determined and a correct pattern has been
received for fixed test patterns.
21.0
CRPAT Sync
When high indicates alignment has been determined and a correct pattern has been
received for continuous test patterns.
RO
Table 2-24. PHY_TEST_PATTERN_COUNTER
ADDRESS: 0x16
BIT(s)
22.15:0
36
NAME
Fixed Test Pattern
Error Counter
Detailed Description
DEFAULT: 0xFFFD
DESCRIPTION
ACCESS
This counter reflects error count for high, Mixed, and Low Frequency test patterns. Counter
increments for each received character that has an error. Counter clears upon read.
COR
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Table 2-25. PHY_CRPAT_PATTERN_COUNTER_1 (1)
ADDRESS: 0x17
BIT(s)
NAME
23.15:0
CRPAT Error
counter[31:16]
(1)
DEFAULT: 0xFFFF
DESCRIPTION
ACCESS
This counter reflects MSW part of error count for CRPAT Frequency test pattern. Counter
increments for each received character that has an error. Counter clears upon read.
COR
User has to make sure that register 23 is read first and then register 24. If user reads register 24 before reading register 23, then the
count value read through register 24 may not be correct.
Table 2-26. PHY_CRPAT_PATTERN_COUNTER_2 (1)
ADDRESS: 0x18
(1)
BIT(s)
NAME
24.15:0
CRPAT Error
counter[15:0]
DEFAULT: 0xFFFD
DESCRIPTION
ACCESS
This counter reflects LSW part of error count for CRPAT Frequency test pattern. Counter
increments for each received character that has an error. Counter clears upon read.
COR
User has to make sure that register 23 is read first and then register 24. If user reads register 24 before reading register 23, then the
count value read through register 24 may not be correct.
Table 2-27. PHY_TEST_MODE_CONTROL
ADDRESS: 0x1B
BIT(s)
27.15
27.14:12
NAME
DEFAULT: 0x7000
DESCRIPTION
ACCESS
Reserved
Reserved, This value always reads zero.
Test Mux Select
Mux control to select debug signals onto test mux data pins. For TI test purposes only
RW/SC
RW
Table 2-28. PHY_CHANNEL_STATUS
ADDRESS: 0x1C
BIT(s)
NAME
DEFAULT: 0x0000
DESCRIPTION
ACCESS
28.15
Signal Detect
When high, indicates that the SERDES detected valid signal.
28.13
Encoder Invalid Code
Word
RO/LL
When high, indicates that the 1000Base-X encoder received an invalid control word.
28:12
Decoder Invalid Code
Word
When high, indicates that the 1000Base-X decoder received an invalid code word.
RO/LH
Table 2-29. PHY_PRBS_HIGH_SPEED_TEST_COUNTER
ADDRESS: 0x1D
BIT(s)
29.15:0
NAME
PRBS High Speed
Test Counter
DEFAULT: 0xFFFD
DESCRIPTION
ACCESS
This counter reflects errors for PRBS (2^7) test pattern verification . Counter increments
by one for each received character that has error. This counter saturates at 16’hffff.
When read, it resets to zero and continues to count.
COR
Table 2-30. PHY_EXT_ADDRESS_CONTROL
ADDRESS: 0x1E
BIT(s)
30.15:0
NAME
Ext address control
DEFAULT: 0x0000
DESCRIPTION
ACCESS
This register should be written with the extended register address to be written/read.
Contents of address written in this register can be accessed from Reg 31 (0x1F).
RW
Table 2-31. PHY_EXT_ADDRESS_DATA
ADDRESS: 0x1F
BIT(s)
31.15:0
NAME
Ext address data
register
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DEFAULT: 0x0000
DESCRIPTION
ACCESS
This register contains the data associated with the register address written in Register
30 (0x1E)
RW
Detailed Description
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Single Channel Multi-Rate Transceiver
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2.9
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Top Level Programmers Reference
Following registers can be addressed indirectly through Clause 22.
Table 2-32. SERDES_PLL_CONFIG
ADDRESS: 0x9000
BIT(s)
DEFAULT: 0x1515
NAME
DESCRIPTION
ACCESS
Loop Bandwidth
RX(LB_RX)
SERDES RX PLL Bandwidth settings
00 = Applicable when JC PLL is not engaged
01 = Reserved
10 = Reserved
11 = Applicable when JC PLL is engaged
RW
36864. 12
ENPLL_RX
0 = Disables PLL in SERDES RX
1 = Enable PLL in SERDES RX
RW
36864.11:8
PLL Multiplier factor RX
(MPY_RX)
SERDES RX PLL multiplier setting
See Table 2-33
RW
BUSWIDTH
1 = 8 bit mode. Applicable for only EBI and REBI modes
0 = 10 Bit mode. Applicable for all other modes
RW
Loop Bandwidth TX
(LB_TX)
SERDES TX PLL Bandwidth settings
00 = Applicable when JC PLL is not engaged
01 = Reserved
10 = Reserved
11 = Applicable when JC PLL is engaged
RW
ENPLL_TX
0 = Disables PLL in SERDES TX
1 = Enable PLL in SERDES TX
RW
PLL Multiplier factor TX
(MPY_TX)
SERDES TX PLL multiplier setting
See Table 2-33
RW
36864.14:13
36864.7
36864.6:5
36864.4
36864. 3:0
Table 2-33. PLL Multiplier Control
36864[11:8]/ 36864[3:0]
36864[11:8]/ 36864[3:0]
VALUE
PLL MULTIPLIER FACTOR
VALUE
PLL MULTIPLIER FACTOR
0000
4x
1000
15x
0001
5x
1001
20x
0010
6x
1010
25x
0011
Reserved
1011
Reserved
0100
8x
1100
Reserved
0101
10x
1101
50x
0110
12x
1110
60x
0111
12.5x
1111
Reserved
Table 2-34. SERDES_RATE_CONFIG_TX_RX
ADDRESS: 0x9001
BIT(s)
38
NAME
DEFAULT: 0x0000
DESCRIPTION
ACCESS
36865.15:14
RATE_0_TX
TX Ch 0 Operating rate
00 = Full rate (2 data samples/output per PLL output clock cycle)
01 = Half rate (1 data sample/output per PLL output clock cycle)
10 = Quarter rate (1 data sample/output per 2 PLL output clock cycle)
11 = Reserved
36865.13:12
Reserved
Reserved
RW
36865.7:6
RATE_0_RX
RX Ch 0 Operating rate
00 = Full rate (2 data samples/output per PLL output clock cycle)
01 = Half rate (1 data sample/output per PLL output clock cycle)
10 = Quarter rate (1 data sample/output per 2 PLL output clock cycle)
11 = Reserved
RW
36865.5:4
Reserved
Reserved
RW
Detailed Description
RW
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Table 2-35. SERDES_RX0_CONFIG (1)
ADDRESS: 0x9002
BIT(s)
DESCRIPTION
ACCESS
36866.15:12
EQUALIZER
Adaptive equalization control
0000 = Adaptive equalization disabled. Equalizer provides flat response at maximum
gain.
0001 = Full adaptive equalization
0010 to 1111 = Reserved
36866.11:9
CDR
Clock data recovery algorithm selection
RW
INVPAIR
1 = Inverts polarity of RXP and RXN
RW
LOS
00 =
01 =
10 =
11 =
RW
ALIGN
Receiver symbol alignment selection
00 = Alignment disabled.
01 = Comma alignment enabled
10 = Symbol alignment will be performed by one bit position when this mode is
selected (i.e ALIGN changes from 00 to 10)
11= Reserved
RW
TERM
Receive Termination selection
00 = Common point connected to VDDT (For DC Coupled Systems)
01 = Common point set to 0.8 VDDT (For AC Coupled Systems)
10 = Reserved
11 = Reserved
RW
36866.1
ENTEST
1= Enables test modes specified in TESTCFG (Register 0x9012)
RW
36866.0
ENRX
1 = Enables receiver
0 = Disables receiver
RW
36866.8
36866.7:6
36866.5:4
36866.3:2
(1)
DEFAULT: 0x0001
NAME
Loss of signal detection disabled
Reserved
Loss of signal detection enabled with threshold in the range of 85-175 mVdfpp.
Reserved.
RW
These are SERDES receiver control bits for channel 0.
Table 2-36. SERDES_RX1_CONFIG (1)
ADDRESS: 0x9004
BIT(s)
36868.15:12
(1)
DEFAULT: 0x0001
NAME
Reserved
DESCRIPTION
ACCESS
Reserved
RW
These are SERDES receiver control bits for channel 1.
Table 2-37. SERDES_TX0_CONFIG
ADDRESS: 0x900A
BIT(s)
NAME
DEFAULT: 0x0001
DESCRIPTION
ACCESS
SWING
Transmitter Output swing control for SERDES transmitter.
Refer Table 2-40: Output Swing Control
If swing is set to 750mV or more, CM bit (36874.8) needs to be set to 1.
If swing is set to 625 mV or less, CM bit (36874.8) needs to be set to 0.
RW
CM
1 = Applicable for SWING settings 750 mV or more.
0 = Applicable for SWING settings 625 mV or less.
RW
DE-EMPHASIS
Transmitter Differential output De-emphasis control
Refer Table 2-39: Transmit De-emphasis Control
RW
36874.3
INVPAIR
Transmitter Polarity
1 = Inverted polarity. TXP considered negative data and TXN
considered positive data
0 = Normal polarity. TXP considered positive data and TXN considered
negative data
RW
36874.1
ENTEST
1= Enables test modes specified in TESTCFG (Register 0x9011)
RW
ENTX
1 = Enables transmitter
0 = Disables transmitter
RW
36874.11:9
36874.8
36874.7:4
36874.0
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Table 2-38. SERDES_TX1_CONFIG
ADDRESS: 0x900C
BIT(s)
36876.11:3, 1:0
DEFAULT: 0x0001
NAME
Reserved
DESCRIPTION
ACCESS
Reserved
RW
Table 2-39. Transmit De-emphasis Control
36874/36876[7:4]
VALUE
AMPLITUDE REDUCTION
%
dB
0000
0
0
0001
4.76
0010
9.52
0011
VALUE
AMPLITUDE REDUCTION
%
dB
1000
38.08
–4.16
–0.42
1001
42.85
–4.86
–0.87
1010
47.61
–5.61
14.28
–1.34
1011
52.38
–6.44
0100
19.04
–1.83
1100
57.14
–7.35
0101
23.8
–2.36
1101
61.9
–8.38
0110
28.56
–2.92
1110
66.66
–9.54
0111
33.32
–3.52
1111
71.42
–10.87
Table 2-40. Output Swing Control
36874/36876[11:9]
40
Detailed Description
Value
Amplitude (mVdfpp)
Value
000
125
100
Amplitude (mVdfpp)
750
001
250
101
1000
010
500
110
1250
011
625
111
1375
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Table 2-41. SERDES_TEST_CONFIG_TX (1)
ADDRESS: 0x9011
BIT(s)
36881.10:8
DESCRIPTION
ACCESS
Reserved
Reserved for TI test.
RW
LOOPBACK_TX
00 =
01 =
10 =
11 =
RW
CLKBYPASS_TX
PLL Bypass control in test mode
00 = No bypass
01 = Reserved
10 = Functional bypass. Macros run using TESCLKT
11 = Refclk observe (Reserved. For TI purposes only)
RW
36881.3
ENRXPATT_TX
0 – Disables test pattern verification in SERDES TX macro.
1 – Enables test pattern verification in SERDES TX macro.
RW
36881.2
ENTXPATT_TX
0 – Disables test pattern generation in SERDES TX macro.
1 – Enables test pattern generation in SERDES TX macro.
RW
TESTPATT_TX
Valid when ENTXPATT_TX, ENRXPATT_TX, ENTEST_TX are set
00 = Reserved (Default)
01 = Clock pattern (Half baud clock pattern with period of 2UI)
10 = 27 – 1 PRBS pattern
11 = 223 – 1 PRBS pattern
RW
36881.7:6
36881.5:4
36881.1:0
(1)
DEFAULT: 0x0000
NAME
Disabled
Pad loopback. For TI purposes only
Inner loopback (CML driver disabled)
Inner loopback (CML driver enabled)
Above control bits are only for vendor testing only. Customer should leave them at their default values
Table 2-42. SERDES_TEST_CONFIG_RX (1)
ADDRESS: 0x9012
BIT(s)
36882.10:8
DESCRIPTION
ACCESS
Reserved
Reserved for TI test.
RW
LOOPBACK_RX
00 =
01 =
10 =
11 =
RW
CLKBYPASS_RX
PLL Bypass control in test mode
00 = No bypass
01 = Reserved
10 = Functional bypass. Macros run using TESCLKR
11 = Refclk observe (Reserved. For TI purposes only)
RW
36882.3
ENRXPATT_RX
0 – Disables test pattern verification in SERDES RX macro.
1 – Enables test pattern verification in SERDES RX macro.
RW
36882.2
ENTXPATT_RX
0 – Disables test pattern generation in SERDES RX macro.
1 – Enables test pattern generation in SERDES RX macro.
RW
TESTPATT_RX
Valid when ENTXPATT_RX, ENRXPATT_RX, ENTEST_RX are set
00 = Reserved (Default)
01 = Clock pattern (Half baud clock pattern with period of 2UI)
10 = 27 – 1 PRBS pattern
11 = 223 – 1 PRBS pattern
36882.7:6
36882.5:4
36882.1:0
(1)
DEFAULT: 0x0000
NAME
Disabled
Pad loopback. For TI purposes only
Inner loopback (CML driver disabled)
Inner loopback (CML driver enabled)
R
Above control bits are only for vendor testing only. Customer should leave them at their default values
Table 2-43. SERDES_RX0_STATUS (1)
ADDRESS: 0x9013
BIT(s)
NAME
DEFAULT: 0x0000
DESCRIPTION
ACCESS
36883.3
LOSDTCT
When HIGH indicates Loss of Signal condition is detected for RX CH 0
RO
36883.2
ODDCG
LOW when SYNC is HIGH. After that toggles every cycle.
RO
36883.1
SYNC
When comma detection is enabled, this bit is HIGH when an aligned comma is received.
RO
36883.0
RX CH 0
TESTFAIL
When HIGH, indicates an error occurred during test pattern verification for SERDES RX CH 0.
This bit status is valid only when SERDES RX test pattern verification bits are set
RO
(1)
Above status bits are only for Receive CH 0.
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Table 2-44. SERDES_RX1_STATUS
ADDRESS: 0x9014
BIT(s)
36884.3:0
DEFAULT: 0x0000
NAME
DESCRIPTION
Reserved
ACCESS
Reserved
RO
Table 2-45. SERDES_TX0_STATUS (1)
ADDRESS: 0x9017
BIT(s)
36887.0
(1)
DEFAULT: 0x0000
NAME
DESCRIPTION
TX CH 0 TESTFAIL
ACCESS
When HIGH, indicates an error occurred during test pattern verification
for SERDES TX CH 0.
RO
Above status bits are only for Receive CH 1.
Table 2-46. SERDES_TX1_STATUS
ADDRESS: 0x9018
BIT(s)
36888.0
DEFAULT: 0x0000
NAME
DESCRIPTION
Reserved
ACCESS
Reserved
RO
Table 2-47. SERDES_PLL_STATUS
ADDRESS: 0x901B
BIT(s)
42
NAME
DEFAULT: 0x0000
DESCRIPTION
ACCESS
36891.4
PLL_LOCK_RX
1 = Indicates PLL is locked within 10ppm of REFCLKP/N in SERDES RX macro
36891.0
PLL_LOCK_TX
1 = Indicates PLL is locked within 10ppm of REFCLKP/N in SERDES TX macro
Detailed Description
RO/LL
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Table 2-48. JC_CLOCK_MUX_CONTROL
ADDRESS: 0x9100
BIT(s)
37120.15:14
37120.13:12
37120.11:10
37120.9:8
37120.7:6
37120.5:4
NAME
DEFAULT: 0x3FF0
DESCRIPTION
ACCESS
REF_SEL[1:0]
Jitter Cleaner Reference clock select control
00 = Selects differential REFCLKP/N as jitter cleaner clock input
01 = Selects CMOS REFCLK as jitter cleaner clock input
10 = Selects recovered clock as jitter cleaner clock input
11 = Reserved
RW
RXB_SEL[1:0]
Jitter Cleaner RXBYTECLK select control
00 = Selects RXB_DIV divider output clock as RXBYTECLK
01 = Selects recovered clock as RXBYTECLK
10 = Selects CMOS REFCLK as RXBYTECLK
11 = Selects differential REFCLKP/N as RXBYTECLK
RW
TX_SEL[1:0]
Jitter Cleaner SERDES TX Reference clock input select control
00 = Selects jitter cleaner output clock as TX SERDES reference clock input
01 = Selects recovered clock as TX SERDES reference clock input
10 = Selects CMOS REFCLK as TX SERDES reference clock input
11 = Selects differential REFCLKP/N as TX SERDES reference clock input
RW
RX_SEL[1:0]
Jitter Cleaner SERDES RX Reference clock input select control
00 = Selects jitter cleaner output clock as RX SERDES reference clock input
01 = Selects recovered clock as RX SERDES reference clock input (Not Recommended)
10 = Selects CMOS REFCLK as RX SERDES reference clock input
11 = Selects differential REFCLKP/N as RX SERDES reference clock input
RW
DEL_SEL[1:0]
Delay stopwatch clock input select control
00 = Selects delay clock divider output clock as delay stopwatch clock input
01 = Selects recovered clock as delay stopwatch clock input
10 = Selects CMOS REFCLK as delay stopwatch clock input
11 = Selects differential REFCLKP/N as delay stopwatch clock input
RW
HSTL_SEL[1:0]
HSTL VTP 2x clock divider input select control
00 = Selects HSTL DIV clock output as HSTL VTP 2x clock divider input
01 = Selects recovered clock as HSTL VTP 2x clock divider input
10 = Selects CMOS REFCLK as HSTL VTP 2x clock divider input
11 = Selects differential REFCLKP/N as HSTL VTP 2x clock divider input
RW
Table 2-49. JC_VTP_CLK_DIV_CONTROL
ADDRESS: 0x9101
BIT(s)
37121.14:8
37121.6:0
NAME
HSTL_DIV[6:0]
HSTL_DIV2[6:0]
DEFAULT: 0x0E06
DESCRIPTION
ACCESS
HSTL Output Divider 1 Value. See Figure 1-2. This value is the divider value for the
clock which runs the HSTL impedance compensation controller. The target output
frequency for the impedance controller clock is 40 MHz. If the jitter cleaner is not
enabled, this value is not used.
Legal programmed values are greater than or equal to 6
RW
HSTL Output Divider 2 Value. See Figure 1-2. This value is the divider value for the
HSTL impedance compensation controller. The target output frequency for this
clock is 40 MHz. When the jitter cleaner (HSTL_DIV1) is used, this value should be
provisioned to 6 decimal. When the jitter cleaner (HSTL_DIV1) is not used, this
divider value should be provisioned according to the following equation:
RW
Value = (Parallel Output Byte Clock Frequency / 40 MHz)
Legal programmed values are 1, and greater than or equal to 4
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Table 2-50. JC_DELAY_STOPWATCH_CLK_DIV_CONTROL
ADDRESS: 0x9102
BIT(s)
DEFAULT: 0x0600
NAME
DESCRIPTION
ACCESS
37122.14:8
DEL_DIV[6:0]
Delay Measurement Clock Output Divider Value. See Figure 1-2. Controls the clock
divider for the delay stop watch function. This value should be provisioned to
decimal 6.This value is only used when the delay calculator circuit is enabled.
Legal programmed values are greater than or equal to 6
RW
37122.2:1
Delay stop watch
lane select[1:0]
Lane select to enable comma monitor. Valid only when 37122:0 is “1”
00 = Comma monitor enabled
01 = Reserved
10 = Reserved
11 = Reserved
RW
37122.0
Delay stop watch
clock enable
When set, enables Delay stop watch clock
RW
Table 2-51. JC_DELAY_STOPWATCH_COUNTER
ADDRESS: 0x9103
BIT(s)
37123.15:0
DEFAULT: 0x0000
NAME
Delay stop watch
counter[15:0]
DESCRIPTION
ACCESS
Delay Counter. This value represents the latency in number of clock cycles. This
counter resets on read and will return 16’h0000 if its read before rx comma is
received. If latency is more than 16’hFFFF clock cycles then this counter returns
16’hFFFF.
RO
Table 2-52. JC_REFCLK_FB_DIV_CONTROL
ADDRESS: 0x9104
BIT(s)
37124.15
37124.14:8
37124.7
37124.6:0
DEFAULT: 0x018E
NAME
DESCRIPTION
ACCESS
REFDIV_EN
1 = Enables Reference clock divider
0 = Disables Reference clock divider
RW
REF_DIV[0:6]
Controls the clock divider value for the reference clock. See Figure 1-2, and
Appendix A for provisioning details
Note: REF_DIV[6:0] = 37124.8:14.
(Example: To program REF_DIV to decimal value 4, 14:8 needs to be set to
7’b0010000)
RW
FBDIV_EN
1 = Enables Feedback divider
0 = Disables feedback divider
RW
FB_DIV[6:0]
Controls the feedback divider value
See Figure 1-2, and Appendix A for provisioning details.
Note: JC_CHARGE_PUMP_ CONTROL (37126) needs to be set accordingly
based on FB_DIV range. Refer Table 2-55: Charge Pump Control Setting
(CP_CTRL)
RW
Table 2-53. JC_RXB_OUTPUT_CLK_DIV_CONTROL
ADDRESS: 0x9105
BIT(s)
NAME
DEFAULT: 0x0E8E
DESCRIPTION
ACCESS
37125.14:8
RXB_DIV[6:0]
Receive Byte Clock Output Divider Value. This divider value is always provisioned with the
same value as RXTX_DIV[6:0]. See Figure 1-2, and Appendix A for provisioning details. This
value is only used when the jitter cleaner is used to source the receive parallel interface
output clock. Legal programmed values are greater than or equal to 6
RW
37125.7
OUTDIV_EN
1 = Enables output divider (RXTX_DIV)
0 = Disables output divider
RW
RXTX_DIV[6:0]
RX/TX SERDES Output Divider Value
See Figure 1-2, and Appendix A for provisioning details Legal programmed values are
greater than or equal to 6
RW
37125.6:0
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Table 2-54. JC_CHARGE_PUMP_CONTROL (1)
ADDRESS: 0x9106
BIT(s)
37126.15:14
37126.13:0
(1)
DEFAULT: 0x00C0
NAME
DESCRIPTION
ACCESS
CP_BUF_CTRL[1:0]
Charge pump buffer control
RW
CP_CTRL[13:0]
Charge pump control. When JC PLL is used, CP_CTRL[13:0] values
need to be set according to FB_DIV[6:0] range. Refer Table 2-55: Charge
Pump Control Setting (CP_CTRL)
RW
When JC PLL is used, this register value should be set according to the values specified in Charge Pump Control Setting Table
Table 2-55. Charge Pump Control Setting (CP_CTRL)
FB DIV VALUE RANGE
(37124[6:0]) (IN DECIMAL)
JC_CHARGE_PUMP_ CONTROL SETTING
(37126 [15:0])
1 - 15
0x00FF
16 - 18
0x00C1
19 - 30
0x0081
31 - 33
0x017F
34 - 45
0x017D
46 - 53
0x011F
54 - 59
0x0151
60 - 68
0x0121
69 - 77
0x01C3
78 - 85
0x0101
86 - 88
0x02FB
89 - 91
0x0183
92 - 99
0x0237
100 - 107
0x0181
108 - 113
0x0261
114 - 127
0x0215
Table 2-56. JC_PLL_CONTROL
ADDRESS: 0x9107
BIT(s)
NAME
DEFAULT: 0x30C4
DESCRIPTION
ACCESS
JC_EN_PLL
0 = Disables Jitter Cleaner
1 = Enables Jitter Cleaner
RW
37127.14:12
VCO_BIAS_CTRL[2:0]
Control bits for VCO tail current
RW
37127.11:8
VCO_CAPBANK_CTRL[3:0]
Control bits for VCO band select
RW
37127.7
DIFFTX_EN
Enable signal for TX differential path
RW
37127.6
DIFFRX_EN
Enable signal for RX differential path
RW
PFD_CTRL[1:0]
Control bits for phase frequency detector
RW
37127.3
AD_SEL_TST
Control bit to select either digital or analog TST_OUT
RW
37127.2
REFCLK_CML_EN
Enable signal for CML buffer inside output divider
RW
37127.15
37127.5:4
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Table 2-57. JC_TEST_CONTROL_1 (1)
ADDRESS: 0x9108
BIT(s)
(1)
DEFAULT: 0x0000
NAME
DESCRIPTION
ACCESS
37128.15:12
REFCK_DIV_TST[3:0]
Test bits for Reference divider
RW
37128.11:8
FB_DIV_TST[3:0]
Test bits for Feedback divider
RW
37128.7:4
TXRX_DIV_TST[3:0]
Test bits for TXRX output divider. Should be set to 4’b1010 when JC PLL
is used
RW
37128.3:2
RXBCLK_DIV_TST[1:0]
Test bits for RXBYTECLK divider
RW
This register value should be written 0x00A0 when JC PLL is used
Table 2-58. JC_TEST_CONTROL_2
ADDRESS: 0x9109
BIT(s)
DEFAULT: 0x0000
NAME
DESCRIPTION
ACCESS
37129.15:14
DEL_DIV_TST[1:0]
Test bits for Delay clock divider
RW
37129.13:12
HSTL_DIV_TST[1:0]
Test bits for HSTL VTP divider
RW
37129.11:10
HSTL_DIV2_TST[1:0]
Test bits for HSTL VTP 2X divider
RW
37129.9:8
PFD_TST[1:0]
Test bits for Phase frequency detector
RW
37129.7:4
CP_TST[3:0]
Test bits for Charge pump
RW
37129.3:0
CP_BUF_TST[3:0]
Test bits for Charge pump Buffer
RW
Table 2-59. JC_TI_TEST_CONTROL_1
ADDRESS: 0x9150
BIT(s)
NAME
DEFAULT:0x0000
DESCRIPTION
ACCESS
37200.15:8
CML_BIAS_TST[7:0]
Test bits for Bias generator for CML divider. For TI purposes only.
RW
37200.7:4
CML_BIAS_CTRL[3:0]
Control bits for Bias generator for CML divider. For TI purposes only.
RW
37200.3
DIFFTX_ENTST
Enable for TX clock out from SERDES REFCLK MUX. For TI purposes
only.
RW
37200.2
DIFFRX_ENTST
Enable for RX clock out from SERDES REFCLK MUX. For TI purposes
only.
RW
Table 2-60. JC_TI_TEST_CONTROL_2
ADDRESS: 0x9151
BIT(s)
NAME
DEFAULT: 0x0000
DESCRIPTION
ACCESS
37201.15:13
VCO_FILCAP_CTRL[2:0]
Control bits for VCO tail current noise filter. For TI purposes only.
RW
37201.12:10
ANA_MUX_CTRL[2:0]
Control bits to select the tested signals. For TI purposes only.
RW
Table 2-61. JC_TRIM_STATUS
ADDRESS: 0x9152
BIT(s)
37202.9:0
NAME
JC_TRIM[9:0]
DEFAULT: 0x0000
DESCRIPTION
ACCESS
Jitter Cleaner Resistor Trim value
RO
Table 2-62. DIE_ID_7
ADDRESS: 0x9200
BIT(s)
37376.15:0
46
NAME
Die ID [127:112]
Detailed Description
DEFAULT: 0x0000
DESCRIPTION
Bits [127:112] of the Die ID. Unique TI DIE identifier.
ACCESS
RO
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Table 2-63. DIE_ID_6
ADDRESS: 0x9201
BIT(s)
37377.15:0
NAME
Die ID [111:96]
DEFAULT: 0x0000
DESCRIPTION
ACCESS
Bits [111:96] of the Die ID. Unique TI DIE identifier.
RO
Table 2-64. DIE_ID_5
ADDRESS: 0x9202
BIT(s)
37378.15:0
NAME
Die ID [95:80]
DEFAULT: 0x0000
DESCRIPTION
ACCESS
Bits [95:80] of the Die ID. Unique TI DIE identifier.
RO
Table 2-65. DIE_ID_4
ADDRESS: 0x9203
BIT(s)
37379.15:0
NAME
Die ID [79:64]
DEFAULT: 0x0000
DESCRIPTION
ACCESS
Bits [79:64] of the Die ID. Unique TI DIE identifier.
RO
Table 2-66. DIE_ID_3
ADDRESS: 0x9204
BIT(s)
37380.15:0
NAME
Die ID [63:48]
DEFAULT: 0x0000
DESCRIPTION
ACCESS
Bits [63:48] of the Die ID. Unique TI DIE identifier.
RO
Table 2-67. DIE_ID_2
ADDRESS: 0x9205
BIT(s)
37381.15:0
NAME
Die ID [47:32]
DEFAULT: 0x0000
DESCRIPTION
ACCESS
Bits [47:32] of the Die ID. Unique TI DIE identifier.
RO
Table 2-68. DIE_ID_1
ADDRESS: 0x9206
BIT(s)
37382.15:0
NAME
Die ID [31:16]
DEFAULT: 0x0000
DESCRIPTION
ACCESS
Bits [31:16] of the Die ID. Unique TI DIE identifier.
RO
Table 2-69. DIE_ID_0
ADDRESS: 0x9207
BIT(s)
37383.15:0
NAME
Die ID [15:0]
DEFAULT: 0x0000
DESCRIPTION
ACCESS
Bits [15:0] of the Die ID. Unique TI DIE identifier.
RO
Table 2-70. EFUSE_STATUS
ADDRESS: 0x9208
BIT(s)
37384.8
37384.4:0
NAME
DEFAULT: 0x0000
DESCRIPTION
ACCESS
EFC ready
When high, indicates that EFUSE autoload operation has completed
EFC error[4:0]
Efuse error bus. Updated when EFC_ready goes high or when instruction
is complete. Non-zero value indicates error condition.
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RO
Detailed Description
47
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
www.ti.com
Table 2-71. EFUSE_CONTROL
ADDRESS: 0x9209
BIT(s)
37385.15
DEFAULT: 0x0000
NAME
EFUSE Auto Load Enable
DESCRIPTION
ACCESS
When HIGH, Re-enables EFUSE Auto load function. Needs to set back to
LOW to complete Auto load function.
RW
Table 2-72. HSTL_INPUT_TERMINATION_CONTROL
ADDRESS: 0x9300
BIT(s)
37632.7:6
37632.3:2
DEFAULT: 0x0000
NAME
DESCRIPTION
ACCESS
Reserved
Reserved
RW
HSTL_TERM_0[1:0]
Termination setting for input HSTL cells (for CH 0)
00 = Termination disable (High Impedance)
01 = Half termination strength (300 Ω to VHSTL&GND)
10 = 3/4 termination strength (200 Ω to VHSTL&GND)
11 = Full termination strength (150 Ω to VHSTL&GND)
RW
Table 2-73. HSTL_OUTPUT_SLEWRATE_CONTROL
ADDRESS: 0x9301
BIT(s)
DEFAULT: 0x0000
NAME
DESCRIPTION
ACCESS
37633.7:6
Reserved
Reserved
37633.3:2
Slew Rate setting for output HSTL cells (for CH 0)
00 = No slew control (fastest edge)
HSTL_SLEW_RATE_0 [1:0] 01 = 33% slew control
10 = 66 % slew control termination strength
11 = Full slew control (slowest edge)
RW
RW
Table 2-74. HSTL_INPUT_VTP_CONTROL
ADDRESS: 0x9302
BIT(s)
DEFAULT: 0x0640
DESCRIPTION
ACCESS
37634.15
I_FORCE_UP_N
When set, increases NFET strength in all HSTL input cells. For TI
purposes Only
37634.14
I_FORCE_UP_P
When set, increases PFET strength in all HSTL input cells. For TI
purposes Only
37634.13
I_FORCE_DOWN_N
When set, decreases NFET strength in all HSTL input cells. For TI
purposes Only
37634.12
I_FORCE_DOWN_P
When set, decreases PFET strength in all HSTL input cells. For TI
purposes Only
I_VTP_DRIVE[2:0]
Drive strength control for HSTL input cells
3’b000 = 30% drive strength increase
3’b001 = 20% drive strength increase
3’b010 = 10% drive strength increase
3’b011 = Normal drive strength (default)
3’b100 = 10% drive strength decrease
3’b101 = 20% drive strength decrease
3’b110 = 30% drive strength decrease
3’b111 = 40% drive strength decrease
RW
I_FILTER_CONTROL[2:0]
Filter Control
3’b000 = Impedance change filtering off
3’b001 = Update on 2 consecutive update requests
3’b010 = Update on 3 consecutive update requests(default)
3’b011 = Update on 4 consecutive update requests
3’b100 = Update on 5 consecutive update requests
3’b101 = Update on 6 consecutive update requests
3’b110 = Update on 7 consecutive update requests
3’b111 = Update on 8 consecutive update requests
RW
I_LOCK
Impedance Lock Control
When set, disables dynamic impedance control updates for HSTL input
cells
RW
37634.11:9
37634.7:5
37634.3
48
NAME
Detailed Description
RW
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Table 2-75. HSTL_OUTPUT_VTP_CONTROL
ADDRESS: 0x9303
BIT(s)
DEFAULT: 0x0640
NAME
DESCRIPTION
ACCESS
37635.15
O_FORCE_UP_N
When set, increases NFET strength in all HSTL output cells . For TI
purposes Only
37635.14
O_FORCE_UP_P
When set, increases PFET strength in all HSTL output cells . For TI
purposes Only
37635.13
O_FORCE_DOWN_N
When set, decreases NFET strength in all HSTL output cells . For TI
purposes Only
37635.12
O_FORCE_DOWN_P
When set, decreases PFET strength in all HSTL output cells . For TI
purposes Only
O_VTP_DRIVE[2:0]
Drive strength control for HSTL output cells
3’b000 = 30% drive strength increase
3’b001 = 20% drive strength increase
3’b010 = 10% drive strength increase
3’b011 = Normal drive strength(default)
3’b100 = 10% drive strength decrease
3’b101 = 20% drive strength decrease
3’b110 = 30% drive strength decrease
3’b111 = 40% drive strength decrease
RW
O_FILTER_CONTROL[2:0]
Filter Control
3’b000 = Impedance change filtering off
3’b001 = Update on 2 consecutive update requests
3’b010 = Update on 3 consecutive update requests(default)
3’b011 = Update on 4 consecutive update requests
3’b100 = Update on 5 consecutive update requests
3’b101 = Update on 6 consecutive update requests
3’b110 = Update on 7 consecutive update requests
3’b111 = Update on 8 consecutive update requests
RW
O_LOCK
Impedance Lock Control
When set, disables dynamic impedance control updates for HSTL output
cells
RW
37635.11:9
37635.7:5
37635.3
RW
Table 2-76. HSTL_GLOBAL_CONTROL
ADDRESS: 0x9304
BIT(s)
NAME
DEFAULT: 0x0088
DESCRIPTION
ACCESS
RW
37636.15
HSTL power down control
When set, triggers HSTL power down sequence and places all HSTL cells
in power down state.
37636.14
HSTL Retrain
When set, triggers retraining of all HSTL inputs and outputs to match the
impedance. Retraining is triggered only when this bit value goes from 0 to
1. HSTL retraining should occur at the end of device provisioning.
RW
37636.11
HSTL_CLK_EN
HSTL impedance control clock (CLK2X) selection
1 = Uses MDC (MDIO clock) as CLK2X
0 = Uses clock generated from Jitter cleaner as CLK2X
RW
37636.7
Voltage reference selection
1 = Internal voltage reference used for HSTL input signals
0 = External voltage reference used for HSTL input signals
RW
37636.3
VTP POWERSAVE
When set, enables power save mode on HSTL VTP controllers
RW
37636.2
GP 3-state Control
When set, 3-states GP outputs
RW
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Table 2-77. TX0_DLL_CONTROL
ADDRESS: 0x9400
BIT(s)
DEFAULT: 0x0008
NAME
DESCRIPTION
ACCESS
37888.15
Lock_en
For TI use only
37888.14
Write_en
For TI use only
37888.13:8
Delay_sel[5:0]
DLL delay control. For TI use only
37888.7:5
Offset[2:0]
Phase shift control. Adds or removes delay element. Each delay element
is 0.15ns. Refer Table 2-81: DLL Offset Control
Filter_en
When asserted, the internal filter is used to reduce the cycle to cycle jitter
of the output clock.
37888.3
RW
Table 2-78. TX1_DLL_CONTROL
ADDRESS: 0x9401
BIT(s)
37889.15:5, 3
DEFAULT: 0x0008
NAME
Reserved
DESCRIPTION
ACCESS
Reserved
RW
Table 2-79. RX0_DLL_CONTROL
ADDRESS: 0x9404
BIT(s)
DEFAULT: 0x0008
NAME
DESCRIPTION
ACCESS
37892.15
Lock_en
For TI use only
37892.14
Write_en
For TI use only
37892.13:8
Delay_sel[5:0]
DLL delay control. For TI use only
37892.7:5
Offset[2:0]
Phase shift control. Adds or removes delay element. Each delay element
is 0.15 ns. Refer Table 2-81: DLL Offset Control
Filter_en
When asserted, the internal filter is used to reduce the cycle to cycle jitter
of the output clock.
37892.3
RW
Table 2-80. RX1_DLL_CONTROL
ADDRESS: 0x9405
BIT(s)
37893.15:5, 3
50
DEFAULT: 0x0008
NAME
Reserved
Detailed Description
DESCRIPTION
Reserved
ACCESS
RW
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Table 2-81. DLL Offset Control
OFFSET[2:0]
VALUE
RESULT
000
No delay elements are added
001
1 extra delay element is added
010
2 extra delay elements are added
011
3 extra delay elements are added
100
No delay elements are removed
101
1 extra delay element is removed
110
2 extra delay elements are removed
111
3 extra delay elements are removed
Table 2-82. TX0_DLL_STATUS
ADDRESS: 0x9408
BIT(s)
37896.5:0
DEFAULT: 0x0000
NAME
DESCRIPTION
Delay_status[5:0]
ACCESS
For TI use only.
RO
Table 2-83. TX1_DLL_STATUS
ADDRESS: 0x9409
BIT(s)
37897.5:0
DEFAULT: 0x0000
NAME
DESCRIPTION
Reserved
ACCESS
Reserved
RO
Table 2-84. RX0_DLL_STATUS
ADDRESS: 0x940C
BIT(s)
37900.5:0
DEFAULT: 0x0000
NAME
DESCRIPTION
Delay_status[5:0]
ACCESS
For TI use only.
RO
Table 2-85. RX1_DLL_STATUS
ADDRESS: 0x940D
BIT(s)
37901.5:0
DEFAULT: 0x0000
NAME
DESCRIPTION
Reserved
ACCESS
Reserved
RO
Table 2-86. CH0_TESTFAIL_ERR_COUNTER
ADDRESS: 0x9500
BIT(s)
38144.7:0
DEFAULT: 0x00FD
NAME
Ch0_Testfail error
counter[7:0]
DESCRIPTION
ACCESS
This counter reflects error count during PRBS test. Counter increments
for each received character that has an error. Counter clears upon read.
Counter value is valid only when SERDES RX test pattern verification bits
are set.
COR
Table 2-87. CH1_TESTFAIL_ERR_COUNTER
ADDRESS: 0x9501
BIT(s)
38145.7:0
DEFAULT: 0x00FD
NAME
Reserved
Submit Documentation Feedback
DESCRIPTION
Reserved
ACCESS
COR
Detailed Description
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Single Channel Multi-Rate Transceiver
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Table 2-88. STCI_CONTROL_STATUS
ADDRESS: 0x9600
BIT(s)
38400.15
DEFAULT: 0x0000
NAME
DESCRIPTION
STCI_CLK
Bit to generate STCI clock in functional mode.
STCI_CFG[1:0]
STCI CFG control
38400.7
STCI_D
STCI data in
38400.3
STCI_Q
STCI read data
38400.11:10
ACCESS
RW
RO
Table 2-89. TESTCLK_CONTROL
ADDRESS: 0x9601
BIT(s)
38401.15
NAME
TESTCLKT
DEFAULT: 0x0000
DESCRIPTION
ACCESS
Bit to generate TESTCLKT clock in functional mode.
For TI test purposes only
RW
Table 2-90. BIDI_CMOS_CONTROL
ADDRESS: 0x9700
BIT(s)
38656.15
NAME
MDIO Disable Comp Test
Control
DEFAULT: 0x0000
DESCRIPTION
ACCESS
0 = MDIO/MDC Bidi cells automatically detects operating voltage (Default)
1 = MDIO/MDC Bidi cells expects 2.5 V operating voltage
RW
Table 2-91. DEBUG_CONTROL
ADDRESS: 0x9800
BIT(s)
NAME
DEFAULT: 0x001F
DESCRIPTION
ACCESS
38912:8
DEBUG_SEL_EN
1 = Sends debug status signals onto debug outputs (GPO)
0 = Debug outputs are tied to 0.
For TI test purposes only
38912.7
DIG_TST_OUT_EN
1 = Enables sending DIG TST debug signal onto GPO4
0 = Disables sending DIG TST debug signal onto GPO4.
For TI test purposes only
DEBUG_SEL
Debug select bits. For TI test purposes only
38912.4:0
RW
Table 2-92. DUTY_CYCLE_CONTROL
ADDRESS: 0x9900
BIT(s)
39168.15
52
NAME
Duty Cycle Correction
Bypass
Detailed Description
DEFAULT: 0x0000
DESCRIPTION
ACCESS
1 = Bypasses duty cycle corrected RX/TXBCLK. (Duty cycle set to 40-60,
same clocks as SERDES parallel launch and capture clocks)
0 = Uses duty cycle corrected RX/TXBCLK. (Duty cycle set to 50-50, no
phase relationship to SERDES parallel launch and capture clock)(Default)
For TI test purposes only
RW
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3
Device Reset Requirements/Procedure
3.1
Gigabit Ethernet Mode (RGMII)
SLLS957 – DECEMBER 2008
Power down sequence for channel 1
Note: Common for all modes after device reset (1)
• Write 1’b0 to 36868.0 to disable receiver for unused channel
• Write 1’b0 to 36876.0 to disable transmitter for unused channel
• Set LSB of PHY address to 1
• Write 1’b1 to 0.11 to power down unused channel
• Set LSB of PHY address to 0
REFCLK frequency = 125 MHz, Serdes Data Rate = Half Rate, Mode = Transceiver, Edge Mode = Source
Centered Mode, RX_CLK[n] out = TXBCLK[n], Jitter Cleaner PLL Multiplier Ratio = 1X or Off
• Device Pin Setting(s) – Pin settings allow for maximum software configurability.
– Ensure CODE input pin is Low.
– Ensure PLOOP input pin is Low.
– Ensure SLOOP input pin is Low.
– Ensure SPEED [1:0] input pins are both High.
– Ensure ENABLE input pin is High.
– Ensure PRBS_EN input pin is Low.
• Reset Device
– Issue a hard or soft reset (RST_N asserted for at least 10 µs -or- Write 1’b1 to 0.15)
• Power Down Sequence Note: This step is mandatory for proper functionality
– Refer to Power down sequence above
• Clock Configuration
– If using JCPLL (JCPLL 1X)
• JCPLL Mux Settings (see Figure 1-2)
– Select REFCLK input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b01 to 37120.15:14
– If Differential REFCLK used – Write 2’b00 to 37120.15:14
• Write 2’b11 to 37120.13:12 to select differential REFCLKP/N as RXBYTECLK
• Write 4’b0000 to 37120.11:8 to select jitter cleaned clock for SERDES TX/RX.
• Write 2’b11 to 37120.7:6 to select differential REFCLKP/N as delay stopwatch clock input
• Write 2’b00 to 37120.5:4 to select jitter cleaned clock for HSTL VTP 2x
• Write 2’b00 to 16.10:9 to select SERDES TX clock as RX_CLK output
• Write 16’h0081 to 37126 to set Charge pump control
• Write 16’h00A0 to 37128 to set TXRX output divider
• Clock Divide Settings (see Figure A-1)
– Write 7’b1000000 to 37124.14:8 to set REF_DIV to value of 1
– Write 1’b1 to 37124.15 REFDIV_EN to enable reference clock divider
– Write 7’h18 to 37124.6:0 to set FB_DIV to value of 24
– Write 1’b1 to 37124.7 FBDIV_EN to enable feedback divider
– Write 7’h18 to 37125.6:0 to set RXTX_DIV to value of 24
– Write 1’b1 to 37125.7 OUTDIV_EN to enable RXTX_DIV output divider
– Write 7’h0D to 37121.14:8 to set HSTL_DIV to value of 13
– Write 7’h06 to 37121.6:0 to set HSTL_DIV2 to value of 6
(1)
Note: All global registers must be accessed indirectly through Clause 22.
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•
54
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– Write 2’b11 to 36864.14:13 to set RX Loop Bandwidth
– Write 2’b11 to 36864.6:5 to set TX Loop Bandwidth
– Write 4’b0101 to 36864.11:8 to set MPY RX multiplier factor to 10
– Write 4’b0101 to 36864.3:0 to set MPY TX multiplier factor to 10
– Write 16’h4040 to 36865 SERDES_RATE_CONFIG_TX_RX to set Half Rate
– Write 3'b000 to 37127.14:12 to set control bits for VCO tail current to 0
– Write 1’b1 to 37127.15 to enable Jitter Cleaner
– Wait 50 ms in order for JCPLL to lock
– If using clock bypass mode (JCPLL Off)
• JCPLL Mux Settings (see Figure 1-2)
– Select REFCLK input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b01 to 37120.15:14
– If Differential REFCLK used – Write 2’b00 to 37120.15:14
– Select RXBYTE_CLK (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 37120.13:12
– If Differential REFCLK used – Write 2’b11 to 37120.13:12
– Select SERDES TX Reference Clock Input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 37120.11:10
– If Differential REFCLK used – Write 2’b11 to 37120.11:10
– Select SERDES RX Reference Clock Input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 37120.9:8
– If Differential REFCLK used – Write 2’b11 to 37120.9:8
– Select DELAY_CLK (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 37120.7:6
– If Differential REFCLK used – Write 2’b11 to 37120.7:6
– Select HSTL_2X_CLK (Default = Differential)
– Write 2b'01 to 4/5.37120.5:4 to select RX SERDES recovered clock as HSTL_2X_CLK
– Write 2’b00 to16.10:9 to select SERDES TX clock as RX_CLK output
– Write 7’h04 to 37121.6:0 to set HSTL_DIV2 to value of 4.
– Write 15’h1515 to 36864.14:0 SERDES_PLL_CONFIG to set MPY RX/TX multiplier factor to
10
– Write 16’h4040 to 36865 SERDES_RATE_CONFIG_TX_RX to set Half Rate
Mode Control (see Table 2-2)
– Write 1’b0 to 17.0 for RX source centered mode
– Write 1’b0 to 17.1 for TX source centered mode
– Write 1’b1 to 17.2 to enable 8B/10B encode decode functions
– Write 1’b1 to 17.3 to enable 1000Base-X PCS TX & PCS RX functions
– Write 1’b1 to 17.4 to set nibble order, LSB on rising edge, MSB on falling edge
– Write 1’b1 to 17.5 to enable DDR data on TX/RX direction
– Write 1’b0 to 17.6 to disable FC_PH overlay detection
– Write 1’b1 to 17.7 to enable comma detection
– Write 1’b0 to 17.9 to disable full DDR mode
– Write 1’b0 to 16.8 to disable Farend Loop back
– Write 1’b0 to 0.14 to disable loop back mode
– Write 3’b111 to 36874.11:9 to set TX swing setting amplitude to 1375 mVdfpp
– Write 1’b1 to 36874.8 to set channel 0 TX CM bit
Device Reset Requirements/Procedure
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•
•
•
•
•
•
SLLS957 – DECEMBER 2008
RX equalization settings
– Write 4’b0001 to 36866.15:12 to turn on adaptive equalization (4’b0000 is off)
– Write 2’b01 to 36866.3:2 for AC coupled mode (2’b00 is DC coupled mode)
TX DLL Offset
– Write 16'h0028 to 37888 TX0_DLL_CONTROL
Poll Serdes PLL Status for Locked State
– Read 36891.4,0 SERDES_PLL_STATUS – PLL_LOCK_TX/RX
– Keep polling until both bits are high.
Issue Data path Reset
– Write 1’b1 to 16.11
– Write 1’b0, then 1’b1, followed by 1’b0 to 37636.14.
Clear Latched Registers
– Read 1 PHY_STATUS_1 to clear
– Read 18 PHY_RX_CTC_FIFO_STATUS to clear
– Read 19 PHY_TX_CTC_FIFO_STATUS to clear
– Read 28 PHY_CHANNEL_STATUS to clear
– Read 36891 SERDES_PLL_STATUS to clear
Operational Mode Status
– Read Verify 1.2 PHY_STATUS_1 – Link Status (1’b1)
– Read Verify 18.15 PHY_RX_CTC_FIFO_STATUS – RX_CTC_Reset (1’b0)
– Read Verify 19.15 PHY_TX_CTC_FIFO_STATUS – TX_FIFO_Reset_1Gx (1’b0)
– Read Verify 28.13:12 PHY_CHANNEL_STATUS – Enc/Dec Invalid Code Word (2’b00)
– Read Verify 36891.4 SERDES_PLL_STATUS – PLL_LOCK_RX (1’b1)
– Read Verify 36891.0 SERDES_PLL_STATUS – PLL_LOCK_TX (1’b1)
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Device Reset Requirements/Procedure
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3.2
www.ti.com
JITTER TEST PATTERN GENERATION AND VERIFICATION PROCEDURES
Use one of the following procedures to generate and verify the respective test patterns. It is assumed that
an appropriate external cable has been connected between serial outputs and serial inputs. No functional
parallel side connections are necessary.
• 1000Base-X Based High/Mixed/Low Frequency Test Pattern:
– Device Pin Setting(s):
• Ensure CODE primary input pin is low.
– Reset Device
• Issue a hard or soft reset (RST_N asserted for at least 10 us -or- Write 1’b1 to 0.15)
– Power down channel 1 per procedure in previous device initialization section.
– Select single ended or differential REFCLK input:
• If Single Ended REFCLK used - Write 2’b01 to 37120.15:14
• If Differential REFCLK used – Write 2’b00 to 37120.15:14
– Select SERDES TX Reference Clock Input:
• If Single Ended REFCLK used - Write 2’b10 to 37120.11:10
• If Differential REFCLK used – Write 2’b11 to 37120.11:10
– Select SERDES RX Reference Clock Input:
• If Single Ended REFCLK used - Write 2’b10 to 37120.9:8
• If Differential REFCLK used – Write 2’b11 to 37120.9:8
– Disable Comma Detection:
• Write 1’b0 to 17.7
– Ensure a legal reference clock operation frequency is selected based on Appendix A, and provision
control settings accordingly. It is also possible to use the Jitter Cleaner during these tests, and the
user should consult Appendix A for further Jitter Cleaner provisioning details.
– Issue Datapath Reset:
• Write 1’b1 to 16.11
• Write 1’b0, then 1’b1, followed by 1’b0 to 37636.14.
– Select Test Pattern:
• If High Frequency Pattern is desired:
– Write 3’b000 to 16.2:0
• If Low Frequency Pattern is desired:
– Write 3’b001 to 16.2:0
• If Mixed Frequency Pattern is desired:
– Write 3’b010 to 16.2:0
– Enable Test Pattern Generation:
• Write 1’b1 to 16.4
– Clear Counters:
• Read 22.15:0 and discard the value.
– Enable Test Pattern Verification:
• Write 1’b1 to 16.3
– Verify Test In Progress:
• Poll 21.1 asserted.
– The pattern verification is now in progress.
– Verify Error Free Operation (as many times as desired during the duration of the test period):
• Read 22.15:0, and verify 16’h0000 is read to confirm error free operation.
56
Device Reset Requirements/Procedure
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SLLS957 – DECEMBER 2008
1000Base-X Based Continuous Random Pattern (CRPAT) Long/Short Test Pattern:
– Device Pin Setting(s):
• Ensure CODE primary input pin is high.
– Reset Device:
• Issue a hard or soft reset (RST_N asserted –or- Write 1 to 0.15)
– Power down channel 1 per procedure in previous device initialization section.
• Select single ended or differential REFCLK input:
– If Single Ended REFCLK used - Write 2’b01 to 37120.15:14
– If Differential REFCLK used – Write 2’b00 to 37120.15:14
– Select SERDES TX Reference Clock Input:
• If Single Ended REFCLK used - Write 2’b10 to 37120.11:10
• If Differential REFCLK used – Write 2’b11 to 37120.11:10
– Select SERDES RX Reference Clock Input:
• If Single Ended REFCLK used - Write 2’b10 to 37120.9:8
• If Differential REFCLK used – Write 2’b11 to 37120.9:8
– Ensure a legal reference clock operation frequency is selected based on Appendix A, and provision
control settings accordingly. It is also possible to use the Jitter Cleaner during these tests, and the
user should consult Appendix A for further Jitter Cleaner provisioning details.
– Enable Encoder/Decoder
• Write 1’b1 to 17.2
– Issue Datapath Reset:
• Write 1’b1 to 16.11
• Write 1’b0, then 1’b1, followed by 1’b0 to 37636.14
– Select Test Pattern:
• If CRPAT Long Pattern is desired:
– Write 3’b011 to 16.2:0
• If CRPAT Short Pattern is desired:
– Write 3’b100 to 16.2:0
– Enable Test Pattern Generation:
• Write 1’b1 to 16.4
– Clear Counters:
• Read 23.15:0 and 24.15:0 and discard the values.
– Enable Test Pattern Verification:
• Write 1’b1 to 16.3
– Verify Test In Progress:
• Poll 21.0 asserted.
– The pattern verification is now in progress.
– Verify Error Free Operation (as many times as desired during the duration of the test period):
• Read 23.15:0, and verify 16’h0000 is read to confirm error free operation.
• Read 24.15:0, and verify 16’h0000 is read to confirm error free operation.
If more than one test is specified results are unpredictable.
If another test type is desired, please begin at the first step of that procedure.
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3.3
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PRBS Test Generation and Verification Procedures
Use one of the following procedures to generate and verify the respective PRBS test patterns. It is
assumed that an appropriate external cable has been connected between serial outputs and serial inputs.
No functional parallel side connections are necessary.
• 1000Base-X 27-1 PRBS Register Based Testing
– Device Pin Setting(s):
• Ensure CODE primary input pin is low.
– Reset Device:
• Issue a hard or soft reset (RST_N asserted –or– Write 1 to 0.15)
– Power down channel 1 per procedure in previous device initialization section.
– Select single ended or differential REFCLK input:
• If Single Ended REFCLK used – Write 2’b01 to 37120.15:14
• If Differential REFCLK used – Write 2’b00 to 37120.15:14
– Select SERDES TX Reference Clock Input:
• If Single Ended REFCLK used – Write 2’b10 to 37120.11:10
• If Differential REFCLK used – Write 2’b11 to 37120.11:10
– Select SERDES RX Reference Clock Input:
• If Single Ended REFCLK used – Write 2’b10 to 37120.9:8
• If Differential REFCLK used – Write 2’b11 to 37120.9:8
– Ensure a legal reference clock operation frequency is selected based on Appendix A, and provision
control settings accordingly. It is also possible to use the Jitter Cleaner during these tests, and the
user should consult Appendix A for further Jitter Cleaner provisioning details.
– Issue Datapath Reset:
• Write 1’b1 to 16.11
• Write 1’b0, then 1’b1, followed by 1’b0 to 37636.14.
– Enable PRBS Generator:
• Write 1’b1 to 16.6
– Enable Test Pattern Verification:
• Write 1’b1 to 16.7
– Clear Counters:
• Read 29.15:0 and discard the value.
– The pattern verification is now in progress.
– Verify Error Free Operation (as many times as desired during the duration of the test period):
• Read 29.15:0, and verify 16’h0000 is read to confirm error free operation.
– GPO0 contains a real time output that when high indicates if the input PRBS pattern on TDx0/RDx0
is errored.
• 27-1 PRBS Pin Based Testing
– Device Pin Setting(s):
• Ensure PRBS_EN primary input pin is high.
• PRBS Selection:
– For PRBS 27-1 will be selected
– Reset Device:
• Issue a hard or soft reset (RST_N asserted -or– Write 1 to 0.15)
– Power down channel 1 per procedure in previous device initialization section.
– Select single ended or differential REFCLK input:
• If Single Ended REFCLK used - Write 2’b01 to 37120.15:14
• If Differential REFCLK used – Write 2’b00 to 37120.15:14
– Select SERDES TX Reference Clock Input:
58
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•
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• If Single Ended REFCLK used – Write 2’b10 to 37120.11:10
• If Differential REFCLK used – Write 2’b11 to 37120.11:10
– Select SERDES RX Reference Clock Input:
• If Single Ended REFCLK used – Write 2’b10 to 37120.9:8
• If Differential REFCLK used – Write 2’b11 to 37120.9:8
– Ensure a legal reference clock operation frequency is selected based on Appendix A, and provision
control settings accordingly. It is also possible to use the Jitter Cleaner during these tests, and the
user should consult Appendix A for further Jitter Cleaner provisioning details.
– Issue Datapath Reset:
• Write 1’b1 to 16.11
• Write 1’b0, then 1'b1, followed by 1'b0 to 37636.14
– GPO0 contains a real time output that when high indicates if the input PRBS pattern on TD×0/RD×0
is errored.
SERDES Macro 27-1/223-1 PRBS Register Based Testing
– Reset Device:
• Issue a hard or soft reset (RST_N asserted –or– Write 1 to 0.15)
– Power down channel 1 per procedure in previous device initialization section.
– Select single ended or differential REFCLK input:
• If Single Ended REFCLK used – Write 2’b01 to 37120.15:14
• If Differential REFCLK used – Write 2’b00 to 37120.15:14
– Select SERDES TX Reference Clock Input:
• If Single Ended REFCLK used – Write 2’b10 to 37120.11:10
• If Differential REFCLK used – Write 2’b11 to 37120.11:10
– Select SERDES RX Reference Clock Input:
• If Single Ended REFCLK used – Write 2’b10 to 37120.9:8
• If Differential REFCLK used – Write 2’b11 to 37120.9:8
– Ensure a legal reference clock operation frequency is selected based on Appendix A, and provision
control settings accordingly. It is also possible to use the Jitter Cleaner during these tests, and the
user should consult Appendix A for further Jitter Cleaner provisioning details.
– PRBS Selection:
• For PRBS 27-1– Write 2’b10 36881.1:0.
– Write 2’b10 36882.1:0.
• For PRBS 223-1– Write 2’b11 36881.1:0.
– Write 2’b11 36882.1:0.
– Enable PRBS Generation:
• Write 1’b1 to 36881.2
• Write 1’b1 to 36874.1
– Enable PRBS Verification:
• Write 1’b1 to 36882.3
• Write 1’b1 to 36866.1
– Clear Counters:
• Read 38144.7:0 and discard the value.
– The pattern verification is now in progress
– Verify Error Free Operation (as many times as desired during the duration of the test period):
• Read 38144.7:0, and verify 8’h00 is read to confirm error free operation on TDx0/RDx0.
– GPO0 contains a real time output that when high indicates if the input PRBS pattern on TDx0/RDx0
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is errored.
3.4
Signal Pin Description
Table 3-1. Global Signals
SIGNAL
RST_N
ENABLE
LOCATION
M2
J4
VOLTAGE
TYPE
DESCRIPTION
VDDO
2.5 V LVCMOS
Input
Chip Reset (Active Low) When asserted (low logic level), this signal
reinitializes the entire device. Must be held asserted (low logic level) for at
least 10 µS after device power up.
VDDO
2.5 V LVCMOS
Input
Device Enable.
When this pin is held low, the device is in a low power state.
When high the device operates normally.
A hard or soft reset must be applied after a change of state occurs on this
input signal.
Speed Selection pins. These pins put all four channels of TLK3131 into
one of the three supported (full/half/quarter) operation speeds.
00 – Full Rate mode
01 – Half Rate mode
10 – Quarter rate mode
11 – Software Selectable Rate
SPEED[1:0]
D2
H11
VDDO
2.5 V LVCMOS
Input
In the software selectable rate mode, the rate may be configured
independently by the MDIO interface.
The SPEED[1:0] inputs control both RX and TX directions.
See Appendix A for further information on speed selection
(full/half/quarter) for proper settings as a function of the application mode
and reference clock frequency.
Note that if these pins are not configured on the application board to select
“Software Selectable Rate”, then the internal speed register bits cannot be
used to control the rate settings, and the full/half/quarter rate selection is
fixed.
PLOOP
SLOOP
PRBS_EN
CODE
60
K11
H10
L1
J2
2.5 V LVCMOS
Input
Parallel Loop Enable. When high, the serial output is internally looped
back to the serial input so that the transmit parallel interface input data is
output onto the receive parallel interface.
2.5 V LVCMOS
Input
Serial Loop Enable. When high, the serial input is internally looped back
to the serial output, making a serial repeater. In device configurations
where clock tolerance compensation is not performed in the transmit
direction, there are two options for error-free serial loopback operation:
1. Frequency lock (0 ppm) the incoming serial data rate to the local
reference clock device input.
2. Provision the TX SERDES REFCLK to run from a jitter cleaned
version of the RX SERDES RXBCLK (Receive Byte Clock).
VDDO
2.5 V LVCMOS
Input
PRBS Enable. When this pin is asserted high, the internal PRBS
generator and comparator circuits are enabled on the transmit and receive
data paths. The PRBS results can be read through MDIO counters.
Primary chip output signal GPO0 remains low during PRBS testing when
the input serial stream PRBS pattern is correct, and pulses high when
PRBS errors are detected on the input serial stream.
GPO0 contains the Channel 0 PRBS currently passing (when low)
indication.
An external loopback connection (via external cables) is required during
PRBS testing.
PRBS 27-1 is transmitted on each transmit channel serial output, and
compared on each receive channel serial input.
VDDO
2.5 V LVCMOS
Input
Code Enable. This signal is logically OR’d with the PCS_EN register bit
(Register Bit 17.3). RGMII/GMII applications can either tie this input signal
high (preferred) or tie this signal low (must program the PCS_EN 17.3
register bit after device reset to high if CODE is tied off low). Non
RGMII/GMII applications must tie this input signal low.
VDDO
VDDO
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Table 3-2. JTAG Signals
SIGNAL
LOCATION
VOLTAGE
TYPE
DESCRIPTION
JTAG Input Data. TDI is used to serially shift test data and test instructions
into the device during the operation of the test port.
TDI
J12
VDDO
2.5 V LVCMOS
Input (Internal
Pullup)
TDO
F11
VDDO
2.5 V LVCMOS
Output
JTAG Output Data. TDO is used to serially shift test data and test
instructions out of the device during operation of the test port. When the JTAG
port is not in use, TDO is in a high impedance state.
TMS
J11
VDDO
2.5 V LVCMOS
Input (Internal
Pullup)
JTAG Mode Select. TMS is used to control the state of the internal test-port
controller.
TCK
H12
VDDO
2.5 V LVCMOS
Input
JTAG Clock. TCK is used to clock state information and test data into and out
of the device during the operation of the test port.
TRST_N
K12
VDDO
2.5 V LVCMOS
Input (Internal
Pullup)
JTAG Test Reset. TRST_N is used to reset the JTAG logic into system
operational mode.
Table 3-3. MDIO Related Signals
SIGNAL
MDC
MDIO
PRTAD[4:
0]
REFCLK
LOCATION
G12
E12
J10
L11
L2
M1
M12
H2
VOLTAGE
TYPE
DESCRIPTION
VDDM
1.2 V OR 2.5 V
LVCMOS Input
Management Interface Clock This clock is used to sample the MDIO signal.
VDDM
1.2 V OR 2.5 V
LVCMOS Input/
Output
Management Interface Data This bidirectional data line for MDIO Port is
sampled on the rising edge of MDC.
THIS SIGNAL MUST BE EXTERNALLY PULLED UP TO VDDM. Consult
IEEE802.3 Clause 22/45 for an appropriate resistance value.
VDDO
2.5 V LVCMOS
Input
Port Address Used to select Port ID in Clause 22 MDIO modes.
PRTAD[4:1] selects a block of two sequential Clause 22 port addresses.
Each channel (second channel datapath is not pinned out) is implemented as
a different port address, and can be accessed by setting the appropriate port
address field within the Clause 22 MDIO transaction.
PRTAD[0] is not used functionally, but is needed for device testability with
other devices in the family of products.
Channel 0 responds to port address 0 within the block of two port addresses.
Channel 1 (datapath not usable) responds to port address 1 within the block
of two port addresses.
VDDO
2.5 V LVCMOS
Input
Single Ended Reference Clock Single ended reference clock input. By
default, the differential reference clock (REFCLKP/N) is selected. This default
value may be changed by a mdio register (37120.15:14). The acceptable
input frequency range on this input signal is 50 MHz → 150 MHz.
Jitter performance is optimal when using the differential REFCLK input.
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Table 3-4. Parallel Data Pins
SIGNAL
TXCLK_0
TXD_[7:0]
E11
A12
B10
C9
D10
B8
D11
C10
A10
VOLTAGE
VDDQ/ VREF1/2
Transmit Data Pins Parallel interface data pins.
See the following tables for functionality per application mode:
Table 2-3 RGMII - Lane To Functional Pin Mapping
Table 2-4 RTBI - Lane To Functional Pin Mapping
Table 2-5 TBI - Lane To Functional Pin Mapping
1.5/1.8 V Table 2-6 GMII - Lane To Functional Pin Mapping
HSTL Input Table 2-7 EBI - Lane To Functional Pin Mapping
Table 2-8 REBI - Lane To Functional Pin Mapping
Table 2-9 NBI - Lane To Functional Pin Mapping
Table 2-10 RNBI - Lane To Functional Pin Mapping
Table 2-11 TBID - Lane To Functional Pin Mapping
Table 2-12 NBID - Lane To Functional Pin Mapping
Transmit Data Control Parallel Control inputs.
See the following tables for functionality per application mode:
Table 2-3 RGMII - Lane To Functional Pin Mapping
Table 2-4 RTBI - Lane To Functional Pin Mapping
Table 2-5 TBI - Lane To Functional Pin Mapping
1.5/1.8 V Table 2-6 GMII - Lane To Functional Pin Mapping
HSTL Input Table 2-7 EBI - Lane To Functional Pin Mapping
Table 2-8 REBI - Lane To Functional Pin Mapping
Table 2-9 NBI - Lane To Functional Pin Mapping
Table 2-10 RNBI - Lane To Functional Pin Mapping
Table 2-11 TBID - Lane To Functional Pin Mapping
Table 2-12 NBID - Lane To Functional Pin Mapping
VDDQ/ VREF1/2
RXCLK_0
A4
VDDQ
RXC_[4,0]
C6
B6
DESCRIPTION
VDDQ/ VREF1/2
C8
B11
C2
B2
B3
B1
A2
A5
A6
C5
TYPE
1.5/1.8 V
Transmit Data Clock (Parallel I/F) This is the parallel side input clock.
HSTL Input
TXC_[4,0]
RXD_[7:0]
62
LOCATION
VDDQ
VDDQ
Device Reset Requirements/Procedure
1.5/1.8 V
HSTL
Output
Receive Data Clock This signal is the parallel side output clock.
1.5/1.8 V
HSTL
Output
Receive Data Pins Parallel interface data pins.
See the following tables for functionality per application mode:
Table 2-3 RGMII - Lane To Functional Pin Mapping
Table 2-4 RTBI - Lane To Functional Pin Mapping
Table 2-5 TBI - Lane To Functional Pin Mapping
Table 2-6 GMII - Lane To Functional Pin Mapping
Table 2-7 EBI - Lane To Functional Pin Mapping
Table 2-8 REBI - Lane To Functional Pin Mapping
Table 2-9 NBI - Lane To Functional Pin Mapping
Table 2-10 RNBI - Lane To Functional Pin Mapping
Table 2-11 TBID - Lane To Functional Pin Mapping
Table 2-12 NBID - Lane To Functional Pin Mapping
1.5/1.8 V
HSTL
Output
Receive Data Control Control inputs.
See the following tables for functionality per application mode:
Table 2-3 RGMII - Lane To Functional Pin Mapping
Table 2-4 RTBI - Lane To Functional Pin Mapping
Table 2-5 TBI - Lane To Functional Pin Mapping
Table 2-6 GMII - Lane To Functional Pin Mapping
Table 2-7 EBI - Lane To Functional Pin Mapping
Table 2-8 REBI - Lane To Functional Pin Mapping
Table 2-9 NBI - Lane To Functional Pin Mapping
Table 2-10 RNBI - Lane To Functional Pin Mapping
Table 2-11 TBID - Lane To Functional Pin Mapping
Table 2-12 NBID - Lane To Functional Pin Mapping
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Table 3-5. Serial Side Data/Clock Pins
SIGNAL
LOCATION
TDP0/TDN0
L4
L3
VOLTAGE
TYPE
AVDD
CML Output
Transmit Differential Pairs High speed serial outputs. The data rate
of these signals is from 600 Mbps minimum to 3.75 Gbps maximum.
DESCRIPTION
RDP0/RDN0
L8
L9
AVDD
CML Input
Receive Differential Pairs, High speed serial inputs with on-chip 100
Ω differential termination. Each input pair is terminated differentially
across an on chip 100 Ω resistor. The data rate of these signals is
from 600 Mbps minimum to 3.75 Gbps maximum.
SIGNAL
LOCATION
VOLTAGE
TYPE
VPP
A7
B7
DVDD
P
TESTEN
J1
VDDO
LVCMOS 2.5 V
Input
Test Mode Enable Input – Must Be Grounded in the System
Application.
AMUX1
M10
N/A
Analog Output
SERDES Analog Mux 1 RX – Must be Unconnected/Open in the
System Application
AMUX0
M6
N/A
Analog Output
SERDES Analog Mux 0 TX – Must be Unconnected/Open in the
System Application
RES[4:3,1]
A9
C12
C3
N/A
Resistive
Connection
GPI1
L12
VDDO
LVCMOS 2.5 V
Input
General Purpose Input – Must be Grounded in the System
Application.
GPO[4:0]
K1
G10
F10
G9
K2
LVCMOS 2.5 V
Output
General Purpose Outputs – Must be Unconnected/Open in the
System Application.
It is recommended that these output ports go to headers or
non-populated resistor pads to facilitate probing of internal device
functions/settings during the initial system bring up process.
Also, to monitor PRBS testing real time, these outputs must be
available for probing on the application board.
Table 3-6. Miscellaneous Pins
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VDDO
DESCRIPTION
Efuse Controller Voltage (1.2 V). Must be tied to 1.2 V (DVDD) in the
system application.
HSTL Impedance Control Resistors – 0.5% Tolerance Resistor
required of the following values:
150 Ohms between RES4 and GND
150 Ohms between RES3 and GND
50 Ohms between RES1 and GND
Note: These resistors cannot be shared between output pins.
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Table 3-7. Voltage Supply and Reference Pins
64
SIGNAL
LOCATION
TYPE
DVDD
D4, D6, D8,
E9, H9, J3, K7
DESCRIPTION
P
Digital Core Power Supply (1.2 V ±5%)
VDDO
D1, G11, H3
P
LVCMOS and Bias Power (2.5 V ±5%)
VDDM
F12
P
MDIO Power (2.5 V or 1.2 V ±5%)
VDDQ
A3, B12, B4, B9,
C1, D5, D7, D9, E10
P
HSTL Power (1.5/1.8 V)
1.5 V Operation Range: 1.4 V → 1.6 V
1.8 V Operation Range: 1.7V → 1.9 V
VREF1, VREF2
D12, A8
P
HSTL Reference Voltage (0.75 V or 0.9 V)
These signals should be equal to VDDQ divided by 2.
DGND
A1, A11, B5, C11,
C4, C7, D3,
E5, E6, E7, E8,
F5, F6, F7, F8, F9,
G5, G6, G7, G8,
H5, H6, H7, H8
G
Digital Ground
AVDD
J5, J7, J8,
K10, L5, L7, M3
P
Analog Power (1.2 V ±5%)
AGND
J6, J9, K4, K8,
L10, L6, M4, M8
G
Analog Ground
VDDR
K5, M9
P
SERDES Voltage Regulator Input (1.5 V –or– 1.8 V)
VDDT
K3, K6, K9
P
SERDES Termination Voltage (1.2 V)
VDDD
M11, M5, M7
P
SERDES Digital Power (1.2 V)
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Table 3-8. Jitter Cleaner Related Pins
SIGNAL
LOCATION
TYPE
DESCRIPTION
REFCLKP/
REFCLKN
G1
F1
I
Differential Reference Clock Inputs
By default, the differential reference clock (REFCLKP/N) is selected.
This default value may be changed by a mdio register (37120.15:14).
Must Be Externally AC Coupled
REFCLKP – DPECL REFCLK P Input
REFCLKN – DPECL REFCLK N Input
Acceptable input frequency range is 50 MHz → 375 MHz.
Jitter performance is optimal when using the differential REFCLK input.
VDDA_VCO
F4
P
Jitter Cleaner – VCO Supply – 1.2 V
VSSA_VCO
E2
G
Jitter Cleaner Ground
VDDA_CP
G3
P
Jitter Cleaner – Charge Pump – 1.2 V
VSSA_CP
G4
G
Jitter Cleaner Ground
VDD_CML
H1
P
Jitter Cleaner – REFCLKP/N Input Supply – 1.2 V
VSS_CML
G2
G
Jitter Cleaner Ground
VDD_PLL
E4
P
Jitter Cleaner Digital Power (1.2 V)
VSS_PLL
E1
G
Jitter Cleaner Ground
VCO_TL_TST
H4
Analog Input
VCO Testability Input. This signal should be grounded in the application.
TST_OUT
E3
Analog
Input/Output
Jitter Cleaner Testability Pin. This signal should be left open (unconnected) in the
application.
CP_OUT
F3
Analog Output
Charge Pump Output. If the internal Jitter Cleaner PLL is used, this signal should be
connected to the input of the external loop filter (See Figure B-1). If the internal Jitter
Cleaner PLL is not used, this node should be left open (unconnected).
VTUNE
F2
Analog Input
LC VCO Bias Voltage. This signal should be connected to the output of the external
loop filter if the Jitter Cleaner PLL is used (Figure B-1). If the internal Jitter Cleaner
PLL is not used, this node should be grounded.
A
B
1
DGND
RXD_4
2
RXD_3
RXD_6
C
D
E
VDDQ
VDDO
VSS_PLL
RXD_7
SPEED1
VSSA_VCO
F
G
H
J
REFCLKN
REFCLKP
VDD_CML
TESTEN
VTUNE
VSS_CML
REFCLK
CODE
K
L
M
GPO4
PRBS_EN
PRTAD1
GPO0
PRTAD2
RST_N
3
VDDQ
RXD_5
RES1
DGND
TST_OUT
CP_OUT
VDDA_CP
VDDO
DVDD
VDDT
TDN0
AVDD
4
RXCLK_0
VDDQ
5
RXD_2
DGND
6
RXD_1
RXC_0
7
VPP
VPP
8
VREF2
TXD_3
9
RES4
VDDQ
10
TXD_0
TXD_6
11
DGND
TXC_0
12
TXD_7
VDDQ
DGND
DVDD
VDD_PLL
RXD_0
VDDQ
DGND
RXC_4
DVDD
DGND
DGND
VDDQ
DGND
TXC_4
DVDD
DGND
TXD_5
VDDQ
DVDD
TXD_1
TXD_4
VDDQ
DGND
TXD_2
TXCLK_0
RES3
VREF1
MDIO
VDDA_VCO
VSSA_CP
VCO_TL_TST
ENABLE
DGND
DGND
DGND
AVDD
DGND
DGND
DGND
AGND
DGND
DGND
DGND
AVDD
DGND
DGND
DGND
AVDD
DGND
GPO1
DVDD
AGND
GPO2
GPO3
SLOOP
PRTAD4
TDO
VDDO
SPEED0
TMS
VDDM
MDC
TCK
TDI
VDDR
AVDD
VDDD
VDDT
AGND
AMUX0
DVDD
AVDD
VDDD
AGND
RDP0
AGND
VDDT
RDN0
VDDR
AVDD
AGND
AMUX1
PLOOP
PRTAD3
VDDD
TRST_N
GPI1
PRTAD0
AGND
TDP0
AGND
Figure 3-1. Device Pinout Diagram – (Top View)
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4
Electrical Specifications
4.1
ABSOLUTE MAXIMUM RATINGS (1) (2)
over operating free-air temperature range (unless otherwise noted)
UNIT
Supply voltage (2)
AVDD, DVDD, VDDT, VDDD, VDDA_VCO, VDD_PLL, VDDA_CP, VDD_CML, VREF1/2
–0.3 to 1.5 V
VDDQ, VDDR
–0.3 to 2.0 V
VDDO, VDDM
–0.3 to 3.0 V
Input Voltage, VI (LVCMOS)
–0.3 to Supply + 0.3 V
Input Voltage, VI (HSTL CLASS 1)
–0.3 to 2.0 V
Storage temperature
–65°C to 150°C
Electrostatic Discharge
HBM: 2KV, CDM:500V
Characterized free-air operating temperature range
(1)
(2)
–40°C to 85°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
4.2
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
DVDD
Core supply voltage
1.14
1.2
1.26
V
AVDD
Analog supply voltage
1.14
1.2
1.26
V
1.4
1.5
1.6
V
VDDQ
Parallel HSTL I/O supply voltage
VDDO
LVCMOS I/O supply voltage
VDDM
MDIO CMOS I/O supply voltage
VREF1/2
HSTL reference voltage
IDD Supply current
1.5 V Application
1.8 V Application
1.7
1.8
1.9
2.37
2.5
2.63
1.2 V Application
1.14
1.2
1.26
2.5 V Application
2.37
2.5
2.63
1.5 V Application
0.65
0.75
0.85
1.8 V Application
0.85
0.90
0.95
66
V
V
AVDD, VDDD, VDDT
172
mA
DVDD
122
mA
VDDR
26
mA
VDDQ (1.6 V)
3.75 Gbps
VDDQ (1.9 V)
PD
V
170
210
mA
VDDO
22
mA
VDDA_VCO, VDD_PLL, VDD_CML, VDDA_CP
98
mA
Total power consumption
Electrical Specifications
See Table 4-3
W
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RECOMMENDED OPERATING CONDITIONS (continued)
PARAMETER
CONDITION
AVDD, VDDD, VDDT (1.26V)
DVDD (1.26V)
VDDR (1.9V)
(1)
ISD Shutdown
current
VDDO (2.63V)
VDDA_VCO, VDD_PLL, VDD_CML, VDDA_CP
(1.26V)
25
ENABLE low, HSTL powerdown
25
ENABLE low
61
ENABLE low, HSTL powerdown
21
ENABLE low
1
ENABLE low, HSTL powerdown
1
UNIT
mA
mA
mA
140
ENABLE low, HSTL powerdown
10
ENABLE low
17
ENABLE low, HSTL powerdown
17
ENABLE low
1
ENABLE low, HSTL powerdown
1
mA
mA
mA
REFERENCE CLOCK TIMING REQUIREMENTS (REFCLKP/N) (1) (2)
PARAMETER
CONDITION
Frequency
Minimum data rate
Accuracy
1G PCS Mode
Accuracy to TXCLK
All
Jitter
MIN
NOM
MAX
UNIT
60
–
375
MHz
100
ppm
ppm
–100
Duty Cycle
0
0
0
45%
50%
55%
Random and deterministic
40
ps
This clock should be crystal referenced to meet the requirements of the above table
Contact TI for specific clocking recommendations
4.4
REFERENCE CLOCK ELECTRICAL CHARACTERISTICS (REFCLKP/N)
PARAMETER
CONDITION
Vid
Differential Input Voltage
CIN
Input Capacitance
RIN
Input Differential Impedance
trise
Rise Time
4.5
MIN NOM
MAX
UNIT
100
2000
mVPP
80
20% to 80%
50
100
3
pF
120
Ω
600
ps
SINGLE ENDED REFERENCE CLOCK ELECTRICAL CHARACTERISTICS (REFCLK)
PARAMETER
CONDITION
MIN
VIH
High-Level Input Voltage
1.7
VIL
Low-Level Input Voltage
–0.3
IIH/IIL
High/Low Input Current
trise
Rise Time
20% → 80%
Jitter
Peak to Peak Jitter
Jitter Cleaner not used on REFCLK
Tcyc
Duty Cycle
4.6
MAX
Toggle RST_N before setting ENABLE low for proper shutdown.
4.3
(1)
(2)
NOM
ENABLE low
VDDQ (1.9V)
(1)
MIN
ENABLE low
NOM
MAX
UNIT
VDDO +
0.3
V
0.7
V
±10
µA
1
ns
40
40%
50%
ps
60%
Period
MIN NOM MAX
UNIT
1
MHz
JITTER CLEANER TIMING PARAMETERS
PARAMETER
PLL Bandwidth
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CONDITION
–3dB
Electrical Specifications
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Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
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JITTER CLEANER TIMING PARAMETERS (continued)
PARAMETER
CONDITION
MIN NOM MAX
Jitter Peaking
UNIT
0.1
dB
2
ps
VCO Output Jitter (rms)
2 MHz → 30 MHz
VCO Output Jitter (rms)
1.2 MHz → 30 MHz
2.5
ps
VCO Output Jitter (rms)
600 kHz → 30 MHz
4
ps
VCO Output Jitter (rms)
300 kHz → 30 MHz
8
ps
4.7
LVCMOS ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITION
VOH
High-level output voltage
IOH = –100 µA, Driver Enabled
VOL
Low-level output voltage
IOL = 100 µA, Driver Enabled
VIH
MIN
NOM
MAX
UNIT
2.1
VDDO
V
0
0.2
V
High-level input voltage
1.7
VDDO +
0.3
V
VIL
Low-level input voltage
–0.3
IIH, IIL
Receiver Only Low/High Input Current
IOZ
Driver Only
Driver Disabled
Driver/Receiver With Pullup/Pulldown
Driver Disabled With Pull Up/Down Enabled
CIN
4.8
0.7
V
±10
µA
±35
µA
±100
µA
5
pF
Input capacitance
MDIO ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITION
VIH
High-level input voltage VDDM = 2.5 V
VIL
Low-level input voltage
VDDM = 2.5 V
VIH
High-level input voltage VDDM = 1.2 V
VIL
Low-level input voltage
VOL
Low Level Output
Voltage
VOH
MIN NOM
MAX
UNIT
VDDM +
0.3
V
–0.3
0.7
V
0.84
VDDM +
0.3
V
–0.3
0.36
V
VDDM = 2.5 V (IOL = 100 µA)
0
0.2
V
VDDM = 1.2 V (IOL = 100 µA)
0
0.2
V
High Level Output
Voltage
VDDM = 1.2/2.5 V (Open Drain Driver) Must be pulled up to VDDM
on the customer board.
–
–
V
IIH,
IIL
Low/High Input Current
MDC Signal
±20
µA
IZ
Low/High input current
MDIO – Driver disabled
±50
µA
CIN
Input capacitance
5
pF
4.9
2.1
VDDM = 1.2 V
HSTL SIGNALS (VDDQ = 1.5/1.8 V)
PARAMETER
CONDITION
VOH(dc)
High-level output voltage
VOL(dc)
Low-level output voltage
VOH(ac)
High-level output voltage
VOL(ac)
Low-level output voltage
VIH(dc)
High-level DC input voltage
DC input, logic high
VIL(dc)
Low-level DC input voltage
DC input, logic low
VIH(ac)
High-level AC input voltage
AC input, logic high
68
–
Electrical Specifications
MIN
VDDQ– 0.4
NOM
MAX
UNIT
VDDQ
V
0.40
V
VDDQ– 0.5
VDDQ
V
0.50
V
VREF1/2 +
0.10
VDDQ + 0.3
V
–0.30
VREF1/2 – 0.1
V
VREF1/2 +
0.20
VDDQ+ 0.3
V
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HSTL SIGNALS (VDDQ = 1.5/1.8 V) (continued)
PARAMETER
CONDITION
AC input, logic low
MIN
VIL(ac)
Low-level AC input voltage
IOH(dc)
High output current
–8
IOL(dc)
Low output current
8
CIN
Input Capacitance
Tacr
AC Test Condition
Rise Time (20 → 80%)
1
Tacs
AC Test Condition
Signal Swing
1
NOM
–0.30
MAX
UNIT
VREF1/2 –
0.20
V
mA
mA
4
pF
1
1
ns
1
1
V
4.10 SERIAL TRANSMITTER/RECEIVER CHARACTERISTICS
PARAMETER
VOD(pp)
TX Output Differential Peak-to-Peak
voltage swing.
De-emphasis Amount = 0%.
See Figure 4-1
MIN
NOM
MAX
SWING = 000 (See Table 2-40)
CONDITION
80
125
180
SWING = 001 (See Table 2-40)
210
250
330
SWING = 010 (See Table 2-40)
425
500
630
SWING = 011 (See Table 2-40)
530
625
780
SWING = 100 (See Table 2-40)
635
750
900
SWING = 101 (See Table 2-40)
900
1000
1200
SWING = 110 (See Table 2-40)
1000
1250
1500
SWING = 111 (See Table 2-40)
1080
1375
1650
4.7%
UNIT
mVPP
VDE
TX Output De-Emphasis (VOD(dpp) =
VDE × Percentage of nominal VOD(pp))
See Table 2-39 for details on de-emphasis settings.
VCMT
TX output common mode voltage
See Figure 4-1.
VID
RX input differential voltage |RXP –
RXN|
See Figure 4-3. Direct Coupled Mode Only
100
600
See Figure 4-3. AC Coupled Mode Only
100
1100
RX input differential peak-to-peak
voltage swing 2 × |RXP – RXN|
See Figure 4-3. Direct Coupled Mode Only
200
1200
See Figure 4-3. AC Coupled Mode Only
200
2200
VCMR
RX input common mode voltage range
See Figure 4-3. Direct Coupled Mode Only
800
0.9 ×
AVDD
mV
Ilkg
RX input leakage current
–10
10
µA
CI
RX input capacitance
2
pF
tr, tf
Differential output signal rise, fall time
(20% to 80%)
RL = 50 Ω, CL = 5 pF, See Figure 4-1
160
ps
JTOL
Jitter Tolerance, Total Jitter at Serial
Input
Zero crossing, See Figure 4-4.
0.65
UI (1)
JDR
Serial Input Deterministic Jitter
Zero crossing, See Figure 4-4.
0.37
UI
JT
Serial Output Total Jitter
3.125 GHz.
0.35
UI
JD
Serial Output Deterministic Jitter
3.125 GHz.
0.17
UI
R(LATENCY)
Total delay from RX input to RD output
1000Base-X Mode
190
Bit Times
T(LATENCY)
Total delay from TD input to TX output
1000Base-X Mode
130
Bit Times
R(LATENCY)
Total delay from RX input to RD output
NBID Mode
110
200
Bit Times
T(LATENCY)
Total delay from TD input to TX output
NBID Mode
90
250
Bit Times
R(LATENCY)
Total delay from RX input to RD output
TBID Mode
90
200
Bit Times
T(LATENCY)
Total delay from TD input to TX output
TBID Mode
80
250
Bit Times
VID(pp)
(1)
72%
AVDD – (0.25
×
VOD(pp))
80
0.20
mV
mV
mVPP
Unit Interval = one serial bit time (min. 320 ps)
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Single Channel Multi-Rate Transceiver
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4.11
4.12
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DRIVER TEMPLATE PARAMETERS
PARAMETER
NEAR END VALUE
FAR END VALUE
UNIT
X1 (See Figure 4-2)
0.175
0.275
UI
X2 (See Figure 4-2)
0.390
0.400
UI
A1 (See Figure 4-2)
400
100
mV
A2 (See Figure 4-2)
800
800
mV
TIMING DEFINITION
VCMT
0.5 * VDE*
0.5 *
VOD(pp)
VOD(pp)
0.25 * VDE * VOD(pp)
0.25 * VOD(pp)
bit
tr, tf
time
Figure 4-1. Transmit Output Waveform Parameter Definitions
D iffe re ntia l A m plitude
(m V )
A2
A1
0
-A1
-A2
X1
X2
1-X2
X2
1.0
Time (UI)
Figure 4-2. Transmit Template
70
Electrical Specifications
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D iffe re ntia l A m plitude
(m V )
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+100
0
-100
0.325
0.675
Unit Interval
1.0
Figure 4-3. Receive Template
JDR
JR
JR
JTOL
Note: JTOL = JR + JDR, where JTOL is the receive jitter tolerance, JDR is the received deterministic jitter, and JR is the
Gaussian random edge jitter distribution at a maximum BER = 10-12.
Figure 4-4. Input Jitter
4.13
APPLICATION MODES
The TLK3131 has several different application modes, which impact parallel interface I/O timing definitions. Each of the
modes is defined below, and then subsequently referred to in the detailed timing parameter definitions. RXDATA and RXCLK,
and TXDATA and TXCLK in the detailed timing specification will be defined by the exact following signal definitions.
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Table 4-1. Parallel Interface – Valid Signal Operational Mode Definitions
TIMING
MODE
NAME
USAGE MODE
TX SIGNALS USED
RX SIGNALS USED
TXDATA = TXD_[4:0]
TXCLK = TXCLK_[0]
RXDATA = RXD_[4:0]
RXCLK = RXCLK_[0]
TBI, GMII
Ten Bit Interface Mode (TBI)
Only SDR Timing Supported
See Section 4.15: HSTL Output Switching Characteristics (SDR Timing
Mode Only) and Section 4.17: HSTL (SDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In GMII Mode
CH0: TX_EN = TXC_[0]
CH0: TX_ER = TXC_[4]
CH0: RX_DV = RXC_[0]
CH0: RX_ER = RXC_[4]
Note: In TBI Mode
CH0: TX Data Bit 8 = TXC_[0]
CH0: TX Data Bit 9 = TXC_[4]
CH0: RX Data Bit 8 = RXC_[0]
CH0: RX Data Bit 9 = RXC_[4]
TXDATA = TXC_ [4],TXC_ [0],
TXD[7:0]
TXCLK = TXCLK_ [0]
RXDATA = RXC_ [4],RXC_ [0],
RXD[7:0]
RXCLK = RXCLK_ [0]
EBI
Eight Bit Interface Mode (EBI)
SDR Timing Support
See Section 4.15: HSTL Output Switching Characteristics (SDR Timing
Mode Only) and Section 4.17: HSTL (SDR Timing Mode Only) Input Timing
Requirements for AC timing details.
TXDATA = TXD_ [7:0]
TXCLK = TXCLK_ [0]
RXDATA = RXD_ [7:0]
RXCLK = RXCLK_ [0]
REBI
Reduced Eight Bit Interface Mode (REBI)
DDR Timing Support
See Section 4.14: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.16: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
TXDATA = TXD_ [3:0]
TXCLK = TXCLK_ [0]
RXDATA = RXD_ [3:0]
RXCLK = RXCLK_ [0]
NBI
Nine Bit Interface Mode (NBI)
(Un-encoded Data Byte + 1 Control Bit)
SDR Timing Support
See Section 4.15: HSTL Output Switching Characteristics (SDR Timing
Mode Only) and Section 4.17: HSTL (SDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In NBI Mode
CH0: TX Control Bit = TXC_[0]
CH0: RX Control Bit = RXC_[0]
TXDATA = TXC_ [0], TXD[7:0]
TXCLK = TXCLK_ [0]
RXDATA = RXC_ [0], RXD[7:0]
RXCLK = RXCLK_ [0]
RNBI
Reduced Nine Bit Interface Mode (RNBI)
(Un-encoded Data Byte + 1 Control Bit)
DDR Timing Support
See Section 4.14: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.16: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In RNBI Mode
CH0: TX Control Bit = TXD_[4]
CH0: RX Control Bit = RXD_[4]
TXDATA = TXD_[4:0]
TXCLK = TXCLK_[0]
RXDATA = RXD_[4:0]
RXCLK = RXCLK_[0]
TBID
Ten Bit Interface DDR Mode (TBID)
Only DDR Timing Supported
See Section 4.14: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.16: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In TBID Mode
CH0: TX Data Bit 8 = TXC_[0]
CH0: TX Data Bit 9 = TXC_[4]
CH0: RX Data Bit 8 = RXC_[0]
CH0: RX Data Bit 9 = RXC_[4]
TXDATA = TXC_ [4],TXC_ [0],
TXD[7:0]
TXCLK = TXCLK_ [0]
RXDATA = RXC_ [4],RXC_ [0],
RXD[7:0]
RXCLK = RXCLK_ [0]
NBID
Nine Bit Interface DDR Mode (NBID)
(Un-encoded Data Byte + 1 Control Bit)
DDR Timing Support
See Section 4.14: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.16: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In NBID Mode
CH0: TX Control Bit = TXC_[0]
CH0: RX Control Bit = RXC_[0]
TXDATA = TXC_ [0], TXD[7:0]
TXCLK = TXCLK_ [0]
RXDATA = RXC_ [0], RXD[7:0]
RXCLK = RXCLK_ [0]
1000Base-X Applications, Reduced Ten Bit Applications (RTBI)
Only DDR Timing Supported
See Section 4.14: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.16: HSTL (DDR Timing Mode Only) Input Timing
RGMII, RTBI
Requirements for AC timing details.
Note: In RGMII Mode
CH0: TX_EN/TX_ER = TXD_[4]
CH0: RX_DV/RX_ER = RXD_[4]
72
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4.14 HSTL Output Switching Characteristics (DDR Timing Mode Only)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
tsetup
RXDATA setup prior to RXCLK
transition high or low
Source Centered, See Figure 4-5.
Note: Cload = 10 pF, using timing reference of
VDDQ/2
0.15 ×
tperiod
ps
thold
RXDATA hold after RXCLK transition
high or low
Source Centered, See Figure 4-5.
Note: Cload = 10 pF, using timing reference of
VDDQ/2
0.15 ×
tperiod
ps
Tduty
RXCLK Duty Cycle
Source Centered and Source Aligned.
Note: Cload = 10 pF, using timing reference of
VDDQ/2.
45%
55%
tperiod
RXCLK Period
Source Centered and Source Aligned
6.25
16.67 (1)
Tfreq
RXCLK Frequency
Source Centered and Source Aligned
60 (2)
160
Tpd
RXCLK rising or falling to RXDATA
valid.
Source Aligned, See Figure 4-6.
Note: Cload = 10 pF, using timing reference of
VDDQ/2
–0.10 ×
tperiod
+0.10 ×
tperiod
(1)
(2)
ns
MHz
ps
In TBID/NBID Modes Only, the maximum allowed RXCLK period is 33.33 ns.
In TBID/NBID Modes Only, the minimum allowed RXCLK frequency is 30 MHz.
tPERIOD
VOH(ac)
VDDQ/2
RXCLK
VOL(ac)
tSETUP
tHOLD
tSETUP
tHOLD
VOH(ac)
RXDATA
VDDQ/2
VOL(ac)
Figure 4-5. HSTL (DDR Timing Mode Only) Source Centered Output Timing Requirements
VOH(ac)
VDDQ/2
RXCLK
VOL(ac)
Tpd
Tpd
VOH(ac)
RXDATA
VDDQ/2
VOL(ac)
Figure 4-6. HSTL (DDR Timing Mode Only) Source Aligned Output Timing Requirements
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4.15 HSTL Output Switching Characteristics (SDR Timing Mode Only)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Tduty
RXCLK Duty Cycle
Rising and Falling Edge Aligned Data
Note: Cload = 10pF, using timing reference of VDDQ/2.
40%
60%
tperiod
RXCLK Period
Rising and Falling Edge Aligned Data
2.67
16.67
Tfreq
RXCLK Frequency
Rising and Falling Edge Aligned Data
60
375
Tpd
RXCLK rising to RXDATA valid.
Rising Edge Aligned, See Figure 4-7
Note: Cload = 10pF, using timing reference of VDDQ/2.
–0.10 ×
tperiod
+0.10 ×
tperiod
ps
Tpd
RXCLK falling to RXDATA valid.
Falling Edge Aligned, See Figure 4-8
Note: Cload = 10pF, using timing reference of VDDQ/2.
–0.10 ×
tperiod
+0.10 ×
tperiod
ps
ns
MHz
tPERIOD
VOH(ac)
VDDQ/2
RXCLK
VOL(ac)
TPD
VOH(ac)
RXDATA
VDDQ/2
VOL(ac)
Figure 4-7. HSTL (SDR Timing Mode Only) Rising Edge Aligned Output Timing Requirements
tPERIOD
VOH(ac)
VDDQ/2
RXCLK
VOL(ac)
TPD
VOH(ac)
RXDATA
VDDQ/2
VOL(ac)
Figure 4-8. HSTL (SDR Timing Mode Only) Falling Edge Aligned Output Timing Requirements
74
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4.16 HSTL (DDR Timing Mode Only) Input Timing Requirements
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM (1)
MAX
UNIT
tsetup
TXDATA setup prior to
TXCLK transition high
or low
Source Centered. See Figure 4-9.
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all input signals.
0.075 × tperiod
ps
thold
TXDATA hold after
TXCLK transition high
or low
Source Centered. See Figure 4-9.
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all input signals.
0.075 × tperiod
ps
tduty
TXCLK Duty Cycle
Source Centered
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all input signals.
40%
60%
tduty
TXCLK Duty Cycle
Source Aligned
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all input signals.
45%
55%
tperiod
TXCLK Period
Source Centered and Aligned.
6.25
16.67 (2)
(3)
160
–0.175 ×
tperiod (4)
+0.175 ×
tperiod (5)
Tfreq
TXCLK Frequency
Source Centered and Aligned.
Tskew
TXCLK rising or falling
to TXDATA valid.
Source Aligned. See Figure 4-10.
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all input signals.
(1)
(2)
(3)
(4)
(5)
60
ns
MHz
ps
All typical values are at 25°C and with a nominal supply.
In TBID/NBID Modes Only, the maximum allowed TXCLK period is 33.33 ns.
In TBID/NBID Modes Only, the minimum allowed TXCLK frequency is 30 MHz.
In TBID/NBID Modes, when the TXCLK is in the 30 → 60 MHz range, this parameter becomes -0.10 × tperiod
In TBID/NBID Modes, when the TXCLK is in the 30→ 60 MHz range, this parameter becomes +0.10 × tperiod
tPERIOD
VIH(ac)
VDDQ/2
TXCLK
VIL(ac)
tSETUP
tHOLD
tSETUP
tHOLD
VIH(ac)
TXDATA
VDDQ/2
VIL(ac)
Figure 4-9. HSTL (DDR Timing Mode Only) Source Centered Data Input Timing Requirements
VOH(ac)
VDDQ/2
TXCLK
VOL(ac)
Tskew
Tskew
VOH(ac)
TXDATA
VDDQ/2
VOL(ac)
Figure 4-10. HSTL (DDR Timing Mode Only) Source Aligned Data Input Timing Requirements
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4.17 HSTL (SDR Timing Mode Only) Input Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
NOM (1)
MAX
UNIT
tsetup
TXDATA setup prior to TXCLK Falling Edge Aligned (Rising Edge Sampled) Data See
transition high
Figure 4-11.
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise
time on all input signals.
480
ps
thold
TXDATA hold after TXCLK
transition high
Falling Edge Aligned (Rising Edge Sampled) Data See
Figure 4-11.
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise
time on all input signals.
480
ps
tsetup
TXDATA setup prior to TXCLK Rising Edge Aligned (Falling Edge Sampled) Data See
transition low
Figure 4-12.
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise
time on all input signals.
480
ps
thold
TXDATA hold after TXCLK
transition low
Rising Edge Aligned (Falling Edge Sampled) Data See
Figure 4-12.
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise
time on all input signals.
480
ps
tduty
TXCLK Duty Cycle
Rising and Falling Edge Sampled Data
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise
time on all input signals.
40%
60%
tperiod TXCLK Period
Rising and Falling Edge Aligned Data
2.67
16.67
Tfreq
Rising and Falling Edge Aligned Data
60
375
(1)
TXCLK Frequency
ns
MHz
All typical values are at 25°C and with a nominal supply.
tPERIOD
VIH(ac)
VDDQ/2
TXCLK
VIL(ac)
tSETUP
tHOLD
VIH(ac)
TXDATA
VDDQ/2
VIL(ac)
Figure 4-11. HSTL (SDR Timing Mode Only) Falling Edge Aligned (Rising Edge Sampled) Data Input
Timing Requirements
tPERIOD
VIH(ac)
VDDQ/2
TXCLK
VIL(ac)
tSETUP
tHOLD
VIH(ac)
TXDATA VDDQ/2
VIL(ac)
Figure 4-12. HSTL (SDR Timing Mode Only) Rising Edge Aligned (Falling Edge Sampled) Data Input
Timing Requirements
76
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4.18 MDIO Timing Requirements Over Recommended Operating Conditions
(Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM MAX
UNIT
tperiod
MDC period
See Figure 4-13.
100
ns
tsetup
MDIO setup to ↑ MDC
See Figure 4-13.
10
ns
thold
MDIO hold to ↑ MDC
See Figure 4-13.
10
ns
Tvalid
MDIO valid from MDC ↑
0
40
ns
MDC
tPERIOD
tSETUP
tHOLD
MDIO
Figure 4-13. MDIO Read/Write Timing
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TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
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4.19 JTAG Timing Requirements Over Recommended Operating Conditions
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
tperiod
TCK period
See Figure 4-14.
66.67
ns
tsetup
TDI/TMS/TRST_N setup to ↑ TCK
See Figure 4-14.
3
ns
thold
TDI/TMS/TRST_N hold from ↑ TCK
See Figure 4-14.
5
ns
Tvalid
TDO delay from TCK falling
See Figure 4-14.
0
5
ns
TCK
tPERIOD
tSETUP
tHOLD
TDI/TMS/
TRST_N
tVALID
TDO
Figure 4-14. JTAG Timing
VDDQ
150/200/
300/Open
(W)
50 W
50 W transmission line
+
150/200/
300/Open
(W)
VDDQ
GND
-
RW
RW
GND
OUTPUT
PCB
VREF
INPUT
Figure 4-15. HSTL I/O Schematic
78
Electrical Specifications
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Table 4-2. TLK3131 Application Mode –vs– Interface Timing Mode Support (1)
Application Mode
RGMII
GMII
TBI
RTBI
NBI
RNBI
EBI
REBI
TBID
NBID
Gigabit Ethernet
(1000Base-X) 1.25 Gbps
Y
Y
N
N
N
N
N
N
N
N
CPRI x1
0.6144 Gbps
N
N
Y
Y
Y
Y
N
N
Y
Y
CPRI x2
1.2288 Gbps
N
N
Y
Y
Y
Y
N
N
Y
Y
CPRI x4
2.4576 Gbps
N
N
Y
N
Y
N
N
N
Y
Y
OBSAI x1
0.768 Gbps
N
N
Y
Y
Y
Y
N
N
Y
Y
OBSAI x2
1.536 Gbps
N
N
Y
Y
Y
Y
N
N
Y
Y
OBSAI x4
3.072 Gbps
N
N
Y
N
Y
N
N
N
Y
Y
Fibre Channel 1X 1.0625
Gbps
N
N
Y
Y
Y
Y
N
N
Y
Y
Fibre Channel 2X 2.125
Gbps
N
N
Y
N
Y
N
N
N
Y
Y
8 Bit SERDES Mode
0.600 → 1.28 Gbps
N
N
N
N
N
N
Y
Y
N
N
8 Bit SERDES Mode
1.28 → 3.0 Gbps
N
N
N
N
N
N
Y
N
N
N
10 Bit SERDES Mode
0.600 → 1.6 Gbps
N
N
Y
Y
N
N
N
N
Y
N
10 Bit SERDES Mode
1.6 → 3.2 Gbps
N
N
Y
N
N
N
N
N
Y
N
10 Bit SERDES Mode
3.2 → 3.75 Gbps
N
N
Y
N
N
N
N
N
N
N
9 Bit SERDES Mode
0.600 → 1.6 Gbps
N
N
N
N
Y
Y
N
N
N
Y
9 Bit SERDES Mode
1.6 → 3.2 Gbps
N
N
N
N
Y
N
N
N
N
Y
9 Bit SERDES Mode
3.2 → 3.75 Gbps
N
N
N
N
Y
N
N
N
N
N
(1)
Latency Measurement only operates in TBI, TBID, and RTBI Modes
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Figure 4-16. PACKAGE Information (Package Designator = ZWQ)
80
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4.20
SLLS957 – DECEMBER 2008
PACKAGE DISSIPATION RATING
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
θJA
Junction to free air thermal resistance
Airflow = 0 M/S
31.9
°C/W
θJA
Junction to free air thermal resistance
Airflow = 0.75 M/S
29.4
°C/W
Table 4-3. Worst Case Device Power Dissipation
Device Total Worst Case Power (All Channels Active, All Supplies +5%, T=85C)
Serial Bit Rate = 3.75 Gbps
VDDQ Voltage
1.6V
JC PLL Enabled
1.9V
N
Y
N
Y
HSTL Input Termination
None
Max.
None
Max.
None
Max.
None
Max.
Total Power (mW)
686
773
748
834
777
903
840
966
Serial Bit Rate = 3.125 Gbps
VDDQ Voltage
1.6V
JC PLL Enabled
1.9V
N
Y
N
Y
HSTL Input Termination
None
Max.
None
Max.
None
Max.
None
Max.
Total Power (mW)
636
720
702
788
728
848
792
912
Serial Bit Rate =1.25 Gbps (Gigabit Ethernet)
VDDQ Voltage
1.6V
JC PLL Enabled
1.9V
N
Y
N
Y
HSTL Input Termination
None
Max.
None
Max.
None
Max.
None
Max.
Total Power (mW)
520
648
565
693
579
765
629
810
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A
www.ti.com
APPENDIX A – Frequency Ranges Supported
The following tables show the details of REFCLK input frequency versus Jitter Cleaner PLL multiplier
value for each application TLK3131 supports.
If the desired serial bit rate is between 2.0 Gbps and 3.75 Gbps, full rate should be selected for the
RATE[1:0] bits for that channel.
If the desired serial bit rate is between 1.0 Gbps and 2.125 Gbps, half rate should be selected for the
RATE[1:0] bits for that channel.
If the desired serial bit rate is between 600 Mbps and 1.0625 Gbps, quarter rate should be selected for the
RATE[1:0] bits for that channel.
If the desired serial bit rate falls in the overlap between the full and half rate ranges defined above, then
either setting is appropriate.
If the desired serial bit rate falls in the overlap between the half and quarter rate ranges defined above,
then either setting is appropriate.
In general, there are many different settings that will yield the same serial bit rate. It should be noted that
selecting the setting with the highest SERDES REFCLK and the lowest SERDES PLL Multiplier will give
the best serial performance.
Table A-1. Reference Clock Selection – Gigabit Ethernet Mode
Gigabit Ethernet Mode - Legal Clocking Mode Settings
TLK3131 REFLK
Input (MHz)
Jitter Cleaner
Multiplier
SERDES
REFCLK Input
(MHz)
SERDES PLL
Multiplier
Full (00)
Half (01)
Qrtr. (10)
62.50000
OFF
62.50000
20
2500.000
1250.000
625.000
62.50000
0.25
15.62500
62.50000
0.5
31.25000
62.50000
1
62.50000
20
2500.000
1250.000
625.000
82
Serial Data Rate = f(SPEED[1:0]) (Mbps)
62.50000
2
125.00000
10
2500.000
1250.000
625.000
125.00000
OFF
125.00000
10
2500.000
1250.000
625.000
125.00000
0.25
31.25000
125.00000
0.5
62.50000
20
2500.000
1250.000
625.000
125.00000
1
125.00000
10
2500.000
1250.000
625.000
125.00000
2
250.00000
5
2500.000
1250.000
625.000
250.00000
OFF
250.00000
5
2500.000
1250.000
625.000
250.00000
0.25
62.50000
20
2500.000
1250.000
625.000
250.00000
0.5
125.00000
10
2500.000
1250.000
625.000
250.00000
1
250.00000
5
2500.000
1250.000
625.000
250.00000
2
500.00000
APPENDIX A – Frequency Ranges Supported
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Table A-2. Reference Clock Selection – 1X/2X Fibre Channel Mode
Fibre Channel Mode - Legal Clocking Mode Settings
TLK3131 REFLK
Input (MHz)
Jitter Cleaner
Multiplier
SERDES
REFCLK Input
(MHz)
SERDES PLL
Multiplier
Serial Data Rate = f(SPEED[1:0]) (Mbps)
Full (00)
Half (01)
53.12500
OFF
53.12500
20
2125.000
1062.500
53.12500
0.25
13.28125
53.12500
0.5
26.56250
53.12500
1
53.12500
20
2125.000
1062.500
53.12500
2
106.25000
10
2125.000
1062.500
106.25000
OFF
106.25000
10
2125.000
1062.500
106.25000
0.25
26.56250
106.25000
0.5
53.12500
20
2125.000
1062.500
106.25000
1
106.25000
10
2125.000
1062.500
106.25000
2
212.50000
5
2125.000
1062.500
212.50000
OFF
212.50000
5
2125.000
1062.500
212.50000
0.25
53.12500
20
2125.000
1062.500
212.50000
0.5
106.25000
10
2125.000
1062.500
212.50000
1
212.50000
5
2125.000
1062.500
Qrtr. (10)
Table A-3. Reference Clock Selection – OBSAI Mode
Gigabit Ethernet Mode - Legal Clocking Mode Settings
TLK3131 REFLK
Input (MHz)
Jitter Cleaner
Multiplier
SERDES
REFCLK Input
(MHz)
SERDES PLL
Multiplier
Full (00)
Half (01)
Qrtr. (10)
76.80000
OFF
76.80000
20
3072.000
1536.000
768.000
76.80000
0.25
19.20000
76.80000
0.5
38.40000
76.80000
1
76.80000
20
3072.000
1536.000
768.000
76.80000
2
153.60000
10
3072.000
1536.000
768.000
153.60000
OFF
153.60000
10
3072.000
1536.000
768.000
153.60000
0.25
38.40000
153.60000
0.5
76.80000
20
3072.000
1536.000
768.000
153.60000
1
153.60000
10
3072.000
1536.000
768.000
153.60000
2
307.20000
5
3072.000
1536.000
768.000
307.20000
OFF
307.20000
5
3072.000
1536.000
768.000
307.20000
0.25
76.80000
20
3072.000
1536.000
768.000
307.20000
0.5
153.60000
10
3072.000
1536.000
768.000
307.20000
1
307.20000
5
3072.000
1536.000
768.000
307.20000
2
614.40000
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Serial Data Rate = f(SPEED[1:0]) (Mbps)
APPENDIX A – Frequency Ranges Supported
83
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
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Table A-4. Reference Clock Selection – CPRI Mode
Reference Clock Selection – CPRI Mode
TLK3131 REFLK
Input (MHz)
Jitter Cleaner
Multiplier
SERDES
REFCLK Input
(MHz)
Serial Data Rate = f(SPEED[1:0]) (Mbps)
61.44000
OFF
61.44000
61.44000
0.25
15.36000
61.44000
0.5
30.72000
61.44000
1
61.44000
20
2457.600
1228.800
614.400
61.44000
2
122.88000
10
2457.600
1228.800
614.400
122.88000
OFF
122.88000
10
2457.600
1228.800
614.400
122.88000
0.25
30.72000
122.88000
0.5
61.44000
20
2457.600
1228.800
614.400
122.88000
1
122.88000
10
2457.600
1228.800
614.400
122.88000
2
245.76000
5
2457.600
1228.800
614.400
245.76000
OFF
245.76000
5
2457.600
1228.800
614.400
245.76000
0.25
61.44000
20
2457.600
1228.800
614.400
245.76000
0.5
122.88000
10
2457.600
1228.800
614.400
245.76000
1
245.76000
5
2457.600
1228.800
614.400
SERDES PLL
Multiplier
Full (00)
Half (01)
Qrtr. (10)
20
2457.600
1228.800
614.400
Table A-5. Reference Clock Selection – 9/10 Bit SERDES Mode – Full Rate (SPEED[1:0] = 00)
Nine/Ten Bit SERDES Mode – Clock Range Support (RATE[1:0]=00) (Full)
REFLK
SERDES REFCLK
Minimum
(MHz)
Maximum
(MHz)
200.0000
375.0000
100.0000
50.0000
200.0000
Jitter Cleaner
Multiplier
FULL
Minimum
(MHz)
Maximum
(MHz)
Minimum
Maximum
OFF
200.0000
375.0000
5
2000.00
3750.00
187.5000
OFF
100.0000
187.5000
10
2000.00
3750.00
93.7500
OFF
50.0000
93.7500
20
2000.00
3750.00
2000.00
3750.00
375.0000
0.25
5
0.25
10
0.25
50.0000
93.7500
0.5
20
5
200.0000
375.0000
0.5
100.0000
187.5000
10
2000.00
3750.00
100.0000
187.5000
0.5
50.0000
93.7500
20
2000.00
3750.00
100.0000
187.5000
1
100.0000
187.5000
10
2000.00
3750.00
50.0000
93.7500
1
50.0000
93.7500
20
2000.00
3750.00
50.0000
93.7500
100.0000
187.5000
10
2000.00
3750.00
1
5
2
2
2
84
Serial Data Rate (Mbps)
SERDES PLL
Multiplier
APPENDIX A – Frequency Ranges Supported
5
20
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Table A-6. Reference Clock Selection – 9/10 Bit SERDES Mode – Half Rate (SPEED[1:0] = 01)
Nine/Ten Bit SERDES Mode – Clock Range Support (RATE[1:0]=01) (Half)
REFLK
SERDES REFCLK
Minimum
(MHz)
Maximum
(MHz)
200.0000
375.0000
100.0000
50.0000
200.0000
Jitter Cleaner
Multiplier
Minimum
(MHz)
Maximum
(MHz)
OFF
200.0000
375.0000
212.5000
OFF
100.0000
106.2500
OFF
50.0000
375.0000
Serial Data Rate (Mbps)
SERDES PLL
Multiplier
Maximum
5
1000.00
1875.00
212.5000
10
1000.00
2125.00
106.2500
20
1000.00
2125.00
1000.00
1875.00
0.25
5
0.25
10
0.25
50.0000
Half
Minimum
93.7500
0.5
20
5
200.0000
375.0000
0.5
100.0000
187.5000
10
1000.00
1875.00
100.0000
212.5000
0.5
50.0000
106.2500
20
1000.00
2125.00
1
5
100.0000
200.0000
1
100.0000
200.0000
10
1000.00
20000.00
50.0000
106.2500
1
50.0000
106.2500
20
1000.00
2125.00
1000.00
2000.00
2
50.0000
100.0000
2
5
100.0000
200.0000
2
10
20
Table A-7. Reference Clock Selection – 9/10 Bit SERDES Mode – Quarter Rate (SPEED[1:0] = 10)
Nine/Ten Bit SERDES Mode – Clock Range Support (RATE[1:0]=10) (Quarter)
REFLK
SERDES REFCLK
Minimum
(MHz)
Maximum
(MHz)
240.0000
375.0000
120.0000
60.0000
Jitter Cleaner
Multiplier
Minimum
(MHz)
Maximum
(MHz)
OFF
240.0000
375.0000
212.5000
OFF
120.0000
106.2500
OFF
60.0000
Maximum
5
600.00
937.50
212.5000
10
600.00
1062.50
106.2500
20
600.00
1062.50
600.00
937.50
5
0.25
375.0000
0.25
Quarter
Minimum
0.25
240.0000
Serial Data Rate (Mbps)
SERDES PLL
Multiplier
10
60.0000
93.7500
0.5
20
5
240.0000
375.0000
0.5
120.0000
187.5000
10
600.00
937.50
120.0000
212.5000
0.5
60.0000
106.2500
20
600.00
1062.50
120.0000
200.0000
1
120.0000
200.0000
10
600.00
1000.00
60.0000
106.2500
1
60.0000
106.2500
20
600.00
1062.50
600.00
1000.00
1
5
2
60.0000
100.0000
2
2
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5
120.0000
200.0000
10
20
APPENDIX A – Frequency Ranges Supported
85
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
www.ti.com
Table A-8. Reference Clock Selection – 8 Bit SERDES Mode – Full Rate (SPEED[1:0] = 00)
Eight Bit SERDES Mode – Clock Range Support (RATE[1:0]=00) (Full)
REFLK
SERDES REFCLK
Minimum
(MHz)
Maximum
(MHz)
250.0000
375.0000
125.0000
187.5000
250.0000
375.0000
Jitter Cleaner
Multiplier
Minimum
(MHz)
Maximum
(MHz)
OFF
250.0000
375.0000
OFF
125.0000
187.5000
187.5000
62.5000
93.7500
Maximum
4
2000.00
3000.00
8
2000.00
3000.00
2000.00
3000.00
2000.00
3000.00
2000.00
3000.00
4
0.25
8
0.5
4
0.5
125.0000
187.5000
1
8
4
125.0000
187.5000
125.0000
187.5000
2
2
FULL
Minimum
0.25
1
125.0000
Serial Data Rate (Mbps)
SERDES PLL
Multiplier
8
4
8
Table A-9. Reference Clock Selection – 8 Bit SERDES Mode – Half Rate (SPEED[1:0] = 01)
Eight Bit SERDES Mode – Clock Range Support (RATE[1:0]=01) (Half)
REFLK
SERDES REFCLK
Minimum
(MHz)
Maximum
(MHz)
250.0000
375.0000
125.0000
265.6250
Jitter Cleaner
Multiplier
375.0000
125.0000
200.0000
Maximum
(MHz)
Minimum
Maximum
OFF
250.0000
375.0000
4
1000.00
1500.00
OFF
125.0000
265.6250
8
1000.00
2125.00
1000.00
1500.00
1000.00
1600.00
1000.00
1600.00
0.25
4
0.25
8
0.5
4
125.0000
187.5000
125.0000
200.0000
1
1
100.0000
2
8
4
2
62.5000
Half
Minimum
(MHz)
0.5
250.0000
Serial Data Rate (Mbps)
SERDES PLL
Multiplier
8
4
125.0000
200.0000
8
Table A-10. Reference Clock Selection – 8 Bit SERDES Mode – Quarter Rate (SPEED[1:0] = 10)
Eight Bit SERDES Mode – Clock Range Support (RATE[1:0]=10) (Quarter)
REFLK
SERDES REFCLK
Minimum
(MHz)
Maximum
(MHz)
300.0000
375.0000
150.0000
265.6250
Jitter Cleaner
Multiplier
375.0000
Maximum
(MHz)
OFF
300.0000
375.0000
4
600.00
750.00
OFF
150.0000
265.6250
8
600.00
1062.50
600.00
750.00
200.0000
600.00
800.00
600.00
800.00
4
0.25
8
0.5
1
86
100.0000
2
APPENDIX A – Frequency Ranges Supported
Maximum
4
150.0000
187.5000
8
4
150.0000
200.0000
2
75.0000
Minimum
0.25
1
150.0000
Quarter
Minimum
(MHz)
0.5
300.0000
Serial Data Rate (Mbps)
SERDES PLL
Multiplier
8
4
150.0000
200.0000
8
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1
1
4
1
53.125
212.5
4
318.75
106.25
1
1
79.6875
159.375
4
312.5
1
1
78.125
156.25
1
4
153.6
76.8
307.2
4
1
245.76
1
61.44
122.88
1
1
4
125
250
56
28
56
38
19
38
40
20
40
40
20
40
48
24
48
48
24
48
(Decimal)
(Decimal)
62.5
4/5.37124:6:0
4/5.37124:14:8
(Mhz)
FB_DIV[6:0]
REF_DIV[6:0]
REFCLK
PLL_MULT[3:0]
5
10
10
5
10
5
10
5
10
5
10
See Note 1 Below
2X
7
14
28
4.75
9.5
19
5
10
20
5
10
20
6
12
24
6
12
24
4/5.37125:6:0
RXTX_DIV[6:0]
PLL_MULT[3:0]
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
5
10
20
10
20
5
10
20
5
10
20
5
10
20
5
10
20
See Note 1 Below
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
FC (1x/2x)
10GFC
XAUI (10 GbE)
OBSAI
(1x/2x/4x)
CPRI
(1x/2x/4x)
Gigabit
Ethernet
Mode
Application
1X
14
28
56
9.5
19
38
10
20
40
10
20
40
12
24
48
12
24
48
4/5.37125:6:0
RXTX_DIV[6:0]
0.5X
10
20
10
20
10
20
10
20
10
20
10
20
See Note 1 Below
PLL_MULT[3:0]
Jitter Cleaner PLL Multiplier Ratio
28
56
19
38
76
20
40
80
20
40
80
24
48
96
24
48
96
4/5.37125:6:0
RXTX_DIV[6:0]
20
20
20
20
20
20
20
See Note 1 Below
PLL_MULT[3:0]
0.25X
56
112
38
76
152
40
80
160
40
80
160
48
96
192
48
96
192
4/5.37125:6:0
RXTX_DIV[6:0]
SERDES
If 2x --> 2'b00 (Full)
If 1x --> 2'b01 (Half)
2'b00 (Full)
2'b00 (Full)
If 4x --> 2'b00 (Full)
If 2x --> 2'b01 (Half)
If 1x --> 2'b10 (1/4)
If 4x --> 2'b00 (Full)
If 2x --> 2'b01 (Half)
If 1x --> 2'b10 (1/4)
2'b01 (Half)
See Note 2 Below
RATE[1:0]
TLK3131
Single Channel Multi-Rate Transceiver
www.ti.com
SLLS957 – DECEMBER 2008
Figure A-1. Standard Based Jitter Cleaner/SERDES Provisioning
APPENDIX A – Frequency Ranges Supported
87
88
REFCLK (Mhz)
SERDES RATE [1:0] (See Note 2 Below)
REF_DIV[6:0]
FB_DIV[6:0]
2'b00 (Full)
2'b01 (Half)
2'b10 (Quarter)
4/5.37124:14:8
4/5.37124:6:0
PLL_MULT[3:0]
RXTX_DIV[6:0]
Min
Max
(Decimal)
(Decimal)
See Note 1 Below
4/5.37125:6:0
Min
Max
Min
Max
Min
Max
50.0000
52.0833
1
60
10
30
2000.000
2083.333
1000.000 1041.667
500.000
520.833
50.4310
53.8793
1
58
10
29
2017.241
2155.172
1008.621 1077.586
504.310
538.793
52.2321
55.8036
1
56
10
28
2089.286
2232.143
1044.643 1116.071
522.321
558.036
54.1667
57.8704
1
54
10
27
2166.667
2314.815
1083.333 1157.407
541.667
578.704
56.2500
60.0962
1
52
10
26
2250.000
2403.846
1125.000 1201.923
562.500
600.962
58.5000
62.5000
1
50
10
25
2340.000
2500.000
1170.000 1250.000
600.000
625.000
60.9375
65.1042
1
48
10
24
2437.500
2604.167
1218.750 1302.083
609.375
651.042
63.5870
67.9348
1
46
10
23
2543.478
2717.391
1271.739 1358.696
635.870
679.348
66.4773
71.0227
1
44
10
22
2659.091
2840.909
1329.545 1420.455
664.773
710.227
69.6429
74.4048
1
42
10
21
2785.714
2976.190
1392.857 1488.095
696.429
744.048
73.1250
78.1250
1
40
10
20
2925.000
3125.000
1462.500 1562.500
731.250
781.250
76.9737
82.2368
1
38
10
19
3078.947
3289.474
1539.474 1644.737
769.737
822.368
81.2500
86.8056
1
36
10
18
3250.000
3472.222
1625.000 1736.111
812.500
868.056
86.0294
91.9118
1
34
10
17
3441.176
3676.471
1720.588 1838.235
860.294
919.118
91.4063
97.6563
1
32
10
16
3656.250
3750.000
1828.125 1953.125
914.063
976.563
97.5000
100.0000
1
30
10
15
3900.000
4000.000
1950.000 2000.000
975.000
1000.000
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
9/10 Bit SERDES Mode - Continuous Mode - Jitter Cleaner (2x) Mode
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
www.ti.com
Note that REFCLK is limited to 93.75 Mhz when in full rate mode to achieve 3750 Mbps serial data rate.
Figure A-2. 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (2x) Provisioning
APPENDIX A – Frequency Ranges Supported
Submit Documentation Feedback
TLK3131
Single Channel Multi-Rate Transceiver
www.ti.com
SLLS957 – DECEMBER 2008
9/10 Bit SERDES Mode - Continuous Mode - Jitter Cleaner (1x) Mode
SERDES
REF_DIV[6:0] FB_DIV[6:0]
RATE[1:0] =2'b00 Full
4/5.37124:14:8 4/5.37124:6:0 PLL_MULT[3:0]
RXTX_DIV[6:0]
Min
Max
(Decimal)
(Decimal)
See Note 1 Below 4/5.37125:6:0
Min
Max
50.0000
53.8793
1
58
20
58
2000.000
2155.172
51.3158
54.8246
1
57
20
57
2052.632
2192.982
52.2321
55.8036
1
56
20
56
2089.286
2232.143
53.1818
56.8182
1
55
20
55
2127.273
2272.727
54.1667
57.8704
1
54
20
54
2166.667
2314.815
55.1887
58.9623
1
53
20
53
2207.547
2358.491
56.2500
60.0962
1
52
20
52
2250.000
2403.846
57.3529
61.2745
1
51
20
51
2294.118
2450.980
58.5000
62.5000
1
50
20
50
2340.000
2500.000
59.6939
63.7755
1
49
20
49
2387.755
2551.020
60.9375
65.1042
1
48
20
48
2437.500
2604.167
62.2340
66.4894
1
47
20
47
2489.362
2659.574
63.5870
67.9348
1
46
20
46
2543.478
2717.391
65.0000
69.4444
1
45
20
45
2600.000
2777.778
66.4773
71.0227
1
44
20
44
2659.091
2840.909
68.0233
72.6744
1
43
20
43
2720.930
2906.977
69.6429
74.4048
1
42
20
42
2785.714
2976.190
71.3415
76.2195
1
41
20
41
2853.659
3048.780
73.1250
78.1250
1
40
20
40
2925.000
3125.000
75.0000
80.1282
1
39
20
39
3000.000
3205.128
76.9737
82.2368
1
38
20
38
3078.947
3289.474
79.0541
84.4595
1
37
20
37
3162.162
3378.378
81.2500
86.8056
1
36
20
36
3250.000
3472.222
83.5714
89.2857
1
35
20
35
3342.857
3571.429
86.0294
91.9118
1
34
20
34
3441.176
3676.471
88.6364
94.6970
1
33
20
33
3545.455
3750.000
91.4063
97.6563
1
32
20
32
3656.250
3750.000
94.3548
100.8065
1
31
20
31
3774.194
4032.258
97.5000
104.1667
1
30
20
30
3900.000
4166.667
100.8621
106.2500
1
29
20
29
4034.483
4250.000
104.4643
106.2500
1
28
20
28
4178.571
4250.000
100.0000
104.1667
1
30
10
30
2000.000
2083.333
100.0000
107.7586
1
29
10
29
2000.000
2155.172
104.4643
111.6071
1
28
10
28
2089.286
2232.143
108.3333
115.7407
1
27
10
27
2166.667
2314.815
112.5000
120.1923
1
26
10
26
2250.000
2403.846
117.0000
125.0000
1
25
10
25
2340.000
2500.000
121.8750
130.2083
1
24
10
24
2437.500
2604.167
127.1739
135.8696
1
23
10
23
2543.478
2717.391
132.9545
142.0455
1
22
10
22
2659.091
2840.909
139.2857
148.8095
1
21
10
21
2785.714
2976.190
146.2500
156.2500
1
20
10
20
2925.000
3125.000
153.9474
164.4737
1
19
10
19
3078.947
3289.474
162.5000
173.6111
1
18
10
18
3250.000
3472.222
172.0588
183.8235
1
17
10
17
3441.176
3676.471
182.8125
195.3125
1
16
10
16
3656.250
3750.000
195.0000
200.0000
1
15
10
15
3900.000
4000.000
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
REFCLK (Mhz)
RATE [1:0] (See Note 2 Below)
RATE[1:0] =2'b01 Half RATE[1:0] =2'b10 Qrtr.
Min
1000.000
1026.316
1044.643
1063.636
1083.333
1103.774
1125.000
1147.059
1170.000
1193.878
1218.750
1244.681
1271.739
1300.000
1329.545
1360.465
1392.857
1426.829
1462.500
1500.000
1539.474
1581.081
1625.000
1671.429
1720.588
1772.727
1828.125
1887.097
1950.000
2017.241
2089.286
1000.000
1000.000
1044.643
1083.333
1125.000
1170.000
1218.750
1271.739
1329.545
1392.857
1462.500
1539.474
1625.000
1720.588
1828.125
1950.000
Max
1077.586
1096.491
1116.071
1136.364
1157.407
1179.245
1201.923
1225.490
1250.000
1275.510
1302.083
1329.787
1358.696
1388.889
1420.455
1453.488
1488.095
1524.390
1562.500
1602.564
1644.737
1689.189
1736.111
1785.714
1838.235
1893.939
1953.125
2016.129
2083.333
2125.000
2125.000
1041.667
1077.586
1116.071
1157.407
1201.923
1250.000
1302.083
1358.696
1420.455
1488.095
1562.500
1644.737
1736.111
1838.235
1953.125
2000.000
Min
500.000
513.158
522.321
531.818
541.667
551.887
562.500
600.000
600.000
600.000
609.375
622.340
635.870
650.000
664.773
680.233
696.429
713.415
731.250
750.000
769.737
790.541
812.500
835.714
860.294
886.364
914.063
943.548
975.000
1008.621
1044.643
500.000
500.000
522.321
541.667
562.500
600.000
600.000
635.870
664.773
696.429
731.250
769.737
812.500
860.294
914.063
975.000
Max
538.793
548.246
558.036
568.182
578.704
589.623
600.962
612.745
625.000
637.755
651.042
664.894
679.348
694.444
710.227
726.744
744.048
762.195
781.250
801.282
822.368
844.595
868.056
892.857
919.118
946.970
976.563
1008.065
1041.667
1062.500
1062.500
520.833
538.793
558.036
578.704
600.962
625.000
651.042
679.348
710.227
744.048
781.250
822.368
868.056
919.118
976.563
1000.000
Note that REFCLK is limited to 187.5 Mhz when in full rate mode to achieve 3750 Mbps serial data rate.
Figure A-3. 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (1x) Provisioning
Submit Documentation Feedback
APPENDIX A – Frequency Ranges Supported
89
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
www.ti.com
9/10 Bit SERDES Mode - Continuous Mode - Jitter Cleaner (0.5X) Mode
SERDES RATE[1:0] (See Note 2 Below)
REF_DIV[6:0]
FB_DIV[6:0]
RATE[1:0] =2'b00 Full
RATE[1:0] =2'b01 Half RATE[1:0] =2'b10 Qrtr.
4/5.37124:14:8 4/5.37124:6:0
PLL_MULT[3:0]
RXTX_DIV[6:0]
Min
Max
(Decimal)
(Decimal)
See Note 1 Below
4/5.37125:6:0
Min
Max
Min
Max
Min
Max
100.0000
105.9322
4
118
20
59
2000.000
2118.644
1000.000
1059.322
500.000
529.661
100.8621
107.7586
4
116
20
58
2017.241
2155.172
1008.621
1077.586
504.310
538.793
102.6316
109.6491
4
114
20
57
2052.632
2192.982
1026.316
1096.491
513.158
548.246
104.4643
111.6071
4
112
20
56
2089.286
2232.143
1044.643
1116.071
522.321
558.036
106.3636
113.6364
4
110
20
55
2127.273
2272.727
1063.636
1136.364
531.818
568.182
108.3333
115.7407
4
108
20
54
2166.667
2314.815
1083.333
1157.407
541.667
578.704
110.3774
117.9245
4
106
20
53
2207.547
2358.491
1103.774
1179.245
551.887
589.623
112.5000
120.1923
4
104
20
52
2250.000
2403.846
1125.000
1201.923
562.500
600.962
114.7059
122.5490
4
102
20
51
2294.118
2450.980
1147.059
1225.490
600.000
612.745
117.0000
125.0000
4
100
20
50
2340.000
2500.000
1170.000
1250.000
600.000
625.000
119.3878
127.5510
4
98
20
49
2387.755
2551.020
1193.878
1275.510
600.000
637.755
121.8750
130.2083
4
96
20
48
2437.500
2604.167
1218.750
1302.083
609.375
651.042
124.4681
132.9787
4
94
20
47
2489.362
2659.574
1244.681
1329.787
622.340
664.894
127.1739
135.8696
4
92
20
46
2543.478
2717.391
1271.739
1358.696
635.870
679.348
130.0000
138.8889
4
90
20
45
2600.000
2777.778
1300.000
1388.889
650.000
694.444
132.9545
142.0455
4
88
20
44
2659.091
2840.909
1329.545
1420.455
664.773
710.227
136.0465
145.3488
4
86
20
43
2720.930
2906.977
1360.465
1453.488
680.233
726.744
139.2857
148.8095
4
84
20
42
2785.714
2976.190
1392.857
1488.095
696.429
744.048
142.6829
152.4390
4
82
20
41
2853.659
3048.780
1426.829
1524.390
713.415
762.195
146.2500
156.2500
4
80
20
40
2925.000
3125.000
1462.500
1562.500
731.250
781.250
150.0000
160.2564
4
78
20
39
3000.000
3205.128
1500.000
1602.564
750.000
801.282
153.9474
164.4737
4
76
20
38
3078.947
3289.474
1539.474
1644.737
769.737
822.368
158.1081
168.9189
4
74
20
37
3162.162
3378.378
1581.081
1689.189
790.541
844.595
162.5000
173.6111
4
72
20
36
3250.000
3472.222
1625.000
1736.111
812.500
868.056
167.1429
178.5714
4
70
20
35
3342.857
3571.429
1671.429
1785.714
835.714
892.857
172.0588
183.8235
4
68
20
34
3441.176
3676.471
1720.588
1838.235
860.294
919.118
177.2727
189.3939
4
66
20
33
3545.455
3750.000
1772.727
1893.939
886.364
946.970
182.8125
195.3125
4
64
20
32
3656.250
3750.000
1828.125
1953.125
914.063
976.563
188.7097
201.6129
4
62
20
31
3774.194
4032.258
1887.097
2016.129
943.548
1008.065
195.0000
208.3333
4
60
20
30
3900.000
4166.667
1950.000
2083.333
975.000
1041.667
201.7241
212.5000
4
58
20
29
4034.483
4250.000
2017.241
2125.000
1008.621 1062.500
208.9286
212.5000
4
56
20
28
4178.571
4250.000
2089.286
2125.000
1044.643 1062.500
200.0000
208.3333
4
60
10
30
2000.000
2083.333
1000.000
1041.667
500.000
520.833
201.7241
215.5172
4
58
10
29
2017.241
2155.172
1008.621
1077.586
504.310
538.793
208.9286
223.2143
4
56
10
28
2089.286
2232.143
1044.643
1116.071
522.321
558.036
216.6667
231.4815
4
54
10
27
2166.667
2314.815
1083.333
1157.407
541.667
578.704
225.0000
240.3846
4
52
10
26
2250.000
2403.846
1125.000
1201.923
562.500
600.962
234.0000
250.0000
4
50
10
25
2340.000
2500.000
1170.000
1250.000
600.000
625.000
243.7500
260.4167
4
48
10
24
2437.500
2604.167
1218.750
1302.083
609.375
651.042
254.3478
271.7391
4
46
10
23
2543.478
2717.391
1271.739
1358.696
635.870
679.348
265.9091
284.0909
4
44
10
22
2659.091
2840.909
1329.545
1420.455
664.773
710.227
278.5714
297.6190
4
42
10
21
2785.714
2976.190
1392.857
1488.095
696.429
744.048
292.5000
312.5000
4
40
10
20
2925.000
3125.000
1462.500
1562.500
731.250
781.250
307.8947
328.9474
4
38
10
19
3078.947
3289.474
1539.474
1644.737
769.737
822.368
325.0000
347.2222
4
36
10
18
3250.000
3472.222
1625.000
1736.111
812.500
868.056
344.1176
367.6471
4
34
10
17
3441.176
3676.471
1720.588
1838.235
860.294
919.118
365.6250
375.0000
4
32
10
16
3656.250
3750.000
1828.125
1875.000
914.063
937.500
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
REFCLK (Mhz)
Figure A-4. 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (0.5x) Provisioning
90
APPENDIX A – Frequency Ranges Supported
Submit Documentation Feedback
TLK3131
Single Channel Multi-Rate Transceiver
www.ti.com
SLLS957 – DECEMBER 2008
9/10 Bit SERDES Mode - Continuous Mode - Jitter Cleaner (0.25X) Mode
SERDES RATE[1:0] (See Note 2 Below)
REFCLK (Mhz)
REF_DIV[6:0]
FB_DIV[6:0]
4/5.37124:14:8
4/5.37124:6:0
PLL_MULT[3:0]
RXTX_DIV[6:0]
(Decimal)
(Decimal)
See Note 1 Below
4/5.37125:6:0
Min
Max
200.0000
211.8644
4
59
20
201.7241
215.5172
4
58
205.2632
219.2982
4
57
208.9286
223.2143
4
212.7273
227.2727
216.6667
231.4815
220.7547
235.8491
RATE[1:0] =2'b00 Full
RATE[1:0] =2'b01 Half
RATE[1:0] =2'b10 Qrtr.
Min
Max
Min
Max
Min
Max
59
2000.000
2118.644
1000.000
1059.322
500.000
529.661
20
58
2017.241
2155.172
1008.621
1077.586
504.310
538.793
20
57
2052.632
2192.982
1026.316
1096.491
513.158
548.246
56
20
56
2089.286
2232.143
1044.643
1116.071
522.321
558.036
4
55
20
55
2127.273
2272.727
1063.636
1136.364
531.818
568.182
4
54
20
54
2166.667
2314.815
1083.333
1157.407
541.667
578.704
4
53
20
53
2207.547
2358.491
1103.774
1179.245
551.887
589.623
225.0000
240.3846
4
52
20
52
2250.000
2403.846
1125.000
1201.923
562.500
600.962
229.4118
245.0980
4
51
20
51
2294.118
2450.980
1147.059
1225.490
573.529
612.745
234.0000
250.0000
4
50
20
50
2340.000
2500.000
1170.000
1250.000
585.000
625.000
238.7755
255.1020
4
49
20
49
2387.755
2551.020
1193.878
1275.510
600.000
637.755
243.7500
260.4167
4
48
20
48
2437.500
2604.167
1218.750
1302.083
609.375
651.042
248.9362
265.9574
4
47
20
47
2489.362
2659.574
1244.681
1329.787
622.340
664.894
254.3478
271.7391
4
46
20
46
2543.478
2717.391
1271.739
1358.696
635.870
679.348
260.0000
277.7778
4
45
20
45
2600.000
2777.778
1300.000
1388.889
650.000
694.444
265.9091
284.0909
4
44
20
44
2659.091
2840.909
1329.545
1420.455
664.773
710.227
272.0930
290.6977
4
43
20
43
2720.930
2906.977
1360.465
1453.488
680.233
726.744
278.5714
297.6190
4
42
20
42
2785.714
2976.190
1392.857
1488.095
696.429
744.048
285.3659
304.8780
4
41
20
41
2853.659
3048.780
1426.829
1524.390
713.415
762.195
292.5000
312.5000
4
40
20
40
2925.000
3125.000
1462.500
1562.500
731.250
781.250
300.0000
320.5128
4
39
20
39
3000.000
3205.128
1500.000
1602.564
750.000
801.282
307.8947
328.9474
4
38
20
38
3078.947
3289.474
1539.474
1644.737
769.737
822.368
316.2162
337.8378
4
37
20
37
3162.162
3378.378
1581.081
1689.189
790.541
844.595
325.0000
347.2222
4
36
20
36
3250.000
3472.222
1625.000
1736.111
812.500
868.056
334.2857
357.1429
4
35
20
35
3342.857
3571.429
1671.429
1785.714
835.714
892.857
344.1176
367.6471
4
34
20
34
3441.176
3676.471
1720.588
1838.235
860.294
919.118
354.5455
375.0000
4
33
20
33
3545.455
3750.000
1772.727
1875.000
886.364
937.500
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
Figure A-5. 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (0.25x) Provisioning
Submit Documentation Feedback
APPENDIX A – Frequency Ranges Supported
91
A.
92
APPENDIX A – Frequency Ranges Supported
67.9348
71.0227
74.4048
78.1250
82.2368
86.8056
91.9118
97.6563
100.0000
63.5870
66.4773
69.6429
73.1250
76.9737
81.2500
86.0294
91.4063
97.5000
1
1
1
1
1
1
1
1
1
1
30
32
34
36
38
40
42
44
46
48
(Decimal)
4/5.37124:6:0
4/5.37124:14:8
(Decimal)
FB_DIV[6:0]
REF_DIV[6:0]
8
8
8
8
8
8
8
8
8
8
See Note 1 Below
PLL_MULT[3:0]
15
16
17
18
19
20
21
22
23
24
4/5.37125:6:0
RXTX_DIV[6:0]
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
Min
3120.000
2925.000
2752.941
2600.000
2463.158
2340.000
2228.571
2127.273
2034.783
Max
3200.000
3000.000
2941.176
2777.778
2631.579
2500.000
2380.952
2272.727
2173.913
2083.333
1560.000
1462.500
1376.471
1300.000
1231.579
1170.000
1114.286
1063.636
1017.391
1000.000
Min
1600.000
1562.500
1470.588
1388.889
1315.789
1250.000
1190.476
1136.364
1086.957
1041.667
Max
2'b01 (Half)
Min
780.000
731.250
688.235
650.000
615.789
600.000
557.143
531.818
508.696
800.000
781.250
735.294
694.444
657.895
625.000
595.238
568.182
543.478
520.833
Max
2'b10 (Quarter)
500.000
SERDES RATE [1:0] (See Note 2 Below)
2'b00 (Full)
2000.000
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
Max
65.1042
Min
62.5000
REFCLK (Mhz)
8 Bit SERDES Mode - Continuous Mode - Jitter Cleaner (2x) Mode
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
www.ti.com
Note that REFCLK is limited to 93.75 Mhz when in Full rate mode to achieve 3000 Mbps serial data rate.
Figure A-6. 8 BIT SERDES Mode – Jitter Cleaner/SERDES (2x) Provisioning(A)
Submit Documentation Feedback
A.
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200.0000
195.0000
1
1
1
1
1
1
1
1
1
1
15
16
17
18
19
20
21
22
23
24
(Decimal)
4/5.37124:6:0
4/5.37124:14:8
(Decimal)
FB_DIV[6:0]
REF_DIV[6:0]
8
8
8
8
8
8
8
8
8
8
See Note 1 Below
PLL_MULT[3:0]
15
16
17
18
19
20
21
22
23
24
4/5.37125:6:0
RXTX_DIV[6:0]
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
Min
2034.783
3120.000
2925.000
2752.941
2600.000
2463.158
2340.000
2228.571
2127.273
Max
3200.000
3000.000
2941.176
2777.778
2631.579
2500.000
2380.952
2272.727
2173.913
2083.333
1560.000
1462.500
1376.471
1300.000
1231.579
1170.000
1114.286
1063.636
1017.391
1000.000
Min
1600.000
1562.500
1470.588
1388.889
1315.789
1250.000
1190.476
1136.364
1086.957
1041.667
Max
2'b01 (Half)
Min
508.696
780.000
731.250
688.235
650.000
615.789
600.000
557.143
531.818
800.000
781.250
735.294
694.444
657.895
625.000
595.238
568.182
543.478
520.833
Max
2'b10 (Quarter)
500.000
SERDES RATE [1:0] (See Note 2 Below)
2'b00 (Full)
2000.000
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
183.8235
195.3125
172.0588
182.8125
164.4737
173.6111
153.9474
162.5000
148.8095
156.2500
139.2857
146.2500
135.8696
142.0455
127.1739
132.9545
Max
130.2083
Min
125.0000
REFCLK (Mhz)
8 Bit SERDES Mode - Continuous Mode - Jitter Cleaner (1x) Mode
TLK3131
Single Channel Multi-Rate Transceiver
www.ti.com
SLLS957 – DECEMBER 2008
Note that REFCLK is limited to 187.5 Mhz when in Full rate mode to achieve 3000 Mbps serial data rate.
Figure A-7. 8 BIT SERDES Mode – Jitter Cleaner/SERDES (1x) Provisioning(A)
APPENDIX A – Frequency Ranges Supported
93
94
APPENDIX A – Frequency Ranges Supported
4
4
4
4
4
4
4
4
4
(Decimal)
REF_DIV[6:0]
4/5.37124:14:8
48
46
44
42
40
38
36
34
32
(Decimal)
FB_DIV[6:0]
4/5.37124:6:0
8
8
8
8
8
8
8
8
8
See Note 1 Below
PLL_MULT[3:0]
24
23
22
21
20
19
18
17
16
4/5.37125:6:0
RXTX_DIV[6:0]
Min
2000.000
2034.783
2127.273
2228.571
2340.000
2463.158
2600.000
2752.941
2925.000
Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865.
Max
2083.333
2173.913
2272.727
2380.952
2500.000
2631.579
2777.778
2941.176
3000.000
1000.000
1017.391
1063.636
1114.286
1170.000
1231.579
1300.000
1376.471
1462.500
Min
1041.667
1086.957
1136.364
1190.476
1250.000
1315.789
1388.889
1470.588
1500.000
Max
2'b01 (Half)
Min
520.833
543.478
568.182
595.238
625.000
657.895
694.444
735.294
750.000
Max
2'b10 (Quarter)
500.000
508.696
531.818
557.143
600.000
615.789
650.000
688.235
731.250
SERDES RATE [1:0] (See Note 2 Below)
2'b00 (Full)
Note 1: PLL_MULT[3:0] bits are found in bits 11:8 and 3:0 in register SERDES_PLL_CONFIG at address 4/5.36864.
Max
260.4167
271.7391
284.0909
297.6190
312.5000
328.9474
347.2222
367.6471
375.0000
Min
250.0000
254.3478
265.9091
278.5714
292.5000
307.8947
325.0000
344.1176
365.6250
REFCLK (Mhz)
8 Bit SERDES Mode - Continuous Mode - Jitter Cleaner (0.5x) Mode
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
www.ti.com
Figure A-8. 8 BIT SERDES Mode – Jitter Cleaner/SERDES (0.5x) Provisioning
Submit Documentation Feedback
TLK3131
Single Channel Multi-Rate Transceiver
www.ti.com
A.1
SLLS957 – DECEMBER 2008
Recovered Byte Clock Jitter Cleaner Mode:
If it is desired to dedicate the Jitter Cleaner PLL to clean the RX SERDES recovered byte clock, then the
following procedure must be followed:
1. Program REF_SEL[1:0] to 2’b10.
2. Program RXB_SEL[1:0] to 2’b00.
3. Program RX_SEL to 2’b10 -or- 2’b11.
4. Program TX_SEL as desired.
5. Program 16.10:9 as desired on a per channel basis.
6. Consult the rows in the appropriate Appendix A table to find the appropriate REFCLK and SERDES
mode settings. Note that only rows indicating that the Jitter Cleaner PLL is OFF may be used.
Provision the SERDES settings appropriately.
7. Divide the selected SERDES serial rate by 8 if in EBI/REBI modes, or 10 otherwise, and use that
frequency as the input to Figure A-9 Recovered Byte Clock Jitter Cleaner Mode, to determine the
appropriate Jitter Cleaner PLL settings. Note that only a 1:1 frequency ratio is supported between the
SERDES output byte clock and the parallel interface output recovered byte clock. Depending upon the
selection of TX_SEL, it may also be necessary to provision RXTX_DIV with the same value as
RXB_DIV.
Submit Documentation Feedback
APPENDIX A – Frequency Ranges Supported
95
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
www.ti.com
Recovered Byte Clock Cleaning Mode - Jitter Cleaner (1x) Mode
Recovered Byte Clock (Mhz)
Min
50.0000
51.3158
52.2321
53.1818
54.1667
55.1887
56.2500
57.3529
58.5000
59.6939
60.9375
62.2340
63.5870
65.0000
66.4773
68.0233
69.6429
71.3415
73.1250
75.0000
76.9737
79.0541
81.2500
83.5714
86.0294
88.6364
91.4063
94.3548
97.5000
100.8621
104.4643
108.3333
112.5000
117.0000
121.8750
127.1739
132.9545
139.2857
146.2500
153.9474
162.5000
172.0588
182.8125
195.0000
208.9286
225.0000
243.7500
265.9091
292.5000
325.0000
365.6250
Max
53.8793
54.8246
55.8036
56.8182
57.8704
58.9623
60.0962
61.2745
62.5000
63.7755
65.1042
66.4894
67.9348
69.4444
71.0227
72.6744
74.4048
76.2195
78.1250
80.1282
82.2368
84.4595
86.8056
89.2857
91.9118
94.6970
97.6563
100.8065
104.1667
107.7586
111.6071
115.7407
120.1923
125.0000
130.2083
135.8696
142.0455
148.8095
156.2500
164.4737
173.6111
183.8235
195.3125
208.3333
223.2143
240.3846
260.4167
284.0909
312.5000
347.2222
375.0000
REF_DIV[6:0] FB_DIV[6:0]
4/5.37124:14:8 4/5.37124:6:0 RXB_DIV[6:0]
(Decimal)
(Decimal)
4/5.37125:14:8
1
58
58
1
57
57
1
56
56
1
55
55
1
54
54
1
53
53
1
52
52
1
51
51
1
50
50
1
49
49
1
48
48
1
47
47
1
46
46
1
45
45
1
44
44
1
43
43
1
42
42
1
41
41
1
40
40
1
39
39
1
38
38
1
37
37
1
36
36
1
35
35
1
34
34
1
33
33
1
32
32
1
31
31
1
30
30
1
29
29
1
28
28
1
27
27
1
26
26
1
25
25
1
24
24
1
23
23
1
22
22
1
21
21
1
20
20
1
19
19
1
18
18
1
17
17
1
16
16
1
15
15
1
14
14
1
13
13
1
12
12
1
11
11
1
10
10
1
9
9
1
8
8
Figure A-9. Recovered Byte Clock Jitter Cleaner Mode
96
APPENDIX A – Frequency Ranges Supported
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TLK3131
Single Channel Multi-Rate Transceiver
www.ti.com
B
SLLS957 – DECEMBER 2008
APPENDIX B – Jitter Cleaner PLL External Loop Filter
The following external loop filter is required anytime the Jitter Cleaner PLL is enabled.
TLK Device
CP_OUT
VTUNE
R3=1.21k
R3=1.21kW
C2=1.5nF
R1=100W
R1=100
C1=3.3uF
VSSA_VCO
C3=1.800nF
VSSA_VCO
VSSA_VCO
External passive loop filter
Figure B-1. Jitter Cleaner External Loop Filter
Submit Documentation Feedback
APPENDIX B – Jitter Cleaner PLL External Loop Filter
97
TLK3131
Single Channel Multi-Rate Transceiver
SLLS957 – DECEMBER 2008
C
www.ti.com
APPENDIX C – Device Test Mode
This device can be placed into one of the three modes: functional mode including JTAG testing mode,
scan testing mode, and Jadis/eFuse testing mode. The scan testing mode and Jadis/eFuse testing modes
are for TI use only, and may be ignored by external users of this device.
Table C-1. Device Mode Configuration
FUNCTIONAL DEVICE PIN
NAME
FUNCTIONAL MODE/JTAG TESTING
SCAN MODE
Jadis/eFuse MODE
TESTEN
0 or 1
0
1
GPI1
0
1
1
Table C-2. Device Test Mode Pin Configuration
FUNCTIONAL
DEVICE PIN NAME
FUNCTIONAL MODE
SIGNAL DIRECTION
TEST MODE
SIGNAL
DIRECTION
FUNCTIONAL
MODE/JTAG
TESTING
SCAN MODE
SPEED1
I
I
SPEED1
Scan In 5
STCI_D
SPEED0
I
I
SPEED0
Scan In 4
EFUSE_TMS
PLOOP
I
I
PLOOP
Scan In 3
EFUSE_TDI
98
Jadis/eFuse
MODE
SLOOP
I
I
SLOOP
Scan In 2
STCICFG1
PRBS_EN
I
I
PRBS_EN
Scan In 1
EFUSE_INITZ
CODE
I
I
CODE
Scan Enable
TDI
I
I
TDI
Adaptive Scan Enable (Test
Mode)
JADIS_EFUSE_SE
L
PRTAD4
I
I
PRTAD4
Scan HS Enable (Transition
Fault)
TESTCLK_R
PRTAD3
I
I
PRTAD3
Scan Clock
STCICLK
PRTAD2
I
I: Jadis/eFuse
O: Scan
PRTAD2
Scan Out 5
STCICFG0
PRTAD1
I
I
PRTAD1
PRTAD0
I
I
PRTAD0
HSTL Force Down
GPO0
O
O
TEST_DOUT0
Scan Out 4
Tied LOW
GPO1
O
O
TEST_DOUT1
Scan Out 3
Tied LOW
GPO2
O
O
TEST_DOUT2
Scan Out 2
STCI_Q
GPO3
O
O
TEST_DOUT3
Scan Out 1
EFUSE_TDO
GPO4
O
O
TEST_DOUT4 or
JC PLL Digital Test
Out
Burnin_Output
Burnin_Output
APPENDIX C – Device Test Mode
TESTCLK_T
Scan Clock Select (0: from
device pin, 1: from Jadis), also EFUSE_SYS_CLK
EFUSE_SYS_CLK
EFUSE_TCK
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TLK3131ZWQ
ACTIVE
BGA
ZWQ
Pins Package Eco Plan (2)
Qty
144
160
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
SNAGCU
MSL Peak Temp (3)
Level-4-260C-72 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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