CXA3038N IQ Detection IC for Digital Satellite Broadcast Tuner Description The CXA3038N is an IC for IQ-detection of DSS, DVB, and other digital satellite broadcast QPSK modulation signals in the 480 MHz band. It consists of an AGC amplifier circuit, oscillator circuit, phase shifter circuit, and phase comparison circuit. In addition, the chip has a PLL circuit for frequency control and built-in control data. It realizes highaccuracy oscillator frequencies through use of a lowcost LC resonance circuit. Features • Built-in PLL for controlling oscillator frequency. • Oscillator frequency based at 479.5 MHz is adjustable in ±4 steps of 50 kHz using the voltage of the control pin. • Reference OSC allows switching to 4 MHz or 10 MHz. • Built-in output buffer for reference OSC. • Low-impedance IQ output. • AGC gain variation 35 dB. 24 pin SSOP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC –0.3 to 5.5 • Storage temperature Tstg –55 to +150 Operating Conditions • Supply voltage VCC • Operating temperature Topr 4.75 to 5.30 –25 to +75 V °C V °C Applications Digital satellite broadcast tuner Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E97650A84-TE CXA3038N XTAL LOCK REFOUT DVCC DGND LPF VC OSCGND OSC1 OSC2 PSVCC LOOUT Block Diagram and Pin Configuration 24 23 22 21 20 19 18 17 16 15 14 13 Ref OSC Buffer Charge Pump Divider 1/80, 1/200 Phase DET Prescaler 1/32 OSC Divider 10bit+4bit Phase Shifter Comparator DC AMP LPF QMIX Buffer DC AMP LPF IMIX Buffer QOUT XCONT IOUT IQGND GND 7 8 9 10 11 12 NSET 6 RFVCC 5 RFIN1 4 RFIN2 3 AGC 2 RFGND 1 IQVCC AGC AMP —2— CXA3038N Pin Description Pin No. Symbol Typical pin voltage 1 IQVCC 5V Equivalent circuit Description IQ output circuit VCC. 1 20 2 QOUT 2 2.7 V Q output. 5 21 3 XCONT Open or 5 V when using 4 MHz crystal ; 0 V when using 10 MHz crystal. Switching pin for reference divider frequency-division ratio. This is set to 80 frequency divisions when open or connected to VCC; 200 frequency divisions when connected to GND. 10k 90k 3 20 1 20 4 IOUT 4 2.7 V I output. 5 5 IQGND 0V IQ output circuit GND. 6 GND 0V GND. 7 RFGND 0V RF circuit (AGCAmp, MIXER) GND. 11 8 AGC 0 to 4 V 20k AGCAmp gain adjustment. 8 20k 7 —3— CXA3038N Pin No. Symbol Typical pin voltage 9 RFIN2 2.1 V Equivalent circuit Description 9 10 5k 10 RFIN1 2.1 V RF signal inputs. 5k 2.2V 7 11 RFVCC RF circuit (AGCAmp, MIXER, OSC) VCC. 5V 21 12 NSET 1.6 V OSC frequency fine-adjustment. The oscillator frequency based at 479.5 MHz is adjustable in ±4 steps of 50 kHz by applying a voltage of 0 to 5 V. 12 20 14 13 LOOUT 4V Output for OSC frequency signal divided into 32 frequency divisions. 13 8k 20 14 PSVCC VCC for 32 frequency division circuit. This is set to open when activating the built-in PLL. 5V 11 15 OSC2 700 3.7 V 700 16 3p 15 3p 16 OSC1 OSC pins. These pins connect the varicap diode and coil resonance circuit. 3.7 V 17 17 OSCGND OSC circuit and phase shifter circuit GND. 0V —4— CXA3038N Pin No. Symbol Typical pin voltage Equivalent circuit Description 21 10k 100 18 VC 0.3 V to 5 V Voltage output for varicap diode making up the VCO. 18 20 21 100 19 LPF 1.8 V to 3.7 V Phase comparison output. This pin connects the loop filter. 19 20 20 21 DGND DVCC 0V 5V PLL circuit GND. PLL circuit VCC. 21 22 REFOUT 4.1 V REFOSC output. 22 20 21 23 LOCK 0.01 V when unlocked; 3.2 V when locked PLL lock/unlock monitor. 23 200k 20 21 60k 20p 24 XTAL 4.4 V 20p Crystal connection. 24 20 —5— CXA3038N Electrical Characteristics Circuit current Item (Ta=25 °C, VCC=5 V, see the Electrical Characteristics Measurement Circuit.) Symbol Circuit current A ICCA Circuit current D ICCD Circuit current L ICCPS AC Characteristics Measurement conditions Analog circuit current at no signal. Total current of IQVCC and RFVCC. PLL circuit current. DVCC current. 32-frequency division circuit current at no signal. PSVCC current. Symbol Measurement conditions Iout=10 MHz, 1 Vp-p VIN GAGC Iout=10 MHz, 1 Vp-p, AGC=4 V-0 V RF=–50 dBm, Iout=10 MHz, AGC=4 V Conversion gain CG (Full gain) RF=–50 dBm, Iout=10 MHz, 1 Vp-p IQ phase error BP RF=–50 dBm, Iout=10 MHz, 1 Vp-p IQ amplitude error BV Phase frequency error ∆fBP RF=–50 dBm, Iout=0 MHz–15 MHz, 1 Vp-p Amplitude frequency error ∆fBV RF=–50 dBm, Iout=0 MHz–15 MHz, 1 Vp-p RF=–50 dBm, Iout=From 1 Vp-p to 3 dB down Cut-off frequency fC RF=–30 dBm, Qout=10 MHz, AGC=4 V VQMAX Maximum Q output (Full gain) RF=–30 dBm, Iout=10 MHz, AGC=4 V VIMAX Maximum I output (Full gain) NF Iout=10 MHz, AGC=4 V (Full gain), DSB Noise figure RF1=489.5 MHz, RF2=490.5 MHz, Third-order IM3 Iout=1 Vp-p intermodulation distortion RF=–50 dBm, Iout=10 MHz, 1Vp-p, Local oscillation CN 10 kHz offset phase noise RF=–50 dBm, Iout=10 MHz, 1Vp-p, refLK PLL reference leak 50 kHz S/I RF input admittance Typ. Max. Unit 41 60 80 mA 2 3.5 5.5 mA 1.1 1.6 2.4 mA (Ta=25 °C, VCC=5 V, see the Electrical Characteristics Measurement Circuit.) Item Input sensitivity Gain control range RF pin local oscillation leak QOUT pin local oscillation leak IOUT pin local oscillation leak REFout pin local oscillation leak Min. Min. Max. 32.5 Typ. –50 35 — Unit dBm dB 52 54 57 dB ±4 ±0.5 ±0.5 ±0.1 deg dB deg dB MHz 25 2.5 3 3.5 Vp-p 2.5 3 3.5 Vp-p 9 dB 32 dB –88 dBc/Hz –81 dB dBm RFLK AGC=4 V, f=479.5 MHz –21 QLK1 QLK2 ILK1 ILK2 AGC=4 V, f=479.5 MHz AGC=0 V, f=479.5 MHz AGC=4 V, f=479.5 MHz AGC=0 V, f=479.5 MHz –34 –40 –34 –40 REFLK f=479.5 MHz rπ Cπ f=479.5 MHz, AGC=4 V (Full gain) Measured value for untuned inputs. Noise figure is the direct reading value from the NF meter. —6— dBm dBm –34 dBm 1.25 k 1.4 Ω pF CXA3038N PLL Block (Ta=25 °C, VCC=5 V, see the Electrical Characteristics Measurement Circuit.) Item Symbol Measurement conditions LPF (charge pump) H output current ILPFH L output current ILPFL VC Output voltage range VVCH XCONT=OPEN, PLL lock LOCK H output voltage VLH XTAL=4 MHz, XCONT=OPEN, PLL lock XTAL=4 MHz, XCONT=GND, PLL unlock L output voltage VLL REFOUT Output frequency fREF XTAL=4 MHz Output amplitude VREF XTAL=4 MHz LOOUT (32 frequency divisions) OSC=479.5 MHz during PLL lock Output frequency fLO Output amplitude VLO OSC=479.5 MHz during PLL lock OSC control 479.7 MHz control voltage f+4 NSET=0 V, f0 V–f0=f∆4 479.65 MHz control voltage f+3 NSET=0.4 V, f0.4 V–f0=f∆3 479.6 MHz control voltage f+2 NSET=0.8 V, f0.8 V–f0=f∆2 479.55 MHz control voltage f+1 NSET=1.2 V, f1.2 V–f0=f∆1 479.5 MHz control voltage f0 NSET=1.6 V 479.45 MHz control voltage f–1 NSET=2.0 V, f2.0 V–f0=f∆–1 479.4 MHz control voltage f–2 NSET=2.4 V, f2.4 V–f0=f∆–2 479.35 MHz control voltage f–3 NSET=2.6 V, f2.6 V–f0=f∆–3 479.3 MHz control voltage f–4 NSET=3.2 V, f3.2 V–f0=f∆–4 —7— Min. Typ. Max. –50 50 0.3 2.8 0 3.2 0.01 230 4.000 280 300 14.9844 380 0.597 VCC 0.517 VCC 0.438 VCC 0.358 VCC 0.279 VCC 0.199 VCC 0.120 VCC 0.042 VCC 0 Unit µA µA VCC V 4.2 0.2 V V 400 MHz mVp-p 500 MHz mVp-p VCC 0.590 VCC 0.515 VCC 0.436 VCC 0.356 VCC 0.277 VCC 0.197 VCC 0.118 VCC 0.04 VCC V V V V V V V V V 1n 1n QOUT 2 1 3 IOUT 4 5 GND 7 XTAL XCONT 4MHz 5V/OPEN 10MHz GND 6 RFGND CXA3038N 8 9 1n 11 10 13 14 15 16 17 18 1n 19 1n 1T362 20 1n 80nH L 21 51k LOOUT 22 10n 4MHz XTAL IQVCC LOCK 2p REFOUT QOUT DVCC XCONT DGND IOUT LPF IQGND VC 23 13k OSCGND AGC OSC1 RFIN2 24 10n 680n 150n 1n OSC2 RFIN1 PSVCC 100k 12 NSET LOOUT RFVCC —8— VCC (+5V) AGC XTAL 10µ 5p 1n 1n REFOUT 51k L: Inductance constant Wire Winding Number diameter diameter of turns 0.5 3.0 2.5 LOCK 1n 10n Electrical Characteristics Measurement Circuit 1n RF IN DVCC (+5V) PSVCC (+5V) VC CXA3038N VCC (+5V) 10µ 1n 80nH L 1T362 3 IOUT 4 5 6 7 AGC 9 8 10 68k 12 11 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. QOUT 2 1 GND CXA3038N 13 14 15 16 17 18 19 20 1n L ; 0.5/3.0/2.5T 51k 21 RFGND XTAL 1n 22 10n 4MHz XTAL IQVCC LOCK 2p REFOUT QOUT DVCC XCONT DGND IOUT LPF IQGND VC 23 13k OSCGND AGC OSC1 RFIN2 OSC2 RFIN1 PSVCC 24 10n 680n 150n 1n 5p 1n 1n Reference Clock for Tuner stage PLL. 1n 1n REFOUT 51k 1n LOOUT RFVCC —9— NSET Application Circuit RF IN 479.5MHz from Tuner stage 33k CXA3038N CXA3038N Description of Operation (See the Electrical Characteristics Measurement Circuit.) Oscillator circuit • This is a differential amplification-type oscillator circuit, and it is oscillated by connecting an LC parallel resonance circuit via a coupling capacitance between Pin 15 and Pin 16. A varicap diode is used as a capacitor for the LC parallel resonance circuit to configure the VCO. Set the L value so that the OSC oscillation frequency is approximately 480 MHz when a voltage of 2.5 V is applied to the varicap diode. • The oscillator signal is injected into the phase shifter circuit. Phase shifter circuit • This is a phase shifter having CR configuration. This circuit produces two local signals having a 90° phase difference at 479.5 MHz and injects these signals to the IQ mixer circuit. AGC amplifier circuit • An IF signal (480 MHz band) from the tuner stage is input to Pins 9 and 10. This IF signal which is input to Pins 9 and 10 is amplified by the AGC amplifier and injected into the IQ mixer circuit. • The gain can be adjusted by applying the AGC voltage to Pin 8. The applied AGC voltage ranges from 0 to 4 V, with the minimum gain at 0 V and the maximum gain at 4 V. IQ mixer circuit • This is a double-balance mixer-type circuit consisting of two mixer circuits. • The IF signal amplified by the AGC amplifier is converted into a base band signal by the local signal. Low-pass filter circuit • This is a low-pass filter with a CR configuration. • The cut-off frequency is set at 25 MHz (–3 dB point). Output amplifier circuit • The signal is converted to a base band signal by the I and Q mixer circuits, and the high-frequency component is removed by the low-pass filter. This signal is then amplified by the output amplifier circuit and output to Pin 2 as a Q signal. In the same way, the I signal is output to Pin 4. • The output is low impedance. —10— CXA3038N PLL circuit (when Pin 21 is connected to VCC) • A PLL is formed by connecting the anode of the LC parallel resonance circuit varicap diode to the Pin 18 output via a high resistance of approximately 10 kΩ and connecting a loop filter between Pin 18 and Pin 19. • The PLL circuit consists of a main divider, reference divider, phase comparator, charge pump, and reference oscillator. • The frequency dividing data is included in the main divider, making external data settings unnecessary. • The reference frequency has been designed at 50 kHz. • Fine adjustment of the VCO frequency can be performed by changing the frequency dividing value of the main divider through an applied voltage to Pin 12. This allows adjustment in ±4 steps at 50 kHz intervals based at 479.5 MHz as shown in the table below. Pin 12 voltage [V] 0.597 VCC or more 0.517VCC to 0.595VCC 0.438VCC to 0.515VCC 0.358VCC to 0.436VCC 0.279VCC to 0.356VCC 0.199VCC to 0.277VCC 0.120VCC to 0.197VCC 0.042VCC to 0.118VCC 0 to 0.04VCC Frequency dividing value 9594 9593 9592 9591 9590 9589 9588 9587 9586 VCO oscillation frequency [MHz] 479.70 479.65 479.60 479.55 479.50 479.45 479.40 479.35 479.30 • The reference divider has two types of frequency dividing data, 80 and 200. • Either 4 MHz or 10 MHz can be selected for the crystal oscillator. When using the 4 MHz crystal oscillator, opening Pin 3 will select a frequency dividing value of 80 for the reference divider, and the reference frequency will become 50 kHz. In the same way, when using the 10 MHz crystal oscillator, connecting Pin 3 to GND will select a frequency dividing value of 200 for the reference divider, and the reference frequency will become 50 kHz. This is summarized in the table below. Crystal oscillator 4 MHz 10 MHz Frequency dividing value of the reference divider Open 80 0.8 V or less 200 Pin 3 voltage —11— Reference frequency 50 kHz 50 kHz CXA3038N Reference oscillator circuit • This is oscillated by connecting a crystal oscillator (4 MHz or 10 MHz) between Pin 24 and GND. • The input capacitance of Pin 24 is approximately 14 pF. Therefore, a crystal with a load capacitance of 12 pF is recommended. When connecting a crystal with a large load capacitance of 16 pF or so, connect a low capacitance between Pin 24 and GND as shown in the figure below, and adjust the frequency. 24 Reference frequency fine-adjustment capacitance Capacitance of DC components eliminated Crystal oscillator 4MHz or 10MHz • The reference oscillator signal is sent to the reference buffer circuit and output from Pin 22 by the emitter follower. The reference oscillator signal becomes the PLL comparison frequency in the IC. • The output amplitude is approximately 300 mVp-p. 200µA 24 22 Usage as PLL reference frequency for the tuner block Charge pump circuit DVCC 1k 1k 10k 19 From phase divider 100 18 From main divider DGND 50µA 1k 500 100 20k • The output current of the charge pump has been designed at 50 µA. • The Pin 18 output voltage ranges from approximately 0.3 V to VCC. • In the loop filter example for the Electrical Characteristics Measurement Circuit, the lockup time is approximately 25 ms. —12— CXA3038N 32 frequency division circuit (when Pin 14 is connected to VCC) • An oscillation signal is sent from the oscillator circuit to the 32 frequency division circuit via a coupling capacitance. The 32 frequency division signal is output from Pin 13 by the counter. • The output is approximately 400 mVp-p ECL output. Notes on Operation • These circuits use high-frequency processes, and the electrostatic strength is weak. Therefore, please be careful of surges and other excessive input. • The IQ error may vary depending on the connection locations of the GND pattern and VCC-GND bypass capacitors, oscillation amplitude of the oscillator circuit, and other factors. —13— CXA3038N RF input level vs. Amplitude error IQ output frequency=1MHz, QOUT=1Vp-p RF input level vs. Phase difference IQ output frequency=1MHz, QOUT=1Vp-p 95 2 94 1.5 1 92 Amplitude error [dB] Phase difference [deg] 93 91 90 89 88 0.5 0 –0.5 –1 87 –1.5 86 –2 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 85 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 RF input level [dBm] RF input level [dBm] IQ output frequency vs. Phase difference RF input level=–40dBm, QOUT=1Vp-p IQ output frequency vs. Amplitude error RF input level=–40dBm, QOUT=1Vp-p 2 95 94 1.5 1 92 Amplitude error [dB] Phase difference [deg] 93 91 90 89 88 0.5 0 –0.5 –1 87 –1.5 86 85 0 2 4 6 8 10 12 14 16 18 –2 20 2 4 6 8 10 12 14 16 18 IQ output frequency [MHz] Supply voltage vs. Current consumption During PLL operation Noise figure characteristics RF input level=–40dBm, QOUT=10MHz 20 35 90 30 80 25 70 NF [dB] Current consumption [mA] 0 IQ output frequency [MHz] 60 20 15 50 10 40 30 4.2 5 4.4 4.6 4.8 5 5.2 5.4 5.6 0 0 5.8 Supply voltage [V] 0.5 1 1.5 2 2.5 3 3.5 AGC voltage [V] —14— 4 4.5 5 CXA3038N AGC voltage vs. Gain RF input level=–40dBm, IQ output frequency=1MHz 60 Third-order intermodulation distortion characteristics 20 55 10 50 Fundamental 0 QOUT output level [dBm] Gain [dB] 45 40 35 30 25 –10 –20 –30 –40 20 –50 15 10 0 1 2 3 AGC voltage [V] RF input level [dBm] Phase noise characteristics RF input level=–40dBm, QOUT=1 MHz, 1Vp-p –50 –60 C/N [dBc/Hz] –70 –80 –90 –100 –110 –120 0.1 1 10 OSC=479.5MHz RF1=498.5MHz RF2=490.5MHz AGC=4V –60 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 5 4 AAAA AAAA AAAA Third-order intermodulation distortion component 100 1000 Offset frequency [kHz] —15— 0 CXA3038N Package Outline Unit : mm 24PIN SSOP(PLASTIC) + 0.2 1.25 – 0.1 ∗7.8 ± 0.1 24 0.1 13 ∗5.6 ± 0.1 7.6 ± 0.2 A 1 + 0.1 0.22 – 0.05 12 + 0.05 0.15 – 0.02 0.13 M 0.65 0.5 ± 0.2 0.1 ± 0.1 0° to 10° NOTE: Dimensions “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-24P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SSOP024-P-0056 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). —16—