DAVICOM DM8603

DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
DAVICOM Semiconductor, Inc.
DM8603
10/100 Mbps 3-port Ethernet Switch Controller
with MII / RMII Interface
DATASHEET
Preliminary Datasheet
Version: DM8603-DS-P01
November 8, 2010
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
1
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
CONTENT
1.
GENERAL DESCRIPTION............................................................................................ 8
2.
BLOCK DIAGRAM........................................................................................................ 8
3.
FEATURES ................................................................................................................... 9
4.
PIN CONFIGURATION ............................................................................................... 10
5.
PIN DESCRIPTION ..................................................................................................... 11
5.1
P2 MII / Reduce MII / Reverse MII.................................................................................................................. 11
5.1.1
MII ............................................................................................................................................................. 11
5.1.2
Reduce MII................................................................................................................................................ 11
5.1.3
Reverse MII............................................................................................................................................... 12
5.2
EEPROM Interface............................................................................................................................................ 12
5.3
LED Pins ............................................................................................................................................................. 12
5.4
Clock Interface ................................................................................................................................................... 13
5.5
Network Interface .............................................................................................................................................. 13
5.6
Miscellaneous Pins.............................................................................................................................................. 13
5.7
Power Pins........................................................................................................................................................... 14
5.8
Strap Pins Table ................................................................................................................................................. 14
6.
PHY REGISTERS ....................................................................................................... 15
6.1
PHY Registers Map............................................................................................................................................ 15
6.2
Basic Mode Control Register (040h, 060h)....................................................................................................... 16
6.3
Basic Mode Status Register (041h, 061h) ......................................................................................................... 17
6.4
PHY ID Identifier Register 1 (042h, 062h)....................................................................................................... 19
6.5
PHY ID Identifier Register 2 (043h, 063h)....................................................................................................... 19
6.6
Auto-negotiation Advertisement Register (044h, 064h) .................................................................................. 20
6.7
Auto-negotiation Link Partner Ability Register (045h, 065h)........................................................................ 21
6.8
Auto-negotiation Expansion Register (046h, 066h) ......................................................................................... 22
6.9
Specified Configuration Register (054h, 074h) ................................................................................................ 23
6.10
Power Saving Control Register (05Dh, 07Dh) ................................................................................................. 24
7.
SWITCH REGISTERS................................................................................................. 25
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
2
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.1
Switch Registers Map......................................................................................................................................... 25
7.2
Per Port Switch Register.................................................................................................................................... 28
7.2.1
Per Port Status Register (110h, 130h, 150h)........................................................................................... 28
7.2.2
Per Port Basic Control Register 1 (111h, 131h, 151h) ........................................................................... 28
7.2.3
Per Port Basic Control Register 2 (112h, 132h, 152h) ........................................................................... 30
7.2.4
Per Port Block Control Register 1 (113h, 133h, 153h)........................................................................... 31
7.2.5
Per Port Block Control Register 2 (114h, 134h, 154h)........................................................................... 32
7.2.6
Per Port Bandwidth Control Register (115h, 135h, 155h)..................................................................... 33
7.2.7
Per Port VLAN Tag Register (116h, 136h, 156h)................................................................................... 35
7.2.8
Per Port Priority & VLAN Control Register (117h, 137h, 157h) ......................................................... 35
7.2.9
Per Port Advanced Control Register (119h, 139h, 159h) ...................................................................... 37
7.3
Global Switch Register....................................................................................................................................... 38
7.3.1
Switch Status Register (210h) .................................................................................................................. 38
7.3.2
Switch Reset Register (211h).................................................................................................................... 38
7.3.3
Switch Control Register (212h)................................................................................................................ 39
7.3.4
Mirror Control Register (213h)............................................................................................................... 39
7.3.5
Special Tag Ether-Type Register (214h)................................................................................................. 40
7.3.6
Global Learning & Aging Control Register (215h) ............................................................................... 40
7.3.7
VLAN Priority Map Register (217h)....................................................................................................... 41
7.3.8
TOS Priority Map Register 1 (218h)....................................................................................................... 41
7.3.9
TOS Priority Map Register 2 (219h)....................................................................................................... 42
7.3.10
TOS Priority Map Register 3 (21Ah) ...................................................................................................... 42
7.3.11
TOS Priority Map Register 4 (21Bh) ...................................................................................................... 43
7.3.12
TOS Priority Map Register 5 (21Ch) ...................................................................................................... 43
7.3.13
TOS Priority Map Register 6 (21Dh) ...................................................................................................... 44
7.3.14
TOS Priority Map Register 7 (21Eh) ...................................................................................................... 44
7.3.15
TOS Priority Map Register 8 (21Fh) ...................................................................................................... 45
7.3.16
MIB Counter Disable Register (230h)..................................................................................................... 46
7.3.17
MIB Counter Control Register (231h) .................................................................................................... 46
7.3.18
MIB Counter Data Register 1 (232h) ...................................................................................................... 47
7.3.19
MIB Counter Data Register 2 (233h) ...................................................................................................... 47
7.3.20
VLAN Mode & Rule Control Register (23Eh) ....................................................................................... 48
7.3.21
VLAN Table Register 0 (270h) ................................................................................................................ 50
7.3.22
VLAN Table Register 1 (271h) ................................................................................................................ 50
7.3.23
VLAN Table Register 2 (272h) ................................................................................................................ 50
7.3.24
VLAN Table Register 3 (273h) ................................................................................................................ 50
7.3.25
VLAN Table Register 4 (274h) ................................................................................................................ 51
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
3
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.26
VLAN Table Register 5 (275h) ................................................................................................................ 51
7.3.27
VLAN Table Register 6 (276h) ................................................................................................................ 51
7.3.28
VLAN Table Register 7 (277h) ................................................................................................................ 51
7.3.29
VLAN Table Register 8 (278h) ................................................................................................................ 52
7.3.30
VLAN Table Register 9 (279h) ................................................................................................................ 52
7.3.31
VLAN Table Register 10 (27Ah) ............................................................................................................. 52
7.3.32
VLAN Table Register 11 (27Bh).............................................................................................................. 52
7.3.33
VLAN Table Register 12 (27Ch) ............................................................................................................. 53
7.3.34
VLAN Table Register 13 (27Dh) ............................................................................................................. 53
7.3.35
VLAN Table Register 14 (27Eh).............................................................................................................. 53
7.3.36
VLAN Table Register 15 (27Fh).............................................................................................................. 53
7.3.37
STP Control Register (292h).................................................................................................................... 54
7.3.38
Snooping Control Register 1 (29Bh) ....................................................................................................... 54
7.3.39
Snooping Control Register 2 (29Ch) ....................................................................................................... 55
7.3.40
Address Table Control & Status Register (2B0h).................................................................................. 56
7.3.41
Address Table Data Register 1 (2B1h).................................................................................................... 57
7.3.42
Address Table Data Register 2 (2B2h).................................................................................................... 57
7.3.43
Address Table Data Register 3 (2B3h).................................................................................................... 57
7.3.44
Address Table Data Register 4 (2B4h).................................................................................................... 57
7.3.45
Address Table Data 4 Register (2B5h).................................................................................................... 57
7.3.46
Vendor ID Register (310h) ....................................................................................................................... 57
7.3.47
Product ID Register (311h) ...................................................................................................................... 58
7.3.48
Port 2 MAC Control Register (315h) ...................................................................................................... 59
7.3.49
EEPROM Control & Address Register (31Ah) ..................................................................................... 60
7.3.50
EEPROM Data Register (31Bh) .............................................................................................................. 60
7.3.51
Strap Pin Control & Status Register (31Ch) .......................................................................................... 61
7.3.52
SMI Bus Error Check Register (339h).................................................................................................... 62
7.3.53
SMI Bus Control Register (33Ah) ........................................................................................................... 62
7.3.54
PHY Control Register (33Eh) .................................................................................................................. 63
8.
EEPROM FORMAT..................................................................................................... 64
9.
FUNCTIONAL DESCRIPTION.................................................................................... 69
9.1
Host Serial Management Interface ................................................................................................................... 69
9.1.1
Host SMI Frame Structure ...................................................................................................................... 69
9.1.2
Host SMI Bus Error Check Function ..................................................................................................... 70
9.2
Switch Functions ................................................................................................................................................ 71
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
4
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.2.1
Address Learning...................................................................................................................................... 71
9.2.2
Address Aging ........................................................................................................................................... 71
9.2.3
Packet Forwarding ................................................................................................................................... 71
9.2.4
Inter-Packet Gap (IPG)............................................................................................................................ 71
9.2.5
Back-off Algorithm................................................................................................................................... 71
9.2.6
Late Collision ............................................................................................................................................ 72
9.2.7
Full Duplex Flow Control......................................................................................................................... 72
9.2.8
Half Duplex Flow Control........................................................................................................................ 72
9.2.9
Partition Mode .......................................................................................................................................... 72
9.2.10
Broadcast Storm Filtering........................................................................................................................ 73
9.2.11
Bandwidth Control ................................................................................................................................... 73
9.2.12
Port Monitoring Support ......................................................................................................................... 73
9.2.13
VLAN Support .......................................................................................................................................... 74
9.2.13.1
Port-Based VLAN .............................................................................................................. 74
9.2.13.2
802.1Q-Based VLAN.......................................................................................................... 74
9.2.13.3
Tag/Untag........................................................................................................................... 74
9.2.14
Special Tag ................................................................................................................................................ 75
9.2.15
Priority Support........................................................................................................................................ 77
9.2.15.1
Port-Based Priority ........................................................................................................... 77
9.2.15.2
802.1p-Based Priority ....................................................................................................... 77
9.2.15.3
DiffServ-Based Priority..................................................................................................... 77
9.2.16
Address Table Accessing .......................................................................................................................... 78
9.2.16.1
Type of Address Table...................................................................................................... 78
9.2.16.2
Access Rules of Address Table ...................................................................................... 78
9.2.17
IGMP Snooping ........................................................................................................................................ 82
9.2.18
IPv6 MLD Snooping ................................................................................................................................. 82
9.2.19
STP / RSTP Support................................................................................................................................. 83
9.3
MII Interface ...................................................................................................................................................... 86
9.3.1
MII Data Interface.................................................................................................................................... 86
9.3.2
MII Serial Management Interface........................................................................................................... 87
9.4
Internal PHY Functions..................................................................................................................................... 88
9.4.1
100Base-TX Operation ............................................................................................................................. 88
9.4.1.1
4B5B Encoder.................................................................................................................... 88
9.4.1.2
Scrambler........................................................................................................................... 88
9.4.1.3
Parallel to Serial Converter .............................................................................................. 88
9.4.1.4
NRZ to NRZI Encoder........................................................................................................ 88
9.4.1.5
MLT-3 Converter................................................................................................................ 88
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
5
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.4.1.6
MLT-3 Driver ...................................................................................................................... 89
9.4.1.7
4B5B Code Group ............................................................................................................. 90
9.4.2
100Base-TX Receiver................................................................................................................................ 91
9.4.2.1
Signal Detect ..................................................................................................................... 91
9.4.2.2
Adaptive Equalization....................................................................................................... 91
9.4.2.3
MLT-3 to NRZI Decoder .................................................................................................... 91
9.4.2.4
Clock Recovery Module.................................................................................................... 91
9.4.2.5
NRZI to NRZ ....................................................................................................................... 92
9.4.2.6
Serial to Parallel ................................................................................................................ 92
9.4.2.7
Descrambler ...................................................................................................................... 92
9.4.2.8
Code Group Alignment..................................................................................................... 92
9.4.2.9
4B5B Decoder.................................................................................................................... 92
9.4.3
10Base-T Operation.................................................................................................................................. 93
9.4.4
Collision Detection .................................................................................................................................... 93
9.4.5
Carrier Sense............................................................................................................................................. 93
9.4.6
Auto-Negotiation....................................................................................................................................... 93
9.5
LFP and FEF Function ...................................................................................................................................... 94
9.6
HP Auto-MDIX Function .................................................................................................................................. 94
10. DC AND AC ELECTRICAL CHARACTERISTICS...................................................... 95
10.1
Absolute Maximum Ratings .............................................................................................................................. 95
10.2
Operating Conditions......................................................................................................................................... 95
10.3
DC Electrical Characteristics............................................................................................................................ 96
10.4
AC Characteristics ............................................................................................................................................. 97
10.4.1
Power On Reset Timing ........................................................................................................................... 97
10.4.2
Port 2 MII Interface Transmit Timing ................................................................................................... 98
10.4.3
Port 2 MII Interface Receive Timing ...................................................................................................... 98
10.4.4
Port 2 RMII Interface Transmit Timing ................................................................................................ 99
10.4.5
Port 2 RMII Interface Receive Timing ................................................................................................... 99
10.4.6
MII Management Interface Timing ...................................................................................................... 100
10.4.7
Host SMI Interface Timing.................................................................................................................... 100
10.4.8
EEPROM Timing ................................................................................................................................... 101
11. APPLICATION INFORMATION ................................................................................ 102
11.1
Application of Reverse MII ............................................................................................................................. 102
11.2
Application of Reduce MII to PHY ................................................................................................................ 103
11.3
Application of Reduce MII to MAC ............................................................................................................... 103
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
6
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
12. PACKAGE INFORMATION ...................................................................................... 104
13. TERMINOLOGY........................................................................................................ 105
14. ORDERING INFORMATION ..................................................................................... 107
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
7
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
1. General Description
The DM8603 is Davicom’s new fully integrated three-port 10M/100Mbps Fast Ethernet
Controller. As a fast Ethernet switch, the DM8603 consists of two PHY ports and a third port with
either MII or RMII interface. As the DM8603 was designed with our customers’ requirements in
mind, the switch is optimized for high performance while being highly cost-effective.
The two PHY ports on the DM8603 are IEEE 802.3u standards compliant. Aside for the first two
PHY ports and in an effort for maximum application flexibility, the third port on the DM8603 offers
the options to either connect with an MII, reversed MII, or RMII. The reversed MII configuration is
used to connect with SoC’s with a MII interface. The RMII interface is the alternative interface
configuration in case of the need to connect a lower pin count Ethernet PHY or SoC.
To maximize the performance of each port, the DM8603 was designed with a number of
features. For proper bandwidth, each port also supports ingress and/or egress rate control. In
support of efficient packet forwarding, the DM8603 has port-based VLAN with tag/un-tag functions
for up to 16 groups of 802.1Q. Each port includes MIB counters, loop-back capability, built in
memory self test (BIST) for the system, and board level diagnostic.
In designing for the requirements of various data, voice, and video applications, enough internal
memory has been provided for usage of the DM8603’s three ports, and the internal memory
supports up to 1K uni-cast MAC address table. Then to meet the demands of various bandwidth
and latency issues in data, voice, and video applications, each port of the DM8603 has four priority
transmit queues. These queues can be defined either through port-based operation, 802.1p
VLAN, or the IP packet TOS field automatically.
2. Block Diagram
Switch Engine
Switch Fabric
Port 0
MDI / MDIX
Port 1
MDI / MDIX
Port 2
MII / RMII
10/100M
PHY
10/100M
MAC
10/100M
PHY
10/100M
MAC
Embedded
Memory
Switch
Controller
Memory
BIST
Memory
Management
LED
Control
10/100M
MAC
LEDs
SMI I/F
Control
Registers
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
MIB
Counters
EEPROM
Interface
EEPROM
8
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
3. Features
•
IEEE 802.3/u 10Base-T/100Base-TX
compatible
•
Supports LFP (Link Fault Pass-through)
and FEF (Far End Fault)
•
Ethernet Switch Ports:
•
Supports hardware-based IGMP v1,v2
Snooping
•
Supports hardware-based MLD v1
Snooping
•
Supports IEEE 802.1d STP (Spanning
Tree Protocol) and IEEE 802.1w RSTP
(Rapid Spanning Tree Protocol)
•
EEPROM Interface
o
Two 10/100Mbps PHY
o
One MII/RMII interface with Reversed
- MII support
•
Supports auto crossover function - HP
Auto-MDIX
•
Flow Control
o
Supports IEEE 802.3x Flow Control in
Full-duplex mode
o
Supports Back Pressure Flow Control
in Half-duplex mode
•
Per port support bandwidth, ingress and
egress rate control
•
Per port support priority queues
o
Each port with four queues
o
Port-based, 802.1P VLAN, or IP TOS
priority
•
Supports 802.1Q VLAN for up-to 16 VLAN
groups
•
Supports VLAN ID tag/untag options
•
Supports special tag and double tag
header
•
Supports up-to 1K Unicast/Multicast
shared MAC addresses
•
Supports store and forward switching
approach
•
Supports Broadcast Storming filter
function
•
Supports Serial Data Management
Interface
•
Automatic aging scheme
•
Supports MIB counters for diagnostic
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
•
o
Power up configurations
o
93C46 or 93C56 auto detection
Package
o
•
64-pin LQFP
Power
o
1.8V/3.3V Dual Power
o
3.3V I/O with 5V tolerance
9
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
4. Pin Configuration
64 pin LQFP:
DM8603EP
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
10
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
5. Pin Description
I = Input,
# = Asserted Low
5.1
O = Output,
I/O = Input / Output,
PD=internal pull-low (about 50K Ohm)
O/D = Open Drain,
P = Power,
P2 MII / Reduce MII / Reverse MII
5.1.1 MII
Pin No.
2
3
5
6
7
9
10
12
14
15
17
18
19
20
21
22
24
25
5.1.2 Reduce MII
Pin No.
2
3
5
6
7
9
10
12
14
15
17
18
19
20
21
22
24
25
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Pin Name
I/O
Description
PHY_MDC
PHY_MDIO
P2_TXD3
P2_TXD2
P2_TXD1
P2_TXD0
O,PD
I/O
O,PD
MII Serial Management Data Clock
MII Serial Management Data
Port 2 MII Transmit Data
4-bit nibble data outputs (synchronous to the P2_TXC)
P2_TXE
P2_TXC
P2_TXER
P2_CRS
P2_COL
P2_RXER
P2_RXC
P2_RXDV
P2_RXD3
P2_RXD2
P2_RXD1
P2_RXD0
O,PD
I/O
O,PD
I/O
I/O
I
I
I
I
Port 2 MII Transmit Enable
Port 2 MII Transmit Clock
Port 2 MII Transmit Error
Port 2 MII Carrier Sense
Port 2 MII Collision Detect
Port 2 MII Receive Error
Port 2 MII Receive Clock
Port 2 MII Receive Data Valid
Port 2 MII Receive Data
4-bit nibble data input (synchronous to P2_RXC)
Pin Name
I/O
PHY_MDC
PHY_MDIO
P2_TXD3
P2_TXD2
P2_TXD1
P2_TXD0
P2_TXE
P2_TXC
P2_TXER
P2_CRS
P2_COL
P2_RXER
P2_RXC
P2_RXDV
P2_RXD3
P2_RXD2
P2_RXD1
P2_RXD0
Description
O,PD
I/O
O,PD
MII Serial Management Data Clock
MII Serial Management Data
Not Used
O,PD
Port 2 RMII Transmit Data
O,PD
O
O
I
I
I
I
I
I
Port 2 RMII Transmit Enable
50MHz Clock Output
Not Used
Port 2 RMII CRS_DV
Not Used, tie to ground in application
Not Used, tie to ground in application
Port 2 RMII 50MHz Reference Clock Input
Not Used, tie to ground in application
Not Used, tie to ground in application
I
Port 2 RMII Receive Data
11
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
5.1.3 Reverse MII
Pin No.
5.2
5.3
Pin Name
I/O
Description
2
3
5
6
7
9
10
12
14
15
PHY_MDC
PHY_MDIO
P2_TXD3
P2_TXD2
P2_TXD1
P2_TXD0
O,PD
I/O
O,PD
Not Used
Not Used
Port 2 RevMII Transmit Data
4-bit nibble data outputs (synchronous to the P2_TXC)
P2_TXE
P2_TXC
P2_TXER
P2_CRS
O,PD
O
O,PD
O
17
P2_COL
O
18
19
20
21
22
24
25
P2_RXER
P2_RXC
P2_RXDV
P2_RXD3
P2_RXD2
P2_RXD1
P2_RXD0
I
I
I
I
Port 2 RevMII Transmit Enable
Port 2 RevMII Transmit Clock
Port 2 RevMII Transmit Error
Port 2 RevMII Carrier Sense
Output when P2_TXE or P2_RXDV are asserted
Port 2 RevMII Collision
Output when P2_TXE and P2_RXDV are asserted
Port 2 RevMII Receive Error
Port 2 RevMII Receive Clock
Port 2 RevMII Receive Data Valid
Port 2 RevMII Receive Data
4-bit nibble data input (synchronous to P2_RXC)
EEPROM Interface
Pin No.
Pin Name
I/O
Description
27
28
EEDIO
EECK
I/O
O,PD
29
EECS
O,PD
LED Pins
Pin No.
Pin Name
I/O
Description
55
P1_LNK_LED
O
56
P1_SPD_LED
O
57
P0_LNK_LED
O
58
P0_SPD_LED
O
Port 1 Link / Active LED
It is the combined LED of link and carrier sense signal
of the internal PHY1
Port 1 Speed LED
Its low output indicates that the internal PHY1 is
operated in 100M/S, or it is floating for the 10M mode of
the internal PHY1
Port 0 Link / Active LED
It is the combined LED of link and carrier sense signal
of the internal PHY0
Port 0 Speed LED
Its low output indicates that the internal PHY0 is
operated in 100M/S, or it is floating for the 10M mode of
the internal PHY0
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
EEPROM Data In/Out
EEPROM Serial Clock
This pin is used as the clock for the EEPROM data transfer
EEPROM Chip Selection
12
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
5.4
Clock Interface
Pin No.
52
53
5.5
5.6
Pin Name
I/O
X1
X2
I
O
Network Interface
Pin No.
Pin Name
I/O
34
35
P1_TX+
P1_TX -
I/O
37
38
P1_RX+
P1_RX-
I/O
41
42
P0_TX+
P0_TX-
I/O
44
45
P0_RX+
P0_RX -
I/O
47
BGRES
I/O
48
49
50
BGGND
VCNTL
VREF
P
I/O
O
Miscellaneous Pins
Pin No.
Pin Name
I/O
30
PWRST#
I
60
62
32
SMI_MDC
SMI_MDIO
TEST1
I
I/O
I,PD
59
TEST2
I,PD
63
TEST3
I,PD
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
Crystal or OSC 25MHz Input
Crystal 25MHz Output
Description
Port 1 TP TX
These two pins are the Twisted Pair transmit in MDI
mode or receive in MDIX mode
Port 1 TP RX
These two pins are the Twisted Pair receive in MDI
mode or transmit in MDIX mode
Port 0 TP TX
These two pins are the Twisted Pair transmit in MDI
mode or receive in MDIX mode
Port 0 TP RX
These two pins are the Twisted Pair receive in MDI
mode or transmit in MDIX mode
Band-Gap Pin
Connect a 6.8K±1% ohm resistor to BGGND in
application
Band-Gap Ground
1.8V Voltage Control
Voltage Reference
Connect a 0.1uF capacitor to ground in application
Description
Power on Reset
Low active with minimum 1ms
Serial Data Management Interface Clock
Serial Data Management Interface Data In/Out
Test Pin 1
Tie to DVDD33 in application
Test Pin 2
Tie to DVDD33 in application
Test Pin 3
Tie to DVDD33 in application
13
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
5.7
Power Pins
Pin No.
Pin Name
I/O
1,13,26,51
11,61
4,8,16,23,31,64
39,46
33,40
36,43,54
DVDD33
DVDD18
DGND
AVDD33
AVDD18
AGND
P
P
P
P
P
P
5.8 Strap Pins Table
Pin No.
Pin Name
10
P2_TXE
28
EECK
29
EECS
14
P2_TXER
5
6
P2_TXD3
P2_TXD2
Description
Digital 3.3V Power
Digital 1.8V Power
Digital GND
Analog 3.3V Power
Analog 1.8V Power
Analog GND
Description
Port 2 Force Mode Enable
0: Port 2 is normal mode
1: Port 2 is force mode
Port 2 Speed Selection in Force Mode
0: Port 2 is forced in 10 Mbps mode
1: Port 2 is forced in 100 Mbps mode
Port 0 Fiber Mode Enable
0: Port 0 is TP mode
1: Port 0 is Fiber mode
Port 1 Fiber Mode Enable
0: Port 1 is TP mode
1: Port 1 is Fiber mode
P2 Mode Configuration
P2_TXD3 P2_TXD2
0
0
Port 2 is MII mode
0
1
Port 2 is Reverse MII mode
1
0
Port 2 is RMII mode
1
1
LFP function is enabled
(Port 2 is MII mode)
Note:
1 = External pull-high with resistor 1K~10K ohm
0 = Internal pull-low (default) or External pull-low
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
14
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
6. PHY Registers
6.1
PHY Registers Map
PHY_ADR
REG_ADR
ABS_ADR
Register Description
Default
02h
00h
01h
02h
03h
04h
05h
06h
14h
1Dh
00h
01h
02h
03h
04h
05h
06h
14h
1Dh
040h
041h
042h
043h
044h
045h
046h
054h
05Dh
060h
061h
062h
063h
064h
065h
066h
074h
07Dh
Port 0 PHY Basic Mode Control Register
Port 0 PHY Basic Mode Status Register
Port 0 PHY Identifier 1 Register
Port 0 PHY Identifier 2 Register
Port 0 PHY Auto-negotiation Advertisement Register
Port 0 PHY Auto-negotiation Link Partner Ability Register
Port 0 PHY Auto-negotiation Expansion Register
Port 0 PHY Specified Configuration Register
Port 0 PHY Power Saving Control Register
Port 1 PHY Basic Mode Control Register
Port 1 PHY Basic Mode Status Register
Port 1 PHY Identifier 1 Register
Port 1 PHY Identifier 2 Register
Port 1 PHY Auto-negotiation Advertisement Register
Port 1 PHY Auto-negotiation Link Partner Ability Register
Port 1 PHY Auto-negotiation Expansion Register
Port 1 PHY Specified Configuration Register
Port 1 PHY Power Saving Control Register
3100h
7849h
0181h
B8B0h
01E1h
0000h
0000h
0000h
3100h
7849h
0181h
B8B0h
01E1h
0000h
0000h
0000h
03h
Note:
PHY_ADR
=
<PHY Address> fields of SMI frame
REG_ADR
=
<Register Address> fields of SMI frame
ABS_ADR
=
{ PHY_ADR[4:0], REG_ADR[4:0] }
Key to Default
In the register description that follows, the default column takes the form:
<Access Type> / <Attribute(s)>, <Reset Value>
Where:
<Access Type>
RO = Read only,
RW = Read/Write
<Attribute (s)>
SC = Self clearing, P = Value permanently set
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
<Reset Value>:
1 = Bit set to logic one
0 = Bit set to logic zero
* = No default value
15
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
6.2
Basic Mode Control Register (040h, 060h)
PHY_ADR
02h, 03h
REG_ADR
00h
Bit
15
Bit Name
Reset
Default
RW/SC
0b
14
Loopback
RW
0b
13
Speed selection
RW
1b
12
Auto-negotiation
enable
RW
1b
11
Power down
RW
0b
10
Isolate
9
Restart
Auto-negotiation
RW
0b
RW/SC
0b
8
Duplex mode
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
RW
1b
ABS_ADR
040, 060h
Description
Reset
This bit sets the status and controls the PHY registers to their default
states. This bit, which is self-clearing, will keep returning a value of
one until the reset process is completed
1 = Software reset
0 = Normal operation
Loopback
Loop-back control register. When in 100Mbps operation mode,
setting this bit may cause the descrambler to lose synchronization
and produce a 720ms "dead time" before any valid data appears at
the MII receive outputs
1 = Loop-back enabled
0 = Normal operation
Speed Select
Link speed may be selected either by this bit or by auto-negotiation.
When auto-negotiation is enabled and bit 12 is set, this bit will return
auto-negotiation selected medium type
1 = 100Mbps
0 = 10Mbps
Auto-negotiation Enable
1 = Auto-negotiation is enabled, bit 8 and 13 will be in
auto-negotiation status
0 = Auto-negotiation is disabled.
Power Down
While in the power-down state, the PHY should respond to
management transactions. During the transition to power-down state
and while in the power-down state, the PHY should not generate
spurious signals on the MII
1 = Power down
0 = Normal operation
Isolate
Force to 0 in application.
Restart Auto-negotiation
Re-initiates the auto-negotiation process. When auto-negotiation is
disabled (bit 12 of this register cleared), this bit has no function and it
should be cleared. This bit is self-clearing and it will keep returning to
a value of 1 until auto-negotiation is initiated by the DM8603. The
operation of the auto-negotiation process will not be affected by the
management entity that clears this bit
1 = Restart auto-negotiation.
0 = Normal operation
Duplex Mode
Duplex selection is allowed when Auto-negotiation is disabled (bit 12
of this register is cleared). With auto-negotiation enabled, this bit
reflects the duplex capability selected by auto-negotiation
1 = Full duplex operation.
0 = Normal operation
16
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7
Collision test
RW
0b
6:0
RESERVED
RO
0h
6.3
Collision Test
When set, this bit will cause the COL signal to be asserted in
response to the assertion of TX_EN in internal MII interface.
1 = Collision test enabled.
0 = Normal operation
Reserved
Write as 0h, ignore when read
Basic Mode Status Register (041h, 061h)
PHY_ADR
02h, 03h
REG_ADR
01h
Bit
15
Bit Name
100BASE-T4
Default
RO/P
0b
14
100BASE-TX
full-duplex
RO/P
1b
13
100BASE-TX
half-duplex
RO/P
1b
12
10BASE-T
full-duplex
RO/P
1b
11
10BASE-T
half-duplex
RO/P
1b
10:7
RESERVED
6
MF preamble
suppression
RO
0h
RO
1b
5
Auto-negotiation
Complete
RO
0b
4
Remote fault
RO
0b
3
Auto-negotiation
ability
RO/P
1b
2
Link status
RO
0b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
ABS_ADR
041, 061h
Description
100BASE-T4 Capable
1 = DM8603 is able to perform in 100BASE-T4 mode
0 = DM8603 is not able to perform in 100BASE-T4 mode
100BASE-TX Full Duplex Capable
1 = DM8603 is able to perform 100BASE-TX in full duplex mode
0 = DM8603 is not able to perform 100BASE-TX in full duplex
mode
100BASE-TX Half Duplex Capable
1 = DM8603 is able to perform 100BASE-TX in half duplex mode
0 = DM8603 is not able to perform 100BASE-TX in half duplex
mode
10BASE-T Full Duplex Capable
1 = DM8603 is able to perform 10BASE-T in full duplex mode
0 = DM8603 is not able to perform 10BASE-TX in full duplex mode
10BASE-T Half Duplex Capable
1 = DM8603 is able to perform 10BASE-T in half duplex mode
0 = DM8603 is not able to perform 10BASE-T in half duplex mode
Reserved
Write as 0h, ignore when read
MII Frame Preamble Suppression
1 = PHY will accept management frames with preamble
suppressed
0 = PHY will not accept management frames with preamble
suppressed
Auto-negotiation Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
Remote Fault
1 = Remote fault condition detected (cleared on read or by a chip
reset). Fault criteria and detection method is DM8603
implementation specific. This bit will set after the RF bit in the
ANLPAR (REG 02h/03h.05h.[13]) is set
0 = No remote fault condition detected
Auto Configuration Ability
1 = DM8603 is able to perform auto-negotiation
0 = DM8603 is not able to perform auto-negotiation
Link Status
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the link status bit to be
17
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
1
Jabber detect
RO
0b
0
Extended
capability
RO/P
1b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
cleared and remain cleared until it is read via the management
interface.
1 = Valid link is established (for either 10Mbps or 100Mbps
operation)
0 = Link is not established
Jabber Detect
This bit is implemented with a latching function. Jabber conditions will
set this bit unless it is cleared by a read to this register through a
management interface or a DM8603 reset. This bit works only in
10Mbps mode
1 = Jabber condition detected
0 = No jabber
Extended Capability
1 = Extended register capable
0 = Basic register capable only
18
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
6.4
PHY ID Identifier Register 1 (042h, 062h)
PHY_ADR
02h, 03h
Bit
15:0
REG_ADR
02h
Bit Name
OUI_MSB
Default
RO
0181h
ABS_ADR
042h, 062h
Description
OUI Most Significant Bits
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI are
ignored (the IEEE standard refers to these as bit 1 and 2)
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM8603. The Identifier
consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a
model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
6.5
PHY ID Identifier Register 2 (043h, 063h)
PHY_ADR
02h, 03h
REG_ADR
03h
Bit
15:10
Bit Name
OUI_LSB
Default
RO/P
101110b
9:4
VNDR_MDL
RO/P
001011b
3:0
MDL_REV
RO/P
0001b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
ABS_ADR
043h, 063h
Description
OUI Least Significant Bits
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
Vendor Model Number
Five bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
Model Revision Number
Five bits of vendor model revision number mapped to bit 3 to 0 (most
significant bit to bit 4)
19
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
6.6
Auto-negotiation Advertisement Register (044h, 064h)
PHY_ADR
02h, 03h
REG_ADR
04h
Bit
15
Bit Name
NP
Default
RO/P
0b
14
ACK
RO
0b
13
RF
RW
0b
12:11
RESERVED
10
FCS
RW
00b
RW
0b
9
T4
RO/P
0b
8
TX_FDX
RW
1b
7
TX_HDX
RW
1b
6
10_FDX
RW
1b
5
10_HDX
RW
1b
4:0
Selector
RW
00001b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
ABS_ADR
044h, 064h
Description
Next page Indication
The DM8603 has no next page, so this bit is permanently set to 0.
0 = No next page available
1 = Next page available
Acknowledge
The DM8603's auto-negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the appropriate
time during the auto-negotiation process. Software should not
attempt to write to this bit.
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
Remote Fault
1 = Local device senses a fault condition
0 = No fault detected
Reserved
Write as 00b, ignore when read
Flow Control Support
1 = Controller chip supports flow control ability
0 = Controller chip doesn’t support flow control ability
100BASE-T4 Support
The DM8603 does not support 100BASE-T4 so this bit is
permanently set to 0
1 = 100BASE-T4 is supported by the local device
0 = 100BASE-T4 is not supported
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the local device
0 = 100BASE-TX full duplex is not supported
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the local device
0 = 100BASE-TX half duplex is not supported
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the local device
0 = 10BASE-T full duplex is not supported
10BASE-T Support
1 = 10BASE-T half duplex is supported by the local device
0 = 10BASE-T half duplex is not supported
Protocol Selection Bits
These bits contain the binary encoded protocol selector supported by
this node
<00001> indicates that this device supports IEEE 802.3 CSMA/CD
20
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
6.7
Auto-negotiation Link Partner Ability Register (045h, 065h)
PHY_ADR
02h, 03h
REG_ADR
05h
Bit
15
Bit Name
NP
Default
RO
0b
14
ACK
RO
0b
13
RF
RO
0b
12:11
RESERVED
10
FCS
RO
00b
RO
0b
9
T4
RO
0b
8
TX_FDX
RO
0b
7
TX_HDX
RO
0b
6
10_FDX
RO
0b
5
10_HDX
RO
0b
4:0
Selector
RO
0h
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
ABS_ADR
045h, 065h
Description
Next Page Indication
0 = Link partner, no next page available
1 = Link partner, next page available
Acknowledge
The DM8603's auto-negotiation state machine will automatically
control this bit from the incoming FLP bursts. Software should not
attempt to write to this bit
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
Remote Fault
1 = Remote fault indicated by link partner
0 = No remote fault indicated by link partner
Reserved
Write as 00b, ignore when read
Flow Control Support
1 = Controller chip supports flow control ability by link partner
0 = Controller chip doesn’t support flow control ability by link
partner
100BASE-T4 Support
1 = 100BASE-T4 is supported by the link partner
0 = 100BASE-T4 is not supported by the link partner
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the link partner
0 = 100BASE-TX full duplex is not supported by the link partner
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the link partner
0 = 100BASE-TX half duplex is not supported by the link partner
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the link partner
0 = 10BASE-T full duplex is not supported by the link partner
10BASE-T Support
1 = 10BASE-T half duplex is supported by the link partner
0 = 10BASE-T half duplex is not supported by the link partner
Protocol Selection Bits
Link partner’s binary encoded protocol selector
21
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
6.8
Auto-negotiation Expansion Register (046h, 066h)
PHY_ADR
02h, 03h
REG_ADR
06h
Bit
15:5
Bit Name
RESERVED
4
PDF
3
LP_NP_ABLE
RO
0b
2
NP_ABLE
1
PAGE_RX
RO/P
0b
RO
0b
0
LP_AN_ABLE
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Default
RO
0h
RO/LH
0b
RO
0b
ABS_ADR
046h, 066h
Description
Reserved
Write as 0h, ignore when read
Local Device Parallel Detection Fault
1 = A fault detected via parallel detection function.
0 = No fault detected via parallel detection function
Link Partner Next Page Ability
1 = Link partner, next page available
0 = Link partner, no next page
Local Device Next Page Ability
DM8603 does not support this function, so this bit is always 0
New Page Received
A new link code word page received. This bit will be automatically
cleared when the register (register 6) is read by management
Link Partner Auto-negotiation Ability
A “1” in this bit indicates that the link partner supports
Auto-negotiation
22
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
6.9
Specified Configuration Register (054h, 074h)
PHY_ADR
02h, 03h
REG_ADR
14h
Bit
15:12
Bit Name
RESERVED
11
PREAMBLEX
10
TX10M_PWR
RW
0b
9
NWAY_PWR
RW
0b
8
RESERVED
7
MDIX_CNTL
6
RESERVED
5
Mdix_fix Value
4
Mdix_down
RW
0b
3:0
RESERVED
RW
0000b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Default
RW
0000b
RW
0b
RO
0b
RO
*
RW
0b
RW
0b
ABS_ADR
054h, 074h
Description
Reserved
Write as 0000b, ignore when read
Preamble Saving Control
0 = When bit 10 is set, the 10BASE-T transmit preamble count is
reduced. When REG 02h/03h.1Dh.[11] is set, 12-bit preamble is
reduced; otherwise 22-bit preamble is reduced.
1 = Transmit preamble bit count is normal in 10BASE-T mode
10BASE-T mode Transmit Power Saving Control
1 = Enable transmit power saving in 10BASE-T mode
0 = Disable transmit power saving in 10BASE-T mode
Auto-negotiation Power Saving Control
1 = Disable power saving during auto-negotiation period
0 = Enable power saving during auto-negotiation period
Reserved
Read as 0, ignore on write
The Polarity of MDI/MDIX value
1 = MDIX mode
0 = MDI mode
Reserved
Write as 0b, ignore when read
MDIX_CNTL force value:
When Mdix_down = 1, MDIX_CNTL value depend on the register
value
MDIX Down
Manual force MDI/MDIX.
MDIX_CNTL value depend on REG 02h/03h.14h.[5]
0 = Enable HP Auto-MDIX
1 = Disable HP Auto-MDIX
Reserved
Write as 0000b, ignore when read
23
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
6.10 Power Saving Control Register (05Dh, 07Dh)
PHY_ADR
02h, 03h
REG_ADR
1Dh
Bit
15:12
Bit Name
RESERVED
11
PREAMBLEX
10
RESERVED
9
TX_PWR
8:0
RESERVED
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Default
RO
0000b
RW
0b
RW
0b
RW
0b
RO
0h
ABS_ADR
05Dh, 07Dh
Description
Reserved
Write as 0000b, ignore when read
Preamble Saving Control
when both bit REG 02h/03h.14h.[11:10] are set, the 10BASE-T
transmit preamble count is reduced.
1 = 12-bit preamble is reduced.
0 = 22-bit preamble is reduced.
Reserved
Write as 0b, ignore when read
Transmit Power Saving Control Disabled
1 = When cable is unconnected with link partner, the driving
current of transmit is reduced for power saving.
0 = Disable transmit driving power saving function
Reserved
Write as 0h, ignore when read
24
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7. Switch Registers
7.1
Switch Registers Map
PHY_ADR
REG_ADR
ABS_ADR
08h
00h~0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah~1Fh
00h~0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah~1Fh
00h~0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah~1Fh
00h~0Fh
10h
11h
12h
100h~10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah~11Fh
120~12F
130h
131h
132h
133h
134h
135h
136h
137h
138h
139h
13Ah~13Fh
140h~14Fh
150h
151h
152h
153h
154h
155h
156h
157h
158h
159h
15Ah~15Fh
200h~20Fh
210h
211h
212h
09h
0Ah
10h
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Register Description
Reserved
Port 0 Status Register
Port 0 Basic Control Register 1
Port 0 Basic Control Register 2
Port 0 Block Control Register 1
Port 0 Block Control Register 2
Port 0 Bandwidth Control Register
Port 0 VLAN Tag Register
Port 0 Priority & VLAN Control Register
Reserved
Port 0 Advanced Control Register
Reserved
Reserved
Port 1 Status Register
Port 1 Basic Control Register 1
Port 1 Basic Control Register 2
Port 1 Block Control Register 1
Port 1 Block Control Register 2
Port 1 Bandwidth Control Register
Port 1 VLAN Tag Register
Port 1 Priority & VLAN Control Register
Reserved
Port 1 Advanced Control Register
Reserved
Reserved
Port 2 Status Register
Port 2 Basic Control Register 1
Port 2 Basic Control Register 2
Port 2 Block Control Register 1
Port 2 Block Control Register 2
Port 2 Bandwidth Control Register
Port 2 VLAN Tag Register
Port 2 Priority & VLAN Control Register
Reserved
Port 2 Advanced Control Register
Reserved
Reserved
Switch Status Register
Switch Reset Register
Switch Control Register
Default
0000h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
093Ah
0000h
0000h
0000h
0000h
0000h
0001h
0000h
0000h
093Ah
0000h
0000h
25
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
11h
13h
14h
15h
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
00h~0Fh
10h
11h
12h
13h
14h~1Dh
1Eh
1Fh
00h~0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
00h~11h
12h
13h~1Ah
1Bh
1Ch
1Dh~1Fh
00h~0Fh
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h~22Fh
230h
231h
232h
233h
234h~23Dh
23Eh
23Fh
260h~26Fh
270h
271h
272h
273h
274h
275h
276h
277h
278h
279h
27Ah
27Bh
27Ch
27Dh
27Eh
27Fh
280h~291h
292h
293h~29Ah
29Bh
29Ch
29Dh~29Fh
2A0h~2AFh
Mirror Control Register
Special Tag Ether-Type Register
Global Learning & Aging Control Register
Reserved
VLAN Priority Map Register
TOS Priority Map Register 1
TOS Priority Map Register 2
TOS Priority Map Register 3
TOS Priority Map Register 4
TOS Priority Map Register 5
TOS Priority Map Register 6
TOS Priority Map Register 7
TOS Priority Map Register 8
Reserved
MIB Counter Disable Register
MIB Counter Control Register
MIB Counter Data Register 1
MIB Counter Data Register 2
Reserved
VLAN Mode & Rule Control Register
Reserved
Reserved
VLAN Table Register 0
VLAN Table Register 1
VLAN Table Register 2
VLAN Table Register 3
VLAN Table Register 4
VLAN Table Register 5
VLAN Table Register 6
VLAN Table Register 7
VLAN Table Register 8
VLAN Table Register 9
VLAN Table Register 10
VLAN Table Register 11
VLAN Table Register 12
VLAN Table Register 13
VLAN Table Register 14
VLAN Table Register 15
Reserved
STP Control Register
Reserved
Snooping Control Register 1
Snooping Control Register 2
Reserved
Reserved
0000h
8606h
0000h
FA50h
FA50h
0000h
5555h
5555h
AAAAh
AAAAh
FFFFh
FFFFh
0000h
0000h
0000h
0000h
0000h
0007h
0007h
0007h
0007h
0007h
0007h
0007h
0007h
0007h
0007h
0007h
0007h
0007h
0007h
0007h
0007h
0000h
0700h
097Dh
26
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
18h
19h
1Ch
10h
11h
12h
13h
14h
15h
16h~1Fh
00h~0Fh
10h
11h
12h~14h
15h
16h~19h
1Ah
1Bh
1Ch
1Dh~1Fh
00h~0Fh
10h~18h
19h
1Ah
1Bh~1Dh
1Eh
1Fh
00h~1Fh
2B0h
2B1h
2B2h
2B3h
2B4h
2B5h
2B6h~2BFh
300h~30Fh
310h
311h
312h~314h
315h
316h~319h
31Ah
31Bh
31Ch
31Dh~31Fh
320h~32Fh
330h~338h
339h
33Ah
33Bh~33Dh
33Eh
33Fh
380h~39Fh
Address Table Control & Status Register
Address Table Data Register 1
Address Table Data Register 2
Address Table Data Register 3
Address Table Data Register 4
Address Table Data Register 5
Reserved
Reserved
Vendor ID Register
Product ID Register
Reserved
Port 2 MAC Control Register
Reserved
EEPROM Control & Address Register
EEPROM Data Register
Strap Pin Control & Status Register
Reserved
Reserved
Reserved
SMI Bus Error Check Register
SMI Bus Control Register
Reserved
PHY Control Register
Reserved
Reserved
0000h
0000h
0000h
0000h
0000h
0000h
0A46h
8603h
0100h
0040h
0000h
0000h
0000h
0003h
-
Key to Default
In the register description that follows, the default column takes the form:
<Access Type>, <Reset Type>, <Default Value>
Where:
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits should be written with 0
Reserved bits are undefined on read access
<Reset Type>
P = Register will be set to default value after hardware
reset (Power-ON Reset) is de-asserted
S = Register will be set to default value after software reset
(Write REG 10h.11h.[0] to 1) is done
E = The value reflect upon EEPROM setting
T = The value reflect upon strap pin setting
<Default Value>:
1 = Logic one
0 = Logic zero
* = No default value
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
27
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.2
Per Port Switch Register
7.2.1
Per Port Status Register (110h, 130h, 150h)
PHY_ADR
08h, 09h, 0Ah
REG_ADR
10h
ABS_ADR
110h, 130h, 150h
Bit
15:5
ROM
---
Type
RO
Default
0h
4
---
P, RO
*
3
---
RO
0b
2
---
P, RO
*
1
---
P, RO
*
0
---
P, RO
*
7.2.2
Description
RESERVED
Write as 0h, ignore when read
LP_FCS
Link Partner Flow Control Support Status
0: Link partner don't support IEEE 802.3x flow control
1: Link partner support IEEE 802.3x flow control
RESERVED
Write as 0b, ignore when read
SPEED
Port Speed Status
0: 10Mbps
1: 100Mbps
FDX
Port Duplex Status
0: Half-duplex
1: Full-duplex
LINK
Port Link Status
0: Link Off
1: Link On
Per Port Basic Control Register 1 (111h, 131h, 151h)
PHY_ADR
08h, 09h, 0Ah
REG_ADR
11h
ABS_ADR
111h, 131h, 151h
Bit
15
ROM
---
Type
RO
Default
0b
14
80h.[14]
90h.[14]
A0h.[14]
PSE,RW
0b
13
80h.[13]
90h.[13]
A0h.[13]
PSE,RW
0b
12
80h.[12]
90h.[12]
A0h.[12]
PSE,RW
0b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0b, ignore when read
UNPLUG_CLS
Unplug Clear Address Enable
Automatically clear address record in address table after cable is
unplugged
0: Disable, retaining address record
1: Enable, clearing address record
AGE_DIS
Address Table Aging
0: Age function is enabled
1: Age function is disabled
ADR_DIS
Address Learning Disabled
0: Address learning function is enabled
1: Address learning function is disabled
28
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
11
80h.[11]
90h.[11]
A0h.[11]
PSE,RW
0b
10
---
RO
0b
9
80h.[9]
90h.[9]
A0h.[9]
PSE,RW
0b
8
80h.[8]
90h.[8]
A0h.[8]
PSE,RW
0b
7
80h.[7]
90h.[7]
A0h.[7]
PSE,RW
0b
6
80h.[6]
90h.[6]
A0h.[6]
PSE,RW
0b
5
80h.[5]
90h.[5]
A0h.[5]
PSE,RW
0b
4
80h.[4]
90h.[4]
A0h.[4]
PSE,RW
0b
3:2
80h.[3:2]
90h.[3:2]
A0h.[3:2]
PSE,RW
00b
1
80h.[1]
90h.[1]
A0h.[1]
PSE,RW
0b
0
80h.[0]
90h.[0]
A0h.[0]
PSE,RW
0b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
DIS_PAUSE
Maximum Pause Packet from Link Partner
0: Always care pause packet from link partner
1: Pause packet by passed after 7 continued pause packet
from link partner
RESERVED
Write as 0b, ignore when read
HOLBP_EN
Head-of-Line Blocking Prevent Control
0: Disable
1: Enable
LOOPBACK
Loop-Back Mode
The transmitted packet will be forward to this port itself
0: Look-back is disabled
1: Look-back is enabled
PAUSE_CON
Send PAUSE Continuously
If buffer congestion occur on full duplex, switch will send
PAUSE frames:
0: Up to 8-times
1: Continuously until alleviation
PARTI_EN
Partition Detection Enable
0: Disable
1: Enable
FCBP_DIS
Backpressure Flow-Control in Half Duplex Disable
0: Backpressure is enabled
1: Backpressure is disabled
FC3X_DIS
IEEE 802.3x Flow Control in Full Duplex Mode
0: 802.3x flow-control is enabled
1: 802.3x flow-control is disabled
MAX_PKTLEN[1:0]
Max accept packet length by RX from this port
00: 1536-bytes
01: 1552-bytes
10: 1800-bytes
11: 2032-bytes
RX_DIS
Packet Receive Disable
0: Receive ability is enabled
1: Receive ability is disabled
TX_DIS
Packet Transmit Disable
0: Transmit ability is enabled
1: Transmit ability is disabled
29
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.2.3
Per Port Basic Control Register 2 (112h, 132h, 152h)
PHY_ADR
08h, 09h, 0Ah
REG_ADR
12h
ABS_ADR
112h, 132h, 152h
Bit
15
ROM
81h.[15]
91h.[15]
A1h.[15]
Type
PSE,RW
Default
0b
14
81h.[14]
91h.[14]
A1h.[14]
PSE,RW
0b
13
81h.[13]
91h.[13]
A1h.[13]
PSE,RW
0b
12
81h.[12]
91h.[12]
A1h.[12]
PSE,RW
0b
11
81h.[11]
91h.[11]
A1h.[11]
PSE,RW
0b
10:9
---
RO
00b
8
81h.[8]
91h.[8]
A1h.[8]
PSE,RW
0b
7
81h.[7]
91h.[7]
A1h.[7]
PSE,RW
0b
6
81h.[6]
91h.[6]
A1h.[6]
PSE,RW
0b
5
81h.[5]
91h.[5]
A1h.[5]
PSE,RW
0b
4
81h.[4]
91h.[4]
A1h.[4]
PSE,RW
0b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
NO_DIS_RX
Not Discard RX Packets when Ingress Bandwidth Control
When received packets bandwidth reach Ingress bandwidth
threshold, the packets over the threshold are not discarded but with
flow control.
BANDWIDTH
Bandwidth Control Mode
0: Separate mode. Bandwidth control with ingress and egress is
separated, the threshold defined in REG 08/09/0Ah.15h.[15:8]
1: Combined mode. Bandwidth control with ingress or egress is
combined, the threshold defined in REG 08/09/0Ah.15h.[3:0]
STORM_UUP
Broadcast Storm Enable for Unlearned Unicast Packets
0: Disable
1: Enable
STORM_MP
Broadcast Storm Filtering for Multicast Packets
Treat multicast packet as source of storm
0: Disable
1: Enable
MIRR_DBP
Don't Mirror Broadcast/Multicast Packets
If Mirror Function is Enabled
0: Broadcast/Multicast would be mirrored
1: Broadcast/Multicast would not be mirrored
RESERVED
Write as 00b, ignore when read
FIR_UUDMAC
Filter Packets with Unlearned Unicast DMAC
0: Disable
1: Enable
FIR_UMDMAC
Filter Packets with Unlearned Multicast DMAC
0: Disable
1: Enable
FIR_BDMAC
Filter Packets with Broadcast DMAC
0: Disable
1: Enable
FIR_MDMAC
Filter Packets with Multicast DMAC
0: Disable
1: Enable
FIR_MSMAC
Filter Packets with Multicast SMAC
0: Disable
1: Enable
30
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
3
---
RO
0b
2
81h.[2]
91h.[2]
A1h.[2]
PSE,RW
0b
1
---
RO
0b
0
81h.[0]
91h.[0]
A1h.[0]
PSE,RW
0b
7.2.4
RESERVED
Write as 0b, ignore when read
MIRR_TX
TX Packet is Mirrored.
The received packets are also forward to sniffer port.
0: Don’t mirror
1: All transmitted packets is mirrored
RESERVED
Write as 0b, ignore when read
MIRR_RX
RX Packet is Mirrored.
The received packets are also forward to sniffer port.
0: Don’t mirror
1: All received packets is mirrored
Per Port Block Control Register 1 (113h, 133h, 153h)
PHY_ADR
08h, 09h, 0Ah
REG_ADR
13h
ABS_ADR
113h, 133h, 153h
Bit
15:11
ROM
---
Type
RO
Default
0h
10:8
82h.[10:8]
92h.[10:8]
A2h.[10:8]
PSE,RW
000b
7:3
---
RO
0h
2:0
82h.[2:0]
92h.[2:0]
A2h.[2:0]
PSE,RW
000b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0h, ignore when read
BLK_MP[2:0]
Block Packet with Multicast DMAC
[10]: Block such packet forward to port 2
[09]: Block such packet forward to port 1
[08]: Block such packet forward to port 0
0: Disable
1: Enable
RESERVED
Write as 0h, ignore when read
BLK_BP[2:0]
Block Packet with Broadcast DMAC
[02]: Block such packet forward to port 2
[01]: Block such packet forward to port 1
[00]: Block such packet forward to port 0
0: Disable
1: Enable
31
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.2.5
Per Port Block Control Register 2 (114h, 134h, 154h)
PHY_ADR
08h, 09h, 0Ah
REG_ADR
14h
ABS_ADR
114h, 134h, 154h
Bit
15:11
ROM
---
Type
RO
Default
0h
10:8
83h.[10:8]
93h.[10:8]
A3h.[10:8]
PSE,RW
000b
7:3
---
RO
0h
2:0
83h.[2:0]
93h.[2:0]
A3h.[2:0]
PSE,RW
000b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0h, ignore when read
BLK_UKP[2:0]
Block Packet with Unlearned Unicast DMAC
[10]: Block such packet forward to port 2
[09]: Block such packet forward to port 1
[08]: Block such packet forward to port 0
0: Disable
1: Enable
RESERVED
Write as 0h, ignore when read
BLK_UP[2:0]
Block Packet with Unicast DMAC
The received unicast packets are not forward to the assigned
ports.
[02]: Block such packet forward to port 2
[01]: Block such packet forward to port 1
[00]: Block such packet forward to port 0
0: Disable
1: Enable
32
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.2.6
Per Port Bandwidth Control Register (115h, 135h, 155h)
PHY_ADR
08h, 09h, 0Ah
REG_ADR
15h
ABS_ADR
115h, 135h, 155h
Bit
15:12
ROM
84h.[15:12]
94h.[15:12]
A4h.[15:12]
Type
PSE,RW
Default
0000b
11:8
84h.[11:8]
94h.[11:8]
A4h.[11:8]
PSE,RW
0000b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
INGRESS[3:0]
Ingress Rate Control (Separated mode)
These bits define the bandwidth threshold that received packets over
the threshold are discarded.
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
EGRESS[3:0]
Egress Rate Control
These bits define the bandwidth threshold that transmitted packets
over the threshold are discarded.
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
33
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7:4
84h.[7:4]
94h.[7:4]
A4h.[7:4]
PSE,RW
0000b
3:0
84h.[3:0]
94h.[3:0]
A4h.[3:0]
PSE,RW
0000b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
BSTH[3:0]
Broadcast Storm Threshold
These bits define the bandwidth threshold that received broadcast
packets over the threshold are discarded
0000: no broadcast storm control
0001: 8K packets/sec
0010: 16K packets/sec
0011: 64K packets/sec
0100: 5%
0101: 10%
0110: 20%
0111: 30%
1000: 40%
1001: 50%
1010: 60%
1011: 70%
1100: 80%
1101: 90%
111X: no broadcast storm control
BW_CTRL[3:0]
Ingress and Egress Rate Control (Combined mode)
Received and Transmitted Bandwidth Control
These bits define the bandwidth threshold that transmitted or
received packets over the threshold are discarded
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
34
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.2.7
Per Port VLAN Tag Register (116h, 136h, 156h)
PHY_ADR
08h, 09h, 0Ah
Bit
15:13
12
11:0
7.2.8
REG_ADR
16h
ROM
85h.[15:13]
95h.[15:13]
A5h.[15:13]
85h.[12]
95h.[12]
A5h.[12]
85h.[11:0]
95h.[11:0]
A5h.[11:0]
ABS_ADR
116h, 136h, 156h
Type
PSE,RW
Default
000b
PSE,RW
0b
PSE,RW
001h
Description
PPRI[2:0]
Port VLAN Priority
PCFI
Port VLAN CFI
PVID[11:0]
Port VLAN Identification
Per Port Priority & VLAN Control Register (117h, 137h, 157h)
PHY_ADR
08h, 09h, 0Ah
REG_ADR
17h
ABS_ADR
117h, 137h, 157h
Bit
15
ROM
---
Type
RO
Default
0b
14
86h.[14]
96h.[14]
A6h.[14]
PSE,RW
0b
13
86h.[13]
96h.[13]
A6h.[13]
PSE,RW
0b
12
86h.[12]
96h.[12]
A6h.[12]
PSE,RW
0b
11:10
---
RO
00b
9:8
86h.[9:8]
96h.[9:8]
A6h.[9:8]
PSE,RW
00b
7
---
RO
0b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0b, ignore when read
TAG_OUT
Output Packet Tagging Enable
The transmitted packets are containing VLAN tagged field
0: Disable
1: Enable
FIR_VIPORT
Enable to Filter Packet with Incoming Port is Non-member in
VLAN
0: Disable
1: Enable
NOTAG_IN
Input Force No Tag
Assume all received frame are untagged
0: Disable
1: Enable
RESERVED
Write as 00b, ignore when read
VLAN_IAC[1:0]
VLAN Ingress Admit Control
00: Accept all frames
01: Accept VLAN-tagged frames only Untagged or priority
tagged(VID=0) frames will be dropped
10: Accept untagged frames only
11: Accept frame's VID equal to ingress PVID
RESERVED
Write as 0b, ignore when read
35
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
6
86h.[6]
96h.[6]
A6h.[6]
PSE,RW
0b
5
86h.[5]
96h.[5]
A6h.[5]
PSE,RW
0b
4
86h.[4]
96h.[4]
A6h.[4]
PSE,RW
0b
3
86h.[3]
96h.[3]
A6h.[3]
PSE,RW
0b
2
86h.[2]
96h.[2]
A6h.[2]
PSE,RW
0b
1:0
86h.[1:0]
96h.[1:0]
A6h.[1:0]
PSE,RW
00b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
PRI_DIS
Priority Queue Disable
Only one transmit queue is supported in this port
0: Priority Queue is enabled
1: Priority Queue is disabled
WRR_EN
Priority Scheduling Algorithm
0: Strict Priority Queuing(SPQ)
1: Weighted Round Robin(WRR)
TOS_PRI
Priority Classification IP ToS over VLAN
If a IP packet with VLAN tag, the priority of this packet is
decode from ToS field.
0: Priority Classification base on VLAN
1: Priority Classification base on IP ToS
TOS_OFF
IP ToS Priority Classification Disable
0: Classification is enabled
1: Classification is disabled
PRI_OFF
VLAN Priority Classification Disable
0: Classification is enabled
1: Classification is disabled
P_PRI[1:0]
Port-based Priority Queue Number
00: Queue 0
01: Queue 1
10: Queue 2
11: Queue 3
36
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.2.9
Per Port Advanced Control Register (119h, 139h, 159h)
PHY_ADR
08h, 09h, 0Ah
REG_ADR
19h
ABS_ADR
119h, 139h, 159h
Bit
15:9
ROM
---
Type
RO
Default
0h
8
88h.[8]
98h.[8]
A8h.[8]
PSE,RW
0b
7:2
---
RO
0h
1:0
---
PS,RW
00b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0h, ignore when read
FAST_LEAVE
IGMP Snooping Fast Leave Enable
0: Disable
1: Enable
RESERVED
Write as 0h, ignore when read
STPS0[1:0]
STP/RSTP Port State.
There are 4 port states for supporting STP, and 3 port states for
supporting RSTP.
00: Forwarding State, The port transmits and receives packets
normally & learning is enabled.
01: Disabled State/Discarding, The port will only forward the
packets that are to and from uP port (span packets) &
learning is disabled.
10: Learning State, The port will only forward the packets that are
to and from uP port (span packets) & leaning is enabled.
11: Blocking/Listening State, The port will only forward the packets
that are to and from uP port (span packets) & learning is
disabled.
37
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3
Global Switch Register
7.3.1
Switch Status Register (210h)
PHY_ADR
10h
REG_ADR
10h
ABS_ADR
210h
Bit
15:2
ROM
---
Type
RO
Default
0h
1
---
PS, RO
*
0
---
PS, RO
*
7.3.2
Description
RESERVED
Write as 0h, ignore when read
BIST_1
Top-Memory BIST Status
0: Pass
1: Fail
BIST_0
Packet-Memory BIST Status
0: Pass
1: Fail
Switch Reset Register (211h)
PHY_ADR
10h
REG_ADR
11h
ABS_ADR
211h
Bit
15:3
ROM
---
Type
RO
Default
0h
2
---
P, RW
0b
1
---
P, RW
0b
0
---
P, RW
0b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0h, ignore when read
PD_ANLG
Power down all analog PHY
RST_ANLG
Analog PHY Core Reset
Auto clear after 10us
RST_SW
Switch Core Reset
Auto clear after 10us
38
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.3
Switch Control Register (212h)
PHY_ADR
10h
REG_ADR
12h
ABS_ADR
212h
Bit
15:6
ROM
---
Type
RO
Default
0h
5
12h.[5]
PSE,RW
0b
4:3
---
RO
00b
2
12h.[2]
PSE,RW
0b
1:0
---
RO
00b
7.3.4
Description
RESERVED
Write as 0h, ignore when read
FDX_FLOW
Flow Control Option
When set In full duplex mode, if link partner’s flow control capability is
disabled, the flow control of DM8603 corresponding port is also
disabled. When this is “0”, the flow control is controlled by REG
08~0Ah.11h.[4].
RESERVED
Write as 00b, ignore when read
DIS_CRCC
CRC Checking Disable
0: CRC checking is enabled
1: CRC checking is disabled
RESERVED
Write as 00b, ignore when read
Mirror Control Register (213h)
PHY_ADR
10h
REG_ADR
13h
ABS_ADR
213h
Bit
15:11
ROM
---
Type
RO
Default
0h
10
13h.[10]
PSE, RW
0b
9:8
---
RO
00b
7
13h.[7]
PSE, RW
0b
6
13h.[6]
PSE, RW
0b
5
---
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
0b
Description
RESERVED
Write as 0h, ignore when read
MIRR_PAIR
Mirror RX/TX Pair Mode Enable
0: Disable (default)
1: Enable
RESERVED
Write as 00b, ignore when read
STAG_TXE
Special Tag Transmit Enable
0: Doesn't insert the Special Tag for outgoing packets
1: Identifies the Special Tag for outgoing packets
STAG_RXE
Special Tag Receive Enable
0: Doesn't identify the Special Tag for incoming packets
1: Identifies the Special Tag for incoming packets
RESERVED
Write as 0b, ignore when read
39
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
4:3
13h.[4:3]
PSE, RW
00b
2:0
---
RO
000b
7.3.5
Special Tag Ether-Type Register (214h)
PHY_ADR
10h
Bit
15:0
7.3.6
SNF_PORT[1 :0]
Sniffer Port Number
00: Sniffer Port is Port 0
01: Sniffer Port is Port 1
10: Sniffer Port is Port 2
11: Reserved
RESERVED
Write as 000b, ignore when read
REG_ADR
14h
ROM
14h
Type
PSE,RW
ABS_ADR
214h
Default
8606h
Description
STAG_ETYPE[15:0]
Special Tag Ether-Type
Global Learning & Aging Control Register (215h)
PHY_ADR
10h
REG_ADR
15h
ABS_ADR
215h
Bit
15:6
ROM
---
Type
RO
Default
0h
5
15h.[5]
PSE,RW
0b
4
15h.[4]
PSE,RW
0b
3:2
---
RO
00b
1:0
15h.[1:0]
PSE,RW
00b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0h, ignore when read
LRN_PAUSE
Learn PAUSE Frame
0: Disable (default)
1: Enable
LRN_VLAN
Address Learning Consider VLAN Member
0: Address learning despite VLAN member (default)
1: Address learning is disable, if incoming port doesn't exist in its
member set.
RESERVED
Write as 00b, ignore when read
AGE_TIME[1:0]
Aging Time Value
00: 512 sec
01: 256 sec
10: 128 sec
11: 64 sec
40
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.7
VLAN Priority Map Register (217h)
PHY_ADR
10h
REG_ADR
17h
ABS_ADR
217h
Bit
15:14
ROM
1Ch.[15:14]
Type
PSE,RW
Default
11b
13:12
1Ch.[13:12]
PSE,RW
11b
11:10
1Ch.[11:10]
PSE,RW
10b
9:8
1Ch.[9:8]
PSE,RW
10b
7:6
1Ch.[7:6]
PSE,RW
01b
5:4
1Ch.[5:4]
PSE,RW
01b
3:2
1Ch.[3:2]
PSE,RW
00b
1:0
1Ch.[1:0]
PSE,RW
00b
7.3.8
Description
VLAN_PM7[1:0]
VLAN tag priority value = 07h
VLAN_PM6[1:0]
VLAN tag priority value = 06h
VLAN_PM5[1:0]
VLAN tag priority value = 05h
VLAN_PM4[1:0]
VLAN tag priority value = 04h
VLAN_PM3[1:0]
VLAN tag priority value = 03h
VLAN_PM2[1:0]
VLAN tag priority value = 02h
VLAN_PM1[1:0]
VLAN tag priority value = 01h
VLAN_PM0[1:0]
VLAN tag priority value = 00h
TOS Priority Map Register 1 (218h)
PHY_ADR
10h
REG_ADR
18h
ABS_ADR
218h
Bit
15:14
ROM
1Dh.[15:14]
Type
PSE,RW
Default
11b
13:12
1Dh.[13:12]
PSE,RW
11b
11:10
1Dh.[11:10]
PSE,RW
10b
9:8
1Dh.[9:8]
PSE,RW
10b
7:6
1Dh.[7:6]
PSE,RW
01b
5:4
1Dh.[5:4]
PSE,RW
01b
3:2
1Dh.[3:2]
PSE,RW
00b
1:0
1Dh.[1:0]
PSE,RW
00b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
TOS_PM07[1:0]
TOS value = 07h
TOS_PM06[1:0]
TOS value = 06h
TOS_PM05[1:0]
TOS value = 05h
TOS_PM04[1:0]
TOS value = 04h
TOS_PM03[1:0]
TOS value = 03h
TOS_PM02[1:0]
TOS value = 02h
TOS_PM01[1:0]
TOS value = 01h
TOS_PM00[1:0]
TOS value = 00h
41
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.9
TOS Priority Map Register 2 (219h)
PHY_ADR
10h
REG_ADR
19h
ABS_ADR
219h
Bit
15:14
ROM
1Eh.[15:14]
Type
PSE,RW
Default
00b
13:12
1Eh.[13:12]
PSE,RW
00b
11:10
1Eh.[11:10]
PSE,RW
00b
9:8
1Eh.[9:8]
PSE,RW
00b
7:6
1Eh.[7:6]
PSE,RW
00b
5:4
1Eh.[5:4]
PSE,RW
00b
3:2
1Eh.[3:2]
PSE,RW
00b
1:0
1Eh.[1:0]
PSE,RW
00b
Description
TOS_PM0F[1:0]
TOS value = 0Fh
TOS_PM0E[1:0]
TOS value = 0Eh
TOS_PM0D[1:0]
TOS value = 0Dh
TOS_PM0C[1:0]
TOS value = 0Ch
TOS_PM0B[1:0]
TOS value = 0Bh
TOS_PM0A[1:0]
TOS value = 0Ah
TOS_PM09[1:0]
TOS value = 09h
TOS_PM08[1:0]
TOS value = 08h
7.3.10 TOS Priority Map Register 3 (21Ah)
PHY_ADR
10h
REG_ADR
1Ah
ABS_ADR
21Ah
Bit
15:14
ROM
1Fh.[15:14]
Type
PSE,RW
Default
01b
13:12
1Fh.[13:12]
PSE,RW
01b
11:10
1Fh.[11:10]
PSE,RW
01b
9:8
1Fh.[9:8]
PSE,RW
01b
7:6
1Fh.[7:6]
PSE,RW
01b
5:4
1Fh.[5:4]
PSE,RW
01b
3:2
1Fh.[3:2]
PSE,RW
01b
1:0
1Fh.[1:0]
PSE,RW
01b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
TOS_PM17[1:0]
TOS value = 17h
TOS_PM16[1:0]
TOS value = 16h
TOS_PM15[1:0]
TOS value = 15h
TOS_PM14[1:0]
TOS value = 14h
TOS_PM13[1:0]
TOS value = 13h
TOS_PM12[1:0]
TOS value = 12h
TOS_PM11[1:0]
TOS value = 11h
TOS_PM10[1:0]
TOS value = 10h
42
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.11 TOS Priority Map Register 4 (21Bh)
PHY_ADR
10h
REG_ADR
1Bh
ABS_ADR
21Bh
Bit
15:14
ROM
20h.[15:14]
Type
PSE,RW
Default
01b
13:12
20h.[13:12]
PSE,RW
01b
11:10
20h.[11:10]
PSE,RW
01b
9:8
20h.[9:8]
PSE,RW
01b
7:6
20h.[7:6]
PSE,RW
01b
5:4
20h.[5:4]
PSE,RW
01b
3:2
20h.[3:2]
PSE,RW
01b
1:0
20h. [1:0]
PSE,RW
01b
Description
TOS_PM1F[1:0]
TOS value = 1Fh
TOS_PM1E[1:0]
TOS value = 1Eh
TOS_PM1D[1:0]
TOS value = 1Dh
TOS_PM1C[1:0]
TOS value = 1Ch
TOS_PM1B[1:0]
TOS value = 1Bh
TOS_PM1A[1:0]
TOS value = 1Ah
TOS_PM19[1:0]
TOS value = 19h
TOS_PM18[1:0]
TOS value = 18h
7.3.12 TOS Priority Map Register 5 (21Ch)
PHY_ADR
10h
REG_ADR
1Ch
ABS_ADR
21Ch
Bit
15:14
ROM
21h.[15:14]
Type
PSE,RW
Default
10b
13:12
21h.[13:12]
PSE,RW
10b
11:10
21h.[11:10]
PSE,RW
10b
9:8
21h.[9:8]
PSE,RW
10b
7:6
21h.[7:6]
PSE,RW
10b
5:4
21h.[5:4]
PSE,RW
10b
3:2
21h.[3:2]
PSE,RW
10b
1:0
21h.[1:0]
PSE,RW
10b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
TOS_PM27[1:0]
TOS value = 27h
TOS_PM26[1:0]
TOS value = 26h
TOS_PM25[1:0]
TOS value = 25h
TOS_PM24[1:0]
TOS value = 24h
TOS_PM23[1:0]
TOS value = 23h
TOS_PM22[1:0]
TOS value = 22h
TOS_PM21[1:0]
TOS value = 21h
TOS_PM20[1:0]
TOS value = 20h
43
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.13 TOS Priority Map Register 6 (21Dh)
PHY_ADR
10h
REG_ADR
1Dh
ABS_ADR
21Dh
Bit
15:14
ROM
22h.[15:14]
Type
PSE,RW
Default
10b
13:12
22h.[13:12]
PSE,RW
10b
11:10
22h.[11:10]
PSE,RW
10b
9:8
22h.[9:8]
PSE,RW
10b
7:6
22h.[7:6]
PSE,RW
10b
5:4
22h.[5:4]
PSE,RW
10b
3:2
22h.[3:2]
PSE,RW
10b
1:0
22h.[1:0]
PSE,RW
10b
Description
TOS_PM2F[1:0]
TOS value = 2Fh
TOS_PM2E[1:0]
TOS value = 2Eh
TOS_PM2D[1:0]
TOS value = 2Dh
TOS_PM2C[1:0]
TOS value = 2Ch
TOS_PM2B[1:0]
TOS value = 2Bh
TOS_PM2A[1:0]
TOS value = 2Ah
TOS_PM29[1:0]
TOS value = 29h
TOS_PM28[1:0]
TOS value = 28h
7.3.14 TOS Priority Map Register 7 (21Eh)
PHY_ADR
10h
REG_ADR
1Eh
ABS_ADR
21Eh
Bit
15:14
ROM
23h.[15:14]
Type
PSE,RW
Default
11b
13:12
23h.[13:12]
PSE,RW
11b
11:10
23h.[11:10]
PSE,RW
11b
9:8
23h.[9:8]
PSE,RW
11b
7:6
23h.[7:6]
PSE,RW
11b
5:4
23h.[5:4]
PSE,RW
11b
3:2
23h.[3:2]
PSE,RW
11b
1:0
23h.[1:0]
PSE,RW
11b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
TOS_PM37[1:0]
TOS value = 37h
TOS_PM36[1:0]
TOS value = 36h
TOS_PM35[1:0]
TOS value = 35h
TOS_PM34[1:0]
TOS value = 34h
TOS_PM33[1:0]
TOS value = 33h
TOS_PM32[1:0]
TOS value = 32h
TOS_PM31[1:0]
TOS value = 31h
TOS_PM30[1:0]
TOS value = 30h
44
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.15 TOS Priority Map Register 8 (21Fh)
PHY_ADR
10h
REG_ADR
1Fh
ABS_ADR
21Fh
Bit
15:14
ROM
24h.[15:14]
Type
PSE,RW
Default
11b
13:12
24h.[13:12]
PSE,RW
11b
11:10
24h.[11:10]
PSE,RW
11b
9:8
24h.[9:8]
PSE,RW
11b
7:6
24h.[7:6]
PSE,RW
11b
5:4
24h.[5:4]
PSE,RW
11b
3:2
24h.[3:2]
PSE,RW
11b
1:0
24h.[1:0]
PSE,RW
11b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
TOS_PM3F[1:0]
TOS value = 3Fh
TOS_PM3E[1:0]
TOS value = 3Eh
TOS_PM3D[1:0]
TOS value = 3Dh
TOS_PM3C[1:0]
TOS value = 3Ch
TOS_PM3B[1:0]
TOS value = 3Bh
TOS_PM3A[1:0]
TOS value = 3Ah
TOS_PM39[1:0]
TOS value = 39h
TOS_PM38[1:0]
TOS value = 38h
45
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.16 MIB Counter Disable Register (230h)
PHY_ADR
11h
REG_ADR
10h
ABS_ADR
230h
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
16h.[2:0]
PSE,RW
000b
Description
RESERVED
Write as 0h, ignore when read
MIB_DIS[2:0]
Per-Port MIB Counter Disable
[2] Port2 MIB counter disabled
[1] Port1 MIB counter disabled
[0] Port0 MIB counter disabled
0: Enable
1: Disable
7.3.17 MIB Counter Control Register (231h)
PHY_ADR
11h
REG_ADR
11h
ABS_ADR
231h
Bit
15
ROM
---
Type
PS,RO
Default
0b
14:10
---
RO
0h
9:8
---
PS,RW
00b
7
---
RO
0b
6:5
---
PS,RW
00b
4:0
---
PS,RW
00000b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
MIB_READY
Counter Data is Ready
RESERVED
Write as 0h, ignore when read
MIB_CMD[1:0]
Command
00: Clear after read
01: Read only
10: Clear specified port
11: Clear all ports
RESERVED
Write as 0b, ignore when read
MIB_PORT[1:0]
Port Index (0~2)
MIB_OFFSET[4:0]
Counter Offset (0~9)
46
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.18 MIB Counter Data Register 1 (232h)
PHY_ADR
11h
Bit
15:0
REG_ADR
12h
ROM
---
Type
PS,RW
ABS_ADR
232h
Default
0h
Description
MIB_DL[15:0]
Counter Data Low Byte (Bit 15:00)
7.3.19 MIB Counter Data Register 2 (233h)
PHY_ADR
11h
Bit
15:0
REG_ADR
13h
ROM
---
Type
PS,RW
ABS_ADR
233h
Default
0h
Description
MIB_DH[15:0]
Counter Data High Byte(Bit 31:16)
MIB Counter (OFFSET 00h): RX Byte Counter Register
MIB Counter (OFFSET 01h): RX Uni-cast Packet Counter Register
MIB Counter (OFFSET 02h): RX Multi-cast Packet Counter Register
MIB Counter (OFFSET 03h): RX Discard Packet Counter Register
MIB Counter (OFFSET 04h): RX Error Packet Counter Register
MIB Counter (OFFSET 05h): TX Byte Counter Register
MIB Counter (OFFSET 06h): TX Uni-cast Packet Counter Register
MIB Counter (OFFSET 07h): TX Multi-cast Packet Counter Register
MIB Counter (OFFSET 08h): TX Discard Packet Counter Register
MIB Counter (OFFSET 09h): TX Error Packet Counter Register
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
47
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.20 VLAN Mode & Rule Control Register (23Eh)
PHY_ADR
11h
REG_ADR
1Eh
ABS_ADR
23Eh
Bit
15
ROM
31h.[15]
Type
PSE,RW
Default
0b
14
31h.[14]
PSE,RW
0b
13:9
---
RO
0h
8
31h.[8]
PSE,RW
0b
7
31h.[7]
PSE,RW
0b
6
---
RO
0b
5
31h.[5]
PSE,RW
0b
4
31h.[4]
PSE,RW
0b
3
31h.[3]
PSE,RW
0b
2
31h.[2]
PSE,RW
0b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
FIR_VIDFFF
Drop Packet with VID==0xFFF Enable
Drop incoming packet, if its VID is equal to 0xFFF
0: Disable
1: Enable
FIR_CFI
Drop Packet with Nonzero CFI Enable
Drop incoming packet, if the CFI field is not equal to zero.
0: Disable
1: Enable
RESERVED
Write as 0h, ignore when read
QINQ_EN
VLAN Stacking Enable (QinQ)
0: Disable
1: Enable
TOS6
Full IP ToS Field for Priority Queue
0: check most significant 3-bit only of TOS
1: check most significant 6-bit of TOS
RESERVED
Write as 0b, ignore when read
UCROSS
Unicast Packet Can Across VLAN Boundary
0: Unicast packet obeys VLAN rule
1: Unicast packet can across VLAN boundary
VIDFFF
Replace VID = 0xFFF
When receive a VLAN tagged packet and VID equals to “0xFFF”,
the outgoing packet's VID will be replaced by PVID.
0: Disable
1: Enable
VID1
When receive a VLAN tagged packet and VID equals to “0x001”, the
outgoing packet's VID will be replaced by PVID.
0: Disable
1: Enable
VID0
Replace VID = 0x000
When receive a VLAN tagged packet and VID equals to “0x000”, the
outgoing packet's VID will be replaced by PVID.
0: Disable
1: Enable
48
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
1
0
31h.[1]
31h.[0]
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
PSE,RW
PSE,RW
0b
0b
VLAN_RPRI
Replace VLAN Priority
Replace the received
08h/09h/0Ah.16h.[15:13]
0: Disable
1: Enable
VLAN Mode Selection
0: Port-based VLAN
1: Tag-based VLAN
packet's
VLAN
priority
by
REG
49
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.21 VLAN Table Register 0 (270h)
PHY_ADR
13h
REG_ADR
10h
ABS_ADR
270h
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
43h.[2:0]
PSE,RW
111b
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB0[2:0]
VLAN Entry 0 VLAN Member
7.3.22 VLAN Table Register 1 (271h)
PHY_ADR
13h
REG_ADR
11h
ABS_ADR
271h
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
44h.[2:0]
PSE,RW
111b
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB1[2:0]
VLAN Entry 1 VLAN Member
7.3.23 VLAN Table Register 2 (272h)
PHY_ADR
13h
REG_ADR
12h
ABS_ADR
272h
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
45h.[2:0]
PSE,RW
111b
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB2[2:0]
VLAN Entry 2 VLAN Member
7.3.24 VLAN Table Register 3 (273h)
PHY_ADR
13h
REG_ADR
13h
ABS_ADR
273h
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
46h.[2:0]
PSE,RW
111b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB3[2:0]
VLAN Entry 3 VLAN Member
50
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.25 VLAN Table Register 4 (274h)
PHY_ADR
13h
REG_ADR
14h
ABS_ADR
274h
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
47h.[2:0]
PSE,RW
111b
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB4[2:0]
VLAN Entry 4 VLAN Member
7.3.26 VLAN Table Register 5 (275h)
PHY_ADR
13h
REG_ADR
15h
ABS_ADR
275h
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
48h.[2:0]
PSE,RW
111b
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB5[2:0]
VLAN Entry 5 VLAN Member
7.3.27 VLAN Table Register 6 (276h)
PHY_ADR
13h
REG_ADR
16h
ABS_ADR
276h
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
49h.[2:0]
PSE,RW
111b
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB6[2:0]
VLAN Entry 6 VLAN Member
7.3.28 VLAN Table Register 7 (277h)
PHY_ADR
13h
REG_ADR
17h
ABS_ADR
277h
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
4Ah.[2:0]
PSE,RW
111b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB7[2:0]
VLAN Entry 7 VLAN Member
51
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.29 VLAN Table Register 8 (278h)
PHY_ADR
13h
REG_ADR
18h
ABS_ADR
278h
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
4Bh.[2:0]
PSE,RW
111b
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB8[2:0]
VLAN Entry 8 VLAN Member
7.3.30 VLAN Table Register 9 (279h)
PHY_ADR
13h
REG_ADR
19h
ABS_ADR
279h
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
4Ch.[2:0]
PSE,RW
111b
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB9[2:0]
VLAN Entry 9 VLAN Member
7.3.31 VLAN Table Register 10 (27Ah)
PHY_ADR
13h
REG_ADR
1Ah
ABS_ADR
27Ah
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
4Dh.[2:0]
PSE,RW
111b
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB10[2:0]
VLAN Entry 10 VLAN Member
7.3.32 VLAN Table Register 11 (27Bh)
PHY_ADR
13h
REG_ADR
1Bh
ABS_ADR
27Bh
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
4Eh.[2:0]
PSE,RW
111b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB11[2:0]
VLAN Entry 11 VLAN Member
52
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.33 VLAN Table Register 12 (27Ch)
PHY_ADR
13h
REG_ADR
1Ch
ABS_ADR
27Ch
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
4Fh.[2:0]
PSE,RW
111b
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB12[2:0]
VLAN Entry 12 VLAN Member
7.3.34 VLAN Table Register 13 (27Dh)
PHY_ADR
13h
REG_ADR
1Ch
ABS_ADR
27Dh
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
50h.[2:0]
PSE,RW
111b
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB13[2:0]
VLAN Entry 13 VLAN Member
7.3.35 VLAN Table Register 14 (27Eh)
PHY_ADR
13h
REG_ADR
1Eh
ABS_ADR
27Eh
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
51h.[2:0]
PSE,RW
111b
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB14[2:0]
VLAN Entry 14 VLAN Member
7.3.36 VLAN Table Register 15 (27Fh)
PHY_ADR
13h
REG_ADR
1Fh
ABS_ADR
27Fh
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
52h.[2:0]
PSE,RW
111b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0h, ignore when read
VTAB_VMB15[2:0]
VLAN Entry 15 VLAN Member
53
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.37 STP Control Register (292h)
PHY_ADR
14h
REG_ADR
12h
ABS_ADR
292h
Bit
15:1
ROM
---
Type
RO
Default
0h
0
---
PS,RW
0b
Description
RESERVED
Write as 0h, ignore when read
STPEN
Spanning Tree Protocol Enable
0: Disable
1: Enable
7.3.38 Snooping Control Register 1 (29Bh)
PHY_ADR
14h
REG_ADR
1Bh
ABS_ADR
29Bh
Bit
15:11
ROM
---
Type
RO
Default
0h
10:8
17h.[10:8]
PSE,RW
111b
7
17h. [8]
PSE,RW
0b
6
---
RO
0b
5:4
17h. [5:4]
PSE,RW
00b
3:2
17h. [3:2]
PSE,RW
00b
1
17h. [1]
PSE,RW
0b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0h, ignore when read
RPP[2:0]
Router Port Portmap
Bit0: Port 0
Bit1: Port 1
Bit2: Port 2
UD_RP
User-defined Router Port Enable
0: Router port is manipulated by hardware
1: Router port is user-defined
RESERVED
Write as 0b, ignore when read
MCP_H[1:0]
Multicast Control Packet Handle
00: Forward Membership Reports to router port. General Query to
all port.
01: Mirror to CPU (Forward to CPU also)
10: Trap to CPU (Forward to CPU only)
11: Flood
UMD_CTRL[1:0]
Unregistered Multicast Data Packet Handle
00: As normal multicast packets
01: Dropped
10: Trap to CPU
11: Flood except CPU
MLDS_EN
MLD Snooping Enable
0: Disable
1: Enable
54
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
0
17h. [0]
PSE,RW
0b
HIGS_EN
Hardware IGMP Snooping Enable
0: Disable
1: Enable
7.3.39 Snooping Control Register 2 (29Ch)
PHY_ADR
14h
REG_ADR
1Ch
ABS_ADR
29Ch
Bit
15:13
ROM
---
Type
RO
Default
000b
12
18h.[12]
PSE,RW
0b
11:10
18h. [11:10]
PSE,RW
10b
9:8
18h. [9:8]
PSE,RW
01b
7:0
18h. [7:0]
PSE,RW
7Dh
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 000b, ignore when read
IGS_TODIS
IGMP Snooping Timeout Scheme Disable
0: Timeout is enabled
1: Timeout is disabled
RP_TV[1:0]
Router Port Timeout Value Selection
00: 1 times of Query Interval
01: 2 times of Query Interval
10: 3 times of Query Interval (default)
11: 4 times of Query Interval
IGS_RV[1:0]
Robustness Variable
00: 1 times
01: 2 times (default)
10: 3 times
11: 4 times
IGS_QI[7:0]
Query Interval
Default = 8’h7D (sec)
55
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.40 Address Table Control & Status Register (2B0h)
PHY_ADR
15h
REG_ADR
10h
ABS_ADR
2B0h
Bit
15
ROM
---
Type
PS,RO
Default
0b
14:13
---
PS,RW
00b
12:5
---
RO
0h
4:2
---
PS,RW
000b
1:0
---
PS,RW
00b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
ATB_S
Address Table Access is Busy
0: Available (Access process is completed)
1: Busy (Access process is operating)
ATB_CR[1:0]
Address Table Command Result
00: Command OK, entry doesn't exist
a. Create an new entry
(Write Command)
b. Do noting
(Delete Command)
c. not found
(Search Command)
d. Entry is invalid
(Read Command)
01: Command OK, entry is exist
a. Overwrite entry
(Write Command)
b. Delete entry
(Delete Command)
c. Entry found
(Search Command)
d. Entry is valid
(Read Command)
1X: Command Error
RESERVED
Write as 0h, ignore when read
ATB_CMD[2:0]
Command
000: Read a entry with sequence number of
address table
001: Write a entry with MAC address
010: Delete a entry with MAC address
011: Search a entry with MAC address
ATB_IDX[1:0]
Address Table Index
00: Unicast Address Table
01: Multicast Address Table
10: IGMP Table
11: Reserved
56
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.41 Address Table Data Register 1 (2B1h)
PHY_ADR
15h
REG_ADR
11h
ABS_ADR
2B1h
Bit
15:3
ROM
---
Type
RO
Default
0h
2:0
---
PS,RW
000b
Description
RESERVED
Write as 0h, ignore when read
ATB_PORT[2:0]
Address Table Port Number or Port Map
7.3.42 Address Table Data Register 2 (2B2h)
PHY_ADR
15h
Bit
15:0
REG_ADR
12h
ROM
---
Type
PS,RW
ABS_ADR
2B2h
Default
0h
Description
ATB_DW1[15:0]
Address Table Data Word 1
7.3.43 Address Table Data Register 3 (2B3h)
PHY_ADR
15h
Bit
15:0
REG_ADR
13h
ROM
---
Type
PS,RW
ABS_ADR
2B3h
Default
0h
Description
ATB_DW2[15:0]
Address Table Data Word 2
7.3.44 Address Table Data Register 4 (2B4h)
PHY_ADR
15h
Bit
15:0
REG_ADR
14h
ROM
---
Type
PS,RW
ABS_ADR
2B4h
Default
0h
Description
ATB_DW3[15:0]
Address Table Data Word 3
7.3.45 Address Table Data 4 Register (2B5h)
PHY_ADR
15h
Bit
15:0
REG_ADR
15h
ROM
---
Type
PS,RW
ABS_ADR
2B5h
Default
0h
Description
ATB_DW4[15:0]
Address Table Data Word 4
7.3.46 Vendor ID Register (310h)
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
57
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
PHY_ADR
18h
Bit
15:0
ROM
04H.[15:0]
REG_ADR
10h
Type
PE,RO
ABS_ADR
310h
Default
0A46h
Description
VID[15:0]
Vendor ID
7.3.47 Product ID Register (311h)
PHY_ADR
18h
Bit
15:0
ROM
05h.[15:0]
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
REG_ADR
11h
Type
PE,RO
ABS_ADR
311h
Default
8603h
Description
PID[15:0]
Product ID
58
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.48 Port 2 MAC Control Register (315h)
PHY_ADR
18h
REG_ADR
15h
ABS_ADR
315h
Bit
15:10
ROM
---
Type
RO
Default
0h
9:8
0Dh.[9:8]
PE,RW
01b
7:4
---
RO
0h
3
0Dh. [3]
PSET,RW
*
2
0Dh. [2]
PSE,RW
0b
1
0Dh. [1]
PSE,RW
0b
0
0Dh. [0]
PSET,RW
*
Description
RESERVED
Write as 0h, ignore when read
P2_CURR[9:8]
Port 2 TXD/TXE Current Driving/Sinking Capability
00: 2mA
01: 4mA (default)
10: 6mA
11: 8mA
RESERVED
Write as 0h, ignore when read
P2_MODE
Port2 status in auto-polling mode for MII/RevMII/RMII
0: Auto-polling mode
1: Force mode
* The default value comes from the strap pin (P2_TXE) and
EEPROM loading sequentially:
P2_TXE
0:
pull-low
1:
pull-high
P2_LINK
When Port2 in force mode for MII/RevMII/RMII
0: Link ON
1: Link OFF
P2_DPX
When Port2 in force mode for MII/RevMII/RMII
0: Full-duplex mode
1: Half-duplex mode
P2_SPEED
When Port2 in force mode for MII/RevMII/RMII
0: 100M mode
1: 10M mode
* The default value comes from the strap pins (P2_TXE, EECK) and
EEPROM loading sequentially:
P2_TXE
EECK
0:
pull-low
don't care
0:
pull-high
pull-high
1:
pull-high
pull-low
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
59
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.49 EEPROM Control & Address Register (31Ah)
PHY_ADR
18h
REG_ADR
1Ah
ABS_ADR
31Ah
Bit
15:8
ROM
---
Type
PS,RW
Default
0h
7
---
RO
0b
6
---
P,RW
1b
5
---
PS,RW
0b
4
---
PS,RW
0b
3
---
PS,RW
0b
2
---
PS,RW
0b
1
---
PS,RW
0b
0
---
PS,RO
0b
Description
EROA[7:0]
EEPROM Word Address
RESERVED
Write as 0b, ignore when read
EETYPE
EEPROM Type
0: 93C46
1: 93C56/66(Default)
REEP
Reload EEPROM.
User needs to clear it up after the operation completes
WEP
Write EEPROM Enable
0: EEPROM write operation is disabled
1: EEPROM write operation is enabled
EPOS
External PHY Operation Select
0: Select EEPROM
1: Select External PHY
ERPRR
EEPROM Read Command
User needs to clear it up after the operation completes
ERPRW
EEPROM Write Command
User needs to clear it up after the operation completes
ERRE
EEPROM or PHY Access Status
0: Idle
1: EEPROM or PHY access is in progress
7.3.50 EEPROM Data Register (31Bh)
PHY_ADR
18h
Bit
15:0
REG_ADR
1Bh
ROM
---
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Type
PS,RW
ABS_ADR
31Bh
Default
0h
Description
EE_DATA[15:0]
EEPROM 16bit Data
60
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.51 Strap Pin Control & Status Register (31Ch)
PHY_ADR
18h
REG_ADR
1Ch
ABS_ADR
31Ch
Bit
15
ROM
---
Type
PT,RO
Default
*
14
---
PT,RO
*
13
---
PT,RO
*
12
---
RW
---
11
---
RO
---
10
---
PT,RO
*
9
---
PT,RO
*
8:6
---
RO
---
5
---
PT,RW
*
4
---
PT,RW
*
3
---
PT,RW
*
2
---
PT,RW
*
1:0
---
RW
---
Description
H_TEST3
hard-strap TEST3
* The default value depend on the pin, TEST3
H_TEST2
hard-strap TEST2
* The default value depend on the pin, TEST2
H_TEST1
hard-strap TEST1
* The default value depend on the pin, TEST1
RESERVED
Write as 0b, ignore when read
RESERVED
Write as 0b, ignore when read
H_EECS
hard-strap EECS
* The default value depend on the strap pin, EECS
H_EECK
hard-strap EECK
* The default value depend on the strap pin, EECK
RESERVED
Write as 000b, ignore when read
HS_TXER2
hard-strap/soft-strap P2_TXER
* The default value depend on the strap pin, P2_TXER
HS_TXE2
hard-strap/soft-strap P2_TXE
* The default value depend on the strap pin, P2_TXE
HS_TXD23
hard-strap/soft-strap P2_TXD3
* The default value depend on the strap pin, P2_TXD3
HS_TXD22
hard-strap/soft-strap P2_TXD2
* The default value depend on the strap pin, P2_TXD2
RESERVED
Write as 0b, ignore when read
Note
1. The default value of Hard-strap in REG 18h.1Ch depends on each pins' strap setting when
power-on reset, refer to the section 5.8 Strap Pins Table for more detail.
2. The Hard-strap's setting can be overridden via Soft-strap (REG 18h.1Ch.[5:0]). The updated setting will
be applied until software reset is asserted (write REG 10h.11h.[0] to 1).
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
61
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.52 SMI Bus Error Check Register (339h)
PHY_ADR
19h
REG_ADR
19h
ABS_ADR
339h
Bit
15:9
ROM
--
Type
RO
Default
0h
8
---
PS,RO
0b
7:0
---
PS,RW
0h
Description
RESERVED
Write as 0h, ignore when read
SMI_ERR
SMI Bus Error Status(Read only)
0: Checksum check correct
1: Checksum check error
SMI_CSUM[7:0]
SMI Bus Command Checksum
Calculated checksum value by HW
7.3.53 SMI Bus Control Register (33Ah)
PHY_ADR
19h
REG_ADR
1Ah
ABS_ADR
33Ah
Bit
15:1
ROM
---
Type
RO
Default
0h
0
---
P,RW
0b
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
RESERVED
Write as 0h, ignore when read
SMI_ECE
SMI Bus Error Check Enable
0: Disable
1: Enable
62
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
7.3.54 PHY Control Register (33Eh)
PHY_ADR
19h
REG_ADR
1Eh
ABS_ADR
33Eh
Bit
15
ROM
07h.[15]
Type
PSE,RW
Default
0b
14
07h. [14]
PSE,RW
0b
13:9
---
RO
0h
8
07h. [8]
PSET,RW
0b
7:4
---
RO
0h
3:0
---
PS,RW
3h
Description
MDIX_DIS_P0
Port0 Auto-MDIX Control
0: Auto_MDIX Enable
1: Auto_MDIX Disable
MDIX_DIS_P1
Port1 Auto-MDIX Control
0: Auto_MDIX Enable
1: Auto_MDIX Disable
RESERVED
Write as 0h, ignore when read
PHY_LFP_EN
PHY LFP Control
0: PHY LFP Disable
1: PHY LFP Enable
RESERVED
Write as 0h, ignore when read
I_TUNE_TX[3:0]
TX Operation Current
To tune the TX operation current
Note:
There are two method to control Auto-MDIX ability on each port, Switch REG 19h.1Eh.[15:14] and per-port's
PHY REG 02h/03h.14h.[4]. For instance, we can control port 0's Auto-MDIX ability by:
Auto-MDIX
Enable
Disable
Disable
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Switch REG 19h.1Eh.[15]
0
1
Don't care
Port 0's PHY REG 02h.14h.[4]
0
Don't care
1
63
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
8. EEPROM Format
Name
Signature
Word
00h
RESERVED
01h~02h
Load Control 0
03h
Vendor ID
04h
Product ID
05h
RESERVED
06h
PHY control
07h
RESERVED
08h
PHY Vendor ID
09h
PHY Device ID
0Ah
RESERVED
0Bh~0Ch
Port 2 MAC Control
0Dh
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Description
When this word is 1049h, the EEPROM data is valid and can be
loaded to DM8603.
Reserved
Set to “0000h” in application
Bit [01:00]
= Load enable of word 04h & 05h
01b: Enable, 00b/10b/11b: Disable
Bit [03:02] = Reserved
Set to “00b” or “11b” in application
Bit [05:04] = Load enable of word 07h
01b: Enable, 00b/10b/11b: Disable
Bit [07:06] = Load enable of word 09h & 0Ah
01b: Enable, 00b/10b/11b: Disable
Bit [09:08] = Load enable of word 0Dh
01b: Enable, 00b/10b/11b: Disable
Bit [11:10] = Reserved
Set to “00b” or “11b” in application
Bit [13:12] = Reserved
Set to “00b” or “11b” in application
Bit [15:14] = Reserved
Set to “00b” or “11b” in application
2 byte vendor ID (Default: 0A46h)
If bit [1:0] of word 03h is “01b”,
Bit [15:0] will be loaded to REG 18h.10h
2 byte product ID (Default: 8603h)
If bit [1:0] of word 03h is “01b”,
Bit [15:0] will be loaded to REG 18h.11h
Reserved
Set to “0000h” in application
PHY Auto-MDIX Control
If bit [5:4] of word 03h is “01b”,
Bit [07:00] = Reserved
Bit [08]
= PHY LFP control
1: ON, 0: OFF
Bit [13:09] = Reserved
Bit [14]
= Port 1 AUTO-MDIX control
1: ON, 0: OFF(default ON)
Bit [15]
= Port 0 AUTO-MDIX control
1: ON 0: OFF(default ON)
Reserved
Set to “0000h” in application
2 byte PHY ID1
If bit [7:6] of word 03h is “01b”,
Bit[15:0] will be loaded to PHY Vendor ID.
2 byte PHY ID2
If bit [7:6] of word 03h is “01b”,
Bit[15:0] will be loaded to PHY Device ID.
Reserved
Set to “0000h” in application
Port 2 MAC Control
64
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
Load Control 1
0Eh
Load Control 2
0Fh
RESERVED
10h~11h
Switch Control
12h
Mirror Control
13h
Special Tag Ether-Type
14h
Global Learning &
Aging Control
MIB Counter Disable
15h
Snoop Ctrl 0
17h
Snoop Ctrl 1
18h
RESERVED
19h~1Bh
VLAN Priority Map
Register
1Ch
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
16h
If bit [9:8] of word 03h is “01b”,
Bit [15:0] will be loaded to REG 18h.15h
Bit [01:00] = Load enable of word 12h ~ 16h
01b: Enable, 00b/10b/11b: Disable
Bit [03:02] = Load enable of word 17h &18h
01b: Enable, 00b/10b/11b: Disable
Bit [05:04] = Load enable of word 1Ch ~ 24h
01b: Enable, 00b/10b/11b: Disable
Bit [07:06] = Reserved
Set to “00b” or “11b” in application
Bit [09:08] = Load enable of word 31h ~ 52h
01b: Enable, 00b/10b/11b: Disable
Bit [11:10] = Reserved
Set to “00b” or “11b” in application
Bit [13:12] = Reserved
Set to “00b” or “11b” in application
Bit [15:14] = Reserved
Set to “00b” or “11b” in application
Bit [01:00] = Load enable of word 80h ~ 8Ah
01b: Enable, 00b/10b/11b: Disable
Bit [03:02] = Load enable of word 90h ~ 9Ah
01b: Enable, 00b/10b/11b: Disable
Bit [05:04] = Load enable of word A0h ~ AAh
01b: Enable, 00b/10b/11b: Disable
Bit [07:06] = Reserved
Set to “00b” or “11b” in application
Bit [09:08] = Reserved
Set to “00b” or “11b” in application
Bit [11:10] = Reserved
Set to “00b” or “11b” in application
Bit [13:12] = Reserved
Set to “00b” or “11b in application
Bit [15:14] = Reserved
Set to “00b” or “11b” in application
Reserved
Set to “0000h” in application
If bit [01:00] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.12h
If bit [01:00] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.13h
If bit [01:00] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.14h
If bit [01:00] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.15h
If bit [01:00] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 11h.10h
If bit [03:02] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 14h.1Bh
If bit [03:02] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 14h.1Ch
Reserved
Set to “0000h” in application
If bit [05:04] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.17h
65
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
TOS Priority Map 0
1Dh
TOS Priority Map 1
1Eh
TOS Priority Map 2
1Fh
TOS Priority Map 3
20h
TOS Priority Map 4
21h
TOS Priority Map 5
22h
TOS Priority Map 6
23h
TOS Priority Map 7
24h
RESERVED
25h~30h
VLAN Mode & Rule
Control
RESERVED
31h
VLAN Table MEMBER_0H
VLAN Table MEMBER_1H
VLAN Table MEMBER_2H
VLAN Table MEMBER_3H
VLAN Table MEMBER_4H
VLAN Table MEMBER_5H
VLAN Table MEMBER_6H
VLAN Table MEMBER_7H
VLAN Table MEMBER_8H
VLAN Table MEMBER_9H
VLAN Table MEMBER_AH
VLAN Table MEMBER_BH
VLAN Table MEMBER_CH
VLAN Table MEMBER_DH
VLAN Table MEMBER_EH
VLAN Table Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
32h~42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
If bit [05:04] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.18h
If bit [05:04] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.19h
If bit [05:04] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.1Ah
If bit [05:04] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.1Bh
If bit [05:04] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.1Ch
If bit [05:04] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.1Dh
If bit [05:04] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.1Eh
If bit [05:04] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 10h.1Fh
Reserved
Set to “0000h” in application
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 11h.1Eh
Reserved
Set to “0000h” in application
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.10h
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.11h
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.12h
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.13h
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.14h
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.15h
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.16h
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.17h
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.18h
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.19h
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.1Ah
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.1Bh
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.1Ch
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.1Dh
If bit [09:08] of word 0Eh is “01b”,
Bit [15:00] will be loaded to REG 13h.1Eh
If bit [09:08] of word 0Eh is “01b”,
66
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
MEMBER_FH
RESERVED
53h~7Fh
P0 Basic Control 0
80h
P0 Basic Control 1
81h
P0 Block Control 0
82h
P0 Block Control 1
83h
P0 Bandwidth Control
84h
P0 VLAN Tag
Information
P0 Priority & VLAN
Control
RESERVED
85h
86h
P0 Advanced Control
88h
RESERVED
89h~8Ah
RESERVED
8Bh~8Fh
P1 Basic Control 0
90h
P1 Basic Control 1
91h
P1 Block Control 0
92h
P1 Block Control 1
93h
P1 Bandwidth Control
94h
P1 VLAN Tag
Information
P1 Priority & VLAN
Control
RESERVED
95h
96h
P1 Advanced Control
98h
RESERVED
99h~9Ah
RESERVED
9Bh~9Fh
P2 Basic Control 0
A0h
P2 Basic Control 1
A1h
P2 Block Control 0
A2h
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
87h
97h
Bit [15:00] will be loaded to REG 13h.1Fh
Reserved
Set to “0000h” in application
If bit [01:00] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 08h.11h
If bit [01:00] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 08h.12h
If bit [01:00] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 08h.13h
If bit [01:00] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 08h.14h
If bit [01:00] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 08h.15h
If bit [01:00] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 08h.16h
If bit [01:00] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 08h.17h
Reserved
Set to “0000h” in application
If bit [01:00] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 08h.19h
Reserved
Set to “0000h” in application
Reserved
Set to “0000h” in application
If bit [03:02] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 09h.11h
If bit [03:02] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 09h.12h
If bit [03:02] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 09h.13h
If bit [03:02] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 09h.14h
If bit [03:02] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 09h.15h
If bit [03:02] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 09h.16h
If bit [03:02] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 09h.17h
Reserved
Set to “0000h” in application
If bit [03:02] of word 0Fhis “01b”,
Bit [15:00] will be loaded to REG 09h.19h
Reserved
Set to “0000h” in application
Reserved
Set to “0000h” in application
If bit [05:04] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 0Ah.11h
If bit [05:04] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 0Ah.12h
If bit [05:04] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 0Ah.13h
67
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
P2 Block Control 1
A3h
P2 Bandwidth Control
A4h
P2 VLAN Tag
Information
P2 Priority & VLAN
Control
RESERVED
A5h
A6h
P2 Advanced Control
A8h
RESERVED
A9h~AAh
RESERVED
ABh~FFh
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
A7h
If bit [05:04] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 0Ah.14h
If bit [05:04] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 0Ah.15h
If bit [05:04] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 0Ah.16h
If bit [05:04] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 0Ah.17h
Reserved
Set to “0000h” in application
If bit [05:04] of word 0Fh is “01b”,
Bit [15:00] will be loaded to REG 0Ah.19h
Reserved
Set to “0000h” in application
Reserved
Set to “0000h” in application
68
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9. Functional Description
9.1
9.1.1
Host Serial Management Interface
Host SMI Frame Structure
Host SMI - Read Frame Structure
Host SMI - Write Frame Structure
The Host SMI consists of two pins, one is SMI_MDC and another is SMI_MDIO. User can access
DM8603’s EEPROM, PHY registers, MIB counters and Configuration registers through Host SMI. The format
is following. The <PHY Address> and <Register Address> fields of the frame are mapped to address of PHY
register and Switch register set of DM8603.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
69
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.1.2
Host SMI Bus Error Check Function
Because SMI bus tends to be interfered by noise on board-level. This function is used to check the
command validity to suppress the mistaken command. In write procedure, the written value in register will be
applied until the correct checksum is written (error proofing) and user can read status for validation (error
detecting). In read procedure, user can compare hardware calculated checksum with software calculated
one to validate the result.
For example:
Write Procedure
z
(1). Set REG 19h.1Ah.[0] = 1 to enable SMI Bus Error Check function
(2). Write data to DM8603's register (general write command)
(3). CPU calculate checksum (CSUM[7:0]) and write it to REG 19h.19h.[7:0]
(4). Check function status REG 19h.19h.[8]
Read Procedure
z
(1). Set REG 19h.1Ah.[0] = 1 to enable SMI Bus Error Check function
(2). Read data from DM8603's register (general read command)
(3). Read hardware calculated checksum from REG 19h.19h.[7:0] and compare it with CPU calculated
one (CSUM[7:0])
Checksum calculate formula:
CSUM[0]
=
D[0]
^
D[8]
^
R[0]
^
A[3]
CSUM[1]
=
D[1]
^
D[9]
^
R[1]
^
A[4]
CSUM[2]
=
D[2]
^
D[10]
^
R[2]
^
OP[0]
CSUM[3]
=
D[3]
^
D[11]
^
R[3]
^
OP[1]
CSUM[4]
=
D[4]
^
D[12]
^
R[4]
CSUM[5]
=
D[5]
^
D[13]
^
A[0]
CSUM[6]
=
D[6]
^
D[14]
^
A[1]
CSUM[7]
=
D[7]
^
D[15]
^
A[2]
Note:
D[15:0]
=
<Data> field of SMI frame
R[4:0]
=
<Register Address> field of SMI frame
A[4:0]
=
<PHY Address> field of SMI frame
OP[1:0]
=
<Op Code> field of SMI frame
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
70
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.2
Switch Functions
9.2.1
Address Learning
The DM8603 has a self-learning mechanism for learning the MAC addresses of incoming packets in real
time. DM8603 stores MAC addresses, port number and time stamp information in the Hash-based Address
Table. It can learn up to 1K unicast address entries.
The switch engine updates address table with new entry if incoming packet’s Source Address (SA) does
not exist and incoming packet is valid (non-error and legal length).
Besides, DM8603 has an option to disable address learning for individual port. This feature can be set by
REG 08h/09h/0Ah.11h.[12].
9.2.2
Address Aging
The time stamp information of address table is used in the aging process. The switch engine updates
time stamp whenever the corresponding SA receives. The switch engine would delete the entry if its time
stamp is not updated for a period of time. The period can be programmed or disabled through
REG 10h.15h.[1:0].
9.2.3
Packet Forwarding
The DM8603 forwards the incoming packet according to following decision:
z
If DA is Multicast/Broadcast, the packet is forwarded to all ports, except to the port on which the
packet was received.
z
Switch engine would look up address table based on DA when incoming packets is UNICAST. If the
DA was not found in address table, the packet is treated as a multicast packet and forward to other
ports. If the DA was found and its destination port number is different to source port number, the
packet is forward to destination port.
z
Switch engine also look up VLAN, Port Monitor setting and other forwarding constraints for the
forwarding decision, more detail will discuss in later sections.
The DM8603 will filter incoming packets under following conditions:
z
Error packets, including CRC errors, alignment errors, illegal size errors.
z
PAUSE packets.
z
If incoming packet is UNICAST and its destination port number is equal to source port number.
9.2.4
Inter-Packet Gap (IPG)
IPG is the idle time between any two valid packets at the same port. The typical number is 96 bits time. In
other word, the value is 9.6u sec for 10Mbps and 960n sec for 100Mbps.
9.2.5
Back-off Algorithm
The DM8603 implements the binary exponential back-off algorithm in half-duplex mode compliant to
IEEE standard 802.3.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
71
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.2.6
Late Collision
Late Collision is a type of collision. If a collision error occurs after the first 512 bit times of data are
transmitted, the packet is dropped.
9.2.7
Full Duplex Flow Control
The DM8603 supports IEEE standard 802.3x flow control frames on both transmit and receive sides. On
the receive side, The DM8603 will defer transmitting next normal frames, if it receives a pause frame from
link partner. On the transmit side, The DM8603 issues pause frame with maximum pause time when internal
resources such as received buffers, transmit queue and transmit descriptor ring are unavailable. Once
resources are available, The DM8603 sends out a pause frame with zero pause time allows traffic to resume
immediately.
9.2.8
Half Duplex Flow Control
The DM8603 supports half-duplex backpressure. The inducement is the same as full duplex mode. When
flow control is required, the DM8603 sends jam pattern and results in a collision. The flow control ability can
be set in REG 08h/09h/0Ah.11h.[5].
9.2.9
Partition Mode
The DM8603 provides a partition mode for each port, see REG 08h/09h/0Ah.11h.[6]. The port enters
partition mode when more than 64 consecutive collisions are occurred. In partition mode the port continuous
to transmit but it will not receive. The port returned to normal operation mode when a good packet is seen on
the wire. The detail description of partition mode represent following:
(1). Entering Partition State
A port will enter the Partition State when either of the following conditions occurs:
z
The port detects a collision on every one of 64 consecutive re-transmit attempts to the same
packet.
z
The port detects a single collision which occurs for more than 512 bit times.
z
Transmit defer timer time out, which indicates the transmitting packet is deferred to long.
(2). While in Partition State:
The port will continue to transmit its pending packet, regardless of the collision detection, and will
not allow the usual Back-off Algorithm. Additional packets pending for transmission will be
transmitted, while ignoring the internal collision indication. This frees up the ports transmit buffers
which would otherwise be filled up at the expense of other ports buffers. The assumption is that
the partition is signifying a system failure situation (bad connection/cable/station), thus dropping
packets is a small price to pay vs. the cost of halting the switch due to a buffer full condition.
(3). Exiting from Partition State
The Port exits from Partition State, following the end of a successful packet transmission. A
successful packet transmission is defined as no collisions were detected on the first 512 bits of the
transmission.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
72
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.2.10 Broadcast Storm Filtering
The DM8603 has an option to limit the traffic of broadcast or multicast packets, to protect the switch from
lower bandwidth availability.
There are two types of broadcast storm control, one is throttling broadcast packet only, the other includes
multicast. This feature can be set through REG 08h/09h/0Ah.12h.
The broadcast storm threshold can be programmed by EEPROM or REG 08h/09h/0Ah.15h, the default
setting is no broadcast storm protecting.
9.2.11 Bandwidth Control
The DM8603 supports two types of bandwidth control for each port. One is the ingress and egress
bandwidth rate can be controlled separately, the other is combined together, this function can be set through
REG 08h/09h/0Ah.12h.[14]. The bandwidth control is disabled by default.
To separate and combined bandwidth control mode, the threshold rate is defined in REG
08h/09h/0Ah.15h.
The behavior of bandwidth control as below:
(1). For the ingress control, if flow control function is enabled, Pause or Jam packet will be transmitted.
The ingress packets will be dropped if flow control is disabled.
(2). For the egress control, the egress port will not transmit any packets. On the other hand, the ingress
bandwidth of source port will be throttled that prevent packets from forwarding.
(3). In combined mode, if the sum of ingress and egress bandwidth over threshold, the bandwidth will
be throttled.
9.2.12 Port Monitoring Support
The DM8603 supports “Port Monitoring” function on per port base, detail as below:
(1). Sniffer Port and Monitor Port
There is only one port can be selected as “sniffer port” by REG 10h.13h, multiple ports can be set
as “receive monitor port” or “transmit monitor port” in REG 08h/09h/0Ah.12h.
(2). Receive monitor
All packets received on the “receive monitor port” are send a copy to “sniffer port”. For example,
port 0 is set as “receive monitor port” and port 2 is selected as a “sniffer port”. If a packet is
received form port 0 and predestined to port 1 after forwarding decision, the DM8603 will forward it
to port 1 and port 2 in the end.
(3). Transmit monitor
All packets transmitted on the “transmit monitor port” are send a copy to “sniffer port”. For example,
port 1 is set as “transmit monitor port” and port 2 is selected as “sniffer port”. If a packet is received
from port 0 and predestined to port 1 after forwarding decision, the DM8603 will forward it to port 1
and port 2 in the end.
(4). Exception
The DM8603 has an optional setting that broadcast/multicast packets are not monitored (see REG
08h/09h/0Ah.12h.[11]). It’s useful to avoid unnecessary bandwidth.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
73
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.2.13 VLAN Support
9.2.13.1
Port-Based VLAN
The DM8603 supports port-based VLAN as default, and up to 16 groups. Each port has a default VID
called PVID (Port VID, see REG 08h/09h/0Ah.16h). For VLAN setting, the DM8603 used LSB 4-bytes of
PVID as index and mapped to the VLAN Group Mapping Registers (REG 13h.10h~1Fh) to decide the
destination port(s).
9.2.13.2
802.1Q-Based VLAN
Regarding IEEE 802.1Q standard, Tag-based VLAN uses an extra tag to identify the VLAN membership
of a frame across VLAN-aware switch/router. A tagged frame is four bytes longer than an untagged frame
and contains two bytes of TPID (Tag Protocol Identifier) and two bytes of TCI (Tag Control Information).
The DM8603 also supports 16 802.1Q-based VLAN groups, as specified in REG 11h.1Eh.[0]. It’s obvious
that the tagged packets can be assigned to several different VLANs which are determined according to the
VID inside the VLAN Tag. Therefore, the operation is similar to port-based VLAN. The DM8603 used LSB
4-bytes VID of received packet with VLAN tag and VLAN Group Mapping Register (REG 13h.10h~1Fh) to
configure the VLAN partition. If the destination port of received packet is not same VLAN group with received
port, it will be discarded.
Dest.
Src.
Dest.
Src.
Length/Type
TPID
TCI
Data
Length / Type
Standard frame
Data
Tagged frame
0x8100
2 bytes
Priority
3 bits
9.2.13.3
CFI
1 bits
VID
12 bits
Tag/Untag
User can define each port as Tag port or Un-tag port by REG 08h/09h/0Ah.17h.[14] in 802.1Q-based
VLAN mode. The operation of Tag and Un-tag can explain as below conditions:
(1). Receive untagged packet and forward to Un-tag port. Received packet will forward to destination
port without modification.
(2). Receive tagged packet and forward to Un-tag port. The DM8603 will remove the tag from the
packet and recalculate CRC before sending it out.
(3). Receive untagged packet and forward to Tag port. The DM8603 will insert the PVID tag when an
untagged packet enters the port, and recalculate CRC before delivering it.
(4). Receive tagged packet and forward to Tag port. Received packet will forward to destination port
without modification.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
74
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.2.14 Special Tag
The Special Tag function provided by the DM8603 is used to exchange control and status information
between Switch and CPU within frame. An extra 4-bytes tag is added into frame to carry different content
according to direction of special tag frame. Received special tag (CPU Æ Switch) specifies the desired port
mapping of packet sent by CPU and some configurations about frame handle rules. Transmitted special tag
(Switch Æ CPU) indicates the source port number of incoming frame.
The following figure shows special tag frame format. In left 2 bytes of special tag field, there is an
identifier called Special Tag Ether-Type that can use to recognize special tag frame. The value of this field
can be set by REG 10h.14h.
The detail information carried by received special tag is described as below. Through received special
tag, CPU can tell Switch the handle rule per frame over the internal setting. This feature can be enable
through REG 10h.13h.[6].
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
75
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
Received Special Tag(CPU Æ Switch) 4-byte Format:
Byte 0/1:
[15:0]
Special Tag Ether-Type (Default: 0x8086)
Byte 2:
[7]
Reserved
[6]
ST_PMAP_en, ST_PMAP Enable
[5:3]
Reserved
[2:0]
ST_PMAP, Force to assign forwarding port map
[7]
Reserved
[6]
ST_CVLAN, Cross VLAN
Byte 3:
0: This frame obeys VLAN boundary.
1: This frame can cross VLAN boundary.
[5]
ST_LRN_DIS, Disable learning
0: This frame will be learned
1: This frame will not be learned
[4]
ST_PRI_EN, ST_PRI Enable
[3:2]
ST_PRI, Priority Queue Number (0~3)
00: Queue 0
01: Queue 1
10: Queue 2
11: Queue 3
[1:0]
ST_TAG
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Beside, transmitted special tag is used to indicate source port number. CPU can use this message to
judge the incoming port number of the frame. REG 10h.13h.[7] can enable this feature by setting to 1.
Transmitted Special Tag (Switch Æ CPU) 4-byte Format:
Byte 0/1:
[15:0]
Special Tag Ether-Type (Default: 0x8086)
Byte 2:
[7:2]
Reserved
[1:0]
ST_SPORT, Source Port Number (0~2)
[7:0]
Reserved
Byte 3:
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
76
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.2.15 Priority Support
The DM8603 supports Quality of Service (QoS) mechanism for multimedia communication such as VoIP
and video conferencing.
The DM8603 provides three priority classifications: Port-based, 802.1p-based and DiffServ-based priority.
See next section for more detail. The DM8603 offers four level queues for transmit on each port.
The DM8603 provides two packet scheduling algorithms: Weighted Round Robin (WRR) and Strict
Priority Queuing (SPQ). WRR based on their priority and queue weight, the priority weight 8, 4, 2 and 1 for
queue 3, 2, 1, and 0 respectively by default. Queues with larger weights get more service than smaller. This
mechanism can get highly efficient bandwidth and smooth the traffic. Strict Priority Queuing (SPQ) based on
priority only. The packets on the highest priority queue is transmitted first. The next highest-priority queue is
work until last queue empties, and so on. This feature can be set in REG 08h/09h/0Ah.17h.[5].
9.2.15.1
Port-Based Priority
Port based priority is the simplest scheme and as default. Each port has a 2-bit priority value as index for
splitting ingress packets to the corresponding transmit queue. This value can be set in REG
08h/09h/0Ah.17h.[1:0].
9.2.15.2
802.1p-Based Priority
The DM8603 extracts 3-bit priority field from received packet with 802.1p VLAN tag, and maps this field
against VLAN Priority Map Registers (REG 10h.17h) to determine which transmit queue is designated. The
VLAN Priority Map is programmable.
9.2.15.3
DiffServ-Based Priority
DiffServ based priority uses the most significant 6-bit of the ToS field in standard IPv4 header, and maps
this field against ToS Priority Map Registers (REG 10h.18h~1Fh) to determine which transmit queue is
designated. The ToS Priority Map is programmable too. In addition, User can only refer to most significant
3-bit of the ToS field optionally, see REG 11h.1Eh.[7].
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
77
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.2.16 Address Table Accessing
9.2.16.1
Type of Address Table
There are three types of address table in the DM8603. The description is represented below:
(1). Unicast Address Table
This table is used for destination MAC address lookup and source MAC address learning. The table
can have up to 1024 entries. If the table is full, the latest one will kick out the eldest one. The
programming method can refer to next section.
(2). Multicast Address Table
The table that stores multicast addresses shares with unicast address table and can be maintained by
host CPU for custom filtering and forwarding multicast packets. If the table is full, the latest one will
kick out the eldest one. All of entries in multicast address table are static one. In addition to host CPU,
multicast address table can be manipulated by internal switch engine, if hardware-based IGMP
Snooping function is enabled.
(3). IGMP Membership Table
This table is used to establish IPv4 multicast forwarding rule under IGMP protocol if hardware-based
IGMP Snooping function is enabled. It is automatic maintained by internal engine according to
snooping IGMP control packets, and can only support to read out by the host CPU. The maximum of
entries of table is 16. If the table is full, never join anymore.
9.2.16.2
Access Rules of Address Table
In DM8603, unicast and multicast address table support “Write”, “Delete”, ”Search” and “Read”
commands. However, for IGMP membership table, there are only three different type commands such as
“Write”, “Delete” and “Read”. The DM8603 procedure and flow chart of Entry Access is described as
following:
z
Entry Write
(1). Check the busy bit of Address Table Control & Status Register (REG 15h.10h.[15]) to seek the
availability of access engine. Waiting until engine is available and to keep on following.
(2). Write the MAC address to the Address Table Data 1~3 Registers (REG 15h.12h~14h).
(3). Write the Port Number or Port Map to Address Table Data 0 Register (REG 15h.11h.[2:0]).
(4). If need, write the entry’s attribute such as static to Address Table Data 4 Register (REG
15h.15h.[0]).
(5). Write the “WRITE” command and assign the target table to Address Table Control & Status Register
(REG 15h.10h.[4:0]) to start the operation.
(6). Check the busy bit again, wait for available.
(7). Read the command status from Address Table Control & Status Register (REG 15h.10h.[14:13]).
z
Entry Delete
(1). Check the busy bit of Address Table Control & Status Register (REG 15h.10h.[15]) to seek the
availability of access engine. Waiting until engine is available and to keep on following.
(2). Write the MAC address to the Address Table Data 1~3 Registers (REG 15h.12h~14h).
(3). Write the “DELETE” command and assign the target table to Address Table Control & Status
Register (REG 15h.10h.[4:0]) to start the operation.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
78
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
(4). Check the busy bit again, wait for available.
(5). Read the command status from Address Table Control & Status Register (REG 15h.10h.[14:13]).
z
Entry Search
(1). Check the busy bit of Address Table Control & Status Register (REG 15h.10h.[15]) to seek the
availability of access engine. Waiting until engine is available and to keep on following.
(2). Write the MAC address to the Address Table Data 1~3 Registers (REG 15h.12h~14h).
(3). Write the “SEARCH” command and assign the target table to Address Table Control & Status
Register (REG 15h.10h.[4:0]) to start the operation.
(4). Check the busy bit again, wait for available.
(5). Read the command status from Address Table Control & Status Register (REG 15h.10h.[14:13]).
(6). Read the Port Number or Port Map to Address Table Data 0 Register (REG 15h.11h.[2:0]).
(7). If need, read the entry sequence (the sequence number of entry in address table) from Address
Table Data 1 Register (REG 15h.12h).
(8). If need, read the entry’s attributes that include static (unicast address table only) and IGMP Entry
(multicast address table only) from Address Table Data 4 Register (REG 15h.15h.[0] for static and
REG 15h.15h.[12] for IGMP Entry).
z
Entry Read
(1). Check the busy bit of Address Table Control & Status Register (REG 15h.10h.[15]) to seek the
availability of access engine. Waiting until engine is available and to keep on following.
(2). Write the entry sequence to the Address Table Data 1 Register (REG 15h.12h).
(3). Write the “READ” command and assign the target table to Address Table Control & Status Register
(REG 15h.10h.[4:0]) to start the operation.
(4). Check the busy bit again, wait for available.
(5). Read the command status from Address Table Control & Status Register (REG 15h.10h.[14:13]).
(6). Read the Port Number or Port Map to Address Table Data 0 Register (REG 15h.11h.[2:0]).
(7). If target is unicast or multicast address table, read the entry’s MAC address from Address Table
Data 1~3 Register (REG 15h.12h~14h). If target is IGMP membership table, read the real memory
address from Address Table Data 1 Register (REG 15h.12h.[10:0]).
(8). If target is unicast address table, read the entry’s attributes such as static from Address Table Data
4 Register (REG 15h.15h.[0]). For multicast address table, IGMP Entry can be read from Address
Table Data 4 Register (REG 15h.15h.[12]). For IGMP membership table, IGMP valid signal and
per-port aged timer can be read from Address Table Data 2~3 Register (REG 15h.13h.[2:0], REG
15h.14h[5:0]).
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
79
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
80
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
81
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.2.17 IGMP Snooping
The Internet Group Management Protocol (IGMP) is a communications protocol used to manage the
membership of Internet Protocol multicast groups. IGMP is used by IP hosts and adjacent multicast routers
to establish multicast group memberships. There are three versions of IGMP, as defined by "Request for
Comments" (RFC) documents of the Internet Engineering Task Force (IETF). IGMP v1 is defined by RFC
1112, IGMP v2 is defined by RFC 2236 and IGMP v3 is defined by RFC 3376.
IGMP snooping is a feature that allows the switch to "listen in" on the IGMP protocol conversation
between hosts and routers. The IGMP snooping switch hears an IGMP report from a host with a given
multicast group address. It adds the host's port number to the multicast list for that group, and when the
switch hears an IGMP Leave, it removes the host's port from the table entry. Finally, switch will only forward
multicast traffic to the hosts interested in that traffic. Therefore, this function can effectively reduce multicast
traffic.
The DM8603 supports IGMP v1/v2 snooping and the maximal group is 16 without any software effort in
this mode. The DM8603 automatically manipulates and updates IGMP membership table and Multicast table
according to IGMP control packets, such as membership report and leave.
If IGMP membership table is full, the later incoming IGMP Membership Report (Join) packet will be
ignored and the group address won’t be registered into multicast address table. After that, the unregistered
IP multicast packets (the destination MAC address can not be found in the multicast address table) will be
treated as normal multicast packets by default. The additional forwarding control method can see the register
REG 14h.1Bh.[3:2].
The DM8603 supports router ports auto-detect and auto-aging mechanism. The port which receives
IGMP Query packets will be treated as router port by default. The router port also can be define as static one
by user (see REG 14h.1Bh.[7]) and the port map of the router port can be programmed at REG
14h.1Bh.[10:8]. Keep in mind that the uP port (Port 2) is never treated as router port. The DM8603 leaves
the router port if the time (Router Present Timeout, 400sec by default) is expired that the port never receives
IGMP Query during this period.
If receiving V1REPORT or V2REPORT (group join), DM8603 creates new or updates the entry. If
receiving LEAVE, DM8603 deletes the entry directly when Fast Leave is enabled, or waiting until timeout.
DM8603 removes the entry that was never updated after the timer of host timeout (Group Membership
Interval) is expired. This timer is programmable in DM8603 and defined by RFC 2236 as ((the Robustness
Variable) times (the Query Interval)) plus (one Query Response Interval). The setting of the Robustness
Variable and the Query Interval can see REG 14h.1Ch.
9.2.18 IPv6 MLD Snooping
The DM8603 forwards the IPv6 Multicast Listener Discovery (MLD) packets to the processor port when MLD Snooping
is enabled and the MLD packets meet following scenario:
z
IPv6 Multicast packets.
z
The Hop Limit in IPv6 header is 1.
z
The Next Header in IPv6 header is 3Ah (ICMPv6) or 00h (and next header of hop-by-hop option header is
3Ah).
z
The Type in ICMP header is 82h (Multicast Listener Query), 83h (Multicast Listener Report) or 84h (Multicast
Listener Done).
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
82
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.2.19 STP / RSTP Support
DM8603 supports both Spanning Tree Protocol (STP) and Rapid Spanning Tree Protocol (RSTP). There
are five types of STP Port State (Disabled, Blocking, Listening, Learning and Forwarding state) and three
types of RSTP Port State (Discarding, Learning and Forwarding) for these two protocols. The following figure
is the port state diagram of STP.
Pow er-on
Initialization
B locking
State
L istening
State
D isabled
State
L earning
State
Forw arding
State
But in RSTP, there are only three port states. The port states comparison between STP and RSTP are
listed as below.
STP Port State
RSTP Port State
Disabled
Discarding
Blocking
Discarding
Listening
Discarding
Learning
Learning
Forwarding
Forwarding
For compatibility and design consideration, this function needs the cooperation with external CPU.
Moreover, the behavior of Disabled/Blocking/Listening states in STP must be equal to the behavior of
Discarding state in RSTP in DM8606. The difference between STP and RSTP should be implemented by
CPU. The following statement describes the STP/RSTP port state behavior and software action in DM8603.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
83
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
(1). Disable State:
Drop all packets including BPDUs
z
Æ Implemented by transmitting BPDUs to CPU and CPU drops BPDUs.
z
Learning is disabled.
z
Does not transmit BPDUs received from CPU
Æ Implemented by CPU does not send BPDUs to this port
(2). Blocking State:
z
Drop all packets except BPDUs and transmit received BPDUs to CPU.
z
Learning is disabled.
z
Does not transmit BPDUs received from CPU.
(3). Listening State:
z
Drop all packets except BPDUs and tranmit received BPDUs to CPU
z
Learning is disabled.
z
Forward BPDUs received from CPU
Æ Implemented by CPU uses special tag function to send BPDUs to decided port.
(4). Learning State:
z
Drop all packets except BPDUs and transmit received BPDUs to CPU
z
Learning is enabled
z
Forward BPDUs received from CPU
(5). Forwarding State:
z
Forward all packets
z
Learning is enabled
z
Forward BPDUs received from CPU
Base on the behavior of different states described above, the port states setting of DM8603 for both
STP and RSTP can see REG 08h/09h/0Ah.19h.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
84
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
The following flow diagram shows how to configure STP/RSTP function.
Start
Set REG 14h.12h.[0] to
enable STP/RSTP
Set Port States to
REG 08h/09h/0A h.19h.[1:0]
[1:0] STPS0
00: Forw arding
01: D isabled/D iscarding
10: Learning
11: Blocking / Listening
ST P/R ST P Setting
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
85
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.3
MII Interface
9.3.1 MII Data Interface
The DM8603 port 2 provides a Media Independent Interface (MII) as defined in the IEEE 802.3u standard
(Clause 22).
The MII consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to
facilitate data transfers between the DM8603 port 2 and external device (a PHY or a MAC in reverse MII).
•
P2_TXD3~0 (transmit data) is a nibble (4 bits) of data that are driven by the DM8603 synchronously
with respect to P2_TXC. For each P2_TXC period, which P2_TXE is asserted, P2_TXD3~0 are
accepted for transmission by the external device.
•
P2_TXC (transmit clock) from the external device is a continuous clock that provides the timing
reference for the transfer of the P2_TXE, P2_TXD3~0. The DM8603 can drive 25MHz clock if it is
configured to reversed MII mode.
•
P2_TXE (transmit enable) from the DM8603 port 2 MAC indicates that nibbles are being presented
on the MII for transmission to the external device.
•
P2_RXD3~0 (receive data) is a nibble (4 bits) of data that are sampled by the DM8603 port 2 MAC
synchronously with respect to P2_RXC. For each P2_RXC period which P2_RXDV is asserted,
P2_RXD3~0 are transferred from the external device to the DM8603 port 2 MAC reconciliation sub
layer.
•
P2_RXC3~0 (receive clock) from external device to the DM8603 port 2 MAC reconciliation sub layer
is a continuous clock that provides the timing reference for the transfer of the P2_RXDV,
P2_RXD3~0, and P2_RXER signals.
•
P2_RXDV (receive data valid) input from the external device to indicates that the external device is
presenting recovered and decoded nibbles to the DM8603 port 2 MAC reconciliation sub layer. To
interpret a receive frame correctly by the reconciliation sub layer, P2_RXDV must encompass the
frame, starting no later than the Start-of-Frame delimiter and excluding any End-Stream delimiter.
•
P2_RXER (receive error) input from the external device is synchronously with respect to P2_RXC.
P2_RXER will be asserted for 1 or more clock periods to indicate to the reconciliation sub layer that
an error was detected somewhere in the frame being transmitted from the external device to the
DM8603 port 2 MAC.
•
P2_CRS (carrier sense) is asserted by the external device when either the transmit or receive
medium is non-idle, and de-asserted by the external device when the transmit and receive medium
are idle. The P2_CRS can also in output mode when the DM8603 port 2 is configured to reversed
MII mode.
•
P2_COL (collision detection) is asserted by the external device, when both the transmit and receive
medium is non-idle, and de-asserted by the external device when the either transmit or receive
medium are idle. The P2_COL can also in output mode when the DM8603 port 2 is configured to
reversed MII mode.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
86
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.3.2
MII Serial Management Interface
The serial control interface uses a simple two-wired serial interface to obtain and control the status of the
physical layer through the MII interface. The serial control interface consists of PHY_MDC (Management
Data Clock to PHY), and PHY_MDIO (Management Data Input/Output to PHY) signals.
In read/write operation, the management data frame is 64-bits long and starts with 32 contiguous logic
one bits (preamble) synchronization clock cycles on PHY_MDC. The Start of Frame Delimiter (SFD) is
indicated by a <01> pattern followed by the operation code (OP) :< 10> indicates Read operation and <01>
indicates Write operation. For read operation, a 2-bit turnaround (TA) filing between Register Address field
and Data field is provided for PHY_MDIO to avoid contention. Following the turnaround time, 16-bit data is
read from or written onto management registers.
Management Interface - Read Frame Structure
Management Interface - Write Frame Structure
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
87
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.4
Internal PHY Functions
9.4.1
100Base-TX Operation
The transmitter section contains the following functional blocks:
z
4B5B Encoder
z
Scrambler
z
Parallel to Serial Converter
z
NRZ to NRZI Converter
z
NRZI to MLT-3
z
MLT-3 Driver
9.4.1.1
4B5B Encoder
The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC Reconciliation Layer into a 5-bit
(5B) code group for transmission, see reference Table 1. This conversion is required for control and packet
data to be combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with
a J/K code-group pair (11000 10001) upon transmit. The 4B5B encoder continues to replace subsequent 4B
preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the
desertions of the Transmit Enable signal from the MAC Reconciliation layer, the 4B5B encoder injects the
T/R code-group pair (01101 00111) indicating the end of frame. After the T/R code-group pair, the 4B5B
encoder continuously injects IDLEs into the transmit data stream until Transmit Enable is asserted and the
next transmit packet is detected.
9.4.1.2
Scrambler
The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy
across the frequency spectrum at the media connector and on the twisted pair cable in 100Base-TX
operation.
By scrambling the data, the total energy presented to the cable is randomly distributed over a wide
frequency range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at
frequencies related to the repeated 5B sequences, like the continuous transmission of IDLE symbols. The
scrambler output is combined with the NRZ 5B data from the code-group encoder via an XOR logic function.
The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical
frequencies.
9.4.1.3
Parallel to Serial Converter
The Parallel to Serial Converter receives parallel 5B scrambled data from the scrambler, and serializes it
(converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ
to NRZI encoder block
9.4.1.4
NRZ to NRZI Encoder
After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for
compatibility with the TP-PMD standard, for 100Base -TX transmission over Category-5 unshielded twisted
pair cable.
9.4.1.5
MLT-3 Converter
The MLT-3 conversion is accomplished by converting The data stream output, from the NRZI encoder
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
88
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
into two binary data streams, with alternately phased logic One event.
9.4.1.6
MLT-3 Driver
The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver,
which converts these streams to current sources and alternately drives either side of the transmit
transformer’s primary winding, resulting in a minimal current MLT-3 signal.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
89
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.4.1.7
4B5B Code Group
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Symbol
Meaning
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
4B code
3210
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
J
K
T
R
H
Idle
SFD (1)
SFD (2)
ESD (1)
ESD (2)
Error
undefined
0101
0101
undefined
undefined
undefined
11111
11000
10001
01101
00111
00100
V
V
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
Table 1
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
90
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.4.2
100Base-TX Receiver
The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial
data to synchronous 4-bit nibble data.
The receive section contains the following functional blocks:
z
Signal Detect
z
Digital Adaptive Equalization
z
MLT-3 to Binary Decoder
z
Clock Recovery Module
z
NRZI to NRZ Decoder
z
Serial to Parallel
z
Descrambler
z
Code Group Alignment
z
4B5B Decoder
9.4.2.1
Signal Detect
The signal detects function meets the specifications mandated by the ANSI XT12 TP-PMD 100Base-TX
standards for both voltage thresholds and timing parameters.
9.4.2.2
Adaptive Equalization
When transmitting data over copper twisted pair cable at high speed, attenuation based on frequency
becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can
vary greatly during normal operation based on the randomness of the scrambled data stream. This
variation in signal attenuation, caused by frequency variations, must be compensated for to ensure the
integrity of the received data. In order to ensure quality transmission when employing MLT-3 encoding, the
compensation must be able to adapt to various cable lengths and cable types depending on the installed
environment. The selection of long cable lengths for a given implementation requires significant
compensation, which will be over-killed in a situation that includes shorter, less attenuating cable lengths.
Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause
serious under-compensation for longer length cables. Therefore, the compensation or equalization must be
adaptive to ensure proper conditioning of the received signal independent of the cable length.
9.4.2.3
MLT-3 to NRZI Decoder
The DM8603 decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data.
9.4.2.4
Clock Recovery Module
The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery
Module locks onto the data stream and extracts the 125 MHz reference clock. The extracted and
synchronized clock and data are presented to the NRZI to NRZ decoder.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
91
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.4.2.5
NRZI to NRZ
The transmit data stream is required to be NRZI encoded for compatibility with the TP-PMD standard for
100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be
reversed on the receive end. The NRZI to NRZ decoder receives the NRZI data stream from the Clock
Recovery Module and converts it to a NRZ data stream to be presented to the Serial to Parallel conversion
block.
9.4.2.6
Serial to Parallel
The Serial to Parallel Converter receives a serial data stream from the NRZI to NRZ converter. It
converts the data stream to parallel data to be presented to the descrambler.
9.4.2.7
Descrambler
Because of the scrambling process requires to control the radiated emissions of transmit data streams,
the receiver must descramble the receive data streams. The descrambler receives scrambled parallel data
streams from the Serial to Parallel converter, and it descrambles the data streams, and presents the data
streams to the Code Group alignment block.
9.4.2.8
Code Group Alignment
The Code Group Alignment block receives un-aligned 5B data from the descrambler and converts it into
5B code group data. Code Group Alignment occurs after the J/K is detected and subsequent data is aligned
on a fixed boundary.
9.4.2.9
4B5B Decoder
The 4B5B Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble)
data. When receiving a frame, the first 2 5-bit code groups receive the start-of-frame delimiter (J/K symbols).
The J/K symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two code
groups are the end-of-frame delimiter (T/R Symbols).
The T/R symbol pair is also stripped from the nibble, presented to the Reconciliation layer.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
92
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.4.3
10Base-T Operation
The 10Base-T transceiver is IEEE 802.3u compliant. When the DM8603 is operating in 10Base-T mode,
the coding scheme is Manchester. Data processed for transmit is presented in nibble format, converted to a
serial bit stream, then the Manchester encoded. When receiving, the bit stream, encoded by the Manchester,
is decoded and converted into nibble format.
9.4.4
Collision Detection
For half-duplex operation, a collision is detected when the transmit and receive channels are active
simultaneously. Collision detection is disabled in full duplex operation.
9.4.5
Carrier Sense
Carrier Sense (CRS) is asserted in half-duplex operation during transmission or reception of data. During
full-duplex mode, CRS is asserted only during Receive operations.
9.4.6
Auto-Negotiation
The objective of Auto-negotiation is to provide a means to exchange information between linked devices
and to automatically configure both devices to take maximum advantage of their abilities. It is important to
note that Auto-negotiation does not test the characteristics of the linked segment. The Auto-Negotiation
function provides a means for a device to advertise supported modes of operation to a remote link partner,
acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes
of operation. This allows devices on both ends of a segment to establish a link at the best common mode of
operation. If more than one common mode exists between the two devices, a mechanism is provided to
allow the devices to resolve to a single mode of operation using a predetermined priority resolution function.
Auto-negotiation also provides a parallel detection function for devices that do not support the
Auto-negotiation feature. During Parallel detection there is no exchange of information of configuration.
Instead, the receive signal is examined. If it is discovered that the signal matches a technology, which the
receiving device supports, a connection will be automatically established using that technology. This allows
devices not to support Auto-negotiation but support a common mode of operation to establish a link.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
93
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
9.5
LFP and FEF Function
The DM8603 pairs Port 0 and Port 1 for media converter application and supports LFP (Link Fault
Pass-through) and FEF (Far End Fault) troubleshooting features. The LFP (Link Fault Pass-through) allows
the DM8603 to monitor both the fiber and TP ports for loss of signal. In case of a loss of RX signal on one
media port, the DM8603 will automatically disable the TX signal to the other media port, thus passing
through the link fault. FEF (Far End Fault) enables the DM8603 to stop sending link pulse to the link partner
once a loss of the fiber RX signal is encountered. Then the link partner will synchronously stop sending data.
FEF prevents loss of valuable data transmitted over invalid link. Combining those two function of DM8603,
both end devices can be notified of a loss of fiber link.
9.6
HP Auto-MDIX Function
The DM8603 supports the automatic detect cable connection type, MDI/MDIX (straight through/cross
over). A manual configuration by register bit for MDI or MDIX is still accepted.
When set to automatic, the polarity of MDI/MDIX controlled timing is generated by 16-bits LFSR. The
switching cycle time is located from 200ms to 420ms. The polarity control is always switch until detect
received signal. After selected MDI or MDIX, this feature is able to detect the required cable connection type.
(Straight through or crossed over) and make correction automatically
RX + /- from DM8603
RX+/- to RJ45
TX + /- from DM8603
TX+/- to RJ45
* MDI: __________
* MDIX: - - - - - - - - -
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
94
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
10. DC and AC Electrical Characteristics
10.1 Absolute Maximum Ratings
Symbol
DVDD33
DVDD18
AVDD33
AVDD18
IOV
TSTG
TA
LT
Parameter
Digital 3.3V Power
Digital 1.8V Power
Analog 3.3V Power
Analog 1.8V Power
Input/Output Voltage
Storage Temperature Range
Ambient Temperature
Lead Temperature
(TL, soldering, 10 sec.).
Min.
-0.3
-0.3
-0.3
-0.3
-0.5
-65
0
-
Max.
3.6
1.95
3.6
1.95
5.5
+150
+70
+260
Unit
V
V
V
V
V
°C
°C
°C
Conditions
10.2 Operating Conditions
Symbol
DVDD33
DVDD18
AVDD33
AVDD18
PD
(Power
Dissipation)
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Parameter
Digital 3.3V Power
Digital 1.8V Power
Analog 3.3V Power
Analog 1.8V Power
100BASE-TX
10BASE-TX
Min.
3.135
1.71
3.135
1.71
-
Typ.
107
54
57
64
Max.
3.465
1.89
3.465
1.89
-
Unit
V
V
V
V
mA
mA
mA
mA
-
11
-
mA
Conditions
1.8V only
3.3V only
TX idle, 1.8V only
100% utilization,
1.8V only
3.3V only
95
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
10.3 DC Electrical Characteristics
Symbol
Inputs
VIL
VIH
IIL
IIH
Outputs
VOL
VOH
Receiver
VICM
Parameter
Min.
Typ.
Max.
Input Low Voltage
Input High Voltage
Input Low Leakage Current
Input High Leakage Current
2.0
-1
-
-
0.8
1
V
V
uA
uA
Vcond1*
Vcond1
VIN = 0.0V, Vcond1
VIN = 3.3V, Vcond1
Output Low Voltage
Output High Voltage
2.4
-
0.4
-
V
V
IOL = 4mA
IOH = -4mA
-
1.8
-
V
100 Ω Termination
Across
1.9
4.4
│19│
│44│
2.0
5
│20│
│50│
2.1
5.6
│21│
│56│
V
V
mA
mA
RX+/RX- Common Mode Input
Voltage
Transmitter
VTD100 100TX+/- Differential Output Voltage
VTD10 10TX+/- Differential Output Voltage
ITD100 100TX+/- Differential Output Current
ITD10
10TX+/- Differential Output Current
Unit
Conditions
Peak to Peak
Peak to Peak
Absolute Value
Absolute Value
Note:
1.
Vcond1: DVDD33 = 3.3V, DVDD18 = 1.8V, AVDD33 = 3.3V, AVDD18 = 1.8V.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
96
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
10.4 AC Characteristics
10.4.1 Power On Reset Timing
Symbol
T1
T2
T3
T4
Parameter
PWRST# Low Period
Strap pin hold time with PWRST#
PWRST# high to EECS high
PWRST# high to EECS burst end
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Min.
1
40
-
Typ.
5
--
Max.
4
Unit
ms
ns
us
ms
Conditions
-
97
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
10.4.2 Port 2 MII Interface Transmit Timing
Symbol
T1
T1
T2
Parameter
100M MII Transmit Clock Period
10M MII Transmit Clock Period
P2_TXE,P2_TXD3~0 to P2_TXC
Rising Output Delay
Min.
-
Typ.
40
400
8
Max.
-
Unit
ns
ns
ns
Min.
5
Typ.
40
400
-
Max.
-
Unit
ns
ns
ns
5
-
-
ns
10.4.3 Port 2 MII Interface Receive Timing
Symbol
T1
T1
T2
T3
Parameter
100M MII Receive Clock Period
10M MII Receive Clock Period
P2_RXER, P2_RXDV and P2_RXD3~0 to P2_RXC
Setup Time
P2_RXER, P2_RXDV and P2_RXD3~0 to P2_RXC
Hold Time
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
98
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
10.4.4 Port 2 RMII Interface Transmit Timing
Symbol
T1
T2
Parameter
RMII REF_CLK Period
P2_TXE,P2_TXD1~0 to REF_CLK
Rising Output Delay
Min.
-
Typ.
20
8
Max.
-
Unit
ns
ns
Min.
4
2
Typ.
20
-
Max.
-
Unit
ns
ns
ns
10.4.5 Port 2 RMII Interface Receive Timing
Symbol
T1
T2
T3
Parameter
RMII REF_CLK Period
CRS_DV, P2_RXD to REF_CLK Setup Time
CRS_DV, P2_RXD1~0 to REF_CLK Hold Time
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
99
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
10.4.6 MII Management Interface Timing
Symbol
T1
T2
T3
T4
Parameter
PHY_MDC Period
PHY_MDIO to PHY_MDC Setup Time on Input State
PHY_MDIO to PHY_MDC Hold Time on Input State
PHY_MDIO to PHY_MDC Rising Output Delay on
Output State
Min.
40
40
-
Typ.
1920
960
Max.
-
Unit
ns
ns
ns
ns
10.4.7 Host SMI Interface Timing
Symbol
T1
T2
T3
T4
Parameter
SMI_MDC Period
SMI_MDIO to SMI_MDC Setup Time on Input State
SMI_MDIO to SMI_MDC Hold Time on Input State
SMI_MDIO to SMI_MDC Rising Output Delay on
Output State
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Min.
80
40
40
-
Typ.
5
Max.
-
Unit
ns
ns
ns
ns
100
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
10.4.8 EEPROM Timing
Symbol
T1
T2
T3
T4
T5
Parameter
EECK Period
EECS to EECK Rising Output Delay
EEDIO to EECK Rising Output Delay on Output State
EEDIO to EECK Rising Setup Time on Input State
EEDIO to EECK Rising Hold Time on Input State
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Min.
8
8
Typ.
5120
4160
4160
-
Max.
-
Unit
ns
ns
ns
ns
ns
101
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
11. Application Information
11.1 Application of Reverse MII
RevMII MAC I/F
SMI_MDC
MDC
SMI_MDIO
MDIO
PHY_MDC
PHY_MDIO
DM8603
MII MAC I/F
NC
NC
P2_RXC
TXCLK
P2_TXC
RXCLK
P2_TXD3~0
RXD[3:0]
P2_TXE
RXDV
P2_RXD3~0
TXD[3:0]
TXEN
P2_RXDV
P2_CRS
P2_COL
P2_RXER
P2_TXER
NC
NC
CRS
COL
RXER
Note: The P2_TXE and P2_TXD2 pins of DM8603 must be pull-up resistor with 4.7K ohm to DVDD33 in
this application.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
102
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
11.2 Application of Reduce MII to PHY
RMII MAC I/F
SMI_MDC
SMI_MDIO
RMII PHY I/F
NC
NC
PHY_MDC
MDC
PHY_MDIO
MDIO
P2_TXD1~0
TXD[1:0]
P2_TXE
TX_EN
P2_RXD1~0
RXD[1:0]
P2_CRS
CRS_DV
P2_RXC
REF_CLK
NC
P2_TXC
RX_ER*
50 MHz
Reference Clock
Note: The P2_TXD3 pin of DM8603 must be pull-up resistor with 4.7K ohm to DVDD33 in this
application.
11.3 Application of Reduce MII to MAC
RMII MAC I/F
RMII MAC I/F
SMI_MDC
MDC
SMI_MDIO
MDIO
PHY_MDC
PHY_MDIO
NC
NC
P2_TXD1~0
RXD[1:0]
P2_TXE
CRS_DV
P2_RXD1~0
TXD[1:0]
P2_CRS
TX_EN
P2_RXC
REF_CLK
P2_TXC
RX_ER
50 MHz
Reference Clock
Note: The P2_TXE and P2_TXD3 pins of DM8603 must be pull-up resistor with 4.7K ohm to DVDD33 in this application.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
103
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
12. Package Information
64 Pins LQFP Package Outline Information:
Symbol
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
R1
R2
S
θ
θ1
θ2
θ3
Min
0.05
1.35
0.17
0.17
0.09
0.09
0.45
0.08
0.08
0.20
0o
0o
Dimension in mm
Nom
Max
1.60
0.15
1.40
1.45
0.22
0.27
0.20
0.23
0.20
0.16
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.50 BSC
0.60
0.75
1.00 REF
0.20
3.5o
7o
12o TYP
o
12 TYP
Dimension in inch
Min
Nom
Max
0.063
0.002
0.006
0.053
0.055
0.057
0.007
0.009
0.011
0.007
0.008
0.009
0.004
0.008
0.004
0.006
0.472 BSC
0.394 BSC
0.472 BSC
0.394 BSC
0.020 BSC
0.018
0.024
0.030
0.039 REF
0.003
0.003
0.008
0.008
0o
3.5o
7o
0o
12o TYP
o
12 TYP
1. Dimension D1 and E1 do not include resin fin.
2. All dimensions are base on metric system.
3. General appearance spec should base on its final visual inspection spec.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
104
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
13. Terminology
B
BIST
BPDU
Byte
C
CFI
COL
CRC
CRS
CSR
D
DMAC
E
ESD
F
FEF
FLP
H
Host
I
IGMP
IPG
L
LFP
LQFP
M
MAC
MDI
MDIX
MII
MIB
MLD
MLT-3
N
NRZI
NRZ
O
OUI
P
PHY
PMD
PVID
Q
QinQ
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Built-in Self-Test
Bridge Protocol Data Unit
8-bits
Canonical Format Indicator
Collision
Cyclic Redundancy Check
Carrier Sense
Control and Status Registers
Destination MAC Address
End of Stream Delimiter
Far End Fault
Fast Link Pulse
External system (Includes processor, application software, etc.)
Internet Group Management Protocol
Inter-Packet Gap
Link Fault Pass-through
Low-profile Quad Flat Package
Media Access Controller
Medium Dependant Interface
Media Independent Interface with Crossover
Media Independent Interface
Management Information Base
Multicast Listener Discovery
Multi-Level Transmission Encoding (3-Levels)
Non Return to Zero Inverter
Non Return to Zero
Organizationally Unique Identifier
Physical Layer
Physical Medium Dependent
Port VID
IEEE 802.1Q-in-Q VLAN Tag, double-tagged
105
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
QoS
R
REG
RevMII
RMII
RSTP
S
SFD
SMAC
SMI
STP
T
TOS
TP
V
VID
VLAN
W
WORD
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
Quality of Service
Register
Reversed MII
Reduce MII
IEEE 802.1w - Rapid Spanning Tree Protocol
Start of Frame Delimiter
Source MAC Address
Serial Management Interface
IEEE 802.1D - Spanning Tree Protocol
Type of Service
Twisted Pair
VLAN Identifier
Virtual LAN
16-bits
106
DM8603
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
14. Ordering Information
Part Number
DM8603EP
Pin Count
64
Package
LQFP
(Pb-free)
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM
makes no warranty, express, statutory, implied or
by description regarding the information in this
publication or regarding the information in this
publication or regarding the freedom of the
described chip(s) from patent infringement.
FURTHER, DAVICOM MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE. DAVICOM reserves the right to halt
production or alter the specifications and prices at
any time without notice. Accordingly, the reader is
cautioned to verify that the data sheets and other
information in this publication are current before
placing orders. Products described herein are
intended for use in normal commercial applications.
Applications involving unusual environmental or
reliability requirements, e.g. military equipment or
medical life support equipment, are specifically not
recommended without additional processing by
DAVICOM for such applications. Please note that
application circuits illustrated in this document are
for reference purposes only.
DAVICOM’s terms and conditions printed on the
order acknowledgment govern all sales by
DAVICOM. DAVICOM will not be bound by any
terms inconsistent with these unless DAVICOM
agrees otherwise in writing. Acceptance of the
buyer’s orders shall be based on these terms.
Company Overview
DAVICOM Semiconductor Inc. develops and
manufactures integrated circuits for integration into
data communication products. Our mission is to
design and produce IC products that are the
industry’s best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal,
we have built an organization that is able to develop
chipsets in response to the evolving technology
requirements of our customers while still delivering
products that meet their cost requirements.
Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards.
Our currently
available and soon to be released products are based on
our proprietary designs and deliver high quality, high
performance chipsets that comply with modem
communication standards and Ethernet networking
standards.
Contact Windows
For additional information about DAVICOM products, contact the Sales department at:
Headquarters
Hsin-chu Office:
No.6 Li-Hsin Rd. VI,
Science-based Park,
Hsin-chu City, Taiwan, R.O.C.
TEL: +886-3-5798797
FAX: +886-3-5646929
MAIL: [email protected]
HTTP: http://www.davicom.com.tw
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the
limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
107