TI LM393TLX/NOPB

LM193-N, LM2903-N, LM293-N, LM393-N
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SNOSBJ6E – OCTOBER 1999 – REVISED MARCH 2013
LM193/LM293/LM393/LM2903 Low Power Low Offset Voltage Dual Comparators
Check for Samples: LM193-N, LM2903-N, LM293-N, LM393-N
FEATURES
DESCRIPTION
•
The LM193 series consists of two independent
precision voltage comparators with an offset voltage
specification as low as 2.0 mV max for two
comparators which were designed specifically to
operate from a single power supply over a wide range
of voltages. Operation from split power supplies is
also possible and the low power supply current drain
is independent of the magnitude of the power supply
voltage. These comparators also have a unique
characteristic in that the input common-mode voltage
range includes ground, even though operated from a
single power supply voltage.
1
2
•
•
•
•
•
•
•
•
•
•
Wide Supply
– Voltage Range: 2.0V to 36V
– Single or Dual Supplies: ±1.0V to ±18V
Very Low Supply Current Drain (0.4 mA) —
Independent of Supply Voltage
Low Input Biasing Current: 25 nA
Low Input Offset Current: ±5 nA
Maximum Offset voltage: ±3 mV
Input Common-Mode Voltage Range Includes
Ground
Differential Input Voltage Range Equal to the
Power Supply Voltage
Low Output Saturation Voltage: 250 mV at 4
mA
Output Voltage Compatible with TTL, DTL,
ECL, MOS and CMOS logic systems
Available in the 8-Bump (12 mil) DSBGA
Package
See AN-1112 (SNVA009) for DSBGA
Considerations
ADVANTAGES
•
•
•
•
•
•
Application areas include limit comparators, simple
analog to digital converters; pulse, squarewave and
time delay generators; wide range VCO; MOS clock
timers; multivibrators and high voltage digital logic
gates. The LM193 series was designed to directly
interface with TTL and CMOS. When operated from
both plus and minus power supplies, the LM193
series will directly interface with MOS logic where
their low power drain is a distinct advantage over
standard comparators.
The LM393 and LM2903 parts are available in TI’s
innovative thin DSBGA package with 8 (12 mil) large
bumps.
High Precision Comparators
Reduced VOS Drift Over Temperature
Eliminates Need for Dual Supplies
Allows Sensing Near Ground
Compatible with All Forms of Logic
Power Drain Suitable for Battery Operation
Figure 1. Squarewave Oscillator
Figure 2. Non-Inverting Comparator with
Hysteresis
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
LM193-N, LM2903-N, LM293-N, LM393-N
SNOSBJ6E – OCTOBER 1999 – REVISED MARCH 2013
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Schematic and Connection Diagrams
Figure 3. Schematic
Figure 4. TO-99 Package
Figure 5. CDIP, PDIP, SOIC Packages
Figure 6. DSBGA Top View
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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SNOSBJ6E – OCTOBER 1999 – REVISED MARCH 2013
Absolute Maximum Ratings (1) (2)
Supply Voltage, V+
Differential Input Voltage
36V
(3)
36V
−0.3V to +36V
Input Voltage
Input Current (VIN<−0.3V)
Power Dissipation
(4)
50 mA
(5)
PDIP
780 mW
TO-99
660 mW
SOIC Package
510 mW
DSBGA Package
Output Short-Circuit to Ground
568mW
(6)
Continuous
Operating Temperature Range
LM393
0°C to +70°C
LM293
−25°C to +85°C
−55°C to +125°C
LM193/LM193A
−40°C to +85°C
LM2903
−65°C to +150°C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
+260°C
Soldering Information
CDIP, PDIP Package Soldering (10 seconds)
260°C
SOIC Package
215°C
Vapor Phase (60 seconds)
Infrared (15 seconds)
220°C
See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices.
ESD rating (1.5 kΩ in series with 100 pF)
(1)
(2)
(3)
(4)
(5)
(6)
1300V
Refer to RETS193AX for LM193AH military specifications and to RETS193X for LM193H military specifications.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the
magnitude of the negative power supply, if used).
This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of
the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is
also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go
to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive
and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3V.
For operating at high temperatures, the LM393 and LM2903 must be derated based on a 125°C maximum junction temperature and a
thermal resistance of 170°C/W which applies for the device soldered in a printed circuit board, operating in a still air ambient. The
LM193/LM193A/LM293 must be derated based on a 150°C maximum junction temperature. The low bias dissipation and the “ON-OFF”
characteristic of the outputs keeps the chip dissipation very small (PD≤100 mW), provided the output transistors are allowed to saturate.
Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 20 mA independent of the magnitude of V+.
Copyright © 1999–2013, Texas Instruments Incorporated
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Electrical Characteristics
(V+=5V, TA = 25°C, unless otherwise stated)
Parameter
LM193A
Test Conditions
Min
(1)
Input Offset Voltage
Input Bias Current
IIN(+) or IIN(−) with Output In Linear
Range, VCM = 0V (2)
Input Offset Current
IIN(+)−IIN(−) VCM = 0V
Input Common Mode Voltage Range
V+ = 30V
Supply Current
Typ
2.0
mV
25
100
nA
25
nA
V+−1.5
V
0.4
1
mA
1
2.5
0
V+=5V
RL=∞
+
Voltage Gain
RL≥15 kΩ, V =15V
VO = 1V to 11V
Large Signal Response Time
VIN=TTL Logic Swing, VREF=1.4V
VRL=5V, RL=5.1 kΩ
Response Time
VRL=5V, RL=5.1 kΩ
Output Sink Current
VIN(−)=1V, VIN(+)=0, VO≈1.5V
Saturation Voltage
VIN(−)=1V, VIN(+)=0, ISINK≤4 mA
250
Output Leakage Current
VIN(−)=0, VIN(+)=1V, VO=5V
0.1
(3)
(4)
50
(4)
6.0
Units
1.0
3.0
(3)
V+=36V
(1)
(2)
Max
mA
200
V/mV
300
ns
1.3
μs
16
mA
400
mV
nA
+
+
At output switch point, VO≃1.4V, RS=0Ω with V from 5V to 30V; and over the full input common-mode range (0V to V −1.5V), at 25°C.
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the reference or input lines.
The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end
of the common-mode voltage range is V+−1.5V at 25°C, but either or both inputs can go to 36V without damage, independent of the
magnitude of V+.
The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 300 ns can be obtained, see
Typical Performance Characteristics.
Electrical Characteristics
(V+=5V, TA = 25°C, unless otherwise stated)
Parameter
Input Offset Voltage
Test Conditions
LM193
Min Typ
(1)
Input Bias Current
IIN(+) or IIN(−) with Output In
Linear Range, VCM = 0V (2)
Input Offset Current
IIN(+)−IIN(−) VCM = 0V
Input Common Mode
Voltage Range
V+ = 30V
Supply Current
RL=∞
(3)
Max
Min Typ
1.0
5.0
25
100
3.0
0
1.0
5.0
2.0
7.0
mV
25
250
25
250
nA
5.0
50
V+−1.5
5.0
0
50
nA
V+−1.5
V
mA
0.4
1
0.4
1
0.4
1.0
1
2.5
1
2.5
1
2.5
VIN=TTL Logic Swing, VREF=1.4V
VRL=5V, RL=5.1 kΩ
Response Time
VRL=5V, RL=5.1 kΩ
Output Sink Current
VIN(−)=1V, VIN(+)=0, VO≤1.5V
Saturation Voltage
VIN(−)=1V, VIN(+)=0, ISINK≤4 mA
250
Output Leakage Current
VIN(−)=0, VIN(+)=1V, VO=5V
0.1
4
Min Typ
0
Max
50
(4)
6.0
200
50
Units
Max
V+=36V
Large Signal Response
Time
(4)
LM2903
V+=5V
RL≥15 kΩ, V+=15V
VO = 1V to 11V
(3)
25
V+−1.5
Voltage Gain
(1)
(2)
LM293, LM393
200
25
mA
100
V/mV
300
300
300
ns
1.3
1.3
1.5
μs
16
6.0
400
16
250
0.1
6.0
400
16
250
0.1
mA
400
mV
nA
At output switch point, VO≃1.4V, RS=0Ω with V+ from 5V to 30V; and over the full input common-mode range (0V to V+−1.5V), at 25°C.
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the reference or input lines.
The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end
of the common-mode voltage range is V+−1.5V at 25°C, but either or both inputs can go to 36V without damage, independent of the
magnitude of V+.
The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 300 ns can be obtained, see
Typical Performance Characteristics.
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Electrical Characteristics
(V+ = 5V)
(1)
Parameter
LM193A
Test Conditions
Min
Input Offset Current
IIN(+)−IIN(−), VCM=0V
Input Bias Current
IIN(+) or IIN(−) with Output in Linear Range,
VCM=0V (3)
+
(4)
Input Common Mode Voltage Range
V =30V
Saturation Voltage
VIN(−)=1V, VIN(+)=0, ISINK≤4 mA
Output Leakage Current
VIN(−)=0, VIN(+)=1V, VO=30V
Differential Input Voltage
Keep All VIN's≥0V (or V−, if Used),
(2)
(3)
(4)
(5)
Max
(2)
Input Offset Voltage
(1)
Typ
Units
4.0
mV
100
nA
300
nA
+
0
(5)
V −2.0
V
700
mV
1.0
μA
36
V
These specifications are limited to −55°C≤TA≤+125°C, for the LM193/LM193A. With the LM293 all temperature specifications are limited
to −25°C≤TA≤+85°C and the LM393 temperature specifications are limited to 0°C≤TA≤+70°C. The LM2903 is limited to
−40°C≤TA≤+85°C.
At output switch point, VO≃1.4V, RS=0Ω with V+ from 5V to 30V; and over the full input common-mode range (0V to V+−1.5V), at 25°C.
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the reference or input lines.
The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end
of the common-mode voltage range is V+−1.5V at 25°C, but either or both inputs can go to 36V without damage, independent of the
magnitude of V+.
Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the
magnitude of the negative power supply, if used).
Electrical Characteristics
(V+ = 5V)
(1)
Parameter
Input Offset Voltage
Test Conditions
LM193
Min Typ
(2)
LM293, LM393
Max
Min Typ
Max
LM2903
Min Typ
Max
Units
9
9
9
15
mV
Input Offset Current
IIN(+)−IIN(−), VCM=0V
100
150
50
200
nA
Input Bias Current
IIN(+) or IIN(−) with Output in Linear
Range, VCM=0V
300
400
200
500
nA
V+−2.0
V
700
mV
(3)
Input Common Mode
Voltage Range
V+=30V
Saturation Voltage
VIN(−)=1V, VIN(+)=0,
ISINK≤4 mA
700
700
Output Leakage Current
VIN(−)=0, VIN(+)=1V, VO=30V
1.0
1.0
1.0
μA
Differential Input Voltage
Keep All VIN's≥0V (or V−, if Used),
36
36
36
V
(1)
(2)
(3)
(4)
(5)
(4)
(5)
0
V+−2.0
0
V+−2.0
0
400
These specifications are limited to −55°C≤TA≤+125°C, for the LM193/LM193A. With the LM293 all temperature specifications are limited
to −25°C≤TA≤+85°C and the LM393 temperature specifications are limited to 0°C≤TA≤+70°C. The LM2903 is limited to
−40°C≤TA≤+85°C.
At output switch point, VO≃1.4V, RS=0Ω with V+ from 5V to 30V; and over the full input common-mode range (0V to V+−1.5V), at 25°C.
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the reference or input lines.
The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end
of the common-mode voltage range is V+−1.5V at 25°C, but either or both inputs can go to 36V without damage, independent of the
magnitude of V+.
Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the
magnitude of the negative power supply, if used).
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Typical Performance Characteristics
LM193/LM293/LM393, LM193A
Supply Current
Input Current
Figure 7.
Figure 8.
Output Saturation Voltage
Response Time for Various Input Overdrives—Negative
Transition
Figure 9.
Figure 10.
Response Time for Various Input Overdrives—Positive Transition
Figure 11.
6
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Typical Performance Characteristics
LM2903
Supply Current
Input Current
Figure 12.
Figure 13.
Output Saturation Voltage
Response Time for Various Input Overdrives—Negative
Transition
Figure 14.
Figure 15.
Response Time for Various Input Overdrives—Positive Transition
Figure 16.
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APPLICATION HINTS
The LM193 series are high gain, wide bandwidth devices which, like most comparators, can easily oscillate if the
output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only
during the output voltage transition intervals as the comparator change states. Power supply bypassing is not
required to solve this problem. Standard PC board layout is helpful as it reduces stray input-output coupling.
Reducing the input resistors to < 10 kΩ reduces the feedback signal levels and finally, adding even a small
amount (1.0 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to
stray feedback are not possible. Simply socketing the IC and attaching resistors to the pins will cause inputoutput oscillations during the small transition intervals unless hysteresis is used. If the input signal is a pulse
waveform, with relatively fast rise and fall times, hysteresis is not required.
All input pins of any unused comparators should be tied to the negative supply.
The bias network of the LM193 series establishes a drain current which is independent of the magnitude of the
power supply voltage over the range of from 2.0 VDC to 30 VDC.
It is usually unnecessary to use a bypass capacitor across the power supply line.
The differential input voltage may be larger than V+ without damaging the device (1). Protection should be
provided to prevent the input voltages from going negative more than −0.3 VDC (at 25°C). An input clamp diode
can be used as shown in Typical Applications.
The output of the LM193 series is the uncommitted collector of a grounded-emitter NPN output transistor. Many
collectors can be tied together to provide an output OR'ing function. An output pull-up resistor can be connected
to any available power supply voltage within the permitted supply voltage range and there is no restriction on this
voltage due to the magnitude of the voltage which is applied to the V+ terminal of the LM193 package. The
output can also be used as a simple SPST switch to ground (when a pull-up resistor is not used). The amount of
current which the output device can sink is limited by the drive available (which is independent of V+) and the β
of this device. When the maximum current limit is reached (approximately 16mA), the output transistor will come
out of saturation and the output voltage will rise very rapidly. The output saturation voltage is limited by the
approximately 60Ω rSAT of the output transistor. The low offset voltage of the output transistor (1.0mV) allows the
output to clamp essentially to ground level for small load currents.
Typical Applications
(V+=5.0 VDC)
Figure 17. Basic Comparator
(1)
8
Figure 18. Driving CMOS
Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the
magnitude of the negative power supply, if used).
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(V+=5.0 VDC)
Figure 19. Driving TTL
Figure 20. Squarewave Oscillator
* For large ratios of R1/R2,
D1 can be omitted.
Figure 21. Pulse Generator
Figure 22. Crystal Controlled Oscillator
V* = +30 VDC
+250 mVDC ≤ VC ≤ +50 VDC
700Hz ≤ fo ≤ 100kHz
Figure 23. Two-Decade High Frequency VCO
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(V+=5.0 VDC)
10
Figure 24. Basic Comparator
Figure 25. Non-Inverting Comparator with
Hysteresis
Figure 26. Inverting Comparator with Hysteresis
Figure 27. Output Strobing
Figure 28. AND Gate
Figure 29. OR Gate
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(V+=5.0 VDC)
Figure 30. Large Fan-in AND Gate
Figure 31. Limit Comparator
Figure 32. Comparing Input Voltages of Opposite
Polarity
Figure 33. ORing the Outputs
Figure 34. Zero Crossing Detector (Single Power
Supply)
Figure 35. One-Shot Multivibrator
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(V+=5.0 VDC)
Figure 36. Bi-Stable Multivibrator
Figure 37. One-Shot Multivibrator with Input Lock
Out
Figure 38. Zero Crossing Detector
Figure 39. Comparator With a Negative Reference
Figure 40. Time Delay Generator
12
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(V+=5.0 VDC)
Split-Supply Applications
(V+=+15 VDC and V−=−15 VDC)
Figure 41. MOS Clock Driver
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
•
14
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM193AH
ACTIVE
TO-99
LMC
8
500
TBD
Call TI
Call TI
-55 to 125
LM193AH
LM193AH/NOPB
ACTIVE
TO-99
LMC
8
500
Green (RoHS
& no Sb/Br)
POST-PLATE
Level-1-NA-UNLIM
-55 to 125
LM193AH
LM193H
ACTIVE
TO-99
LMC
8
500
TBD
Call TI
Call TI
-55 to 125
LM193H
LM193H/NOPB
ACTIVE
TO-99
LMC
8
500
Green (RoHS
& no Sb/Br)
POST-PLATE
Level-1-NA-UNLIM
-55 to 125
LM193H
LM2903ITL/NOPB
ACTIVE
DSBGA
YZR
8
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C
03
LM2903ITLX/NOPB
ACTIVE
DSBGA
YZR
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C
03
LM2903M
ACTIVE
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 85
LM
2903M
LM2903M/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM
2903M
LM2903MX
ACTIVE
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 85
LM
2903M
LM2903MX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM
2903M
LM2903N
ACTIVE
PDIP
P
8
40
TBD
Call TI
Call TI
-40 to 85
LM
2903N
LM2903N/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
-40 to 85
LM
2903N
LM293H
ACTIVE
TO-99
LMC
8
500
TBD
Call TI
Call TI
-25 to 85
LM293H
LM293H/NOPB
ACTIVE
TO-99
LMC
8
500
Green (RoHS
& no Sb/Br)
POST-PLATE
Level-1-NA-UNLIM
-25 to 85
LM293H
LM393M
ACTIVE
SOIC
D
8
95
TBD
Call TI
Call TI
0 to 70
LM
393M
LM393M/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LM
393M
LM393MX
ACTIVE
SOIC
D
8
2500
TBD
Call TI
Call TI
0 to 70
LM
393M
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM393MX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
LM
393M
LM393N
ACTIVE
PDIP
P
8
40
TBD
Call TI
Call TI
0 to 70
LM
393N
LM393N/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
0 to 70
LM
393N
LM393TL/NOPB
ACTIVE
DSBGA
YZR
8
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
0 to 70
C
02
LM393TLX/NOPB
ACTIVE
DSBGA
YZR
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
0 to 70
C
02
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM2903ITL/NOPB
DSBGA
YZR
8
250
178.0
LM2903ITLX/NOPB
DSBGA
YZR
8
3000
LM2903MX
SOIC
D
8
2500
LM2903MX/NOPB
SOIC
D
8
LM393MX
SOIC
D
B0
(mm)
K0
(mm)
P1
(mm)
8.4
1.7
1.7
0.76
4.0
178.0
8.4
1.7
1.7
0.76
330.0
12.4
6.5
5.4
2.0
2500
330.0
12.4
6.5
5.4
8
2500
330.0
12.4
6.5
5.4
W
Pin1
(mm) Quadrant
8.0
Q1
4.0
8.0
Q1
8.0
12.0
Q1
2.0
8.0
12.0
Q1
2.0
8.0
12.0
Q1
LM393MX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM393TL/NOPB
DSBGA
YZR
8
250
178.0
8.4
1.7
1.7
0.76
4.0
8.0
Q1
LM393TLX/NOPB
DSBGA
YZR
8
3000
178.0
8.4
1.7
1.7
0.76
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM2903ITL/NOPB
DSBGA
YZR
8
250
210.0
185.0
35.0
LM2903ITLX/NOPB
DSBGA
YZR
8
3000
210.0
185.0
35.0
LM2903MX
SOIC
D
8
2500
367.0
367.0
35.0
LM2903MX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM393MX
SOIC
D
8
2500
367.0
367.0
35.0
LM393MX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM393TL/NOPB
DSBGA
YZR
8
250
210.0
185.0
35.0
LM393TLX/NOPB
DSBGA
YZR
8
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0008xxx
D
0.600±0.075
E
TLA08XXX (Rev C)
D: Max = 1.54 mm, Min = 1.479 mm
E: Max = 1.54 mm, Min = 1.479 mm
4215045/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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