LF147JAN LF147JAN Wide Bandwidth Quad JFET Input Operational Amplifier Literature Number: SNOSAJ9 LF147JAN Wide Bandwidth Quad JFET Input Operational Amplifier General Description Features The LF147 is a low cost, high speed quad JFET input operational amplifier with an internally trimmed input offset voltage (BI-FET II™ technology). The device requires a low supply current and yet maintains a large gain bandwidth product and a fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The LF147 is pin compatible with the standard LM148. This feature allows designers to immediately upgrade the overall performance of existing LF148 and LM124 designs. The LF147 may be used in applications such as high speed integrators, fast D/A converters, sample-and-hold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The device has low noise and offset voltage drift. j Internally trimmed offset voltage: 5 mV max j Low input bias current: 50 pA Typ. 0.01 pA/√Hz Typ. j Low input noise current: j Wide gain bandwidth: 4 MHz Typ. j High slew rate: 13 V/µs Typ. j Low supply current: 7.2 mA Typ. 1012Ω Typ. j High input impedance: j Low total harmonic distortion: AV = 10, RL = 10KΩ, VO = 20VP-P BW = 20Hz — 20KHz ≤0.02% Typ. j Low 1/f noise corner: 50 Hz Typ. j Fast settling time to 0.01%: 2 µs Typ. Ordering Information NS Part Number JAN Part Number JL147BCA JM38510/11906BCA NS Package Number J14A Package Description 14LD CERDIP Connection Diagram Dual-In-Line Package 20129801 Top View See NS Package Number J14A BI-FET II™ is a trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation DS201298 www.national.com LF147JAN Wide Bandwidth Quad JFET Input Operational Amplifier April 2005 LF147JAN Simplified Schematic ⁄ Quad 14 20129813 Detailed Schematic 20129809 www.national.com 2 LF147JAN Absolute Maximum Ratings (Note 1) ± 18V ± 30V ± 15V Supply Voltage Differential Input Voltage Input Voltage Range (Note 2) Output Short Circuit Duration (Note 3) Continuous Power Dissipation (Notes 4, 5) 900 mW TJ max 150˚C θJA CERDIP 70˚C/W Operating Temperature Range −55˚C ≤ TA ≤ 125˚C Storage Temperature Range −65˚C ≤ TA ≤ 150˚C Lead Temperature (Soldering, 10 sec.) 260˚C ESD (Note 6) 900V Recommended Operating Conditions ± 5V to ± 15V Supply Voltage Range Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description 1 Static tests at Temp (˚C) 25 2 Static tests at 125 3 Static tests at -55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at -55 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at -55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at -55 12 Settling Time at 25 3 www.national.com LF147JAN LF147 JAN Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified: Symbol VIO ± IIB IIO Parameter Input Offset Voltage Input Bias Current Input Offset Current VCC = ± 15V, VCM = 0V Conditions Notes Subgroups Min Max Unit +VCC = 26V, -VCC = -4V, VCM = -11V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 4V, -VCC = -26V, VCM = 11V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 15V, -VCC = -15V, VCM = 0V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 5V, -VCC = -5V, VCM = 0V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 26V, -VCC = -4V, VCM = -11V -0.4 0.2 nA 1 -10 50 nA 2 +VCC = 15V, -VCC = -15V, VCM = 0V -0.2 0.2 nA 1 -10 50 nA 2 +VCC = 4V, -VCC = -26V, VCM = 11V -0.2 1.2 nA 1 -10 70 nA 2 +VCC = 15V, -VCC = -15V, VCM = 0V -0.1 0.1 nA 1 -20 20 nA 2 +PSRR Power Supply Rejection Ratio -VCC = -15V, +VCC = 20V to 10V 80 dB 1, 2, 3 -PSRR Power Supply Rejection Ratio +VCC = 15V, -VCC = -20V to -10V 80 dB 1, 2, 3 CMRR Input Voltage Common Mode Rejection ± VCC = ± 4V to ± 26V, VCM = -11V to +11V 80 dB 1, 2, 3 +IOS Output Short Circuit Current +VCC = 15V, -VCC = -15V, VCM = -10V, t ≤ 25mS -80 mA 1, 2, 3 −IOS Output Short Circuit Current +VCC = 15V, -VCC = -15V, VCM = 10V, t ≤ 25mS 80 mA 1, 2, 3 ICC Supply Current 14 mA 1, 2 16 mA 3 +VCC = 15V, -VCC = -15V Delta VIO / Delta T Input Offset Voltage Temp. Sensitivity 25˚C ≤ TA ≤ +125˚C (Note 7) -30 30 µV/˚C 2 -55˚C ≤ TA ≤ 25˚C (Note 7) -30 30 µV/˚C 3 +VOP Output Voltage Swing +VCC = 15V, -VCC = -15V, RL=10KΩ, VCM = -15V 12 V 4, 5, 6 +VCC = 15V, -VCC = -15V, RL=2KΩ, VCM = -15V 10 V 4, 5, 6 -VOP Output Voltage Swing +VCC = 15V, -VCC = -15V, RL=10KΩ, VCM = 15V -12 V 4, 5, 6 +VCC = 15V, -VCC = -15V, RL = 2KΩ, VCM = 15V -10 V 4, 5, 6 +AVS Open Loop Voltage Gain +VCC = 15V, -VCC = -15V, RL = 2KΩ, VO = 0 to 10V 50 V/mV 4 25 V/mV 5, 6 −AVS Open Loop Voltage Gain +VCC = 15V, -VCC = -15V, RL = 2KΩ, VO = 0 to -10V 50 V/mV 4 25 V/mV 5, 6 20 V/mV 4, 5, 6 AVS Open Loop Voltage Gain www.national.com +VCC = 5V, -VCC = -5V, RL = 10KΩ, VO = ± 2V 4 JAN Electrical Characteristics LF147JAN LF147 (Continued) AC Parameters The following conditions apply, unless otherwise specified: Symbol Parameter +SR Slew Rate -SR Slew Rate VCC = ± 15V Conditions Notes VI = -5V to +5V VI = +5V to -5V Unit Subgroups 7 V/µS 7 5 V/µS 8A, 8B 7 V/µS 7 5 V/µS 8A, 8B Min Max TRTR Transient Response Rise Time AV=1, VI=50mV, CL= 100pF, RL=2KΩ 200 nS 7, 8A, 8B TROS Transient Response Overshoot AV=1, VI=50mV, CL= 100pF, RL=2KΩ 40 % 7, 8A, 8B NIBB Noise Broadband BW = 10Hz to 15KHz, RS = 0Ω 15 µVRMS 7 NIPC Noise Popcorn BW = 10Hz to 15KHz, RS = 100KΩ 80 µVPK 7 CS Channel Separation RL = 2KΩ 80 dB 7 RL = 2KΩ, VI = ± 10V, A to B 80 dB 7 RL = 2KΩ, VI = ± 10V, A to C 80 dB 7 RL = 2KΩ, VI = ± 10V, A to D 80 dB 7 RL = 2KΩ, VI = ± 10V, B to A 80 dB 7 RL = 2KΩ, VI = ± 10V, B to C 80 dB 7 RL = 2KΩ, VI = ± 10V, B to D 80 dB 7 RL = 2KΩ, VI = ± 10V, C to A 80 dB 7 RL = 2KΩ, VI = ± 10V, C to B 80 dB 7 RL = 2KΩ, VI = ± 10V, C to D 80 dB 7 RL = 2KΩ, VI = ± 10V, D to A RL = 2KΩ, VI = ± 10V, D to B RL = 2KΩ, VI = ± 10V, D to C 80 dB 7 80 dB 7 80 dB 7 nS 12 ± tS Settling Time AV = 1 1,500 Drift Values ± VCC = ± 15V, VCM = 0V, “Delta calculations performed on The following conditions apply, unless otherwise specified: DC JAN S and QMLV devices at group B, subgroup 5 only” Min Max Unit Subgroups -1.0 1.0 mV 1 +VCC = 15V, -VCC = -15V, VCM = 0V -0.1 0.1 nA 1 +VCC = 15V, -VCC = -15V, VCM = 0V -0.1 0.1 nA 1 Symbol Parameters Conditions Notes VIO Input Offset Voltage +VCC = 15V, -VCC = -15V, VCM = 0V +IIB Input Bias Current -IIB Input Bias Current Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 3: Any of the amplifier outputs can be shorted to ground indefinitely, however, more than one should not be simultaneously shorted as the maximum junction temperature will be exceeded. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (Package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax — TA) / θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 5: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside guaranteed limits. Note 6: Human body model, 1.5 kΩ in series with 100 pF. Note 7: Calculated parameters. 5 www.national.com LF147JAN Typical Performance Characteristics Input Bias Current Input Bias Current 20129814 20129815 Positive Common-Mode Input Voltage Limit Supply Current 20129816 20129817 Negative Common-Mode Input Voltage Limit Positive Current Limit 20129819 20129818 www.national.com 6 LF147JAN Typical Performance Characteristics (Continued) Negative Current Limit Output Voltage Swing 20129820 20129821 Output Voltage Swing Gain Bandwidth 20129823 20129822 Bode Plot Slew Rate 20129824 20129825 7 www.national.com LF147JAN Typical Performance Characteristics (Continued) Undistorted Output Voltage Swing Distortion vs Frequency 20129826 20129827 Open Loop Frequency Response Common-Mode Rejection Ratio 20129829 20129828 Power Supply Rejection Ratio Equivalent Input Noise Voltage 20129830 www.national.com 20129831 8 LF147JAN Typical Performance Characteristics (Continued) Open Loop Voltage Gain Output Impedance 20129833 20129832 Inverter Settling Time 20129834 9 www.national.com LF147JAN Pulse Response RL=2 kΩ, CL=10 pF Large Signal Inverting Small Signal Inverting 20129806 Large Signal Non-Inverting 20129804 Small Signal Non-Inverting 20129807 20129805 Current Limit (RL=100Ω) 20129808 www.national.com 10 The LF147 is an op amp with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on ± 4.5V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. 11 www.national.com LF147JAN The LF147 will drive a 2 kΩ load resistance to ± 10V over the full temperature range. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Application Hints LF147JAN Typical Applications Digitally Selectable Precision Attenuator 20129810 All resistors 1% tolerance • Accuracy of better than 0.4% with standard 1% value resistors No offset adjustment necessary • Expandable to any number of stages • Very high input impedance A1 A2 A3 VO 0 0 0 0 0 0 1 −1 dB 0 1 0 −2 dB 0 1 1 −3 dB 1 0 0 −4 dB 1 0 1 −5 dB 1 1 0 −6 dB 1 1 1 −7 dB Attenuation www.national.com 12 LF147JAN Typical Applications (Continued) Long Time Integrator with Reset, Hold and Starting Threshold Adjustment 20129811 • VO starts from zero and is equal to the integral of the input voltage with respect to the threshold voltage: • Output starts when VIN ≥ VTH • Switch S1 permits stopping and holding any output value • Switch S2 resets system to zero 13 www.national.com LF147JAN Typical Applications (Continued) Universal State Variable Filter 20129812 For circuit shown: fO=3 kHz, fNOTCH=9.5 kHz Q=3.4 Passband gain: Highpass — 0.1 Bandpass — 1 Lowpass — 1 Notch — 10 • foxQ≤200 kHz • 10V peak sinusoidal output swing without slew limiting to 200 kHz • See LM148 data sheet for design equations www.national.com 14 Revision 04/18/05 A Section Originator Changes New Release into corporate format L. Lytle 1 MDS datasheets converted into one Corp. datasheet format. MJLF147–X rev 1B1 MDS will be archived 15 www.national.com LF147JAN Date Released LF147JAN Wide Bandwidth Quad JFET Input Operational Amplifier Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) NS Package Number J14A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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