TI LM158AWGRQMLV

LM158QML
LM158QML Low Power Dual Operational Amplifiers
Literature Number: SNOSAP3E
LM158QML
Low Power Dual Operational Amplifiers
General Description
Advantages
The LM158 series consists of two independent, high gain, internally frequency compensated operational amplifiers which
were designed specifically to operate from a single power
supply over a wide range of voltages. Operation from split
power supplies is also possible and the low power supply
current drain is independent of the magnitude of the power
supply voltage.
Application areas include transducer amplifiers, dc gain
blocks and all the conventional op amp circuits which now can
be more easily implemented in single power supply systems.
For example, the LM158 series can be directly operated off
of the standard +5V power supply voltage which is used in
digital systems and will easily provide the required interface
electronics without requiring the additional ±15V power supplies.
■
■
■
■
■
■
■
■
Unique Characteristics
■
Features
■ Available with radiation guarantee
■ In the linear mode the input common-mode voltage range
includes ground and the output voltage can also swing to
ground, even though operated from only a single power
supply voltage.
■ The unity gain cross frequency is temperature
compensated.
■ The input bias current is also temperature compensated.
Two internally compensated op amps
Eliminates need for dual supplies
Allows direct sensing near Gnd and VO also goes to Gnd
Compatible with all forms of logic
Power drain suitable for battery operation
■
■
■
■
■
100 krad(Si)
— High Dose Rate
100 krad(Si)
— ELDRS Free
Internally frequency compensated for unity gain
Large dc voltage gain: 100 dB
Wide bandwidth (unity gain): 1 MHz
(temperature compensated)
Wide power supply range:
— Single supply: 3V to 32V
— or dual supplies: ±1.5V to ±16V
Very low supply current drain (500 μA) − essentially
independent of supply voltage
Low input offset voltage: 2 mV
Input common-mode voltage range includes ground
Differential input voltage range equal to the power supply
voltage
Large output voltage swing: 0V to V+ − 1.5V
Ordering Information
NS Part Number
SMD Part Number
LM158H/883
NS Package Number
Package Description
H08C
8LD T0–99 Metal Can
LM158J/883
5962–8771001PA
J08A
8LD Ceramic DIP
LM158H-SMD
5962–8771001GA
H08C
8LD T0–99 Metal Can
LM158AH/883
5962–8771002GA
H08C
8LD T0–99 Metal Can
8LD Ceramic DIP
LM158AJ/883
5962–8771002PA
J08A
LM158AWG/883
5962–8771002QXA
WG10A
LM158AHRQMLV
HIGH DOSE RATE ONLY (Note 11)
5962R8771002VGA
100 krad(Si)
H08C
8LD T0–99 Metal Can
LM158AJ-QMLV
5962–8771002VPA
J08A
8LD Ceramic DIP
LM158AJRQMLV
HIGH DOSE RATE ONLY (Note 11)
5962R8771002VPA
100 krad(Si)
J08A
8LD Ceramic DIP
LM158AWGRQMLV
HIGH DOSE RATE ONLY (Note 11)
5962R8771002VXA
100 krad(Si)
WG10A
LM158A MDR
HIGH DOSE RATE ONLY DIE (Notes 1, 11)
5962R8771002V9A
100 krad(Si)
LM158AHRLQMLV
ELDRS FREE ONLY (Note 12)
5962R8771003VGA
100 krad(Si)
H08C
8LD T0–99 Metal Can
LM158AJRLQMLV
ELDRS FREE ONLY (Note 12)
5962R8771003VPA
100 krad(Si)
J08A
8LD Ceramic DIP
© 2009 National Semiconductor Corporation
201502
10LD Ceramic SOIC
10LD Ceramic SOIC
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LM158QML Low Power Dual Operational Amplifiers
January 13, 2009
LM158QML
NS Part Number
SMD Part Number
NS Package Number
LM158AWGRLQMLV
ELDRS FREE ONLY (Note 12)
5962R8771003VXA
100 krad(Si)
WG10A
LM158A MDE
ELDRS FREE ONLY DIE (Notes 1, 12)
5962R8771003V9A
100 krad(Si)
Package Description
10LD Ceramic SOIC
Note 1: FOR ADDITIONAL DIE INFORMATION, PLEASE VISIT THE HI REL WEB SITE AT: www.national.com/analog/space/level_die
Connection Diagrams
Metal Can Package
20150201
Top View
See NS Package Number H08C
DIP Package
10LD Ceramic SOIC
20150202
Top View
See NS Package Number WG10A
20150204
Top View
See NS Package Number J08A
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2
LM158QML
Schematic Diagram
(Each Amplifier)
20150203
3
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LM158QML
Absolute Maximum Ratings (Note 2)
Supply Voltage, V+
Differential Input Voltage
Input Voltage
Power Dissipation (Note 3)
Output Short-Circuit to GND(Note 4)
(One Amplifier)
V+ ≤ 15VDC and TA = 25°C
Maximum Junction Temperature (TJmax)
Input Current (VI < −0.3V)(Note 5)
Operating Temperature Range
32VDC
32VDC
−0.3VDC to +32VDC
830 mW
Continuous
150°C
50 mA
−55°C ≤ TA ≤ +125°C
−65°C ≤ TA ≤ +150°C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Metal Can
Ceramic DIP
Ceramic SOIC
Thermal Resistance
300°C
260°C
260°C
θJA
Metal Can (Still Air)
Metal Can (500LF/Min Air Flow)
Ceramic DIP (Still Air)
Ceramic DIP (500LF/Min Air Flow)
Ceramic SOIC (Still Air)
Ceramic SOIC (500LF/Min Air Flow)
155°C/W
80°C/W
132°C/W
81°C/W
195°C/W
131°C/W
θJC
Metal Can
Ceramic DIP
Ceramic SOIC
Package Weight
Metal Can
Ceramic DIP
Ceramic SOIC
ESD Tolerance (Note 8)
42°C/W
23°C/W
33°C/W
1,000mg
1,100mg
220mg
250V
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Temp °C
1
Static tests at
+25
2
Static tests at
+125
3
Static tests at
-55
4
Dynamic tests at
+25
5
Dynamic tests at
+125
6
Dynamic tests at
-55
7
Functional tests at
+25
8A
Functional tests at
+125
8B
Functional tests at
-55
9
Switching tests at
+25
10
Switching tests at
+125
11
Switching tests at
-55
12
Settling time at
+25
13
Settling time at
+125
14
Settling time at
-55
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4
LM158QML
LM158 Electrical Characteristics
SMD 5962–8771001
DC Parameters
The following conditions apply, unless otherwise specified.
Symbol
ICC
VOH
VOL
ISink
ISource
All voltages referenced to device ground.
Max
Units
Subgroups
+VCC = 5V, RL = 100K,
VO = 1.4V
1.2
mA
1, 2, 3
+VCC = 30V, RL = 100K,
VO = 1.4V
3.0
mA
1
4.0
mA
2, 3
Parameter
Conditions
Power Supply Current
Output Voltage High
Output Voltage Low
Output Sink Current
Output Source Current
Notes
Min
+VCC = 30V, RL = 2KΩ
26
V
1, 2, 3
+VCC = 30V, RL = 10KΩ
27
V
1, 2, 3
+VCC = 30V, RL = 10KΩ
20
mV
1, 2, 3
+VCC = 30V, ISink = 1µA
20
mV
1, 2, 3
+VCC = 5V, RL = 10KΩ
20
mV
1, 2, 3
+VCC = 15V, VO = 200mV,
+VI = 0V, -VI = +65mV
12
µA
1
+VCC = 15V, VO = 2V,
+VI = 0V, -VI = +65mV
10
mA
1
mA
2, 3
5.0
+VCC = 15V, VO = 2V,
+VI = 0V, -VI = -65mV
-20
mA
1
-10
mA
2, 3
mA
1
IOS
Short Circuit Current
+VCC = 5V, VO = 0V
-60
VIO
Input Offset Voltage
+VCC = 30V, VCM = 0V,
-5.0
5.0
mV
1
RS = 50Ω, VO = 1.4V
-7.0
7.0
mV
2, 3
+VCC = 30V, VCM = 28.5V,
-5.0
5.0
mV
1
-7.0
7.0
mV
2, 3
+VCC = 5V, VCM = 0V,
-5.0
5.0
mV
1
RS = 50Ω, VO = 1.4V
-7.0
7.0
mV
2, 3
dB
1
RS = 50Ω, VO = 1.4V
+VCC = 30V, VCM = 28V,
RS = 50Ω, VO = 1.4V
CMRR
Common Mode Rejection Ratio
+VCC = 30V, RS = 50Ω
VI = 0V to 28.5V,
±IIB
Input BIas Current
+VCC = 5V, VCM = 0V
IIO
Input Offset Current
Power Supply Rejection Ratio
+VCC = 5V to 30V,
VCM = 0V
VCM
Common Mode Voltage Range
+VCC = 30V
Differential Input Voltage
AVS
Large Signal Gain
(Note 6)
-150
-1.0
nA
1
(Note 6)
-300
-1.0
nA
2, 3
-30
30
nA
1
-100
100
nA
2, 3
dB
1
+VCC = 5V, VCM = 0V
PSRR
VDiff
70
65
+VCC = 15V, RL = 2KΩ,
VO = 1V to 11V
5
(Note 7),
(Note 9)
28.5
V
1
(Note 7),
(Note 9)
28.0
V
2, 3
(Note 10)
32
V
1, 2, 3
50
V/mV
4
25
V/mV
5, 6
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LM158QML
LM158A Electrical Characteristics
SMD 5962–8771002, High Dose Rate
DC Parameters
The following conditions apply, unless otherwise specified.
Symbol
ICC
VOH
VOL
All voltages referenced to device ground.
Max
Units
Subgroups
+VCC = 5V, RL = 100K,
VO = 1.4V
1.2
mA
1, 2, 3
+VCC = 30V, RL = 100K,
VO = 1.4V
3.0
mA
1
4.0
mA
2, 3
Parameter
Conditions
Power Supply Current
Output Voltage High
Output Voltage Low
Notes
Min
+VCC = 30V, RL = 2KΩ
26
V
1, 2, 3
+VCC = 30V, RL = 10KΩ
27
V
1, 2, 3
+VCC = 30V, RL = 10KΩ
+VCC = 30V, ISink = 1µA
+VCC = 5V, RL = 10KΩ
ISink
ISource
Output Sink Current
Output Source Current
40
mV
1
100
mV
2, 3
40
mV
1
100
mV
2, 3
40
mV
1
100
mV
2, 3
+VCC = 15V, VO = 200mV,
+VI = 0V, -VI = +65mV
12
µA
1
+VCC = 15V, VO = 2V,
+VI = 0V, -VI = +65mV
10
mA
1
mA
2, 3
5.0
+VCC = 15V, VO = 2V,
+VI = 0V, -VI = -65mV
-20
mA
1
-10
mA
2, 3
mA
1
IOS
Short Circuit Current
+VCC = 5V, VO = 0V
-60
VIO
Input Offset Voltage
+VCC = 30V, VCM = 0V,
-2.0
2.0
mV
1
RS = 50Ω, VO = 1.4V
-4.0
4.0
mV
2, 3
+VCC = 30V, VCM = 28.5V,
-2.0
2.0
mV
1
-4.0
4.0
mV
2, 3
+VCC = 5V, VCM = 0V,
-2.0
2.0
mV
1
RS = 50Ω, VO = 1.4V
-4.0
4.0
mV
2, 3
dB
1
RS = 50Ω, VO = 1.4V
+VCC = 30V, VCM = 28V,
RS = 50Ω, VO = 1.4V
CMRR
Common Mode Rejection Ratio
+VCC = 30V, RS = 50Ω
VI = 0V to 28.5V,
±IIB
Input BIas Current
+VCC = 5V, VCM = 0V
IIO
Input Offset Current
Power Supply Rejection Ratio
+VCC = 5V to 30V,
VCM = 0V
VCM
Common Mode Voltage Range
+VCC = 30V
Differential Input Voltage
AVS
Large Signal Gain
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(Note 6)
-50
-1.0
nA
1
(Note 6)
-100
-1.0
nA
2, 3
-10
10
nA
1
-30
30
nA
2, 3
dB
1
+VCC = 5V, VCM = 0V
PSRR
VDiff
70
65
+VCC = 15V, RL = 2KΩ,
VO = 1V to 11V
6
(Notes 7,
9)
28.5
V
1
(Notes 7,
9)
28.0
V
2, 3
(Note 10)
32
V
1, 2, 3
50
V/mV
4
25
V/mV
5, 6
LM158QML
SMD 5962–8771002, High Dose Rate
DC Drift Parameters
The following conditions apply, unless otherwise specified. All voltages referenced to device ground.
Delta calculations are performed on QMLV devices at Group B, Subgroup 5 only.
Symbol
VIO
Parameter
Input Offset Voltage
Conditions
Notes
+VCC = 30V, VCM = 0V,
Min
Max
Units
Subgroups
-0.5
0.5
mV
1
-0.5
0.5
mV
1
-0.5
0.5
mV
1
-10
10
nA
1
RS = 50Ω, VO = 1.4V
+VCC = 30V, VCM = 28.5V,
RS = 50Ω, VO = 1.4V
+VCC = 5V, VCM = 0V,
RS = 50Ω, VO = 1.4V
±IIB
Input Bias Current
+VCC = 5V, VCM = 0V
SMD 5962–8771002, High Dose Rate
100K Post Radiation Limits @ +25°C
DC Parameters
The following conditions apply, unless otherwise specified.
Symbol
Parameter
VIO
Input Offset Voltage
(Note 6)
(Note 11)
All voltages referenced to device ground.
Conditions
Notes
Min
Max
Units
Sub groups
(Note 11)
-4.0
4.0
mV
1
(Note 11)
-4.0
4.0
mV
1
(Note 11)
-4.0
4.0
mV
1
+VCC = 5V, VCM = 0V
(Notes 6,
11)
-60
-1.0
nA
1
+VCC = 5V, RL = 100K,
VO = 1.4V
(Note 11)
1.5
mA
1
+VCC = 30V, VCM = 0V,
RS = 50Ω, VO = 1.4V
+VCC = 30V, VCM = 28.5V,
RS = 50Ω, VO = 1.4V
+VCC = 5V, VCM = 0V,
RS = 50Ω, VO = 1.4V
±IIB
Input Bias Current
ICC
Power Supply Current
7
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LM158QML
LM158A Electrical Characteristics
SMD 5962–8771003 ELDRS Free Only
DC Parameters
The following conditions apply, unless otherwise specified.
Symbol
ICC
VOH
VOL
All voltages referenced to device ground.
Max
Units
Subgroups
+VCC = 5V, RL = 100K,
VO = 1.4V
1.2
mA
1, 2, 3
+VCC = 30V, RL = 100K,
VO = 1.4V
3.0
mA
Parameter
Conditions
Power Supply Current
Output Voltage High
Output Voltage Low
Notes
Min
4.0
+VCC = 30V, RL = 2KΩ
26
V
1, 2, 3
+VCC = 30V, RL = 10KΩ
27
V
1, 2, 3
+VCC = 30V, RL = 10KΩ
+VCC = 30V, ISink = 1µA
+VCC = 5V, RL = 10KΩ
ISink
ISource
Output Sink Current
Output Source Current
1,
2, 3
40
mV
1
100
mV
2, 3
40
mV
1
100
mV
2, 3
40
mV
1
100
mV
2, 3
+VCC = 15V, VO = 200mV,
+VI = 0V, -VI = +65mV
12
µA
1
+VCC = 15V, VO = 2V,
+VI = 0V, -VI = +65mV
10
mA
1
mA
2, 3
5.0
+VCC = 15V, VO = 2V,
+VI = 0V, -VI = -65mV
-20
mA
1
-10
mA
2, 3
mA
1
IOS
Short Circuit Current
+VCC = 5V, VO = 0V
-60
VIO
Input Offset Voltage
+VCC = 30V, VCM = 0V,
-2.0
2.0
mV
1
RS = 50Ω, VO = 1.4V
-4.0
4.0
mV
2, 3
+VCC = 30V, VCM = 28.5V,
-2.0
2.0
mV
1
-4.0
4.0
mV
2, 3
+VCC = 5V, VCM = 0V,
-2.0
2.0
mV
1
RS = 50Ω, VO = 1.4V
-4.0
4.0
mV
2, 3
dB
1
RS = 50Ω, VO = 1.4V
+VCC = 30V, VCM = 28V,
RS = 50Ω, VO = 1.4V
CMRR
Common Mode Rejection Ratio
+VCC = 30V, RS = 50Ω
VI = 0V to 28.5V,
±IIB
Input BIas Current
+VCC = 5V, VCM = 0V
IIO
Input Offset Current
Power Supply Rejection Ratio
+VCC = 5V to 30V,
VCM = 0V
VCM
Common Mode Voltage Range
+VCC = 30V
Differential Input Voltage
AVS
Large Signal Gain
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(Note 6)
-50
-1.0
nA
1
(Note 6)
-100
-1.0
nA
2, 3
-10
10
nA
1
-30
30
nA
2, 3
dB
1
+VCC = 5V, VCM = 0V
PSRR
VDiff
70
65
+VCC = 15V, RL = 2KΩ,
VO = 1V to 11V
8
(Note 7),
(Note 9)
28.5
V
1
(Note 7),
(Note 9)
28.0
V
2, 3
(Note 10)
32
V
1, 2, 3
50
V/mV
4
25
V/mV
5, 6
LM158QML
SMD 5962–8771003, ELDRS Free Only
DC Drift Parameters
The following conditions apply, unless otherwise specified. All voltages referenced to device ground.
Delta calculations are performed on QMLV devices at Group B, Subgroup 5 only.
Symbol
VIO
Parameter
Input Offset Voltage
Conditions
Notes
+VCC = 30V, VCM = 0V,
Min
Max
Units
Subgroups
-0.5
0.5
mV
1
-0.5
0.5
mV
1
-0.5
0.5
mV
1
-10
10
nA
1
RS = 50Ω, VO = 1.4V
+VCC = 30V, VCM = 28.5V,
RS = 50Ω, VO = 1.4V
+VCC = 5V, VCM = 0V,
RS = 50Ω, VO = 1.4V
±IIB
Input Bias Current
+VCC = 5V, VCM = 0V
(Note 6)
SMD 5962–8771003, ELDRS Free Only
100K Post Radiation Limits @ +25°C (Note 12)
DC Parameters
The following conditions apply, unless otherwise specified.
Symbol
Parameter
VIO
Input Offset Voltage
All voltages referenced to device ground.
Conditions
+VCC = 30V, VCM = 0V,
Notes
Min
Max
Units
Sub groups
(Note 12)
-4.0
4.0
mV
1
(Note 12)
-4.0
4.0
mV
1
(Note 12)
-4.0
4.0
mV
1
(Notes 6,
12)
-60
-1.0
nA
1
RS = 50Ω, VO = 1.4V
+VCC = 30V, VCM = 28.5V,
RS = 50Ω, VO = 1.4V
+VCC = 5V, VCM = 0V,
RS = 50Ω, VO = 1.4V
±IIB
Input Bias Current
+VCC = 5V, VCM = 0V
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/
θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 4: Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output
current is approximately 40 mA independent of the magnitude of V+. At values of supply voltage in excess of +15V, continuous short-circuits can exceed the
power dissipation ratings and cause eventual destruction. Destructive dissipation can result from simultaneous shorts on all amplifiers.
Note 5: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP
transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action
on the IC chip. This transistor action can cause the output voltages of the op amps to go to the V+voltage level (or to ground for a large overdrive) for the time
duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again
returns to a value greater than −0.3V (at 25°C).
Note 6: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output
so no loading change exists on the input lines.
Note 7: The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V (at 25°C). The upper end of the
common-mode voltage range is V+ −1.5V (at 25°C), but either or both inputs can go to +32V without damage, independent of the magnitude of V+.
Note 8: Human body model, 1.5 kΩ in series with 100 pF.
Note 9: Guaranteed by input offset voltage.
Note 10: Guaranteed parameter not tested.
Note 11: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table.
These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate sensitivity. Radiation end point limits for the noted
parameters are guaranteed only for the conditions as specified in MIL-STD-883, per Test Method 1019, Condition A.
Note 12: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table.
These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a wafer-by-wafer basis, per Test Method 1019, Condition
D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS).
9
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LM158QML
Typical Performance Characteristics
Input Voltage Range
Input Current
20150234
20150235
Supply Current
Voltage Gain
20150236
20150237
Open Loop Frequency Response
Common-Mode Rejection Ratio
20150238
20150239
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Voltage Follower Pulse Response (Small Signal)
20150241
20150240
Large Signal Frequency Response
Output Characteristics Current Sourcing
20150242
20150243
Output Characteristics Current Sinking
Current Limiting
20150244
20150245
11
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LM158QML
Voltage Follower Pulse Response
LM158QML
Application Hints
The LM158 series are op amps which operate with only a
single power supply voltage, have true-differential inputs, and
remain in the linear mode with an input common-mode voltage of 0 VDC. These amplifiers operate over a wide range of
power supply voltage with little change in performance characteristics. At 25°C amplifier operation is possible down to a
minimum supply voltage of 2.3 VDC.
Precautions should be taken to insure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
test socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
Large differential input voltages can be easily accommodated
and, as input differential voltage protection diodes are not
needed, no large input currents result from large differential
input voltages. The differential input voltage may be larger
than V+ without damaging the device. Protection should be
provided to prevent the input voltages from going negative
more than −0.3 VDC (at 25°C). An input clamp diode with a
resistor to the IC input terminal can be used.
To reduce the power supply current drain, the amplifiers have
a class A output stage for small signal levels which converts
to class B in a large signal mode. This allows the amplifiers
to both source and sink large output currents. Therefore both
NPN and PNP external current boost transistors can be used
to extend the power capability of the basic amplifiers. The
output voltage needs to raise approximately 1 diode drop
above ground to bias the on-chip vertical PNP transistor for
output current sinking applications.
For ac applications, where the load is capacitively coupled to
the output of the amplifier, a resistor should be used, from the
output of the amplifier to ground to increase the class A bias
current and prevent crossover distortion. Where the load is
directly coupled, as in dc applications, there is no crossover
distortion.
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Capacitive loads which are applied directly to the output of the
amplifier reduce the loop stability margin. Values of 50 pF can
be accommodated using the worst-case non-inverting unity
gain connection. Large closed loop gains or resistive isolation
should be used if larger load capacitance must be driven by
the amplifier.
The bias network of the LM158 establishes a drain current
which is independent of the magnitude of the power supply
voltage over the range of 3 VDC to 30 VDC.
Output short circuits either to ground or to the positive power
supply should be of short time duration. Units can be destroyed, not as a result of the short circuit current causing
metal fusing, but rather due to the large increase in IC chip
dissipation which will cause eventual failure due to excessive
junction temperatures. Putting direct short-circuits on more
than one amplifier at a time will increase the total IC power
dissipation to destructive levels, if not properly protected with
external dissipation limiting resistors in series with the output
leads of the amplifiers. The larger value of output source current which is available at 25°C provides a larger output current
capability at elevated temperatures (see typical performance
characteristics) than a standard IC op amp.
The circuits presented in the section on typical applications
emphasize operation on only a single power supply voltage.
If complementary power supplies are available, all of the standard op amp circuits can be used. In general, introducing a
pseudo-ground (a bias voltage reference of V+/2) will allow
operation above and below this value in single power supply
systems. Many application circuits are shown which take advantage of the wide input common-mode voltage range which
includes ground. In most cases, input biasing is not required
and input voltages which range to ground can easily be accommodated.
12
LM158QML
Typical Single-Supply Applications
(V+ = 5.0 VDC)
Non-Inverting DC Gain (0V Output)
20150206
20150207
*R not needed due to temperature independent IIN
DC Summing Amplifier
(VIN'S ≥ 0 VDC and VO ≥ 0 VDC)
Power Amplifier
20150209
20150208
VO = 0 VDC for VIN = 0 VDC
AV = 10
Where: VO = V1 + V2 −V3 − V4
(V1 + V2) ≥ (V3 + V4) to keep VO > 0 VDC
13
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LM158QML
“BI-QUAD” RC Active Bandpass Filter
20150210
fo = 1 kHz
Q = 50
Av = 100 (40 dB)
Fixed Current Sources
Lamp Driver
20150212
20150211
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14
LM158QML
LED Driver
Current Monitor
20150213
20150214
*(Increase R1 for IL small)
VL ≤ V+ −2V
Driving TTL
Voltage Follower
20150215
20150217
VO = VIN
Pulse Generator
20150216
15
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LM158QML
Squarewave Oscillator
Pulse Generator
20150218
20150219
Low Drift Peak Detector
20150220
HIGH ZIN
LOW ZOUT
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16
LM158QML
High Compliance Current Sink
Comparator with Hysteresis
20150222
20150221
IO = 1 amp/volt VIN
(Increase RE for IO small)
Voltage Controlled Oscillator (VCO)
20150223
*WIDE CONTROL VOLTAGE RANGE: 0 VDC ≤ VC ≤ 2 (V+ −1.5V DC)
17
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LM158QML
AC Coupled Inverting Amplifier
20150224
Ground Referencing a Differential Input Signal
20150225
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18
LM158QML
AC Coupled Non-Inverting Amplifier
20150226
Av = 11 (As Shown)
DC Coupled Low-Pass RC Active Filter
20150227
fo = 1 kHz
Q=1
AV = 2
19
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LM158QML
Bandpass Active Filter
20150228
fo = 1 kHz
Q = 25
High Input Z, DC Differential Amplifier
20150229
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20
LM158QML
Photo Voltaic-Cell Amplifier
Bridge Current Amplifier
20150230
20150233
High Input Z Adjustable-Gain
DC Instrumentation Amplifier
20150231
21
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LM158QML
Using Symmetrical Amplifiers to
Reduce Input Current (General Concept)
20150232
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22
Date Released Revision
Section
Originator
Changes
07/12/05
A
New release to corporate fomat.
L. Lytle
2 MDS datasheets converted into one
Corporate datasheet format. MNLM158-X-RH
Rev 1C1 & MNLM158-X Rev 1A1 will be
archived.
01/09/06
B
Typical Single-Supply Applications
R. Malone
Correct an equation From: V1 + V2 + V3 + V4
To: V1 + V2 - V3 - V4 (right after art -08, pg
12). Reason: To reflect same correction made
in commercial data sheet. Revision A will be
archived.
01/27/06
C
Features, Ordering Information Table
and Post Radiation Electrical's
Larry McGee
Added reference to radiation, NSID's to
Ordering Table and Post Rad limits for 100k
10/05/06
D
Connection Diagram, page 2
R. Malone
Corrected typo title for Ceramic SOIC.
Revision C will be Archived
08/21/08
E
Features, Ordering Information,
Electrical Sections and Notes.
Larry McGee
Added reference to ELDRS, NSID's to
Ordering Table, and ELDRS Electricals.
Deleted 50k Rad NSID's and Post Rad table.
Revision D will be Archived.
01/13/09
F
Ordering Information, ELDRS
Electrical Section, Notes 11 and 12
Larry McGee
Deleted NSID's LM158AH-QMLV and
LM158AWG-QMLV code K. Changed DC and
Post Rad ELDRS Electricals. Changed Notes
11 and 12 wording. Revision E will be
Archived.
23
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LM158QML
Revision History
LM158QML
Physical Dimensions inches (millimeters) unless otherwise noted
Metal Can Package (H)
NS Package Number H08C
CERDIP Package (J)
NS Package Number J08A
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24
LM158QML
10LD Ceramic SOIC Package
NS Package Number WG10A
25
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LM158QML Low Power Dual Operational Amplifiers
Notes
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