DATA SHEET MOS INTEGRATED CIRCUIT MC-458CA727 8M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE ★ Description The MC-458CA727EFA and MC-458CA727PFA are 8,388,608 words by 72 bits synchronous dynamic RAM module on which 5 pieces of 128M SDRAM : µPD45128163 are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. Features • 8,388,608 words by 72 bits organization (ECC Type) • Clock frequency and access time from CLK Part number /CAS latency MC-458CA727EFA-A75 ★ ★ MC-458CA727PFA-A75 ★ Clock frequency Access time from CLK (MAX.) (MAX.) CL = 3 133 MHz 5.4 ns CL = 2 100 MHz 6.0 ns CL = 3 133 MHz 5.4 ns CL = 2 100 MHz 6.0 ns • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface • Possible to assert random column address in every cycle • Quad internal banks controlled by BA0 and BA1 (Bank Select) • Programmable burst-length (1, 2, 4, 8 and full page) • Programmable wrap sequence (sequential / interleave) ★ • Programmable /CAS latency (2, 3) • Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • All DQs have 10 Ω ± 10 % of series resistor • Single 3.3 V ± 0.3 V power supply • LVTTL compatible • 4,096 refresh cycles /64 ms • Burst termination by Burst Stop command and Precharge command • 168-pin dual in-line memory module (Pin pitch = 1.27 mm) • Unbuffered type • Serial PD The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14278EJ3V0DS00 (3rd edition) Date Published January 2000 NS CP(K) Printed in Japan The mark • shows major revised points. © 1999 MC-458CA727 Ordering Information Part number Clock frequency Package Mounted devices (MAX.) MC-458CA727EFA-A75 133 MHz 168-pin Dual In-line Memory Module (Socket Type) ★ MC-458CA727PFA-A75 Edge connector : Gold plated 25.4 mm height 2 Data Sheet M14278EJ3V0DS00 5 pieces of µPD45128163G5 (Rev. E) (10.16 mm (400) TSOP (II)) 5 pieces of µPD45128163G5 (Rev. P) (10.16 mm (400) TSOP (II)) MC-458CA727 Pin Configuration 168-pin Dual In-line Memory Module Socket Type (Edge connector : Gold plated) /××× indicates active low signal. 85 86 87 88 89 90 91 92 93 94 VSS DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 10 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 DQ40 DQ8 VSS VSS DQ41 DQ9 DQ42 DQ10 DQ43 DQ11 DQ44 DQ12 DQ45 DQ13 Vcc Vcc DQ46 DQ14 DQ47 DQ15 CB4 CB0 CB5 CB1 VSS VSS NC NC NC NC Vcc Vcc /WE /CAS DQMB0 DQMB4 DQMB1 DQMB5 /CS0 NC NC /RAS VSS VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA0 (A13) BA1 (A12) A11 Vcc Vcc 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 CLK1 NC VSS CKE0 NC DQMB6 DQMB7 NC Vcc NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 Vcc 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 Vcc CLK0 VSS NC /CS2 DQMB2 DQMB3 NC Vcc NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL Vcc Data Sheet M14278EJ3V0DS00 A0 - A11 : Address Inputs [Row: A0 - A11, Column: A0 - A8] BA0 (A13), BA1 (A12) : SDRAM Bank Select DQ0 - DQ63, CB0 - CB7 : Data Inputs/Outputs CLK0 - CLK3 : Clock Input CKE0 : Clock Enable Input /CS0, /CS2 : Chip Select Input /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQMB0 - DQMB7 : DQ Mask Enable SA0 - SA2 : Address Input for EEPROM SDA : Serial Data I/O for PD SCL : Clock Input for PD VCC : Power Supply VSS : Ground WP : Write Protect NC : No Connection 3 MC-458CA727 ★ Block Diagram /WE /CS0 /CS2 DQMB 4 LDQM DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 38 DQ 37 DQ 39 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQMB 0 UDQM DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQMB 5 LDQM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /CS /WE DQMB 6 D1 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 /CS /WE UDQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 LDQM D5 UDQM DQMB 3 UDQM DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 /CS /WE CLK0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 CLK2 CLK : D4, D5 15 pF A0 - A11: D1 - D5 BA0 A13: D1 - D5 BA1 A12: D1- D5 /RAS /RAS: D1 - D5 /CAS /CAS: D1 - D5 CKE0 CKE: D1 - D5 CLK1, CLK3 10 pF SERIAL PD SDA VCC D1- D5 C V SS SCL WP A0 A1 A2 D1- D5 47 kΩ SA0 SA1 SA2 Remarks 1. The value of all resistors is 10 Ω except WP. 2. D1 - D5 : µPD45128163 (2M words × 16 bits × 4 banks) 4 A0 - A11 CLK : D1 - D3 10 pF D3 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 /CS /WE DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQM CB7 CB6 CB4 CB5 CB3 CB2 CB1 CB0 DQMB 2 DQMB 7 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 UDQM /CS /WE D4 D2 DQMB 1 LDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 Data Sheet M14278EJ3V0DS00 MC-458CA727 Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings ★ Parameter Symbol Voltage on power supply pin relative to GND Voltage on input pin relative to GND Condition Rating Unit VCC –0.5 to +4.6 V VT –0.5 to +4.6 V Short circuit output current IO 50 mA Power dissipation PD 5 W Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg –55 to +125 °C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter ★ Symbol Condition MIN. TYP. 3.3 MAX. Unit Supply voltage VCC 3.0 3.6 V High level input voltage VIH 2.0 VCC + 0.3 V Low level input voltage VIL −0.3 +0.8 V Operating ambient temperature TA 0 70 °C Capacitance (TA = 25 °C, f = 1 MHz) Parameter Input capacitance Data input/output capacitance Symbol Test condition MIN. CI1 A0 - A11, BA0(A13), BA1(A12), /RAS, /CAS, /WE CI2 MAX. Unit 25 44 pF CLK0, CLK2 24 40 CI3 CKE0 24 40 CI4 /CS0, /CS2 12 24 CI5 DQMB0 - DQMB7 7 16 CI/O DQ0 - DQ63, CB0 - CB7 7 13 Data Sheet M14278EJ3V0DS00 TYP. pF 5 MC-458CA727 DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter ★ Operating current Precharge standby current in ★ power down mode Precharge standby current in Symbol ICC1 ICC2P Test condition MIN. ICC2N power down mode Active standby current in ★ CBR (Auto) refresh current /CAS latency = 3 575 5 mA 5 CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.), 100 mA ICC3P 40 CKE ≤ VIL(MAX.), tCK = 15 ns 25 ICC3PS CKE ≤ VIL(MAX.), tCK = ∞ ICC3N mA 20 CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.), 150 mA Input signals are changed one time during 30 ns. ICC4 ICC5 tCK ≥ tCK(MIN.), IO = 0 mA tRC ≥ tRC(MIN.) ★ 100 /CAS latency = 2 725 /CAS latency = 3 925 /CAS latency = 2 1,150 /CAS latency = 3 1,200 ICC6 CKE ≤ 0.2 V Input leakage current II(L) VI = 0 to 3.6 V, All other pins not under test = 0 V Output leakage current IO(L) DOUT is disabled, VO = 0 to 3.6 V High level output voltage VOH IO = –4 mA 2.4 Low level output voltage VOL IO = +4 mA Self refresh current 1 tRC ≥ tRC(MIN.), IO = 0 mA CKE ≤ VIL(MAX.), tCK = 15 ns ICC3NS CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable. Operating current (Burst mode) mA 550 Input signals are changed one time during 30 ns. non power down mode ★ Notes /CAS latency = 2 ICC2NS CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable. Active standby current in Unit Burst length = 1 ICC2PS CKE ≤ VIL(MAX.), tCK = ∞ non power down mode MAX. mA 2 mA 3 10 mA –5 +5 µA –1.5 +1.5 µA V 0.4 V Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.). 6 Data Sheet M14278EJ3V0DS00 MC-458CA727 AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) ★ Test Conditions Parameter AC high level input voltage / low level input voltage Value Unit 2.4 / 0.4 V 1.4 V 1 ns 1.4 V Input timing measurement reference level Transition time (Input rise and fall time) Output timing measurement reference level tCK tCH CLK tCL 2.4 V 1.4 V 0.4 V tSETUP tHOLD Input 2.4 V 1.4 V 0.4 V tAC tOH Output Data Sheet M14278EJ3V0DS00 7 MC-458CA727 ★ Synchronous Characteristics Parameter Clock cycle time Access time from CLK Symbol -A75 Unit MIN. MAX. /CAS latency = 3 tCK3 7.5 (133 MHz) ns /CAS latency = 2 tCK2 10 (100 MHz) ns /CAS latency = 3 tAC3 5.4 ns 1 /CAS latency = 2 tAC2 6.0 ns 1 CLK high level width tCH 2.5 ns CLK low level width tCL 2.5 ns Data-out hold time tOH 3.0 ns Data-out low-impedance time tLZ 0 ns /CAS latency = 3 tHZ3 3.0 5.4 ns /CAS latency = 2 tHZ2 3.0 6.0 ns Data-in setup time tDS 1.5 ns Data-in hold time tDH 0.8 ns Address setup time tAS 1.5 ns Address hold time tAH 0.8 ns CKE setup time tCKS 1.5 ns CKE hold time tCKH 0.8 ns CKE setup time (Power down exit) tCKSP 1.5 ns Command (/CS0, /CS2, /RAS, /CAS, /WE, tCMS 1.5 ns tCMH 0.8 ns Data-out high-impedance time DQMB0 - DQMB7) setup time Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 - DQMB7) hold time Note 1. Output load Z = 50 Ω Output 50 pF Remark These specifications are applied to the monolithic device. 8 Note Data Sheet M14278EJ3V0DS00 1 MC-458CA727 ★ Asynchronous Characteristics Parameter Symbol -A75 MIN. Unit ACT to REF/ACT command period (operation) tRC 67.5 ns REF to REF/ACT command period (refresh) tRC1 67.5 ns ACT to PRE command period tRAS 45 PRE to ACT command period tRP 20 ns Delay time ACT to READ/WRITE command tRCD 20 ns ACT(one) to ACT(another) command period tRRD 15 ns Data-in to PRE command period Note MAX. 120,000 ns tDPL 8 ns Data-in to ACT(REF) command /CAS latency = 3 tDAL3 1CLK+22.5 ns 1 period (Auto precharge) /CAS latency = 2 tDAL2 1CLK+20 ns 1 tRSC 2 CLK tT 0.5 Mode register set cycle time Transition time Refresh time (4,096 refresh cycles) tREF 30 ns 64 ms Note This device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125 MHz operation. Data Sheet M14278EJ3V0DS00 9 MC-458CA727 Serial PD (1/2) Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 0 Defines the number of bytes written into 80H 1 0 0 0 0 0 0 0 128 bytes 08H 0 0 0 0 1 0 0 0 256 bytes serial PD memory 1 Total number of bytes of serial PD memory 2 Fundamental memory type 04H 0 0 0 0 0 1 0 0 SDRAM 3 Number of rows 0CH 0 0 0 0 1 1 0 0 12 rows 4 Number of columns 09H 0 0 0 0 1 0 0 1 9 columns 5 Number of banks 01H 0 0 0 0 0 0 0 1 1 bank 6 Data width 48H 0 1 0 0 1 0 0 0 72 bits 7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0 8 Voltage interface 01H 0 0 0 0 0 0 0 1 LVTTL 9 CL = 3 Cycle time 75H 0 1 1 1 0 1 0 1 7.5 ns 10 CL = 3 Access time 54H 0 1 0 1 0 1 0 0 5.4 ns 11 DIMM configuration type 02H 0 0 0 0 0 0 1 0 ECC 12 Refresh rate/type 80H 1 0 0 0 0 0 0 0 Normal ★ 13 SDRAM width 10H 0 0 0 1 0 0 0 0 ×16 ★ 14 Error checking SDRAM width 10H 0 0 0 1 0 0 0 0 ×16 15 Minimum clock delay 01H 0 0 0 0 0 0 0 1 1 clock 16 Burst length supported 8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F 17 Number of banks on each SDRAM 04H 0 0 0 0 0 1 0 0 4 banks 18 /CAS latency supported 06H 0 0 0 0 0 1 1 0 2, 3 19 /CS latency supported 01H 0 0 0 0 0 0 0 1 0 20 /WE latency supported 01H 0 0 0 0 0 0 0 1 0 21 SDRAM module attributes 00H 0 0 0 0 0 0 0 0 22 SDRAM device attributes : General 0EH 0 0 0 0 1 1 1 0 ★ 23 CL = 2 Cycle time A0H 1 0 1 0 0 0 0 0 10 ns ★ 24 CL = 2 Access time 60H 0 1 1 0 0 0 0 0 6 ns 00H 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 25-26 ★ ★ 10 27 tRP(MIN.) 14H 28 tRRD(MIN.) 0FH 0 0 0 0 1 1 1 1 15 ns 29 tRCD(MIN.) 14H 0 0 0 1 0 1 0 0 20 ns 30 tRAS(MIN.) 2DH 0 0 1 0 1 1 0 1 45 ns 31 Module bank density 10H 0 0 0 1 0 0 0 0 64M bytes Data Sheet M14278EJ3V0DS00 20 ns MC-458CA727 (2/2) Byte No. 32 Function Described Command and address signal input Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 15H 0 0 0 1 0 1 0 1 1.5 ns 08H 0 0 0 0 1 0 0 0 0.8 ns 15H 0 0 0 1 0 1 0 1 1.5 ns 0.8 ns setup time 33 Command and address signal input hold time 34 Data signal input setup time 35 Data signal input hold time 36-61 08H 0 0 0 0 1 0 0 0 00H 0 0 0 0 0 0 0 0 ★ 62 SPD revision 12H 0 0 0 1 0 0 1 0 ★ 63 Checksum for bytes 0 - 62 C0H 1 1 0 0 0 0 0 0 64-71 72 1.2 Manufacture’s JEDEC ID code Manufacturing location 73-90 Manufacture’s P/N 91-92 Revision code 93-94 Manufacturing date 95-98 Assembly serial number 99-125 Mfg specific 126 Intel specification frequency 64H 0 1 1 0 0 1 0 0 127 Intel specification /CAS latency support A5H 1 0 1 0 0 1 0 1 Timing Chart Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E). Data Sheet M14278EJ3V0DS00 11 MC-458CA727 ★ Package Drawing 168-PIN DUAL IN-LINE MODULE (SOCKET TYPE) A(AREA B) Y N Z M1(AREA B) Q R M L M2(AREA A) S A B H (OPTIONAL HOLES) T U K J C B I G E D A1(AREA A) ITEM A detail of A part detail of B part D2 W V P X 12 D1 Data Sheet M14278EJ3V0DS00 MILLIMETERS 133.35 A1 133.35±0.13 B C 11.43 36.83 D 6.35 D1 2.00 D2 3.125 E G 54.61 6.35 H 1.27 (T.P.) I J 8.89 24.495 K L 42.18 17.78 M 25.4±0.13 M1 M2 N 5.62 19.78 2.80 MAX. P 1.00 Q R S T R2.0 4.00±0.10 φ 3.00 1.27±0.10 U V 4.0 MIN. 0.20±0.15 W X 1.00±0.05 2.54±0.10 Y 3.00 MIN. Z 3.00 MIN. M168S-50A102 MC-458CA727 [ MEMO ] Data Sheet M14278EJ3V0DS00 13 MC-458CA727 [ MEMO ] 14 Data Sheet M14278EJ3V0DS00 MC-458CA727 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14278EJ3V0DS00 15 MC-458CA727 CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8