EON EN29PL032A

EN29PL032A
EN29PL032A
32 Mbit (2 M x 16-Bit) CMOS 3.0 Volt- only,
Simultaneous-Read/Write Flash Memory
Distinctive Characteristics
Software Features
Architectural Advantages
• Software command-set compatible with
JEDEC 42.4 standard
• CFI (Common Flash Interface) compliant
- Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
• Erase Suspend / Erase Resume
- Suspends an erase operation to allow read or
program operations in other sectors of same
bank
• Program Suspend / Program Resume
- Suspends a program operation to allow read
operation from sectors other than the one
being programmed
• 32 Mbit Page Mode devices
- Page size of 4 words: Fast page read access
from random locations within the page
• Single power supply operation
- Voltage range of 2.7V to 3.3V valid for MCP
product
- Single Voltage, 2.7V to 3.6V for Read and Write
operations
• Simultaneous Read/Write Operation
- Data can be continuously read from one bank
while executing erase/ program functions in
another bank
- Zero latency switching from write to read
operations
• FlexBank Architecture
- 4 separate banks, with up to two simultaneous
operations per device
- Bank A: 4 Mbit (4 Kw x 8 and 32 Kw x 7)
- Bank B: 12 Mbit (32 Kw x 24)
- Bank C: 12 Mbit (32 Kw x 24)
- Bank D: 4 Mbit (4 Kw x 8 and 32 Kw x 7)
• Secured Silicon Sector region
- 64 words Secured Silicon Sector region
• Both top and bottom boot blocks in one device
• Cycling Endurance: 100K cycles per sector
typical
Hardware Features
• Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting
program or erase cycle completion
• Hardware reset pin (RESET#)
- Hardware method to reset the device to reading
array data
• WP#/ ACC (Write Protect/Acceleration) input
- At VIL, hardware level protection for the first and
last two 4K word sectors.
- At VIH, allows removal of sector protection
- At VHH, provides accelerated programming in a
factory setting
• Persistent Sector Protection
- A command sector protection method to lock
combinations of individual sectors and sector
groups to prevent program or erase operations
within that sector
- Sectors can be locked and unlocked in-system at
VCC level
• Package options
- 48-pin TSOP-1
Performance Characteristics
•
•
-
High Performance
Page access times as fast as 25 ns
Random access times as fast as 70 ns
Power consumption (typical values at 10 MHz)
45 mA active read current
17 mA program/erase current
0.2 µA typical standby mode current
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
GENERAL DESCRIPTION
The EN29PL032A is a 32 Mega bit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash
memory device organized as 2 Mega words. The devices are offered in the following packages: 48-pin
TSOP
The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in
standard EPROM programmers. An 11.0 volt VPP is not required for write or erase operations.
The device offers fast page access times of 25 ns, with corresponding random access times of 70 ns,
respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#)
controls.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
1. Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory
space into 4 banks, which can be considered to be four separate memory arrays as far as certain
operations are concerned. The device can improve overall system performance by allowing a host
system to program or erase in one bank, then immediately and simultaneously read from another bank
with zero latency (with two simultaneous operations operating at any one time). This releases the
system from waiting for the completion of a program or erase operation, greatly improving system
performance.
The device can be organized in both top and bottom sector configurations. The banks are organized
as follows:
Bank
Sectors
A
4 Mbit (4 Kw x 8 and 32 Kw x 7)
B
12 Mbit (32 Kw x 24)
C
12 Mbit (32 Kw x 24)
D
4 Mbit (4 Kw x 8 and 32 Kw x 7)
1.1 Page Mode Features
The page size is 4 words. After initial page access is accomplished, the page mode operation provides
fast read access speed of random locations within that page.
1.2 Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions.
Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash
standard. Commands are written to the command register using standard microprocessor write timing.
Register contents serve as inputs to an internal state-machine that controls the erase and programming
circuitry. Write cycles also internally latch addresses and data needed for the programming and erase
operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. The Accelerated Program
mode facilitates faster programming times by requiring only two write cycles to program data instead of
four. Device erasure occurs by executing the erase command sequence.
The host system can detect whether a program or erase operation is complete by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the
device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write
operations during power transitions. The hardware sector protection feature disables both program and
erase operations in any combination of sectors of memory. This can be achieved in-system or via
programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of
time to read data from, or program data to, any sector that is not selected for erasure. True background
erase can thus be achieved. If a read is needed from the Secured Silicon Sector area (One Time
Program area) after an erase suspend, then the user must use the proper command sequence to enter
and exit this region.
The Program Suspend/Program Resume feature enables the user to hold the program operation to
read data from any sector that is not selected for programming. If a read is needed from the Secured
Silicon Sector area, Persistent Protection area, or the CFI area, after a program suspend, then the user
must use the proper command sequence to enter and exit this region.
The device offers two power-saving features. When addresses have been stable for a specified amount
of time, the device enters the automatic sleep mode. The system can also place the device into the
standby mode. Power consumption is greatly reduced in both these modes.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
Purpose
Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking
on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and
the compositions of the ICs. Eon is still keeping the promise of quality for all the products with
the same as that of Eon delivered before. Please be advised with the change and appreciate
your kindly cooperation and fully support Eon’s product family.
Eon products’ Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX
Lot Number: XXXXX
Date Code:
XXXXX
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
2. Ordering Information
EN29PL032A
-
70
T
I
P
PACKAGING CONTENT
P = RoHS compliant
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
PACKAGE
T = 48-pin TSOP
SPEED
70 = 70ns
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
29PL = FLASH, 3.0V Read Program Erase,
Simultaneous-Read/Write, Page-Mode
032 = 32 Megabit (2 M x 16-Bit)
A = version identifier
3. Product Selector Guide
Part Number
Speed Option
EN29PL032A
VCC = 2.7 V – 3.6 V
70
Max Access Time, ns (tACC)
70
Max CE# Access , ns (tCE)
Max Page Access, ns (tPACC)
25
Max OE# Access, ns (tOE)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
4. BLOCK DIAGRAM
Notes
1.
2.
RY/BY# is an open drain output.
Amax = A20
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
6
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
5. Simultaneous Read/Write Block Diagram
Note
Amax = A20
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
7
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
6. Connection Diagrams
Figure 6.1 48-pin TSOP
7. Pin Description
Amax–A0
Address bus
DQ15–DQ0
16-bit data inputs/outputs/float
CE#
Chip Enable Inputs
OE#
Output Enable Input
WE#
Write Enable
VSS
Device Ground
NC
Pin Not Connected Internally
Ready/Busy output and open drain.
When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/ BY#=
VOL, the device is either executing an embedded algorithm or the device is executing a hardware
reset operation.
RY/BY#
WP#/ACC
Write Protect/Acceleration Input.
When WP#/ACC= VIL, the highest and lowest two 4K-word sectors are write protected regardless of
other sector protection configurations. When WP#/ACC= VIH, these sector are unprotected unless
the PPB is programmed. When WP#/ACC= 9.0V, program and erase operations are accelerated.
VCC
Chip Power Supply
(2.7 V to 3.6 V)
RESET#
Hardware Reset Pin
Note
Amax = A20
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
8
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
8. Logic Symbol
Note: Amax = A20
9. Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated
through the internal command register. The command register itself does not occupy any addressable
memory location. The register is a latch used to store the commands, along with the address and data
information needed to execute the command. The contents of the register serve as inputs to the internal
state machine. The state machine outputs dictate the function of the device. Table 9.1 lists the device
bus operations, the inputs and control levels they require, and the resulting output. The following
subsections describe each of these operations in further detail.
Table 9.1 Device Bus Operations
Operation
CE#
Read
L
Write
L
Standby
Vcc±0.3 V
Output Disable
L
Reset
X
Temporary Sector
X
Unprotect (High Voltage)
OE#
L
H
X
H
X
WE#
H
L
X
H
X
RESET#
H
H
Vcc ±0.3 V
H
L
WP#/ACC
X
X (Note 2)
X (Note 2)
X
X
Addresses
(Amax–A0)
AIN
AIN
X
X
X
DQ15–
DQ0
DOUT
DIN
High-Z
High-Z
High-Z
X
X
VID
X
AIN
DIN
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = VHH = 8.5–9.5 V, X = Don’t Care, SA = Sector Address, AIN =
Address In, DIN = Data In, DOUT = Data Out
Notes
1.
2.
The sector protect and sector unprotect functions may also be implemented via programming equipment.
See High Voltage Sector Protection
WP#/ACC must be high when writing to upper two and lower two sectors.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
9
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
9.1 Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appropriate CE# pins. CE# is
the power control. OE# is the output control and gates array data to the output pins. WE# should remain
at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the memory content occurs during the power transition. No
command is necessary in this mode to obtain array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs produce valid data on the device data outputs.
Each bank remains enabled for read access until the command register contents are altered.
Refer to Table 20.3 for timing specifications and to Figure 20.3 for the timing diagram. ICC1 in the DC
Characteristics table represents the active current specification for reading array data.
9.1.1 Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The
chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data
at the output inputs. The output enable access time is the delay from the falling edge of the OE#
to valid data at the output inputs (assuming the addresses have been stable for at least tACC–tOE
time).
9.1.2 Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM
read operation. This mode provides faster read access speed for random locations within a page.
Address bits Amax–A2 select a 4 word page, and address bits A1–A0 select a specific word
within that page. This is an asynchronous operation with the microprocessor supplying the
specific word location.
The random or initial page access is tACC or tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When
CE# is deasserted (=VIH), the reassertion of CE# for subsequent access has access time of tACC
or tCE. Here again, CE# selects the device and OE# is the output control and should be used to
gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by
keeping Amax–A2 constant and changing A1–A0 to select the specific word within that page.
Table 9.2 Page Select
Word
A1
A0
Word 0
Word 1
0
0
0
1
Word 2
1
0
Word 3
1
1
9.2 Simultaneous Read/Write Operation
In addition to the conventional features (read, program, erase-suspend read, erase-suspend program,
and program-suspend read), the device is capable of reading data from one bank of memory while a
program or erase operation is in progress in another bank of memory (simultaneous operation). The
bank can be selected by bank addresses (A20–A18) with zero latency.
The simultaneous operation can execute multi-function mode in the same bank.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
Table 9.3 Bank Select
Bank
A20–A18
Bank A
Bank B
000
001, 010, 011
Bank C
100, 101, 110
Bank D
111
9.3 Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and
erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Accelerated Program mode to facilitate faster programming. Once a bank enters
the Accelerated Program mode, only two write cycles are required to program a word, instead of four.
Word Program Command Sequence has details on programming data to the device using both
standard and Accelerated Program command sequences.
An erase operation can erase one sector or the entire device. Table 9.4 indicates the set of address
space that each sector occupies. A “bank address” is the set of address bits required to uniquely select
a bank. Similarly, a “sector address” refers to the address bits required to uniquely select a sector.
Command Definitions has details on erasing a sector or the entire chip, or suspending / resuming the
erase operation.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. See
the timing specification tables and timing diagrams in section Reset for write operations.
9.3.1 Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This function is
primarily intended to allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned
Accelerated Program mode, temporarily unprotects any protected sectors, and uses the higher
voltage on the pin to reduce the time required for program operations. The system would use a
two-cycle program command sequence as required by the Accelerated Program mode.
Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must
not be asserted on WP#/ACC for operations other than accelerated programming, or device
damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That
is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the
device may result.
9.3.2 Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode.
The system can then read autoselect codes from the internal register (which is separate from the
memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to section
9.8 and section 15.3 for more information.
9.4 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3
V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater.
The device requires standard access time (tCE) for read access when the device is in either of these
standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
ICC3 in DC Characteristics represents the CMOS standby current specification.
9.5 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new
data when addresses are changed. While in sleep mode, output data is latched and always available to
the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces
current to the stated sleep mode specification. ICC5 in DC Characteristics represents the automatic sleep
mode current specification.
9.6 RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was
interrupted should be reinitiated once the device is ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the
device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the
standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until
the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms).
The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET#
is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation
is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH
after the RESET# pin returns to VIH.
Refer to the tables in AC Characteristic for RESET# parameters and to Figure 20.5 for the timing
diagram.
9.7 Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#)
are placed in the highest Impedance state
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
12
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
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EN29PL032A
Table 9.4 Sector Architecture (Sheet 1 of 2)
Bank
Bank
A
Bank
B
Sector
Sector Address (A20-A12)
Sector Size (Kwords)
Address Range (x16)
SA0
000000000
4
000000h–000FFFh
SA 1
000000001
4
001000h–001FFFh
SA 2
000000010
4
002000h–002FFFh
SA 3
000000011
4
003000h–003FFFh
SA 4
000000100
4
004000h–004FFFh
SA 5
000000101
4
005000h–005FFFh
SA 6
000000110
4
006000h–006FFFh
SA 7
000000111
4
007000h–007FFFh
SA 8
000001XXX
32
008000h–00FFFFh
SA 9
000010XXX
32
010000h–017FFFh
SA 10
000011XXX
32
018000h–01FFFFh
SA 11
000100XXX
32
020000h–027FFFh
SA 12
000101XXX
32
028000h–02FFFFh
SA 13
000110XXX
32
030000h–037FFFh
SA 14
000111XXX
32
038000h–03FFFFh
SA 15
001000XXX
32
040000h–047FFFh
SA16
001001XXX
32
048000h–04FFFFh
SA 17
001010XXX
32
050000h–057FFFh
SA 18
001011XXX
32
058000h–05FFFFh
SA 19
001100XXX
32
060000h–067FFFh
SA 20
001101XXX
32
068000h–06FFFFh
SA 21
001110XXX
32
070000h–077FFFh
SA 22
001111XXX
32
078000h–07FFFFh
SA 23
010000XXX
32
080000h–087FFFh
SA 24
010001XXX
32
088000h–08FFFFh
SA25
010010XXX
32
090000h–097FFFh
SA 26
010011XXX
32
098000h–09FFFFh
SA 27
010100XXX
32
0A0000h–0A7FFFh
SA 28
010101XXX
32
0A8000h–0AFFFFh
SA 29
010110XXX
32
0B0000h–0B7FFFh
SA 30
010111XXX
32
0B8000h–0BFFFFh
SA 31
011000XXX
32
0C0000h–0C7FFFh
SA 32
011001XXX
32
0C8000h–0CFFFFh
SA 33
011010XXX
32
0D0000h–0D7FFFh
SA 34
011011XXX
32
0D8000h–0DFFFFh
SA 35
011100XXX
32
0E0000h–0E7FFFh
SA 36
SA 37
SA 38
011101XXX
011110XXX
011111XXX
32
32
32
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
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EN29PL032A
Table 9.4 Sector Architecture (Sheet 2 of 2)
Bank
Bank
C
Bank
D
Sector
Sector Address (A20-A12)
Sector Size (Kwords)
Address Range (x16)
SA39
100000XXX
32
100000h–107FFFh
SA40
SA41
100001XXX
100010XXX
32
32
108000h–10FFFFh
110000h–117FFFh
SA42
100011XXX
32
118000h–11FFFFh
SA43
100100XXX
32
120000h–127FFFh
SA44
100101XXX
32
128000h–12FFFFh
SA45
100110XXX
32
130000h–137FFFh
SA46
100111XXX
32
138000h–13FFFFh
SA47
101000XXX
32
140000h–147FFFh
SA48
101001XXX
32
148000h–14FFFFh
SA49
SA50
101010XXX
101011XXX
32
32
150000h–157FFFh
158000h–15FFFFh
SA51
101100XXX
32
160000h–167FFFh
SA52
101101XXX
32
168000h–16FFFFh
SA53
101110XXX
32
170000h–177FFFh
SA54
101111XXX
32
178000h–17FFFFh
SA55
110000XXX
32
180000h–187FFFh
SA56
110001XXX
32
188000h–18FFFFh
SA57
110010XXX
32
190000h–197FFFh
SA58
110011XXX
32
198000h–19FFFFh
SA59
110100XXX
32
1A0000h–1A7FFFh
SA60
110101XXX
32
1A8000h–1AFFFFh
SA61
110110XXX
32
1B0000h–1B7FFFh
SA62
110111XXX
32
1B8000h–1BFFFFh
SA63
111000XXX
32
1C0000h–1C7FFFh
SA64
111001XXX
32
1C8000h–1CFFFFh
SA65
111010XXX
32
1D0000h–1D7FFFh
SA66
111011XXX
32
1D8000h–1DFFFFh
SA67
111100XXX
32
1E0000h–1E7FFFh
SA68
111101XXX
32
1E8000h–1EFFFFh
SA69
111110XXX
32
1F0000h–1F7FFFh
SA70
111111000
4
1F8000h–1F8FFFh
SA71
111111001
4
1F9000h–1F9FFFh
SA72
111111010
4
1FA000h–1FAFFFh
SA73
111111011
4
1FB000h–1FBFFFh
SA74
111111100
4
1FC000h–1FCFFFh
SA75
111111101
4
1FD000h–1FDFFFh
SA76
111111110
4
1FE000h–1FEFFFh
SA77
111111111
4
1FF000h–1FFFFFh
Table 9.5 Secured Silicon Sector Addresses
Sector Size
64 words
Customer-Lockable Area
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
14
Address Range
000040h-00007Fh
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
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EN29PL032A
9.8 Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Address
pins must be as shown in Table 9.6. In addition, when verifying sector protection, the sector address
must appear on the appropriate highest order address bits (see Table 9.4). Table 9.6 show the
remaining address bits that are don’t care. When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier code on DQ7–DQ0. However, the
autoselect codes can also be accessed in-system through the command register, for instances when
the device is erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 15.1. Note that if a Bank Address (BA) (on address bits A20–
A18) is asserted during the third write cycle of the autoselect command, the host system can read
autoselect data from that bank and then immediately read array data from the other bank, without
exiting the autoselect mode.
To access the autoselect codes in-system, the host system can issue the autoselect command via the
command register, as shown in Table 15.1. This method does not require VID. Refer to Section 15.3
Autoselect Command Sequence for more information.
Table 9.6 Autoselect Codes (High Voltage Method)
Description
CE# OE# WE#
A10 A9
A8 A7 A6
A5
to A3 A2 A1 A0
A4
1
Manufacturer ID:
Eon
L
Read Cycle 1
L
Read Cycle 2
L
Read Cycle 3
L
Device ID
Amax
to
A12
L
L
H
H
X
BA
BA
X
V ID
VI D
H
L
X
L
L
L
L
X
L
DQ15
to DQ0
001Ch
007Fh
L
L
L
L
L
L
L
H 227Eh
H
H
H
L 220Ah
H
H
H
H 2201h
Sector Protection
Verification
L
L
H
SA
X
VI D
X
L
L
L
L
L
H
L
0001h (protected),
0000h (unprotected)
Secured Silicon
Indicator Bit
(DQ7, DQ6)
L
L
H
BA (See Note)
X
VI D
X
X
L
X
L
L
H
H
DQ7=1
(Factory locked)
DQ6=1
(customer locked)
L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.
Note
1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will
output a configuration code 7Fh.
2. A9 = V ID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect
Mode.
B
B
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
15
©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
9.9 Selecting a Sector Protection Mode
Table 9.7 Boot Sector/Sector Block Addresses for Protection/Unprotection
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11-SA14
SA15-SA18
SA19-SA22
SA23-SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55-SA58
SA59-SA62
SA63-SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
A20-A12
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001XXX
000010XXX
000011XXX
0001XXXXX
0010XXXXX
0011XXXXX
0100XXXXX
0101XXXXX
0110XXXXX
0111XXXXX
1000XXXXX
1001XXXXX
1010XXXXX
1011XXXXX
1100XXXXX
1101XXXXX
1110XXXXX
111100XXX
111101XXX
111110XXX
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
Sector/Sector Block Size
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
32 Kwords
32 Kwords
32 Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
32 Kwords
32 Kwords
32 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
The device is shipped with all sectors unprotected. Optional Eon programming services enable
programming and protecting sectors at the factory prior to shipping the device. Contact your local sales
office for details.
It is possible to determine whether a sector is protected or unprotected. See section 9.8 and section
15.3 for details.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
16
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
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EN29PL032A
10. Sector Protection
The EN29PL032A features several levels of sector protection, which can disable both the program and
erase operations in certain sectors or sector groups:
■ Persistent Sector Protection
A command sector protection method that replaces the old 11 V controlled protection method.
■ WP# Hardware Protection
A write protect pin that can prevent program or erase operations in sectors SA0, SA1, SA76 and SA77.
The WP# Hardware Protection feature is always available, independent of the software managed
protection method chosen.
■ Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The device is shipped with all
sectors unprotected. Optional Eon’s programming services enable programming and protecting sectors
at the factory prior to shipping the device. Contact your local sales office for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details.
10.1 Persistent Sector Protection
The Persistent Sector Protection method replaces the 11 V controlled protection method in previous
flash devices. This new method provides the sector protection states:
■ Persistently Locked—The sector is protected and cannot be changed.
To achieve these states, two types of “bits” are used:
■ Persistent Protection Bit
■ Persistent Protection Bit Lock
10.1.1 Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the
sector address tables for specific sector protection groupings). All 4 Kword boot-block sectors
have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is
individually modifiable through the PPB Write Command.
The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed
to preprogram all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector
PPBs can potentially be over-erased. The flash device does not have a built-in means of
preventing sector PPBs over-erasure.
10.1.2 Persistent Protection Bit Lock (PPB Lock)
The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to “1”, the PPBs
cannot be changed. When cleared (“0”), the PPBs are changeable. There is only one PPB Lock
bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command
sequence to unlock the PPB Lock.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
17
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
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EN29PL032A
10.2 Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting the upper two and lower two
sectors without using VID. This function is provided by the WP# pin and overrides the previously
discussed High Voltage Sector Protection method.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the
two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously
protected or unprotected.
If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two and lower two sectors
to whether they were last set to be protected or unprotected. That is, sector protection or unprotection
for these sectors depends on whether they were last protected or unprotected using the method
described in the High Voltage Sector Protection .
Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device
may result.
10.3 High Voltage Sector Protection
Sector protection and unprotection may also be implemented using programming equipment. The
procedure requires high voltage (VID) to be placed on the RESET# pin. Refer to Figure 10.1 for details
on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to
the first sector write cycle.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
18
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
Figure 10.1 In-System Sector Protection/Sector Unprotection Algorithms
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
19
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
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EN29PL032A
11. Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system.
The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly
protected sectors can be programmed or erased by selecting the sector addresses. Once VID is
removed from the RESET# pin, all the previously protected sectors are protected again. Figure 11.1
shows the algorithm, and Figure 21.1 shows the timing diagrams, for this feature. While PPB lock is set,
the device cannot enter the Temporary Sector Unprotection Mode.
Figure 11.1 Temporary Sector Unprotect Operation
Notes:
1.
2.
All protected sectors unprotected (If WP#/ACC = VIL, upper two and lower two sectors will remain protected).
All previously protected sectors are protected once again
12. Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region. The Secured Silicon Sector is 64
words in length and all Secured Silicon read outside of the 64-word address range returns invalid data.
The Secured Silicon Sector Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether
or not the Secured Silicon Sector is locked when shipped from the factory.
Please note the following general conditions:
■ On power-up, or following a hardware reset, the device reverts to sending commands to the normal
address space.
■ Read outside of sector SA0 return memory array data.
■ Sector SA0 is remapped from memory array to Secured Silicon Sector array.
■ Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command
must be issued to exit Secured Silicon Sector Mode.
■ The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or
Embedded Erase algorithm.
■ The ACC function is not available when the Secured Silicon Sector is enabled.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
20
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
12.1 Customer- Lockable Secured Silicon Sector (64 words)
The Customer Lockable Secured Silicon Sector is always shipped unprotected (DQ0 set to “0”),
allowing customers to utilize that sector in any manner they choose. If the security feature is not
required, the Secured Silicon Sector can be treated as an additional Flash memory space.
Please note the following:
■ Once the Secured Silicon Sector area is protected, the Secured Silicon Sector Indicator Bit (DQ0) is
permanently set to “1”.
■ The Secured Silicon Sector can be read any number of times, but can be programmed and locked
only once. The Secured Silicon Sector lock must be used with caution as once locked, there is no
procedure available for unlocking the Secured Silicon Sector area and none of the bits in the Secured
Silicon Sector memory space can be modified in any way.
■ The accelerated programming (ACC) is not available when the Secured Silicon Sector is enabled.
■ Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured
Silicon Sector Region command sequence which return the device to the memory array at sector 0.
12.2 Secured Silicon Sector Protection Bits
The Secured Silicon Sector Protection Bits prevent programming of the Secured Silicon Sector memory
area. Once set, the Secured Silicon Sector memory area contents are non-modifiable.
Figure 12.1 Secured Silicon Sector Protect Verify
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
21
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
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EN29PL032A
13. Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes. In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might otherwise be caused by spurious system level
signals during VCC power-up and power-down transitions, or from system noise.
13.1 Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO.
The system must provide the proper signals to the control pins to prevent unintentional writes when VCC
is greater than VLKO.
13.2 Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#, or WE# do not initiate a write cycle.
13.3 Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write
cycle, CE# and WE# must be a logical zero while OE# is a logical one.
13.4 Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the
rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
14. Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device families. Flash vendors can standardize their
existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address 55h, any time the device is ready to read array data. The system can read CFI information at
the addresses given in Table 14.1 to Table 14.4. To terminate reading CFI data, the system must write
the reset command. The CFI Query mode is not accessible when the device is executing an Embedded
Program or embedded Erase algorithm.
The system can also write the CFI query command when the device is in the autoselect mode. The
device enters the CFI query mode, and the system can read CFI data at the addresses given in Table
14.1 to Table 14.4. The system must write the reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100. Contact your
local sales office for copies of these documents.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
22
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
Table 14.1 CFI Query Identification String
Addresses
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
Data
Description
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
Table 14.2 System Interface String
Addresses
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
VPP Min. voltage (00h = no VPP pin present)
1Bh
0027h
1Ch
0036h
1Dh
0000h
1Eh
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
0003h
Typical timeout per single byte/word write 2 µs
N
N
20h
0004h
Typical timeout for Min. size buffer write 2 µs (00h = not supported)
21h
0009h
Typical timeout per individual block erase 2 ms
22h
0000h
Typical timeout for full chip erase 2 ms (00h = not supported)
N
N
N
23h
0005h
Max. timeout for byte/word write 2 times typical
24h
0005h
Max. timeout for buffer write 2 times typical
25h
26h
0004h
0004h
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
N
Table 14.3 Device Geometry Definition
Addresses
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
Data
0016h
0001h
0000h
0006h
0000h
0003h
0007h
0000h
0020h
0000h
003Dh
0000h
0000h
0001h
0007h
0000h
0020h
0000h
0000h
0000h
0000h
0000h
Description
N
Device Size = 2 byte
Flash Device Interface description (refer to CFI publication 100)
N
Max. number of byte in multi-byte write = 2
(00h = not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
23
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
Table 14.4 Primary Vendor-Specific Extended Query
Addresses
40h
41h
42h
43h
Data
0050h
0052h
0049h
0031h
Description
44h
0034h
45h
000Ch
46h
0002h
47h
0001h
48h
0001h
49h
0002h
4Ah
003Fh
4Bh
0000h
4Ch
0001h
4Dh
0085h
4Eh
0095h
4Fh
0001h
50h
0001h
Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (Bits 1-0)
00 = Required, 01 = Not Required
Silicon technology (Bits 5-2)
0001 = 0.18um, 0010 = 0.13um, 0011 = 90nm
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
00h = High Voltage Sector Protection
01h = High Voltage + In-System Sector Protection
02h = HV + In-System Software Command Sector Protection
Simultaneous Operation
00 = Not Supported, X = Number of Sectors excluding Bank 1
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
00h = Uniform device, 01h = Both top and bottom boot with write
protect,
02h = Bottom Boot Device, 03h = Top Boot Device,
04h = Both Top and Bottom
Program Suspend
0 = Not supported, 1 = Supported
52h
0007h
53h
000Fh
54h
0009h
55h
0005h
Erase Suspend Latency Maximum 2 μs
56h
0005h
Program Suspend Latency Maximum 2 μs
57h
0004h
58h
000Fh
59h
0018h
5Ah
0018h
5Bh
000Fh
Query-unique ASCII string “PRI”
Major version number, ASCII (reflects modifications to the silicon)
Secured Silicon Sector (Customer OTP Area) Size 2N bytes
Hardware Reset Low Time-out during an embedded algorithm to read
N
mode Maximum 2 ns
Hardware Reset Low Time-out not during an embedded algorithm to
read
N
mode Maximum 2 ns
N
N
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
Bank 1 Region Information
X = Number of Sectors in Bank 1
Bank 2 Region Information
X = Number of Sectors in Bank 2
Bank 3 Region Information
X = Number of Sectors in Bank 3
Bank 4 Region Information
X = Number of Sectors in Bank 4
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
24
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
15. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device
operations. Table 15.1 defines the valid register command sequences. Writing incorrect address and
data values or writing them in the improper sequence may place the device in an unknown state. A
reset command is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is
latched on the rising edge of WE# or CE#, whichever happens first. Refer to AC Characteristic for
timing diagrams.
15.1 Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required
to retrieve data. Each bank is ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank enters the erasesuspend-read mode, after which the system can read data from any non-erase-suspended sector within
the same bank. The system can read array data using the standard read timing, except that if it reads at
an address within erase-suspended sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the system may once again read array data with
the same exception. See Erase Suspend/Erase Resume Commands for more information.
After the device accepts a Program Suspend command, the corresponding bank enters the programsuspend-read mode, after which the system can read data from any non-program-suspended sector
within the same bank. See Program Suspend/Program Resume Commands for more information.
The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode
if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode.
See the next section, Reset Command, for more information.
See also Requirements for Reading Array Data for more information. The table AC Characteristic
provides the read parameters, and Figure 16.2 shows the timing diagram.
15.2 Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence
before erasing begins. This resets the bank to which the system was writing to the read mode. Once
erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence
before programming begins. This resets the bank to which the system was writing to the read mode. If
the program command sequence is written to a bank that is in the Erase Suspend mode, writing the
reset command returns that bank to the erase-suspend-read mode. Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank
entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that
bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to
the read mode (or erase-suspend-read mode if that bank was in Erase Suspend and program-suspendread mode if that bank was in Program Suspend).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
25
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
15.3 Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device
codes, and determine whether or not a sector is protected. The autoselect command sequence may be
written to an address within a bank that is either in the read or erase-suspend-read mode. The
autoselect command may not be written while the device is actively programming or erasing in the other
bank.
The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a
third write cycle that contains the bank address and the autoselect command. The bank then enters the
autoselect mode. The system may read any number of autoselect codes without reinitiating the
command sequence.
Table 15.1 shows the address and data requirements. To determine sector protection information, the
system must write to the appropriate bank address (BA) and sector address (SA).
The system must write the reset command to return to the read mode (or erase-suspend-read mode if
the bank was previously in Erase Suspend).
15.4 Enter/Exit Secured Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing a random, eight word
electronic serial number (ESN). The system can access the Secured Silicon Sector region by issuing
the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the
Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector
command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal
operation. The Secured Silicon Sector is not accessible when the device is executing an Embedded
Program or embedded Erase algorithm. Table 15.2 shows the address and data requirements for both
command sequences. See also Secured Silicon Sector Flash Memory Region for further information.
Note that the ACC function mode is not available when the Secured Silicon Sector is enabled.
15.5 Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up command. The program address and data are
written next, which in turn initiate the Embedded Program algorithm. The system is not required to
provide further controls or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin. Table 15.1 shows the address and data requirements
for the program command sequence. Note that the Secured Silicon Sector, autoselect, and CFI
functions are unavailable when a [program/erase] operation is in progress.
When the Embedded Program algorithm is complete, that bank then returns to the read mode and
addresses are no longer latched. The system can determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. Refer to Write Operation Status for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program operation. The program command sequence
should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that
the Secured Silicon Sector, autoselect and CFI functions are unavailable when the Secured Silicon
Sector is enabled.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show
that the data is still “0.” Only erase operations can convert a “0” to a “1.”
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
26
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
Figure 15.1 Program Operation
Note
See Table 15.1 for program command sequence.
15.6 Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by
the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not
require the system to preprogram prior to erase. The Embedded Erase algorithm automatically
preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations. Table 15.1 shows the
address and data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/ BY#. Refer to Write Operation Status for information on these status bits.
Any commands written during the chip erase operation are ignored. Note that Secured Silicon Sector,
autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. However,
note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase
command sequence should be reinitiated once that bank has returned to reading array data, to ensure
data integrity.
Figure 15.2 illustrates the algorithm for the erase operation. Refer to the tables in Erase/Program
Operations for parameters, and Figure 20.8 for timing diagrams.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
27
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
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EN29PL032A
15.7 Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed
by the address of the sector to be erased, and the sector erase command. The command Definitions
table shows the address and data requirements for the sector erase command sequence.
Once the sector erase operation has begun, only the Sector Erase Suspend command is valid. All other
commands are ignored. If there are several sectors to be erased, Sector Erase Command sequences
must be issued for each sector. That is, only a sector address can be specified for each Sector
Erase command. Users must issue another Sector Erase command for the next sector to be erased
after the previous one is completed.
When the Embedded Erase algorithm is completed, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of the erase operation by
reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to “Write Operation Status” for
information on these status bits. Refer to the Erase/Program Operations tables in the “AC
Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing
waveforms.
Figure 15.2 Erase Operation
START
Write Erase
Command Sequence
Data Poll from
System or Toggle Bit
successfully
completed
Data =FFh?
No
Yes
Erase Done
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
28
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
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EN29PL032A
15.8 Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then
read data from, or program data to, any sector not selected for erasure. The sector address is required
when writing this command. This command is valid only during the sector erase operation. The Erase
Suspend command is ignored if written during the chip erase operation or Embedded Program
algorithm. Addresses are don’t-cares when writing the Sector Erase Suspend command.
When the Erase Suspend command is written during the sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation.
After the erase operation has been suspended, the device enters the erase-suspend-read mode. The
system can read data from or program data to any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors
produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is erase-suspended.
After an erase-suspended program operation is complete, the device returns to the erase-suspend-read
mode. The system can determine the status of the program operation using write operation status bits,
just as in the standard Word Program operation.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer
to the Autoselect for details.
To resume the sector erase operation, the system must write the Erase Resume command (address
bits are don’t care). The address of the erase-suspended sector is required when writing this command.
Further writes of the Resume command are ignored. Another Erase Suspend command can be written
after the chip has resumed erasing.
15.9 Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation
so that data can read from any non-suspended sector. When the Program Suspend command is written
during a programming process, the device halts the programming operation within 15 µs maximum (5
µs typical) and updates the status bits. Addresses are “don’t-cares” when writing the Program Suspend
command.
After the programming operation has been suspended, the system can read array data from any nonsuspended sector. The Program Suspend command may also be issued during a programming
operation while an erase is suspended. In this case, data may be read from any addresses not within a
sector in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area,
then user must use the proper command sequences to enter and exit this region.
The system may also write the autoselect command sequence when the device is in Program Suspend
mode. The device allows reading autoselect codes in the suspended sectors, since the codes are not
stored in the memory array. When the device exits the autoselect mode, the device reverts to Program
Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for
more information.
After the Program Resume command is written, the device reverts to programming. The system can
determine the status of the program operation using the write operation status bits, just as in the
standard program operation. See “Write Operation Status” for more information. The system must write
the Program Resume command (address bits are “don’t care”) to exit the Program Suspend mode and
continue the programming operation. Further writes of the Program Resume command are ignored.
Another Program Suspend command can be written after the device has resumed programming.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
29
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
15.10 Command Definitions Tables
Command Sequence
Cycles
Table 15.1 Memory Array Command Definitions
Bus Cycles (Notes 1- 4)
1
st
Cycle
Addr Data
P
P
Read (5)
1
RA
RD
Reset (6)
1
XXX
F0
Autoselect
Manufacturer ID
4
555
AA
2
nd
3
rd
Cycle
Addr Data
Cycle
Addr
Data
2AA
(BA)
555
P
P
55
P
(BA)
555
(BA)
555
4
th
5
th
6
th
Cycle
Addr Data
Cycle
Addr Data
Addr
(BA)
000
(BA)
100
(BA)
X01
001C
(BA)
X0E
220A
(BA)
X0F
2201
90
X03
(8)
(SA)
X02
XX00
XX01
P
90
Device ID (10)
6
555
AA
2AA
55
90
Secured Silicon Sector
Factory Protect (8)
4
555
AA
2AA
55
Sector Group
Protect Verify (9)
4
555
AAA
2AA
55
(BA)
555
90
P
P
P
P
P
P
Cycle
Data
007F
227E
Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase/Program Suspend (11)
1
BA
B0
Erase/Program Resume (12)
1
BA
30
CFI Query (13)
1
55
98
Accelerated Program
2
XX
A0
PA
PD
Legend
X = Don’t care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
BA = Address of bank switching to autoselect mode or erase operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A16 uniquely select any sector.
Notes
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
See Table 9.1 for description of bus operations.
All values are in hexadecimal.
Shaded cells in table denote read cycles. All other cycles are write operations.
During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than
A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.
No unlock or command cycles required when bank is reading array data.
The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend)
when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information).
Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer
ID or device ID information. See Autoselect Command Sequence for more information.
The data is DQ6=1 for customer locked.
The data is 00h for an unprotected sector group and 01h for a protected sector group.
Device ID must be read across cycles 4, 5, and 6. (X01h = 227Eh, X0Eh = 220Ah, X0Fh = 2201h).
System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode.
Program/ Erase Suspend command is valid only during a sector erase operation, and requires bank address.
Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address.
Command is valid when device is ready to read array data or when device is in autoselect mode.
WP#/ACC must be at VID during the entire operation of command.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
30
©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
Command Sequence
Cycles
Table 15.2 Sector Protection Command Definitions
Bus Cycles (Notes 1-4)
1
st
Cycle
Addr Data
P
P
2
nd
Cycle
Addr Data
P
P
3
rd
Cycle
Addr
Data
P
P
4
th
Cycle
Addr Data
P
P
5
th
6
th
Cycle
Addr Data
Addr
Cycle
Data
OW
RD
(0)
P
P
P
P
Reset
Secured Silicon
Sector Entry (12)
Secured Silicon
Sector Exit (12)
Secured Silicon Protection Bit
Program (Notes 5, 7)
Secured Silicon Protection Bit
Status
1
XXX
3
555
AA
2AA
55
555
88
4
555
AA
2AA
55
555
90
XX
00
6
555
AA
2AA
55
555
60
OW
68
OW
48
5
555
AA
2AA
55
555
60
OW
48
OW
RD
(0)
PPB Program (Notes 5, 7, 8)
6
555
AA
2AA
55
555
60
68
(SA)
WP
48
(SA)
WP
RD
(0)
PPB Status
4
555
AA
2AA
55
6
555
AA
2AA
55
(SA)
40
(SA)
WP
RD
(0)
3
555
AA
2AA
55
All PPB Erase
(Notes 5, 6, 7, 9, 10)
PPB Lock Bit Set
PPB Lock Bit Status (11)
4
555
F0
AA
2AA
55
(BA)
555
90
555
60
555
78
(BA)
555
58
(SA)
WP
(SA)
WP
(BA)
WP
SA
RD
(0)
60
RD
(1)
Legend
OW = Address (A7:A0) is (00011010)
PD[3:0] = Password Data (1 of 4 portions)
PPB = Persistent Protection Bit
RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock status.
SA = Sector Address where security command applies. Address bits Amax: A12 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)
WP = PPB Address (A7:A0) is (00000010)
X = Don’t care
Notes
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
See Table 9.1 for description of bus operations.
All values are in hexadecimal.
Shaded cells in table denote read cycles. All other cycles are write operations.
During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits
higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.
The reset command returns device to reading array.
If will retry the All PPB Erase, the reset command must be issued again before the All PPB Erase
command.
Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when
DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again.
A 2 µs timeout is required between any two portions of password.
A 1.2 ms timeout is required between cycles 4 and 5.
Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in
cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should
be programmed to prevent PPB over erasure.
DQ1 = 1 if PPB locked, 0 if unlocked.
Once the Secured Silicon Sector Entry Command sequence has been entered, the standard array cannot be
accessed until the Exit SecSi Sector command has been entered or the device has been reset.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN29PL032A
16. Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3,
DQ5, DQ6, and DQ7. Table 16.1 and the following subsections describe the function of these bits. DQ7
and DQ6 each offer a method for determining whether a program or erase operation is complete or in
progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an
Embedded Program or Erase operation is in progress or has been completed.
16.1 DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase
algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid
after the rising edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The
system must provide the program address to read valid status information on DQ7. If a program
address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that
bank returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded
Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a
“1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read
valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 1 µs, then the bank returns to the read mode. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at
DQ15–DQ0 on the following read cycles. Just prior to the completion of an Embedded Program or
Erase operation, DQ7 may change asynchronously with DQ15–DQ0 while Output Enable (OE#) is
asserted low. That is, the device may change from providing status information to valid data on DQ7.
Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if
the device has completed the program or erase operation and DQ7 has valid data, the data outputs on
DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 will appear on successive read cycles.
Table 16.1 shows the outputs for Data# Polling on DQ7. Figure 16.1 shows the Data# Polling algorithm.
Figure 20.10 shows the Data# Polling timing diagram.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2010/12/27
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EN29PL032A
Figure 16.1 Data# Polling Algorithm
Notes
1.
2.
VA = Valid address for programming. During a sector erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a valid address is any non-protected sector address.
DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
16.2 RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the
command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together
in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby
mode, or one of the banks is in the erase-suspend-read mode.
Table 16.1 shows the outputs for RY/BY#.
16.3 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any
address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address
cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the
operation is complete, DQ6 stops toggling.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2010/12/27
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EN29PL032A
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately 400 µs, then returns to reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in
progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended.
Alternatively, the system can use DQ7 (see the DQ7: Data# Polling ).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the
program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded
Program algorithm is complete.
Table 16.1 shows the outputs for Toggle Bit I on DQ6. Figure 16.2 shows the toggle bit algorithm.
Figure 20.11 shows the toggle bit timing diagrams. Figure 20.12 shows the differences between DQ2
and DQ6 in graphical form. See also the DQ2: Toggle Bit II.
Figure 16.2 Toggle Bit Algorithm
Start
R ead D ata tw ice
No
D Q 6 = T ogg le?
Yes
No
D Q 5 = 1?
Yes
R ead D ata twice (2)
D Q 6 = T ogg le?
No
Yes
F ail
P ass
Note:
The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the DQ6: Toggle Bit I and DQ2: Toggle Bit II for more information.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2010/12/27
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EN29PL032A
16.4 DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for
erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot
distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates
whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are
selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table
16.1 to compare outputs for DQ2 and DQ6.
Figure 16.2 shows the toggle bit algorithm in flowchart form, and the DQ2: Toggle Bit II explains the
algorithm. See also the DQ6: Toggle Bit I. Figure 20.11 shows the toggle bit timing diagram. Figure
20.12 shows the differences between DQ2 and DQ6 in graphical form.
16.5 Reading Toggle Bits DQ6/DQ2
Refer to Figure 16.2 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is
not toggling, the device has completed the program or erase operation. The system can read array data
on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still toggling, the device did not completed the
operation successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read
cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system must start at the beginning of the algorithm when it
returns to determine the status of the operation.
16.6 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not
successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was
previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this
condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces
a “1.”
Under both these conditions, the system must write the reset command to return to the read mode (or to
the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
16.7 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the output on DQ3 can be checked to determine
whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase
command.) When sector erase starts, DQ3 switches from “0” to “1”. This device does not support
multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since
it immediately shows as a “1” after the first 30h command. Future devices may support this feature.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
35
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com
EN29PL032A
Table 16.1 Write Operation Status
Status
Embedded Program
Standard Algorithm
Mode Embedded Erase
Algorithm
Erase
SuspendRead
Erase
Suspend
Mode
Erase
Suspended
Sector
Non-Erase
Suspended
Sector
Erase-Suspend
-Program
Program
Suspend
Mode
(Note 3)
Reading within
Program
Suspended Sector
Reading within
Non-program
Suspended Sector
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
0
1
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
DQ7#
Toggle
0
N/A
N/A
0
Invalid
Invalid
Invalid
Invalid
Invalid
(Not Allowed) (Not Allowed) (Not Allowed) (Not Allowed) (Not Allowed)
Data
Data
Data
Data
Data
1
1
Notes:
1.
2.
3.
DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum
timing limits. Refer to DQ5: Exceeded Timing Limits for more information.
DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection
for further details.
When reading write operation status bits, the system must always provide the bank address where the
Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
17. Absolute Maximum Ratings
Parameter
Value
Unit
Storage Temperature
-65 to +150
℃
Plastic Packages
-65 to +125
℃
Ambient Temperature
With Power Applied
-55 to +125
℃
200
mA
-0.5 to +9.5
V
-0.5 to Vcc+0.5
V
-0.5 to + 4.0
V
Output Short Circuit Current 1
P
P
A9, RESET# and
WP#/ACC 2
P
P
Voltage with
Respect to Ground
P
P
All other pins
3
P
P
Vcc
Notes:
1.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2.
Minimum DC input voltage on A9, OE#, RESET# and WP#/ACC pins is –0.5V. During voltage transitions, A9, OE#,
RESET# and WP#/ACC pins may undershoot V ss to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns.
See figure below. Maximum DC input voltage on A9, OE#, and RESET# is 8.5V which may overshoot to 9.5V for periods up
to 20ns.
3.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot V ss to –1.0V for
periods of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O
pins is V cc + 0.5 V. During voltage transitions, outputs may overshoot to V cc + 1.5 V for periods up to 20ns. See figure
below.
4.
Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress
rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the
device to the maximum rating values for extended periods of time may adversely affect the device reliability.
B
B
B
B
B
B
18. RECOMMENDED OPERATING RANGES 1
P
B
B
P
Parameter
Value
Unit
Ambient Operating Temperature
Industrial Devices
Wireless Devices (For MCP product)
-40 to 85
-25 to 85
℃
Operating Supply Voltage
Vcc
Full Voltage Range:
2.7 to 3.6V
V
1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
37
©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
19.
DC Characteristics
Table 19.1 CMOS Compatible
Parameter
Parameter Description (notes)
Test Conditions
VIN = VSS to VCC,
VCC = VCC max
Min
Typ
Max
Unit
±1.0
µA
VCC = VCC max; VID= 9.5 V
35
µA
35
µA
±1.0
µA
ILI
Input Load Current
ILIT
A9, OE#, RESET#
Input Load Current
ILR
Reset Leakage Current
VCC = VCC max; VID= 9.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC, OE# = VIH
VCC = VCC max
ICC1
VCC Active Read Current
(1, 2)
OE# = VIH, VCC = VCC max
ICC2
VCC Active Write Current (2, 3)
ICC3
VCC Standby Current (2)
ICC4
VCC Reset Current (2)
ICC5
Automatic Sleep Mode
(Notes 2, 4)
ICC6
VCC Active Read-While-Program
Current (1, 2)
OE# = VIH,
ICC7
VCC Active Read-While-Erase
Current (1, 2)
OE# = VIH,
ICC8
VCC Active Program-While-EraseSuspended Current (2, 5)
OE# = VIH
ICC9
VIL
VIH
VCC Active Page Read Current (2)
OE# = VIH, 4 word Page Read
Input Low Voltage
VIO = 2.7–3.6 V
–0.5
Input High Voltage
VIO = 2.7–3.6 V
2
VCC+0.3
V
VHH
Voltage for ACC
Program Acceleration
VCC = 3.0 V ± 10%
8.5
9.5
V
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 3.0 V ± 10%
8.5
9.5
V
VOL
Output Low Voltage
IOL = 2.0 mA, VCC = VCC min,
VIO = 2.7–3.6 V
0.4
V
VOH
Output High Voltage
IOH = –100 µA, VIO = VCC min
VLKO
Low VCC Lock-Out Voltage (5)
5 MHz
10
30
10 MHz
20
55
OE# = VIH, WE# = VIL
15
30
mA
CE#, RESET#, WP#/ACC
= VIO ± 0.3 V
0.2
10
µA
RESET# = VSS ± 0.3 V
0.2
10
µA
VIH = VIO ± 0.3 V;
VIL = VSS ± 0.3 V
0.2
10
µA
mA
5 MHz
21
45
10 MHz
46
70
5 MHz
21
45
10 MHz
46
70
17
25
mA
15
mA
0.8
V
10
VCC0.2V
2.3
mA
mA
V
2.5
V
Notes
1.
2.
3.
4.
5.
The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH.
Maximum ICC specifications are tested with VCC = VCCmax.
ICC active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode
current is 2 µA.
Not 100% tested.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
38
©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
20. AC Characteristic
20.1 Test Conditions
Figure 20.1 Test Setups
Device Under Test
CL
Table 20.1 Test Specifications
Test Conditions
All Speeds
Unit
Output Load Capacitance, CL (including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
0.0-3.0
V
Input timing measurement reference levels
Vcc/2
V
Output timing measurement reference levels
Vcc/2
V
Input Pulse Levels
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
39
©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
20.2 Switching Waveforms
Table 20.2 Key To Switching Waveforms
Figure 20.2 Input Waveforms and Measurement Levels
20.3 VCC Ramp Rate
All DC characteristics are specified for a VCC ramp rate > 1V/100 µs. If the VCC ramp rate is < 1V/100 µs,
a hardware reset required.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
20.4
Read Operations
Table 20.3 Read-Only Operations
Parameter
Speed Options
JEDEC
Std.
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tRC
tACC
tCE
tPACC
tOE
tDF
tDF
tAXQX
Description (Notes)
Read Cycle Time (1)
Test Setup
Address to Output Delay
Chip Enable to Output Delay
70
Min
70
ns
CE#, OE# = VIL Max
70
ns
Max
70
ns
Page Access Time
Output Enable to Output Delay
OE# = VIL
Max
25
ns
Max
25
ns
Chip Enable to Output High Z (3)
Max
16
ns
Max
16
ns
tOH
Output Enable to Output High Z (1, 3)
Output Hold Time From Addresses,
CE# or OE#, Whichever Occurs First (3)
Min
5
ns
tOEH
Output Enable Hold Time (1)
Min
Min
0
10
ns
ns
Read
Toggle and Data# Polling
Notes
1.
2.
3.
Unit
Not 100% tested.
See Figure 20.1 and Table 20.1 for test specifications
Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time
from OE# high to the data bus driven to VCC /2 is taken as tDF.
Figure 20.3 Read Operation Timings
tBRCB
Addresses
Addresses Stable
tBACC
CE#
tBDF
tBOEB
OE#
tBOEHB
tBCEB
WE#
tBOH
HIGH Z
Output Valid
HIGH Z
Outputs
RESET#
0V
Figure 20.4 Page Read Operation Timings
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
20.5
Reset
Table 20.4 Hardware Reset (RESET#)
Parameter
JEDEC Std
tRP1
tRP2
tRH
tRB1
tRB2
tREADY1
tREADY2
All Speed
Options
Unit
Min
Min
Min
Min
Min
10
500
50
0
50
us
ns
ns
ns
ns
Max
20
us
Max
500
ns
Description
RESET# Pulse Width (During Embedded Algorithms)
RESET# Pulse Width (NOT During Embedded Algorithms)
Reset# High Time Before Read
RY/BY# Recovery Time ( to CE#, OE# go low)
RY/BY# Recovery Time ( to WE# go low)
Reset# Pin Low (During Embedded Algorithms) to Read Mode
(See Note)
Reset# Pin Low (NOT During Embedded Algorithms) to Read Mode
(See Note)
Note
Not 100% tested.
Figure 20.5 Reset Timings
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
42
©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
20.6
Erase/Program Operations
Table 20.5 Erase and Program Operations
Parameter
Speed Options (ns)
Description
JEDEC
Std
tAVAV
tAVWL
tWC
tAS
tASO
tAH
Write Cycle Time (Note 1)
Min
Address Setup Time
Min
0
ns
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
Address Hold Time
Min
35
ns
Min
0
ns
Min
30
ns
tWLAX
70
tAHT
Address Hold Time From CE# or OE# high during toggle bit polling
tDVWH
tWHDX
tDS
tDH
Data Setup Time
tGHWL
tELWL
tWHEH
tWLWH
tWHDL
tOEPH
tGHWL
tCS
tCH
tWP
tWPH
tSR/W
tWHWH 1 tWHW H1
tWHWH 1 tWHW H1
tWHWH 2 tWHW H2
tVCS
tRB
Data Hold Time
Min
0
ns
Output Enable High during toggle bit polling
Min
10
ns
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
CE# Setup Time
Min
0
ns
CE# Hold Time
Min
0
ns
Write Pulse Width
Min
35
ns
Write Pulse Width High
Min
25
ns
Latency Between Read and Write Operations
Min
0
ns
Programming Operation (Note 2)
Typ
8
µs
Accelerated Programming Operation (Note 2)
Typ
7
µs
Sector Erase Operation (Note 2)
Typ
0.1
sec
VCC Setup Time (Note 1)
Min
50
µs
Write Recovery Time from RY/BY#
Min
0
ns
Max
90
ns
Min
35
ns
Program Suspend Latency
Max
35
µs
Erase Suspend Latency
Max
35
µs
tBUSY Program/Erase Valid to RY/BY# Delay
tPSL
tESL
Notes:
1.
2.
Unit
70
Not 100% tested.
See Table 21.4 for more information.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
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EN29PL032A
20.7
Timing Diagrams
Figure 20.6 Program Operation Timings
Notes
1.
PA = program address, PD = program data, DOUT is the true data at the program address
Figure 20.7 Accelerated Program Timing Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
Figure 20.8 Chip/Sector Erase Operation Timings
Notes
1.
SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation
Status )
Figure 20.9 Back-to-back Read/Write Cycle Timings
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
Figure 20.10 Data# Polling Timings (During Embedded Algorithms)
Note
VA = Valid address. The illustration shows first status cycle after command sequence, last status read cycle,
and array data read cycle
Figure 20.11 Toggle Bit Timings (During Embedded Algorithms)
Notes
1.
VA = Valid address; not required for DQ6. The illustration shows first two status cycle after command
sequence, last status read cycle, and array data read cycle
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
Figure 20.12 DQ2 vs. DQ6
Note
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
21. Protect/Unprotect
Table 21.1 Temporary Sector Unprotect
Parameter
JEDEC
Std
tVIDR
Description
VID Rise and Fall Time (See Note)
All Speed Options
Unit
Min
500
ns
tVHH
VHH Rise and Fall Time (See Note)
Min
250
ns
tRSP
RESET# Setup Time for Temporary Sector Unprotect
Min
4
µs
tRRB
RESET# Hold Time from RY/BY# High for Temporary
Sector Unprotect
Min
4
µs
Note
Not 100% tested
Figure 21.1 Temporary Sector Unprotect Timing Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
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EN29PL032A
Figure 21.2 Sector/Sector Block Protect and Unprotect Timing Diagram
Notes
1.
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
21.1 Controlled Erase Operations
Table 21.2 Alternate CE# Controlled Erase and Program Operations
Parameter
JEDEC
Std
tAVAV
tAVWL
tELAX
tDVEH
tEHDX
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
tWHWH1
tWHWH1
tWHWH2
tWC
tAS
tAH
tDS
tDH
tGHEL
tWS
tWH
tCP
tCPH
Speed Options
Description (Notes)
70
Unit
Write Cycle Time (Note 1)
Min
70
ns
Address Setup Time
Min
0
ns
Address Hold Time
Min
35
ns
Data Setup Time
Min
30
ns
Data Hold Time
Min
0
ns
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
WE# Setup Time
Min
0
ns
WE# Hold Time
Min
0
ns
CE# Pulse Width
Min
35
ns
CE# Pulse Width High
Min
25
ns
Typ
8
µs
tWHWH1 Programming Operation (Note 2)
tWHWH1 Accelerated Programming Operation (Note 2)
tWHWH2 Sector Erase Operation (Note 2)
Typ
7
µs
Typ
0.1
sec
Notes
1.
2.
Not 100% tested.
See Erase and Programming Performance for more information.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
Figure 21.3 Alternate CE# Controlled Write (Erase/Program) Operation Timings 555 for program PA for
program
Notes
1.
2.
3.
Figure indicates last two bus cycles of a program or erase operation.
PA = program address, SA = sector address, PD = program data.
DQ7# is the complement of the data written to the device. DOUT is the data written to the device
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
Table 21.4 Erase and Programming Performance
Parameter
Sector Erase Time
Typ (Note 1) Max (Note 2)
0.1
2
Unit
sec
Chip Erase Time
8
62.4
sec
Word Program Time
8
200
µs
Accelerated Word Program Time
Chip Program Time
(Note 3)
7
200
µs
12.6
25.2
sec
Comments
Excludes 00h programming
prior to erasure (Note 4)
Excludes system level
overhead (Note 5)
Notes
1.
2.
3.
4.
5.
6.
Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, Additionally, programming
typical assume checkerboard pattern. All values are subject to change.
Under worst case conditions of VCC = 2.7 V, 100,000 cycles. All values are subject to change.
The typical chip programming time is considerably less than the maximum chip programming time listed,
since most bytes program faster than the maximum program times listed.
In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before
erasure.
System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 15.1 for further information on command definitions.
The device has a minimum erase and program cycle endurance of 100,000 cycles.
22. 48-PIN TSOP PACKAGE CAPACITANCE
Parameter Symbol
Test Setup
Typ
Max
Unit
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
CIN
B
B
B
B
B
B
Parameter Description
B
B
B
B
B
B
Note: Test conditions are Temperature = 25°C and f = 1.0 MHz
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
23. Physical Dimensions
Figure 24.1 TSOP 48-pin 12mm x 20mm
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2004 Eon Silicon Solution, Inc.,
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EN29PL032A
Revisions List
Revision No Description
Date
A
Initial Release
2010/11/23
B
Update Selecting a Sector Protection Mode description on page 17.
2010/12/27
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
52
©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2010/12/27
www.eonssi.com