EVERLIGHT PLR155

Technical Data Sheet
Photo link Light Receiver Unit
PLR155 Series
Features
1. High PD sensitivity optimized for red light
2. Data : NRZ signal
3. Low power consumption for extended battery
life
4. Built-in threshold control for improved noise
Margin
5. Good ESD protection: up to 8KV
6. Pb Free
7. Receiver sensitivity: up to –27dBm (Min. for 16Mbps)
up to –21dBm (Min. for 25Mbps)
8. The product itself will remain within RoHS compliant version.
Descriptions
The optical receiver is packaged with custom
optic data link interface, integrated on a proprietary
CMOS PDIC process.
The unit functions by converting optical signals
into electric ones.
The unit is operated at 2.4 ~ 5.5 V and the signal
output interface is TTL compatible with high
performance at low power consumption.
Applications
1. Digital Optical Data-Link
2. Dolby AC-3 Digital Audio Interface
EVERLIGHT ELECTRONICS CO., LTD.
http://www.everlight.com
Rev 4
Page: 1 of 8
Device NO: DPL-155-001
Prepared Date:07-25-2005
Prepared By: Chin-Chia Hsu
PLR155 Series
Package Dimensions
2.20±0.1
A
0
0.90
A1
2.48
AT
4.95±0.1
R1
.4
1.50
3
2
1
3-0.50±0.05
0.25±0.03
2.54
5.08
A'
Rear View
Front View
5.70±0.1
Unit: mm
Side View
Pin Function
1 :V
2 :GND
3 :Vcc
Notes: 1.All dimensions are in mm.
2.General Tolerance: Tolerance is ±0.20 mm
3.Plating Thickness: Tin Layer>2um
4.It must be placed a 0.1uF capacitor in the between of Vcc and GND within 7mm.
5.Device Selection Table:
Device Name
Pin Length A1 (mm)
PLR155
12.55±0.25
PLR155/S1
7.50±0.25
PLR155/S2
5.22±0.25
PLR155/S3
10.20±0.25
PLR155/S5
16.50 Min
EVERLIGHT ELECTRONICS CO., LTD.
http://www.everlight.com
Rev 4
Page: 2 of 8
Device NO: DPL-155-001
Prepared Date:07-25-2005
Prepared By: Chin-Chia Hsu
PLR155 Series
Absolute Maximum Ratings( Ta = 25 ºC)
Parameter
Symbol
Rating
Unit
Supply Voltage
Output Voltage
Vcc
Vout
-0.5 ~ +5.5
Vcc +0.3
V
V
Storage Temperature
Operating Temperature
Soldering Temperature
Tstg
Topr
Tsol
-40 to 85
-20 to 70
260*
ºC
ºC
ºC
* Soldering time ≤ 10 s.
Electro-Optical Characteristics(Ta=-20~70℃,Vcc=3V)
Parameter
Symbol
Conditions
Vcc
-
2.40
3.00
5.50
V
Peak sensitivity wavelength
Maximum receiver power
λp
Pc,max
-
-
650
-
Refer to Fig.1
-
-
-14
nm
dBm
Minimum receiver power
Pc,min
Refer to Fig.1
-27
-
-
dBm
Icc
Refer to Fig.2
-
4
12
mA
VOH
VOL
Refer to Fig.3
Refer to Fig.3
2.1
2.5
-
V
-
0.2
0.4
V
Rise time
tr
Refer to Fig.3
10
20
ns
Fall time
tf
Refer to Fig.3
10
20
ns
Propagation delay Low to High
tPLH
Refer to Fig.3
-
-
120
ns
Propagation delay High to Low
tPHL
Refer to Fig.3
-
-
120
ns
Pulse Width Distortion
∆tw
Refer to Fig.3
-25
-
+25
ns
Jitter
∆tj
Refer to Fig.3, Pc=-14dBm
-
1
15
ns
Refer to Fig.3, Pc=-27dBm
-
5
20
Transfer rate
T
NRZ signal
0.1
-
16
ns
Mb/s
Power supply voltage
Dissipation current
High level output voltage
Low level output voltage
MIN. TYP. MAX. Unit
*Standard plastic optic fiber cable:1m
EVERLIGHT ELECTRONICS CO., LTD.
http://www.everlight.com
Rev 4
Page: 3 of 8
Device NO: DPL-155-001
Prepared Date:07-25-2005
Prepared By: Chin-Chia Hsu
PLR155 Series
Measuring Method
*Fig.1 Measuring Method of Maximum and Minimum Input Power that Receiver Unit Need
Optical Power Meter
Standard plastic
optic fiber cable
PLR155 Receiver Unit
Standard Transmitter unit
Control Circuit
*Fig.2 Measuring Method of Dissipation Current
Standard plastic optic fiber cable
Standard Transmitter Unit
Vin
Vcc
PLR155 Receiver Unit
GND
Vcc
Vout
0.1uF
47uH
Signal
Input
GND
A
16 Mbps NRZ "0101" successive signal input
3V
EVERLIGHT ELECTRONICS CO., LTD.
http://www.everlight.com
Rev 4
Page: 4 of 8
Device NO: DPL-155-001
Prepared Date:07-25-2005
Prepared By: Chin-Chia Hsu
PLR155 Series
*Fig.3 Measuring Method of Output Voltage, Pulse and Jitter
Standard plastic optic fiber cable
Standard Transmitter Unit
Vin
Vcc
PLR155 Receiver Unit
GND
Vcc
Vout
0.1uF
47uH
Signal
Input
GND
A
3V
16 Mbps NRZ "0101" successive signal input
TPHL
TPLH
CH1
50%
Input
CH2
Output
50%
tj1
tj2
tw = TPHL-TPLH
Application Circuit
(1) General application circuit for Vcc=3V (2) General application circuit for Vcc=5V
Receiver Unit
Receiver Unit
C1
Vcc
C1
GND
L2
Vout
C1:0.1uF
3V
Vcc
C2
GND
L2
5V
L2:47uH
Vout
C1:0.1uF
C2:30pF (Suggestion)
L2:47uH
Note: For having good coupling, the C1,C2 capacitor must be placed within 7mm
EVERLIGHT ELECTRONICS CO., LTD.
http://www.everlight.com
Rev 4
Page: 5 of 8
Device NO: DPL-155-001
Prepared Date:07-25-2005
Prepared By: Chin-Chia Hsu
PLR155 Series
Typical Electro-Optical Characteristics Curves
Power supply voltage vs. Minimum
receiver power
Optical Input Sensitivity (dBm)
-30
*Fig.5
Operating Voltage Vcc=3.3V
-28
-26
-24
-22
-20
2.0
Transfer rate vs. Minimum receiver
power
-32
Operating Transfer Rate
16Mbps
25Mbps
Optical Input Sensitivity (dBm)
*Fig.4
-30
-28
-26
-24
-22
-20
-18
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
5
10
15
20
25
Transfer Rate (Mbps)
Operating Voltage (V)
Note: Before using the PLR155 device, please confirm the minimum sensitivity at different
operating voltage and transmission rate.
EVERLIGHT ELECTRONICS CO., LTD.
http://www.everlight.com
Rev 4
Page: 6 of 8
Device NO: DPL-155-001
Prepared Date:07-25-2005
Prepared By: Chin-Chia Hsu
PLR155 Series
RELIABILITY TEST ITEMS
Test
Sample Size
Number (n)
Hour/Cycle
(Piece)
Failure (c)
10 seconds
22
n=22, c=0
2 High Temp. Storage Ta=100℃
1000hrs
22
n=22, c=0
Ta=-55℃
1000hrs
22
n=22, c=0
Ta=85℃, RH=85%
1000hrs
22
n=22, c=0
300cycle
22
n=22, c=0
300cycle
22
n=22, c=0
1000hrs
22
n=22, c=0
No.
Item
1 Soldering Heat
3 Low Temp. Storage
4
High Temp. &
Test Condition
260℃±5℃
Humid. Test
-40℃
~~~~
85℃
5 Temperature Cycle
(30min) (5min) (30min)
-10℃
~~~~
100℃
6 Thermal Shock
(5min) (10sec) (5min)
7 DC Operating Life
Vcc=5V, Ta=25℃
*Icc(mA): Current Consumption DIFFERENCE (END) <±20%
*PWD(ns): Pluse Width Distortion < Standard ±25(ns) ;
Pluse Width Distortion DIFFERENCE(END)<±5(ns)
JUDGEMENT:ACCEPTABLE
EVERLIGHT ELECTRONICS CO., LTD.
http://www.everlight.com
Rev 4
Page: 7 of 8
Device NO: DPL-155-001
Prepared Date:07-25-2005
Prepared By: Chin-Chia Hsu
PLR155 Series
Application Notes: PLR155 Series PCB layout for motherboard integration
To achieve better jitter and low input optical power performances, several PCB layout
guidelines must be followed. These guidelines ensure the most reliable PLR155 POF performance
for the motherboard integration. Failed to implement these PCB guidelines may affect the PLR155
jitter and low input power performances.
1. Careful decoupling of the power supplies is very important. Place a 0.1uf surface mount (size
805 or smaller) capacitor as close as (less than 2cm) to the POF Vdd and Gnd leads. The 0.1uf
act as a low impedance path to ground for any stray high frequency transient noises.
2. To reduce the digital noises form the digital IC on the motherboard, the planar capacitance
formed by an isolated Vcc and Gnd planes is critical. The POF device must be mounted directly
on these two planes to reduce the lead parasitic inductance.
3. The isolated Vdd and Gnd planes must be connected to the main Vcc and Gnd (digital) planes at
a single point using ferrite beads. The beads are used to block the high frequency noises from
the digital planes while still allowing the DC connections between the planes
EVERLIGHT ELECTRONICS CO., LTD.
Office: No 25, Lane 76, Sec 3, Chung Yang Rd,
Tucheng, Taipei 236, Taiwan, R.O.C
Tel: 886-2-2267-2000, 2267-9936
Fax:886-2-2269-8114, 2267-6189, 2267-6306
http://www.everlight.com
EVERLIGHT ELECTRONICS CO., LTD.
http://www.everlight.com
Rev 4
Page: 8 of 8
Device NO: DPL-155-001
Prepared Date:07-25-2005
Prepared By: Chin-Chia Hsu