Technical Data Sheet Photo link Light Receiver Unit PLR233 Features 1. 2. 3. 4. 5. 6. 7. 8. 9. High speed signal transmission（26Mbps NRZ Signal） High PD sensitivity optimized for red light Data : NRZ signal Low power consumption for extended battery life Built-in threshold control for improved noise Margin Good ESD protection: up to 8KV Pb Free The product itself will remain within RoHS compliant version. Receiver sensitivity: up to –29dBm (Min. for 16Mbps) up to –27dBm (Min. for 26Mbps) Descriptions The optical receiver is packaged with custom optic data link interface, integrated on a proprietary CMOS PDIC process. The unit functions by converting optical signals into electric ones. The unit is operated at 2.4 ~ 5.5 V and the signal output interface is TTL compatible with high performance at low power consumption. Applications 1. Digital Optical Data-Link 2. Dolby AC-3 Digital Audio Interface 3. HDMI Digital (192kHz) Audio Interface Everlight Electronics Co., Ltd. http://www.everlight.com Device NO.: DPL-233-001 Prepared date: 06-01-2006 Rev 1 Page: 1 of 8 Prepared By: Richard Hsu PLR233 Package Dimensions Pin Function 1 : Vout 2 : GND 3 : Vcc 3 2 1 Notes: 1.All dimensions are in mm. 2.General Tolerance: ±0.10 mm 3.It must be placed a 0.1uF capacitor in the between of Vcc and GND within 7mm. Everlight Electronics Co., Ltd. http://www.everlight.com Device NO.: DPL-233-001 Prepared date: 06-01-2006 Rev 1 Page: 2 of 8 Prepared By: Richard Hsu PLR233 Absolute Maximum Ratings( Ta = 25 ºC) Parameter Symbol Rating Unit Supply Voltage Output Voltage Vcc Vout -0.5 ~ +6.0 Vcc -0.1 V V Storage Temperature Operating Temperature Soldering Temperature Tstg Topr Tsol -40 to 85 -25 to 80 260* ºC ºC ºC * Soldering time ≤ 10 s. Electro-Optical Characteristics(Ta=-20~70℃,Vcc=3.3V) Parameter Symbol Conditions Vcc - 2.40 3.30 5.50 V Peak sensitivity wavelength Maximum receiver power λp Pc,max - - 660 - Refer to Fig.1 - - -14 nm dBm Minimum receiver power Pc,min Refer to Fig.1 -27 - - dBm Icc Vcc=3V; Refer to Fig.2 - 2 4 mA Icc Vcc=5V; Refer to Fig.2 - 3 6 Refer to Fig.3 Refer to Fig.3 3.0 3.2 - V - 0.2 0.4 V Rise time VOH VOL tr Refer to Fig.3 - 10 14 ns Fall time tf Refer to Fig.3 - 10 14 ns Propagation delay Low to High tPLH Refer to Fig.3 - - 80 ns Propagation delay High to Low tPHL Refer to Fig.3 - - 80 ns Pulse Width Distortion Δtw Refer to Fig.3 -15 - +15 ns Jitter Δtj Refer to Fig.3, Pc=-14dBm - 1 5 ns Refer to Fig.3, Pc=-27dBm - 5 - Transfer rate T NRZ signal 0.1 - 26 ns Mb/s Power supply voltage Dissipation current High level output voltage Low level output voltage MIN. TYP. MAX. Unit *Standard plastic optic fiber cable：1m Everlight Electronics Co., Ltd. http://www.everlight.com Device NO.: DPL-233-001 Prepared date: 06-01-2006 Rev 1 Page: 3 of 8 Prepared By: Richard Hsu PLR233 Measuring Method *Fig.1 Measuring Method of Maximum and Minimum Input Power that Receiver Unit Need Control Circuit Standard plastic optic fiber cable Transmitter PLR233 Receiver Unit Optical Power Meter *Fig.2 Measuring Method of Dissipation Current Standard plastic optic fiber cable Standard Transmitter unit Vin Vcc PLR233 Receiver Unit GND Vcc GND 0.1uF 47uH A Signal Input 3.3V 26Mbps NRZ "0101" successive signal input Everlight Electronics Co., Ltd. http://www.everlight.com Device NO.: DPL-233-001 Prepared date: 06-01-2006 Rev 1 Page: 4 of 8 Prepared By: Richard Hsu Vout PLR233 *Fig.3 Measuring Method of Output Voltage, Pulse and Jitter Standard plastic optic fiber cable Standard Transmitter Unit Vin Vcc PLR233 Receiver Unit GND Vcc Vout 0.1uF 47uH Signal Input GND A 3.3V 26 Mbps NRZ "0101" successive signal input TPHL TPLH tw = TPHL-TPLH CH1 50% Input tr Output tf CH2 50% tj1 tj2 tr = 10% --> 90% Rise Time tf = 90% --> 10% Fall Time Application Circuit (1) General application circuit C1 Vcc GND L2 Vout C1:0.1uF Vcc L2:47uH Note:1. For having good coupling, the C1 capacitor must be placed within 7mm 2. For having good signal waveform, the Vout –GND circuit capacitor shall be smaller than 30pF. Everlight Electronics Co., Ltd. http://www.everlight.com Device NO.: DPL-233-001 Prepared date: 06-01-2006 Rev 1 Page: 5 of 8 Prepared By: Richard Hsu PLR233 Typical Electro-Optical Characteristics Curves *Fig.4 Power supply voltage vs. Minimum receiver power *Fig.5 -32 Operating Transfer Rate 16Mbps 25Mbps -30 Operating Voltage Vcc=3.3V Optical Input Sensitivity (dBm) Optical Input Sensitivity (dBm) -32 -28 -26 -24 -22 2.0 Transfer rate vs. Minimum receiver power 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -30 -28 -26 -24 -22 0 5 10 15 20 25 Transfer Rate (Mbps) Operating Voltage (V) Note: Before using the PLR233 device, please confirm the minimum sensitivity at different operating voltage and transmission rate. Everlight Electronics Co., Ltd. http://www.everlight.com Device NO.: DPL-233-001 Prepared date: 06-01-2006 Rev 1 Page: 6 of 8 Prepared By: Richard Hsu PLR233 Packing Quantity Specification 1. 500 pcs/bag 2. 4 bag/box Label Form Specification CPN: Customer’s Production Number P/N : Production Number QTY: Packing Quantity CAT: None HUE: None REF: Reference LOT No: Lot Number MADE IN TAIWAN: Production Place Notes 1. Above specification may be changed without notice. EVERLIGHT will reserve authority on material change for above specification. 2. When using this product, please observe the absolute maximum ratings and the instructions for using outlined in these specification sheets. EVERLIGHT assumes no responsibility for any damage resulting from use of the product that does not comply with the absolute maximum ratings and the instructions included in these specification sheets. 3. These specification sheets include materials protected under copyright of EVERLIGHT Corporation. Please don’t reproduce or cause anyone to reproduce them without EVERLIGHT’s consent. Everlight Electronics Co., Ltd. http://www.everlight.com Device NO.: DPL-233-001 Prepared date: 06-01-2006 Rev 1 Page: 7 of 8 Prepared By: Richard Hsu PLR233 Application Notes: PLR233 Series PCB layout for motherboard integration To achieve better jitter and low input optical power performances, several PCB layout guidelines must be followed. These guidelines ensure the most reliable PLR233 POF performance for the motherboard integration. Failed to implement these PCB guidelines may affect the PLR233 jitter and low input power performances. 1. Careful decoupling of the power supplies is very important. Place a 0.1uf surface mount (size 805 or smaller) capacitor as close as (less than 2cm) to the POF Vdd and Gnd leads. The 0.1uf act as a low impedance path to ground for any stray high frequency transient noises. 2. To reduce the digital noises form the digital IC on the motherboard, the planar capacitance formed by an isolated Vcc and Gnd planes is critical. The POF device must be mounted directly on these two planes to reduce the lead parasitic inductance. 3. The isolated Vdd and Gnd planes must be connected to the main Vcc and Gnd (digital) planes at a single point using ferrite beads. The beads are used to block the high frequency noises from the digital planes while still allowing the DC connections between the planes EVERLIGHT ELECTRONICS CO., LTD. Office: No 25, Lane 76, Sec 3, Chung Yang Rd, Tucheng, Taipei 236, Taiwan, R.O.C Tel: 886-2-2267-2000, 2267-9936 Fax: 886-2267-6244, 2267-6189, 2267-6306 http://www.everlight.com Everlight Electronics Co., Ltd. http://www.everlight.com Device NO.: DPL-233-001 Prepared date: 06-01-2006 Rev 1 Page: 8 of 8 Prepared By: Richard Hsu