SGLS148A − DECEMBER 2002 − REVISED OCTOBER 2004
D Qualification in Accordance With
D PACKAGE
(TOP VIEW)
AEC-Q100†
D Qualified for Automotive Applications
D Customer-Specific Configuration Control
D
D
D
D
D
D
1B
2B
3B
4B
5B
6B
7B
E
Can Be Supported Along With
Major-Change Approval
ESD Protection Exceeds 200 V Using
Machine Model (C = 200 pF, R = 0)
500-mA Rated Collector Current
(Single Output)
High-Voltage Outputs . . . 50 V
Output Clamp Diodes
Inputs Compatible With Various Types of
Logic
Relay-Driver Applications
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1C
2C
3C
4C
5C
6C
7C
COM
† Contact Texas Instruments for details. Q100 qualification data
available on request.
description
The ULQ2003A-Q1 and ULQ2004A-Q1 are high-voltage, high-current Darlington transistor arrays. Each
consists of seven npn Darlington pairs that feature high-voltage outputs with common-cathode clamp diodes
for switching inductive loads. The collector-current rating of a single Darlington pair is 500 mA. The Darlington
pairs can be paralleled for higher current capability. Applications include relay drivers, hammer drivers, lamp
drivers, display drivers (LED and gas discharge), line drivers, and logic buffers.
The ULQ2003A-Q1 has a 2.7-kΩ series base resistor for each Darlington pair, for operation directly with TTL
or 5-V CMOS devices. The ULQ2004A-Q1 has a 10.5-kΩ series base resistor to allow operation directly from
CMOS devices that use supply voltages of 6 V to 15 V. The required input current of the ULQ2004A-Q1 is below
that of the ULQ2003A-Q1.
AVAILABLE OPTIONS
D PACKAGES{
TA
SMALL OUTLINE
ULQ2003ATDQ1
ULQ2003ATDRQ1
−40°C to 105°C
ULQ2004ATDQ1}
ULQ2004ATDRQ1
† The D package is available taped and reeled. Add the suffix R to
device type (e.g., ULQ2003TDADRQ1).
‡ ULQ2004ATDQ1 is Product Preview only.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&+
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"&#"0 !)) '!!&"&#+
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1
SGLS148A − DECEMBER 2002 − REVISED OCTOBER 2004
logic diagram
9
1B
2B
3B
4B
5B
6B
7B
1
16
2
15
3
14
4
13
5
12
6
11
7
10
COM
1C
2C
3C
4C
5C
6C
7C
schematics (each Darlington pair)
COM
Input
B
ULQ2003A-Q1: RB = 2.7 kΩ
ULQ2004A-Q1: RB = 10.5 kΩ
Output
C
RB
7.2 kΩ
3 kΩ
E
ULQ2003A-Q1, ULQ2004A-Q1
All resistor values shown are nominal.
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)†
Collector-emitter voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V
Clamp diode reverse voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V
Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
Peak collector current (see Figure 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Output clamp current, IOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Total emitter-terminal current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2.5 A
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Package thermal impedance, θJA (see Note 2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Operating free-air temperature range, TA, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 105°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SGLS148A − DECEMBER 2002 − REVISED OCTOBER 2004
DISSIPATION RATING TABLE
PACKAGE
25°C
TA = 25
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
85°C
TA = 85
C
POWER RATING
105°C
TA = 105
C
POWER RATING
D
950 mW
7.6 mW/°C
494 mW
342 mW
electrical characteristics over recommended operating conditions (unless otherwise noted)
ULQ2003A-Q1
PARAMETER
TEST CONDITIONS
MIN
TYP
IC = 125 mA
IC = 200 mA
VI(on)
On-state input voltage, See Figure 6
VCE(sat)
ICEX
Collector-emitter saturation voltage,
See Figure 5
Collector cutoff current
VF
Clamp forward voltage,
See Figure 8
II(off)
Off-state input current, See Figure 3
II
Input current, see Figure 4
VCE = 2 V
II = 250 µA,
II = 350 µA,
ULQ2004A-Q1
MAX
MIN
TYP
MAX
5
2.7
IC = 250 mA
IC = 275 mA
2.9
IC = 300 mA
IC = 350 mA
3
6
7
0.9
1.2
0.9
1.1
1
1.4
1
1.3
II = 500 µA,
IC = 350 mA
VCE = 50 V, II = 0,
See Figure 1
1.2
1.7
1.2
1.6
100
V
50
II = 0
VI = 1 V
100
A
µA
500
IF = 350 mA
VCE = 50 V,
VI = 3.85 V
V
8
IC = 100 mA
IC = 200 mA
VCE = 50 V,
See Figure 2
UNIT
1.7
IC = 500 µA
A
30
2.2
65
0.93
1.7
50
Clamp reverse current,
See Figure 7
VR = 50 V,
VR = 50 V
TA = 25°C
Ci
Input capacitance
VI = 0,
f = 1 MHz
V
µA
A
65
1.35
VI = 5 V
VI = 12 V
IR
2.1
15
0.35
0.5
1
1.45
100
50
100
100
25
15
25
mA
A
µA
pF
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ULQ2003A-Q1,
ULQ2004A-Q1
MIN
tPLH
tPHL
VOH
Propagation delay time, low-to-high level output
See Figure 9
Propagation delay time, high-to-low level output
See Figure 9
High-level output voltage after switching
VS = 50 V,
See Figure 10
POST OFFICE BOX 655303
IO ≈ 300 mA,
• DALLAS, TEXAS 75265
VS−500
UNIT
TYP
MAX
1
10
µs
1
10
µs
mV
3
SGLS148A − DECEMBER 2002 − REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
Open
Open
VCE
ICEX
VCE
ICEX
Open
VI
Figure 1. ICEX Test Circuit
Open
Figure 2. ICEX Test Circuit
VCE
Open
II(off)
IC
II(on)
Open
VI
Figure 3. II(off) Test Circuit
Figure 4. II Test Circuit
Open
Open
IC
hFE =
II
VCE
II
IC
VI(on)
VCE
IC
NOTE: II is fixed for measuring VCE(sat), variable for
measuring hFE.
Figure 5. hFE, VCE(sat) Test Circuit
Figure 6. VI(on) Test Circuit
VR
IR
VF
Open
Open
Figure 7. IR Test Circuit
4
POST OFFICE BOX 655303
Figure 8. VF Test Circuit
• DALLAS, TEXAS 75265
IF
SGLS148A − DECEMBER 2002 − REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
50%
Input
50%
tPHL
tPLH
50%
Output
50%
VOLTAGE WAVEFORMS
Figure 9. Propagation Delay-Time Waveforms
VS
2 mH
Open
1N3064
200 Ω
Pulse
Generator
(see Note A)
Output
ULQ2003A-Q1
ULQ2004A-Q1
CL = 15 pF
(see Note B)
TEST CIRCUIT
≤5 ns
≤10 ns
90%
1.5 V
Input
10%
VIH
(see Note C)
90%
1.5 V
10%
40 µs
0V
VOH
Output
VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. For testing the ULQ2003A-Q1, VIH = 3 V; for the ULQ2004A-Q1, VIH = 8 V.
Figure 10. Latch-Up Test Circuit and Voltage Waveforms
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5
SGLS148A − DECEMBER 2002 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
COLLECTOR-EMITTER SATURATION VOLTAGE
vs
TOTAL COLLECTOR CURRENT
(TWO DARLINGTONS IN PARALLEL)
VCE(sat)
VCE(sat) − Collector-Emitter Saturation Voltage − V
VCE(sat)
VCE(sat) − Collector-Emitter Saturation Voltage − V
COLLECTOR-EMITTER SATURATION VOLTAGE
vs
COLLECTOR CURRENT
(ONE DARLINGTON)
2.5
TA = 25°C
2
II = 250 µA
II = 350 µA
II = 500 µA
1.5
1
0.5
0
0
100
200
300
400
500
600
700
2.5
TA = 25°C
II = 250 µA
2
II = 350 µA
1.5
II = 500 µA
1
0.5
0
0
800
100
200
300
Figure 12
Figure 11
COLLECTOR CURRENT
vs
INPUT CURRENT
500
RL = 10 Ω
TA = 25°C
IIC
C − Collector Current − mA
450
400
VS = 10 V
350
VS = 8 V
300
250
200
150
100
50
0
0
500
600
700
IC(tot) − Total Collector Current − mA
IC − Collector Current − mA
25
50
75
100
125
150
II − Input Current − µA
Figure 13
6
400
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• DALLAS, TEXAS 75265
175
200
800
SGLS148A − DECEMBER 2002 − REVISED OCTOBER 2004
THERMAL INFORMATION
MAXIMUM COLLECTOR CURRENT
vs
DUTY CYCLE
IIC
C − Maximum Collector Current − mA
600
500
N=1
N=4
400
N=3
300
N=2
N=6
N=7
N=5
200
100
TA = 70°C
N = Number of Outputs
Conducting Simultaneously
0
0
10
20
30
40
50
60
70
80
90 100
Duty Cycle − %
Figure 14
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7
SGLS148A − DECEMBER 2002 − REVISED OCTOBER 2004
APPLICATION INFORMATION
ULQ2004A-Q1
ULQ2003A-Q1
VCC
VDD
V
V
1
16
1
16
2
15
2
15
3
14
3
14
4
13
4
13
5
12
5
12
6
11
6
11
7
10
7
10
8
9
8
9
CMOS
Lamp Output
Test
TTL
Output
Figure 16. Buffer for Higher Current Loads
Figure 15. TTL to Load
ULQ2003A-Q1
VCC
V
1
16
2
15
RP 3
14
4
13
5
12
6
11
7
10
8
9
TTL
Output
Figure 17. Use of Pullup Resistors
to Increase Drive Current
8
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
ULQ2003ATDQ1
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
ULQ2003ATDRQ1
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
ULQ2004ATDRQ1
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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