SN54ABT32245, SN74ABT32245 36-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS228C – JUNE 1992 – APRIL 1995 • • • • • Members of the Texas Instruments Widebus + Family State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C • • • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise High-Drive Outputs (– 32-mA IOH, 64-mA IOL ) Bus-Hold Inputs Eliminate the Need for External Pullup Resistors Packaged in 100-Pin Plastic Thin Quad Flat (PZ) Package With 14 × 14-mm Body Using 0.5-mm Lead Pitch 1A8 1A7 1A6 GND 1A5 1A4 1A3 1A2 1A1 GND 1DIR 1OE VCC 2OE 2DIR GND 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 SN74ABT32245 . . . PZ PACKAGE (TOP VIEW) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1A9 2A1 GND 2A2 2A3 2A4 2A5 GND 2A6 2A7 2A8 2A9 VCC 3A1 3A2 3A3 3A4 GND 3A5 3A6 3A7 3A8 GND 3A9 4A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1B9 2B1 GND 2B2 2B3 2B4 2B5 GND 2B6 2B7 2B8 2B9 VCC 3B1 3B2 3B3 3B4 GND 3B5 3B6 3B7 3B8 GND 3B9 4B1 4A2 4A3 4A4 GND 4A5 4A6 4A7 4A8 4A9 GND 4DIR 4OE VCC 3OE 3DIR GND 4B9 4B8 4B7 4B6 4B5 GND 4B4 4B3 4B2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 description The ′ABT32245 are 36-bit (quad 9-bit) noninverting 3-state transceivers designed for synchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. These devices can be used as four 9-bit transceivers, two18-bit transceivers, or one 36-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) inputs. The output-enable (OE) inputs can be used to disable the device so that the buses are effectively isolated. Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT32245, SN74ABT32245 36-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS228C – JUNE 1992 – APRIL 1995 description (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or floating data inputs at a valid logic level. The SN54ABT32245 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ABT32245 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE (each 9-bit section) INPUTS 2 OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT32245, SN74ABT32245 36-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS228C – JUNE 1992 – APRIL 1995 logic diagram (positive logic) 1DIR 90 3DIR 89 1A1 92 39 1OE One of Nine Channels 3A1 84 40 14 2DIR 62 4DIR 87 2A1 3B1 To Eight Other Channels 86 2 One of Nine Channels 1B1 To Eight Other Channels 3OE 37 2OE One of Nine Channels 4A1 74 36 25 One of Nine Channels 51 2B1 To Eight Other Channels 4OE 4B1 To Eight Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . – 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT32245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT32245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT32245, SN74ABT32245 36-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS228C – JUNE 1992 – APRIL 1995 recommended operating conditions SN54ABT32245 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current ∆t /∆v Input transition rise or fall rate ∆t /∆VCC Power-up ramp rate 200 TA Operating free-air temperature – 55 High-level input voltage 2 2 0.8 Input voltage 0 Low-level output current Outputs enabled PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 SN74ABT32245 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC – 24 V V 0.8 0 UNIT VCC – 32 V V mA 48 64 mA 10 10 ns / V µs / V 200 125 – 40 85 °C SN54ABT32245, SN74ABT32245 36-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS228C – JUNE 1992 – APRIL 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = – 3 mA VCC = 5 V, IOH = – 3 mA IOH = – 24 mA VCC = 4 4.5 5V VOL II II(hold) I(h ld) SN54ABT32245 TYP† MAX TEST CONDITIONS VCC = 4 4.5 5V MIN –1.2 –1.2 2.5 2.5 3 3 IOH = – 32 mA IOL = 48 mA V 2 0.55 0.55 IOL = 64 mA 0.55 Control inputs VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 A or B ports VCC = 2.1 V to 5.5 V, ± 20 ± 20 A or B ports VCC = 4 4.5 5V VI = VCC or GND VI = 0.8 V VI = 2 V VO = 0.5 V to 2.7 V, VCC = 0 to 2.1 V, OE = X IOZPD‡ VCC = 2.1 V to 0, OE = X VO = 0.5 V to 2.7 V, IOZH§ IOZL§ VCC = 2.1 V to 5.5 V, VCC = 2.1 V to 5.5 V, VO = 2.7 V, VO = 0.5 V, Ioff ICEX IO¶ VCC = 0, VCC = 5.5 V, VI or VO ≤ 4.5 V VO = 5.5 V Outputs high VCC = 5.5 V, VO = 2.5 V Outputs high 100 100 –100 –100 OE ≥ 2 V OE ≥ 2 V ICC VCC = 5.5 V, IO = 0, VI = VCC or GND ∆ICC# VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Control inputs UNIT V 2 IOZPU‡ Ci SN74ABT32245 TYP† MAX MIN – 50 –100 Outputs low Outputs disabled VI = 2.5 V or 0.5 V 3.5 V µA µ µA ± 50 ± 50 µA ± 50 ± 50 µA 10 10 µA – 10 – 10 µA ±100 ±100 µA 50 50 µA –180 mA –180 – 50 –100 3 3 20 20 2 2 1 1 mA mA 3.5 pF Cio A or B ports VO = 2.5 V or 0.5 V 9.5 9.5 † All typical values are at VCC = 5 V, TA = 25°C. ‡ This parameter is specified by characterization. § The parameters IOZH and IOZL include the input leakage current. ¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT32245, SN74ABT32245 36-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS228C – JUNE 1992 – APRIL 1995 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) VCC = 5 V,, TA = 25°C TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OE B or A tPHZ tPLZ OE B or A SN54ABT32245 UNIT MIN TYP MAX MIN MAX MIN 1.7 3.2 4.4 1.7 5.3 1.7 5 1.7 3.3 4.6 1.7 5.3 1.7 5.2 1.6 4.2 6.1 1.6 7.6 1.6 7.3 2.7 5.2 7 2.7 8.2 2.7 8.1 1.3 3.9 6.1 1.3 6.7 1.3 6.5 2 4.4 6.6 2 7.2 2 6.9 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 SN74ABT32245 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX ns ns ns SN54ABT32245, SN74ABT32245 36-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS228C – JUNE 1992 – APRIL 1995 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V Input 1.5 V th 3V 1.5 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 0V 1.5 V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) VOH Output 1.5 V tPZL tPHL tPLH 3V Output Control 1.5 V Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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