54ACT16470, 74ACT16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS237A – JUNE 1990 – REVISED APRIL 1996 D D D D D D D Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Shrink Small-Outline 300-mil (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings description The ’ACT16470 are 16-bit registered transceivers that contain two sets of D-type flip-flops for temporary storage of data flowing in either direction. They can be used as two 8-bit transceivers or one 16-bit transceiver. Separate clock (CLKAB or CLKBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data to B. If both CEAB and CLKAB are low, then B port will have the level of A port prior to the most recent low-to-high transition of CLKAB. Data flow from B to A is similar, but requires the use of CEBA, CLKBA, and OEBA inputs. 54ACT16470 . . . WD PACKAGE 74ACT16470 . . . DL PACKAGE (TOP VIEW) 1OEAB 1CLKAB 1CEAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2CEAB 2CLKAB 2OEAB 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OEBA 1CLKBA 1CEBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2CEBA 2CLKBA 2OEBA To avoid false clocking of the flip-flops, CE should not be switched from high to low while CLK is high. The 74ACT16470 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16470 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74ACT16470 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 54ACT16470, 74ACT16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS237A – JUNE 1990 – REVISED APRIL 1996 FUNCTION TABLE† INPUTS CEAB CLKAB H X OUTPUT B OEAB A X X X Z X H X Z L L L X L ↑ L L B0‡ L L ↑ L H H † A-to-B data flow is shown: B-to-A flow is similar but uses CEBA, CLKBA, and OEBA. ‡ Output level before the indicated steady-state input conditions were established 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54ACT16470, 74ACT16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS237A – JUNE 1990 – REVISED APRIL 1996 logic symbol† 1OEBA 1CEBA 1CLKBA 1OEAB 1CEAB 1CLKAB 56 54 55 1 3 2 29 2OEBA 2CEBA 2CLKBA 31 30 28 2OEAB 2CEAB 2CLKAB 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 26 27 5 1EN3 G1 1C5 2EN4 G2 2C6 7EN9 G7 7C11 8EN10 G8 8C12 3 1 5D 6D 1 4 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 9 1 11D 12D 1 10 41 17 40 19 38 20 37 21 36 23 34 24 33 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 54ACT16470, 74ACT16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS237A – JUNE 1990 – REVISED APRIL 1996 logic diagram (positive logic) 1OEBA 1CEBA 1CLKBA 1OEAB 1CEAB 1CLKAB 1A1 56 54 55 1 3 2 C1 5 1D 52 1B1 C1 1D To Seven Other Channels 2OEBA 2CEBA 2CLKBA 2OEAB 2CEAB 2CLKAB 2A1 29 31 30 28 26 27 C1 15 1D C1 1D To Seven Other Channels 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 42 2B1 54ACT16470, 74ACT16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS237A – JUNE 1990 – REVISED APRIL 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCC + 0.5 V Input voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA Maximum power package dissipation at TA = 55°C (in still air)(see Note 2): DL package . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. recommended operating conditions (see Note 3) 54ACT16470 NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current IOL ∆t/∆v Low-level output current High-level input voltage 74ACT16470 MIN 2 2 0.8 Input transition rise or fall rate 0 TA Operating free-air temperature –55 NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. UNIT V V 0.8 V VCC VCC V –24 –24 mA 24 24 mA VCC VCC 0 0 V 10 0 10 ns/V 125 –40 85 °C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 54ACT16470, 74ACT16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS237A – JUNE 1990 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 4.5 V IOH = –50 50 µA VOH 24 mA IOH = –24 IOH = –75 mA† II IOZ‡ A or B ports ICC Control inputs VI = VCC or GND VO = VCC or GND 54ACT16470 MIN IO = 0 MAX 74ACT16470 MIN 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 4.5 V 3.94 3.8 3.8 5.5 V 4.94 4.8 4.8 3.85 3.85 0.1 0.1 MAX UNIT V 0.1 5.5 V 0.1 0.1 0.1 4.5 V 0.36 0.44 0.44 5.5 V 0.36 0.44 0.44 1.65 1.65 ±1 ±1 µA 5.5 V One input at 3.4 V, Other inputs at VCC or GND ∆ICC§ Ci IOL = 75 mA† VI = VCC or GND VO = VCC or GND VI = VCC or GND, TA = 25°C TYP MAX 4.5 V IOL = 24 mA Control inputs MIN 5.5 V IOL = 50 µA VOL VCC V 5.5 V ±0.1 5.5 V ±0.5 ±5 ±5 µA 5.5 V 8 80 80 µA 5.5 V 0.9 1 1 mA 5V 3 pF Cio A or B ports 5V 11.5 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. pF timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency 0 CLK high 74ACT16470 MIN MAX MIN MAX 0 55 0 55 4 4 4 8.5 8.5 8.5 UNIT MHz tw Pulse duration tsu th Setup time, data before CLK↑ 6 6 6 ns Hold time, data after CLK↑ 1 1 1 ns CLK low PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 55 54ACT16470 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns 54ACT16470, 74ACT16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS237A – JUNE 1990 – REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX 55 CLK A or B OE A or B OE A or B CE A or B CE A or B 54ACT16470 MIN 74ACT16470 MAX MIN 55 MAX 55 UNIT MHz 3.9 8.3 10.3 3.9 11.8 3.9 11.8 3.8 8.4 10.3 3.8 11.7 3.8 11.7 3.2 8.3 10.5 3.2 11.9 3.2 11.9 3.6 9.5 11.8 3.6 13.4 3.6 13.4 4.6 7.4 9.3 4.6 9.9 4.6 9.9 4.6 7 8.8 4.6 9.5 4.6 9.5 3.5 8.8 10.9 3.5 12.5 3.5 12.5 4.2 10.1 12.4 4.2 14.3 4.2 14.3 5.2 8.3 10.3 5.2 11.2 5.2 11.2 5.2 7.9 10 5.2 10.9 5.2 10.9 ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d Power dissipation capacitance per transceiver TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, pF f = 1 MHz TYP 59 39 UNIT pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 54ACT16470, 74ACT16470 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS237A – JUNE 1990 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V 1.5 V th 3V 1.5 V 1.5 V Data Input 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS 3V Input 1.5 V 1.5 V 0V tPHL tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL 3V Output Waveform 2 S1 at GND (see Note B) 1.5 V 1.5 V 0V tPZL [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL Out-of-Phase Output Output Control (low-level enabling) 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated