FUJITSU SEMICONDUCTOR DATA SHEET DS07-13742-1E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90980 Series MB90982/MB90F983/MB90V485B ■ DESCRIPTION The MB90980 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in consumer devices and other applications requiring high-speed real-time processing. The F2MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing. The MB90980 series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up/down-counter, PWC timer, I2C*2 interface, DTP/ external interrupt, chip select, and 16-bit reload timer. *1 : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. *2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C standard Specification as defined by Philips. ■ FEATURES • Clock • Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied × 4 (25 MHz internal operating frequency/3.3 V ± 0.3 V) 62.5 ns/4 MHz base frequency multiplied × 4 (16 MHz internal operating frequency/3.0 V ± 0.3 V) PLL clock multiplier (Continued) Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://jp.fujitsu.com/microelectronics/products/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2006 FUJITSU LIMITED All rights reserved MB90980 Series (Continued) • Maximum memory space • 16 Mbytes • Instruction set optimized for controller applications • Supported data types (bit, byte, word, or long word) • Typical addressing modes (23 types) • Enhanced signed multiplication/division instruction and RETI instruction functions • 32-bit accumulator for enhanced high-precision calculation • Instruction set designed for high-level language (C) and multi-task operations • System stack pointer adopted • Instruction set compatibility and barrel shift instructions • Enhanced execution speed • 4 byte instruction queue • Enhanced interrupt functions • 8 levels setting with programmable priority, 8 external interrupt pins • Data transmission function (µDMAC) • Up to 16 channels • Embedded ROM • Flash versions : 192 Kbytes, Mask versions : 128 Kbytes • Embedded RAM • Flash versions : 12 Kbytes, Mask versions : 10 Kbytes • General purpose ports • Up to 48 ports (10 ports with output open-drain settings) • 8/10-bit A/D converter • 8-channel RC sequential comparison type (10-bit resolution, 3.68 µs conversion time (at 25 MHz) ) • I2C interface • 1 channel, P76/P77 N-ch open drain pin (without P-ch) • UART • 1 channel • Extended I/O serial interface (SIO) • 2 channels • 8/16-bit PPG • 2 channels (with 8-bit × 4 channels/16-bit × 2 channels mode switching function) • 8/16-bit up/down timer • 1 channel (with 8-bit × 2 channels/16-bit × 1-channel mode switching function) • 16-bit PWC • 2 channels (Capable of compare the inputs) • 16-bit reload timer • 1 channel • 16-bit I/O timer • 2 channels input capture, 4 channels output compare, 1 channel free run timer • On chip dual clock generator system • Low-power consumption (standby) mode • With stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, timebase timer mode 2 MB90980 Series • Packages • LQFP 64 • Process • CMOS technology • Power supply voltage 3 V, single source (some ports can be operated by 5 V power supply.) 3 MB90980 Series ■ PRODUCT LINEUP Part number Item Classification ROM size RAM size MB90982 MB90F983 MB90V485B Mask ROM product Flash memory product Evaluation product 128 Kbytes 192 Kbytes ⎯ 10 Kbytes 12 Kbytes 16 Kbytes Number of instructions : 351 Instruction bit length : 8-bit, 16-bit CPU function Instruction length : 1 byte to 7 bytes Data bit length : 1-bit, 8-bits, 16-bits Minimum execution time : 40 ns (25 MHz machine clock) General-purpose I/O ports: up to 48 General-purpose I/O ports (CMOS output) Ports General-purpose I/O ports (with pull-up resistance Input) General-purpose I/O ports (N-ch open drain output) UART 1 channel, start-stop synchronized 8-bit × 6 channels/ 8/16-bit PPG 8-bit × 4 channels/16-bit × 2 channels 16-bit × 3 channels 8/16-bit up/down 6 event input pins, 8-bit up/down counters : 2 counter/timer 8-bit reload/compare registers : 2 16-bit free run Number of channels : 1 timer Overflow interrupt Number of channels : 6 16-bit Output compare Number of channels : 4 Pin input factor : A match I/O timers (OCU) Pin input factor : A match signal of compare register signal of compare register Input capture Number of channels : 2 (ICU) Rewriting a register value upon a pin input (rising, falling, or both edges) DTP/external interrupt circuit Number of external interrupt channels : 8 (edge or level detection) Extended I/O serial interface 2 channels, embedded 1 channel I2C interface*2 PWC 2 channels 3 channels 18-bit counter Timebase timer Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator) Conversion resolution : 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels, A/D converter programmable up to 8 channels) Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause) Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms Watchdog timer (minimum value, at 4 MHz base oscillator) Low-power consumption Sleep mode, stop mode, CPU intermittent mode, watch timer mode, timebase timer (standby) modes mode Process CMOS Mask model 3V/5V Flash model 3V/5V 3V/5V power supply*1 Type power supply*1 power supply*1 Emulator power supply*3 ⎯ ⎯ Yes (Continued) 4 MB90980 Series (Continued) *1 : 3V/5V I/F pin : All pins should be for 3 V power supply without P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76, and P77. *2 : P76/P77 pins are N-ch open drain pins (without P-ch) at built-in I2C. *3 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the hardware manual of MB2147-01 or MB2147-20 (“3.3 Emulator-dedicated Power Supply Switching”) about details. Note : Ensure that you must write to Flash at VCC = 3.13 V to 3.60 V (3.3 V + 10%, −5%) . 5 MB90980 Series ■ PIN ASSIGNMENT AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 P82/IRQ2 P83/IRQ3 RST X0A X1A 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (TOP VIEW) AVCC 1 48 VSS AVRH 2 47 X1 P27/PPG3 3 46 X0 P26/PPG2 4 45 MOD2 P25/PPG1 5 44 MOD1 30 31 32 VCC3 VSS P97/IN1 P96/IN0 33 PA0/OUT0 34 16 29 15 VCC5 PA1/OUT1 P42/SCK2 28 P93/FRCK/ADTG 27 P92/SCK1 35 PA2/OUT2 36 14 PA3/OUT3 13 P30/AIN0 26 P31/BIN0 P70/SIN0 P91/SOT1 25 P90/SIN1 37 24 38 12 P71/SOT0 11 P32/ZIN0 P72/SCK0 P33/AIN1 23 P87/IRQ7 P73/TIN0 39 22 10 P74/TOT0 P34/BIN1 21 P86/IRQ6 20 P85/IRQ5 40 P76/SCL 41 9 P77/SDA 8 P35/ZIN1 19 P36/PWC0 P40/SIN2 P84/IRQ4 18 MOD0 42 17 43 7 VSS 6 P41/SOT2 P24/PPG0 P37/PWC1 (FPT-64P-M03) Notes : • I2C pin P76 and P77 are N-ch open drain pin (without P-ch) . • P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76 and P77 also used as 3 V/5 V I/F pin. 6 MB90980 Series ■ PIN DESCRIPTIONS Pin No. Pin name I/O Circuit type* 46 X0 A Oscillator pin 47 X1 A Oscillator pin 50 X0A A 32 kHz oscillator pin 49 X1A A 32 kHz oscillator pin 51 RST B Reset input pin P27 to P24 E (CMOS/H) General purpose I/O port E (CMOS/H) General purpose I/O port E (CMOS/H) General purpose I/O port E (CMOS/H) General purpose I/O port 3 to 6 14 13 12 11 10 9 7, 8 19 18 15 60 to 63 56 to 59 26 25 PPG3 to PPG0 P30 AIN0 P31 BIN0 P32 ZIN0 P33 AIN1 P34 BIN1 P35 ZIN1 P37, P36 PWC1, PWC0 P40 SIN2 P41 SOT2 P42 SCK2 P63 to P60 AN3 to AN0 P67 to P64 AN7 to AN4 P70 SIN0 P71 SOT0 Function PPG timer output pin 8/16-bit up/down timer counter input pin (ch.0) 8/16-bit up/down timer counter input pin (ch.0) 8/16-bit up/down timer counter input pin (ch.0) E (CMOS/H) General purpose I/O port E (CMOS/H) General purpose I/O port E (CMOS/H) E (CMOS/H) 8/16-bit up/down timer counter input pin (ch.1) 8/16-bit up/down timer counter input pin (ch.1) General purpose I/O port 8/16-bit up/down timer counter input pin (ch.1) General purpose I/O port PWC input pin G (CMOS/H) General purpose I/O port F (CMOS) General purpose I/O port G (CMOS/H) Simple serial I/O 2-input pin Simple serial I/O 2-output pin General purpose I/O port Simple serial I/O 2-clock I/O pin H (CMOS) General purpose I/O port F (CMOS) General purpose I/O port G (CMOS/H) General purpose I/O port F (CMOS) General purpose I/O port Analog input pin Analog input pin UART data input pin UART data output pin (Continued) 7 MB90980 Series Pin No. 24 23 22 Pin name P72 SCK0 P73 TIN0 P74 TOT0 P76 21 SCL P77 20 52 to 55 39 to 42 38 37 36 SDA P83 to P80 IRQ3 to IRQ0 P87 to P84 IRQ7 to IRQ4 P90 SIN1 P91 SOT1 P92 SCK1 I/O Circuit type* G (CMOS/H) General purpose I/O port G (CMOS/H) General purpose I/O port F (CMOS) I (NMOS/H) I (NMOS/H) FRCK UART clock I/O pin 16-bit reload timer event input pin General purpose I/O port 16-bit reload timer output pin General purpose I/O port This pin functions as the I2C interface clock I/O pin. Set port output to Hi-Z during the I2C interface operation. General purpose I/O port This pin functions as the I2C interface data I/O pin. Set port output to Hi-Z during the I2C interface operation. E (CMOS/H) General purpose I/O port E (CMOS/H) General purpose I/O port E (CMOS/H) General purpose I/O port D (CMOS) General purpose I/O port E (CMOS/H) P93 35 Function External interrupt input pin External interrupt input pin Simple serial I/O1-data input pin Simple serial I/O-1 data output pin General purpose I/O port Simple serial I/O-1 data I/O pin General purpose I/O port E (CMOS/H) When using free-run timer, this pin functions as the external clock input pin. When using A/D converter, this pin fuctions as the external trigger input pin. ADTG E (CMOS/H) General purpose I/O port E (CMOS/H) General purpose I/O port General purpose I/O port OUT3 to OUT0 D (CMOS) 1 AVCC ⎯ A/D converter power supply pin 2 AVRH ⎯ A/D converter external reference power supply pin 64 AVSS ⎯ A/D converter power supply pin 43 to 45 MD0 to MD2 J (CMOS/H) 32 VCC3 ⎯ 34 31 27 to 30 P96 IN0 P97 IN1 PA3 to PA0 Input capture ch.0 trigger input pin Input capture ch.1 trigger input pin Output compare event output pin Operating mode selection input pins 3.3 V ± 0.3 V power supply pins (VCC3) (Continued) 8 MB90980 Series (Continued) Pin No. Pin name I/O Circuit type* Function 16 VCC5 ⎯ 3 V/5 V power supply pin. 5 V power supply pin when P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76 and P77 are used as 5 V I/F pins. Usually, use VCC = VCC3 = VCC5 as a 3 V power supply (when the 3 V power supply is used alone) . 17, 33, 48 VSS ⎯ Power supply input pins (GND) * : Refer to “■ I/O CIRCUIT TYPES” for I/O circuit types. 9 MB90980 Series ■ I/O CIRCUIT TYPES Type Circuit Remarks • Oscillator feedback resistance X1, X0 : approx. 1 MΩ X1A, X0A : approx. 10 MΩ • With standby control X1, X1A X0, X0A A Hard/soft standby control signal Hysteresis input with pull-up resistance B HYS • With input pull-up resistance control • CMOS level input/output CTL P-ch C P-ch N-ch CMOS Standby control signal CMOS level input/output P-ch N-ch D CMOS Standby control signal • Hysteresis input • CMOS level output P-ch N-ch E CMOS Standby control signal (Continued) 10 MB90980 Series (Continued) Type Circuit P-ch Remarks • CMOS level input/output • With open drain control Open drain control signal N-ch F CMOS Standby control signal P-ch • CMOS level output • Hysteresis input • With open drain control Open drain control signal N-ch G Standby control signal • CMOS level input/output • Analog input P-ch N-ch H CMOS Standby control signal Analog input Digital output • Hysteresis input • N-ch open drain output I HYS Standby control signal • CMOS level input • With high voltage control for flash testing Flash memory model Control signal J Mode input Diffusion resistance Hysteresis input Mask ROM model Hysteresis input 11 MB90980 Series ■ CAUTION OF USING DEVICES 1. Maximum rated voltages (preventing latchup) In CMOS IC devices, a condition known as latchup may occur if voltages higher than VCC or lower than VSS are applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between VCC and VSS exceeds the rated voltage level. When latchup occurs, the power supply current increases rapidly causing the possibility of thermal damage to circuit elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation. Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply voltages (AVCC and AVRH) and analog input voltages do not exceed the digital power supply (VCC) . 2. Treatment of unused pins Leaving unused input pins unconnected can cause abnormal operation or latchup, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. 3. Notes on Using External Clock Even when using an external clock signal, an oscilltion stabilization delay is applied after a power-on reset or when recovering from sub-clock or stop mode. When using an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals. X0 OPEN X1 4. Treatment of Power Supply Pins (VCC/VSS) When multiple VCC pins or VSS pins are present, device design considerations for prevention of latch-up and unwanted electromagnetic interference, abnormal storobe signal operation due to ground level rise, and conformity with total output current ratings require that all power supply pins must be externally connected to power supply or ground. Consideration should be given to connecting power supply sources to the VCC pin or VSS pin of this device with as low impedane as possible. It is also recommended that a bypass capacitor of approximately 0.1 µF be placed between the VCC and VSS lines as close to this device as possible. 5. Crystal Oscillator Circuits Noise around the high-speed oscillation pins (X0 and X1) and low-speed oscillation pins (X0A and X1A) may cause this device to operate abnormally. Design the printed circuit board so that the crystal oscillator (or ceramic oscillator) and bypass capacitor to the ground are located as close to the high-speed oscillation pins and lowspeed oscillation pins as possible. Also, design the printed circuit board to prevent the wiring from crossing another writing. It is highly recommended to provide a printed circuit board artwork surrounding the high-speed oscillation pins and low-speed oscillation pins with a ground area for stabilizing the operation. 12 MB90980 Series 6. Notes on during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 7. Proper power-on/off sequence The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power supply (VCC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut off before the digital power supply (VCC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed AVCC. 8. Treatment of power supply pins on models with A/D converters Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC, and AVSS = VSS. 9. Precautions when turning the power supply on In order to prevent abnormal operation in the chip’s internal step-down circuits, a voltage rise time during poweron of 50 µs (0.2 V to 2.7 V) or greater should be assured. 10. Supply Voltage Stabilization Even within the operating range of VCC supply voltage, rapid voltage fluctuations may cause abnormal operation. As a standard for power supply voltage stability, it is recommended that the peak-to-peak VCC ripple voltage at commercial supply frequency (50 Hz/60 Hz) be 10 % or less of VCC, and that the transient voltage fluctuation be no more than 0.1 V/ms or less when the power supply is turned on or off. 11. Notes on Using Power Supply Only the MB90980 series usually uses a 3 V power supply. By setting VCC3 = 3 V power supply and VCC5 = 5 V power supply, P24 to P27, P30 to P37, P40 to P42 and P70 to P74, P76, P77 can be intefaced as 5 V power supplies separately from the main 3 V power supply. Note that the analog power supplies (such as AVCC and AVSS) for the A/D converter can be used only as 3 V power supplies. 12. Treatment of NC pins NC (internally connected) pins should always be left open. 13. Writing to Flash memory For serial writing to Flash memory, always ensure that the operating voltage VCC is between 3.13 V and 3.6 V. For normal writing to Flash memory, always ensure that the operating voltage VCC is between 3.0 V and 3.6 V. 13 MB90980 Series ■ BLOCK DIAGRAM X0, X1, RST X0A, X1A MD2, MD1, MD0 8 CPU F2MC16LX series core Clock control Circuit RAM Interrupt controller ROM 2 8/16-bit PPG 8/16-bit up/down counter Communication prescaler PPG0, PPG1 2 PPG2, PPG3 2 2 2 SIN1, SIN2 SOT1, SOT 2 SCK1, SCK2 AVCC AVRH AVSS ADTG AN0 to AN7 F2MC-16LX Bus 2 SIN0 SOT0 SCK0 UART 2 2 2 8 Extended I/O serial interface × 2 channels Input/output timer 16-bit input capture × 2 2 channels 16-bit output compare × 4 channels 16-bit free-run timer 4 IN0, IN1 OUT0, OUT1, OUT2, OUT3, 16-bit reload timer TIN0 TOT0 I2C interface SCL SDA A/D converter ( 8/10-bit ) PWC0 PWC1 AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 External interrupt 8 IRQ0 to IRQ7 PWC × 2 channels I/O port 4 8 P24 3 P30 8 P40 5 P60 2 P70 to to to to to P27 P37 P42 P67 P74 P76, P77 8 4 P80 2 P90 to to P87 P93 P96, P97 4 PA0 to PA3 P40 to P42 ( × 3) : with an open drain setting register I2C pin P77 and P76 are N-ch open drain pin (without P-ch) . Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a set of pins is used with an internal module, it cannot also be used as an I/O port. 14 MB90980 Series ■ MEMORY MAP Single chip FFFFFFH ROM area Address #1 FC0000H 010000H ROM area, Image of FF bank Address #2 Address #3 RAM Register 000100H 0000D0H Peripheral 000000H Internal access Model Address #1 MB90F983 FC0000H *1 No access Address #2 004000H or 008000H, selected by the MS bit in MB90982 FD0000H*2 the ROMM register *1 : No memory cells from FC0000H to FC7FFFH and FE0000H to FE7FFFH. Address #3 003100H 002900H *2 : No memory cells from FE0000H to FEFFFFH. The upper part of the 00 bank is set up to mirror the image of FF bank ROM, to enable efficient use of small model C compilers. Because the lower 16-bit address of the FF bank and the lower 16-bit address of the 00 bank is the same, enabling reference to tables in ROM without the “far” pointer declaration. For example, in accessing address 00C000H it is actually the contents of ROM at FFC000H that are accessed. If the MS bit in the ROMM register is set to “0”, the ROM area in the FF bank will exceed 48 Kbytes and it is not possible to reflect the entire area in the image in the 00 bank. Therefore the image from FF4000H to FFFFFFH is reflected in the 00 bank and the area from FF0000H to FF3FFFH can be seen in the FF bank only. 15 MB90980 Series ■ F2MC-16LX CPU PROGRAMMING MODEL •Dedicated registers AH Accumulator AL USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program counter bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8-bit 16-bit 32-bit •General purpose registers MSB LSB 16-bit 000180H + RP × 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 •Processor status bit 13 bit 12 bit 15 PS 16 ILM bit 8 bit 7 RP bit 0 CCR MB90980 Series ■ I/O MAP Abbreviated Address register name 000000H, 000001H PDR2 000002H 000003H PDR3 000004H PDR4 000005H PDR6 000006H 000007H PDR7 000008H PDR8 000009H PDR9 00000AH PDRA Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register 00000BH UDER Up/down timer input enable register R/W 00000CH 00000DH 00000EH 00000FH 000010H, 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH ENIR EIRR Interrupt/DTP enable register Interrupt/DTP source register Request level setting register Request level setting register R/W R/W R/W R/W DDR2 DDR3 DDR4 Port 2 direction register Port 3 direction register Port 4 direction register DDR6 DDR7 DDR8 DDR9 DDRA Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register 00001BH ODR4 Port 4 output pin register ELVR Register name Port 2 data register Port 3 data register Port 4 data register Port 7 output pin register 00001FH 000020H ADER SMR Analog input enable register Serial mode register 000024H 000025H R/W R/W R/W Reserved area R/W R/W R/W R/W R/W Port 2 Port 3 Port 4 XXXXXXXXB XXXXXXXXB XXXXXXXXB Port 6 Port 7 Port 8 Port 9 Port A Up/down timer input control XXXXXXXXB 11XXXXXXB XXXXXXXXB XXXXXXXXB - - - - XXXXB XX 0 0 0 0 0 0B DTP/external interrupts 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B R/W R/W R/W Reserved area R/W R/W R/W R/W R/W Port 2 Port 3 Port 4 0 0 0 0 XXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B Port 6 Port 7 Port 8 Port 9 Port A Port 4 (Open-drain control) 0 0 0 0 0 0 0 0B XX 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 XX 0 0 0 0B - - - - 0 0 0 0B R/W Port 7 (Open-drain control) Port 6, A/D XXX 0 0 0 0 0B XXXXX 0 0 0B Reserved area ODR7 000023H Initial value Reserved area 00001EH 000022H Resource name Reserved area 00001CH, 00001DH 000021H R/W R/W R/W R/W W, SCR Serial control register R/W SIDR/SODR Serial input/output register R/W R, SSR Serial status register R/W Reserved area Communication prescaler control CDCR R/W register 1 1 1 1 1 1 1 1B 0 0 0 0 0 X 0 0B 0 0 0 0 0 1 0 0B UART XXXXXXXXB 0 0 0 0 1 0 0 0B Communication prescaler (UART) 0 0 - - 0 0 0 0B (Continued) 17 MB90980 Series Abbreviated Address register Register name name SMCS0 Serial mode control status register 0 000026H 000027H SMCS0 Serial mode control status register 0 000028H SDR0 Serial data register 0 R/W Resource name Initial value R, R/W R, R/W R/W SIO1 (ch.0) - - - - 0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB R/W Communication prescaler SIO1 (ch.0) 0 - - - 0 0 0 0B R, R/W R, R/W R/W SIO2 (ch.1) - - - - 0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB Communication prescaler SIO2 (ch.1) 0 - - - 0 0 0 0B 8/16-bit PPG (ch.0 to ch.3) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 8/16-bit PPG (ch.0 to ch.3) 0 X 0 0 0XX 1B 0 X 0 0 0 0 0 1B 0 X 0 0 0XX 1B 0 X 0 0 0 0 0 1B 8/16-bit PPG 0 0 0 0 0 0 0 0B 8/16-bit PPG 0 0 0 0 0 0 0 0B 8/10-bit A/D converter 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 XXXB 000029H SDCR0 Communication prescaler control register 0 00002AH 00002BH 00002CH SMCS1 SMCS1 SDR1 Serial mode control status register 1 Serial mode control status register 1 Serial data register 1 00002DH SDCR1 Communication prescaler control register 1 R/W 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H to 000039H 00003AH 00003BH 00003CH 00003DH 00003EH, 00003FH 000040H 000041H 000042H 000043H to 000045H 000046H 000047H 000048H 000049H PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 Reload register L (ch.0) Reload register H (ch.0) Reload register L (ch.1) Reload register H (ch.1) Reload register L (ch.2) Reload register H (ch.2) Reload register L (ch.3) Reload register H (ch.3) R/W R/W R/W R/W R/W R/W R/W R/W Reserved area PPGC0 PPGC1 PPGC2 PPGC3 PPG0 operating mode control register PPG1 operating mode control register PPG2 operating mode control register PPG3 operating mode control register R/W R/W R/W R/W Reserved area PPG01 PPG23 PPG0, PPG1 output control register R/W Reserved area PPG2, PPG3 output control register R/W Reserved area ADCS1 ADCS2 ADCR1 ADCR2 Control status register Data register R/W W, R/W R W, R (Continued) 18 MB90980 Series Abbreviated Address register Register name name 00004AH Output compare register (ch.0) lower digits OCCP0 00004BH Output compare register (ch.0) upper digits 00004CH 00004DH 00004EH 00004FH 000050H 000051H OCCP1 OCCP2 OCCP3 Output compare register (ch.1) lower digits Output compare register (ch.1) upper digits Output compare register (ch.2) lower digits Output compare register (ch.2) upper digits Output compare register (ch.3) lower digits Output compare register (ch.3) upper digits R/W Resource name 0 0 0 0 0 0 0 0B R/W R/W R/W Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 16-bit I/O timer 0 0 0 0 0 0 0 0B output compare (ch.0 to ch.3) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B R/W 0 0 0 0 0 0 0 0B 000052H to 000055H Reserved area 000056H Output compare control register (ch.0, ch.1) lower digits R/W 0 0 0 0 - - 0 0B 000057H Output compare control register (ch.0, ch.1) upper digits R/W 000058H Output compare control register (ch.2, ch.3) lower digits R/W 16-bit I/O timer - - - 0 0 0 0 0B output compare (ch.0 to ch.3) 0 0 0 0 - - 0 0B 000059H Output compare control register (ch.2, ch.3) upper digits R/W - - - 0 0 0 0 0B 00005AH, 00005BH Reserved area R XXXXXXXXB OCS01 OCS23 00005CH 00005DH 00005EH 00005FH 000060H IPCP0 IPCP1 Input capture data register (ch.0) lower digits Input capture data register (ch.0) upper digits R Input capture data register (ch.1) lower digits R Input capture data register (ch.1) upper digits R ICS01 Input capture control status register 000062H TCDT 000063H 16-bit I/O timer input capture (ch.0, ch.1) XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W 0 0 0 0 0 0 0 0B Timer counter data register lower digits R/W 0 0 0 0 0 0 0 0B TCDT Timer counter data register upper digits R/W 0 0 0 0 0 0 0 0B 000064H TCCS Timer counter control status register R/W 000065H TCCS Timer counter control status register R/W 16-bit I/O timer 0 0 0 0 0 0 0 0B free-run timer 0 - - 0 0 0 0 0B 000061H 000066H 000067H Reserved area CPCLR Compare clear register lower digits Compare clear register upper digits 000068H UDCR0 Up/down count register (ch.0) XXXXXXXXB R/W XXXXXXXXB R 0 0 0 0 0 0 0 0B 000069H UDCR1 Up/down count register (ch.1) R 0 0 0 0 0 0 0 0B 00006AH RCR0 Reload/compare register (ch.0) W 0 0 0 0 0 0 0 0B 00006BH RCR1 Reload/compare register (ch.1) W 00006CH CCRL0 Counter control register (ch.0) lower digits W, R/W 00006DH CCRH0 Counter control register (ch.0) upper digits R/W 8/16-bit up/ down counter/ timer 0 0 0 0 0 0 0 0B 0 X 0 0 X 0 0 0B 0 0 0 0 0 0 0 0B (Continued) 19 MB90980 Series Abbreviated Address register name Register name 00006EH R/W Resource name Initial value ROM mirroring function - - - - - - 0 1B Reserved area 00006FH ROMM 000070H CCRL1 000071H CCRH1 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH to 000081H 000082H 000083H 000084H 000085H to 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH, 00008EH 00008FH to 00009BH 00009CH 00009DH CSR0 CSR1 PWCSR0 PWCR0 PWCSR1 PWCR1 ROM mirror function select register R/W Counter control register (ch.1) R/W lower digits Counter control register (ch.1) R/W upper digits Counter status register (ch.0) R/W Reserved area Counter status register (ch.1) R, R/W Reserved area 0 X 0 0 X 0 0 0B 8/16-bit up/down counter/timer - 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 8/16-bit UDC 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 XB PWC timer (ch.0) 0 0 0 0 0 0 0 0B R/W 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B R, R/W 0 0 0 0 0 0 0 XB PWC timer (ch. 1) 0 0 0 0 0 0 0 0B R/W 0 0 0 0 0 0 0 0B PWC control/status register R, R/W PWC data buffer register PWC control/status register PWC data buffer register Reserved area DIVR0 DIVR1 Dividing ratio control register R/W Reserved area Dividing ratio control register R/W PWC (ch.0) - - - - - - 0 0B PWC (ch.1) - - - - - - 0 0B I2C 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - 0 X X X X XB - X X X X X X XB XXXXXXXXB Reserved area IBSR IBCR ICCR IADR IDAR Bus status register Bus control register Clock control register Address register Data register R R/W R/W R/W R/W Reserved area Disabled DSRL DSRH 00009EH PACSR 00009FH DIRR µDMAC status register µDMAC status register Program address detection control status resister Dilayed interrupt source generator/ cancel register R/W R/W R/W R/W µDMAC 0 0 0 0 0 0 0 0B µDMAC 0 0 0 0 0 0 0 0B Address match 0 0 0 0 0 0 0 0B detection function Delayed interruput - - - - - - - 0B generator module (Continued) 20 MB90980 Series Abbreviated Address register name Register name R/W Resource name Initial value 0000A0H LPMCR Low-power consumption mode control register W, R/W Low-power operation 0 0 0 1 1 0 0 0B 0000A1H CKSCR Clock select register R, R/W Low-power operation 1 1 1 1 1 1 0 0B 0000A2H to 0000A7H Reserved area 0000A8H WDTC Watchdog timer control register R, W Watchdog timer XXXXX 1 1 1B 0000A9H TBTC Timebase timer control register W, R/W Timebase timer 1 X X 0 0 1 0 0B 0000AAH WTC Watch timer control register R, R/W Watch timer 1 0 0 0 1 0 0 0B 0000ABH Reserved area 0000ACH DERL µDMAC enable register R/W µDMAC 0 0 0 0 0 0 0 0B 0000ADH DERH µDMAC enable register R/W µDMAC 0 0 0 0 0 0 0 0B 0000AEH FMCS Flash memory control status register 0000AFH W, R/W Flash memory I/F 0 0 0 X 0 0 0 0B Disabled 0000B0H ICR00 Interrupt control register 00 W, R/W 0 0 0 0 0 1 1 1B 0000B1H ICR01 Interrupt control register 01 W, R/W 0 0 0 0 0 1 1 1B 0000B2H ICR02 Interrupt control register 02 W, R/W 0 0 0 0 0 1 1 1B 0000B3H ICR03 Interrupt control register 03 W, R/W 0 0 0 0 0 1 1 1B 0000B4H ICR04 Interrupt control register 04 W, R/W 0 0 0 0 0 1 1 1B 0000B5H ICR05 Interrupt control register 05 W, R/W 0 0 0 0 0 1 1 1B 0000B6H ICR06 Interrupt control register 06 W, R/W 0 0 0 0 0 1 1 1B 0000B7H ICR07 interrupt control register 07 W, R/W 0000B8H ICR08 Interrupt control register 08 W, R/W 0000B9H ICR09 Interrupt control register 09 W, R/W 0 0 0 0 0 1 1 1B 0000BAH ICR10 Interrupt control register 10 W, R/W 0 0 0 0 0 1 1 1B 0000BBH ICR11 Interrupt control register 11 W, R/W 0 0 0 0 0 1 1 1B 0000BCH ICR12 Interrupt control register 12 W, R/W 0 0 0 0 0 1 1 1B 0000BDH ICR13 Interrupt control register 13 W, R/W 0 0 0 0 0 1 1 1B 0000BEH ICR14 Interrupt control register 14 W, R/W 0 0 0 0 0 1 1 1B 0000BFH ICR15 Interrupt control register 15 W, R/W 0 0 0 0 0 1 1 1B 0000C0H to 0000C9H 0000CAH 0000CBH 0000CCH 0000CDH 0000CEH Interrupt controller 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B Reserved area TMCSR TMR/TMRLR Timer control status register 16-bit timer register/ 16-bit reload register 0 0 0 0 0 0 0 0B R/W 16-bit reload timer R/W - - - - 0 0 0 0B XXXXXXXXB Reserved area (Continued) 21 MB90980 Series (Continued) Abbreviated Address register name 0000CFH PLLOS Register name PLL output select register 0000D0H to 0000FFH External area 000100H to 00000#H RAM area PADR0 Program address detection resister 0 (Middle order address) 001FF2H Program address detection resister 0 (High order address) 001FF3H Program address detection resister 1 (Low order address) 001FF4H 001FF5H PADR1 Program address detection resister 1 (Middle order address) Program address detection resister 1 (High order address) Notes : • Descriptions for R/W R/W : Enabled to read and write R : Read only W : Write only • Descriptions for initial value 0 : The initila value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. : This bit is not used. 22 Resource name Initial value W Low-power operation - - - - - - 0 0B R/W Address match detection function XXXXXXXXB R/W Address match detection function XXXXXXXXB Program address detection resister 0 (Low order address) 001FF0H 001FF1H R/W MB90980 Series ■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS Clear of EI2OS µDMAC cnannel number Number Address Number Address Reset × ⎯ #08 FFFFDCH ⎯ ⎯ INT9 instruction × ⎯ #09 FFFFD8H ⎯ ⎯ Exception × ⎯ #10 FFFFD4H ⎯ ⎯ INT0 (IRQ0) 0 #11 FFFFD0H INT1 (IRQ1) × #12 FFFFCCH ICR00 0000B0H INT2 (IRQ2) × #13 FFFFC8H INT3 (IRQ3) × #14 FFFFC4H ICR01 0000B1H INT4 (IRQ4) × #15 FFFFC0H INT5 (IRQ5) × #16 FFFFBCH ICR02 0000B2H INT6 (IRQ6) × #17 FFFFB8H INT7 (IRQ7) × #18 FFFFB4H ICR03 0000B3H PWC1 × #19 FFFFB0H ⎯ #20 FFFFACH ICR04 0000B4H 1 #21 FFFFA8H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH Interrupt source ⎯ ⎯ PWC0 Interrupt vector PPG0/PPG1 counter borrow × 2 #22 FFFFA4H PPG2/PPG3 counter borrow × 3 #23 FFFFA0H ⎯ ⎯ #24 FFFF9CH 8/16-bit up/down counter/ timer (ch.0, ch.1) compare/ underflow/overflow/inversion × #25 FFFF98H Input capture (ch.0) load 5 #26 FFFF94H Input capture (ch.1) load 6 #27 FFFF90H Output compare (ch.0) match 8 #28 FFFF8CH Output compare (ch.1) match 9 #29 FFFF88H Output compare (ch.2) match 10 #30 FFFF84H Output compare (ch.3) match × #31 FFFF80H ⎯ ⎯ ⎯ ⎯ #32 FFFF7CH ⎯ ⎯ ⎯ #33 FFFF78H UART sending completed 11 #34 FFFF74H 16-bit free run timer overflow, 16-bit reload timer underflow*2 12 #35 FFFF70H UART receiving compleated 7 #36 FFFF6CH SIO1 (ch.0) 13 #37 FFFF68H SIO2 (ch.1) 14 #38 FFFF64H Interrupt control register (Continued) 23 MB90980 Series (Continued) Interrupt source I2C interface Clear of EI2OS µDMAC channel number Number Address × × #39 FFFF60H 15 #40 FFFF5CH × #41 FFFF58H 8/10-bit A/D converter Flash write/erase, timebase timer,watch timer *1 × Delay interrupt generator module × × Interrupt vector #42 Interrupt control register Number Address ICR14 0000BEH ICR15 0000BFH FFFF54H × : Interrupt request flag is not cleared by the interrupt clear signal. : Interrupt request flag is cleared by the interrupt clear signal. : Interrupt request flag is cleared by the interrupt clear signal (stop request present) . *1 : Caution : The Flash write/erase, timebase timer, and watch timer cannot be used at the same time. *2 : When the 16-bit reload timer underflow interrupt is changed from enable (TMCSR : INTE = 1) to disable (TMCSR : INTE = 0) , disable the interrupt in the interrupt control register (ICR12 : IL2 to IL0 : 111B) , then set the INTE bit to 0. Note : If there are two interrupt sources for the same interrupt number, the interrupt request flags of both resources are cleared by the EI2OS/µDMAC. Therefore if either of the two sources uses the EI2OS/µDMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the resource that does not use the EI2OS/µDMAC function should be set to “0” and the interrupt function should be handled by software polling. 24 MB90980 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min Max VCC3 VSS − 0.3 VSS + 4.0 V VCC5 VSS − 0.3 VSS + 7.0 V AVCC VSS − 0.3 VSS + 4.0 V AVRH VSS − 0.3 VSS + 4.0 V VSS − 0.3 VSS + 4.0 V *3 VSS − 0.3 VSS + 7.0 V *3, *8, *9 VSS − 0.3 VSS + 4.0 V *3 VSS − 0.3 VSS + 7.0 V *3, *8, *9 ICLAMP −2.0 +2.0 mA *7 Σ⏐ICLAMP⏐ ⎯ 20 mA *7 IOL ⎯ 10 mA *4 “L” level average output current IOLAV ⎯ 3 mA *5 “L” level maximum total output current ΣIOL ⎯ 60 mA “L” level total average output current ΣIOLAV ⎯ 30 mA *6 IOH ⎯ −10 mA *4 “H” level average output current IOHAV ⎯ −3 mA *5 “H” level maximum total output current ΣIOH ⎯ −60 mA “H” level total average output current ΣIOHAV ⎯ −30 mA Power consumption PD ⎯ 320 mW Operating temperature TA −40 +85 °C Tstg −55 +150 °C Power supply voltage*1 Input voltage*1 VI Output volatage*1 VO Maximum clamp current Total maximum clamp current “L” level maximum output current “H” level maximum output current Storage temperature *2 *6 *1 : This parameter is based on VSS = AVSS = 0.0 V. *2 : AVCC and AVRH must not exceed VCC. Also, AVRH must not exceed AVCC. *3 : V1 and V0 must not exceed VCC + 0.3 V. However, if the maximum current to/from input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Maximum output current is defined as the peak value for one of the corresponding pins. *5 : Average output current is defined as the average current flow in a 100 ms interval at one of the corresponding pins. *6 : Average total output current is defined as the average current flow in a 100 ms interval at all corresponding pins. *7 : • Applicable to pins : P24 to P27, P30 to P37, P40 to P42, P60 to P67, P70 to P74, P76, P77, P80 to P87, P90 to P93, P96, P97, PA0 to PA3 • Use within recommended operating conditions. • Use at DC voltage (current) . • The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. 25 MB90980 Series • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits: • Input/Output Equivalent circuits Protective diode +B input (0 V to 16 V) VCC Limiting resistance P-ch N-ch R *8 : P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76, P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin. P76 and P77 is N-ch open drain pin. *9 : As for P76 and P77 (N-ch open drain pin) , even if using at 3 V simplicity (VCC3 = VCC5) , the ratings are applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 26 MB90980 Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Symbol 2.7 3.6 V During normal operation 1.8 3.6 V To maintain RAM state in stop mode 2.7 5.5 V During normal operation* 1.8 5.5 V To maintain RAM state in stop mode* VIH 0.7 VCC VCC + 0.3 V All pins other than VIH2, VIHS, VIHM and VIHX VIH2 0.7 VCC VSS + 5.8 V P76, P77 pins (N-ch open drain pins) VIHS 0.8 VCC VCC + 0.3 V Hysteresis input pins VIHM VCC − 0.3 VCC + 0.3 V MD pin input VIHX 0.8 VCC VCC + 0.3 V X0A pin, X1A pin VIL VSS − 0.3 0.3 VCC V All pins other than VILS, VILM and VIHX VILS VSS − 0.3 0.2 VCC V Hysteresis input pins VILM VSS − 0.3 VSS + 0.3 V MD pin input VILX VSS − 0.3 0.1 V X0A pin, X1A pin TA −40 +85 °C VCC5 Operating temperature Remarks Max Supply voltage “L” level input voltage Unit Min VCC3 “H” level input voltage Value * : P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76, P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 27 MB90980 Series 3. DC Characteristics (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name “H” level output voltage VOH “L” level output voltage VOL Input leakage current Pull-up resistance Open drain output current IIL All output pins All output pins All input pins RPULL ⎯ Ileak P40 to P42, P70 to P74, P76, P77 ICC ⎯ ICCS ⎯ ICCL ⎯ ICCT ⎯ ICCH ⎯ CIN Other than AVCC, AVSS, VCC, VSS Power supply current Input capacitance Condition VCC = 2.7 V, IOH = −1.6 mA VCC = 4.5 V, IOH = −4.0 mA VCC = 2.7 V, IOL = 2.0 mA VCC = 4.5 V, IOH = 4.0 mA VCC = 3.3 V, VSS < VI < VCC VCC = 3.0 V, at TA = +25 °C ⎯ At VCC = 3.3 V, internal 25 MHz operation, normal operation At VCC = 3.3 V, internal 25 MHz operation, Flash programming At VCC = 3.3 V, internal 25 MHz operation, sleep mode At VCC = 3.3 V, external 32 kHz, internal 8 kHz operation, sub clock operation (TA = +25 °C) At VCC = 3.3 V, external 32 kHz, internal 8 kHz operation, watch mode (TA = +25 °C) TA = +25 °C, stop mode, at VCC = 3.3 V ⎯ Min Value Typ Max Unit VCC3 − 0.3 ⎯ ⎯ V VCC5 − 0.5 ⎯ ⎯ V ⎯ ⎯ 0.4 V ⎯ ⎯ 0.4 V −10 ⎯ +10 µA 20 53 200 kΩ ⎯ 0.1 10 µA ⎯ 45 60 mA ⎯ 55 70 mA ⎯ 17 35 mA ⎯ 15 140 µA ⎯ 1.8 40 µA ⎯ 0.8 40 µA ⎯ 5 15 pF Remarks At using 5 V power supply At using 5 V power supply Notes : • Pins P40 to P42, P70 to P74, P76, and P77 are N-ch open drain pins with control, which are usually used as CMOS. • P76 and P77 are open drain pins without P-ch. • For use as a single 3 V power supply products, set VCC = VCC3 = VCC5. • When the device is used with dual power supplies, P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76 and P77 serve as 5 V pins while the other pins serve as 3 V I/O pins. 28 MB90980 Series 4. AC Characteristics (1) Clock Timing (VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rise, fall time Internal operating clock frequency Internal operating clock cycle time SymPin name bol X0, X1 FCH Value Condition Min Typ Max ⎯ 3 ⎯ 25 External crystal oscillator ⎯ 3 ⎯ 50 External clock input ⎯ 4 ⎯ 25 1 multiplied PLL ⎯ 3 ⎯ 12.5 ⎯ 3 ⎯ 6.66 MHz 2 multiplied PLL 3 multiplied PLL ⎯ 3 ⎯ 6.25 4 multiplied PLL ⎯ 3 ⎯ 4.16 6 multiplied PLL ⎯ 3 ⎯ 3.12 8 multiplied PLL Unit Remarks FCL X0A, X1A ⎯ ⎯ 32.768 ⎯ kHz tC X0, X1 ⎯ 20 ⎯ 333 ns tCL X0A, X1A ⎯ ⎯ 30.5 ⎯ µs PWH PWL X0 ⎯ 5 ⎯ ⎯ ns PWLH PWLL X0A ⎯ ⎯ 15.2 ⎯ µs *2 tcr tcf X0 ⎯ ⎯ ⎯ 5 ns With external clock fCP ⎯ ⎯ 1.5 ⎯ 25 MHz *1 fCPL ⎯ ⎯ ⎯ 8.192 ⎯ kHz tCP ⎯ ⎯ 40.0 ⎯ 666 ns tCPL ⎯ ⎯ ⎯ 122.1 ⎯ µs *1 *1 *1 : Be careful of the operating voltage. *2 : Duty raito should be 50 % ± 3 %. 29 MB90980 Series • X0, X1 clock timing tC 0.8 VCC X0 0.2 VCC PWH PWL tcf tcr • X0A, X1A clock timing tCL 0.8 VCC X0A 0.1 V PWLL PWLH tcf 30 tcr MB90980 Series • Range of warranted PLL operation Internal operating clock frequency vs. Power supply voltage Supply voltage VCC (V) 3.6 Range of warranted PLL operation 3.0 2.7 Normal operating range 1.5 16 4 25 Internal clock fCP (MHz) Notes: • Only at 1 multiplied PLL, use with more than fCP = 4 MHz. • For A/D operating frequency, refer to “5. A/D Converter Electrical Characteristics”. Base oscillator frequency vs. Internal operating clock frequency Internal clock fCP (MHz) 25 24 × 8*3 × 6*3 20 18 16 No multiplied × 3*1 × 2*1,*2 × 1*1 ×4 *1,*2 12 9 8 6 4 1.5 3 4 5 6 8 10 12.5 16 20 25 32 40 50 Base oscillator clock FCH (MHz) *1 : In setting as 1, 2, 3 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP ≤ 25 MHz, set the PLLOS register to “DIV2 bit = 1” and “PLL2 bit = 1”. [Example] When using the base oscillator frequency of 24 MHz at 1 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “0” PLLOS register : DIV2 bit = “1”, PLL2 bit = “1” [Example] When using the base oscillator frequency of 6 MHz at 3 multiplied PLL : CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : DIV2 bit = “1”, PLL2 bit = “1” *2 : In setting as 2 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP ≤ 25 MHz, the following setting is also enabled. 2 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “0” PLLOS register : DIV2 bit = “0”, PLL2 bit = “1” 4 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “1” PLLOS register : DIV2 bit = “0”, PLL2 bit = “1” *3 : When using in setting as 6 and 8 multiplied PLL, set the PLLOS register to “DIV2 bit = 0” and “PLL2 bit = 1”. [Example] When using the base oscillator frequency of 4 MHz at 6 multiplied PLL : CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : DIV2 bit = “0”, PLL2 bit = “1” [Example] When using the base oscillator frequency of 3 MHz at 8 multiplied PLL : CKSCR register : CS1 bit = “1”, CS0 bit = “1” PLLOS register : DIV2 bit = “0”, PLL2 bit = “1” 31 MB90980 Series AC standards are set at the following measurement voltage values. • Input signal waveform Hysteresis input pins Output pins 0.8 VCC 2.4 V 0.2 VCC 0.8 V • Pins other than hysteresis input/MD input 0.7 VCC 0.3 VCC 32 • Output signal waveform MB90980 Series (2) Reset Input Standards (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Reset input time Symbol Pin name tRSTL RST Value Conditions ⎯ Unit Remarks ⎯ ns Normal operation ⎯ ms Stop mode Min Max 16 tCP*1 Oscillator oscillation time*2 + 4 tCP*1 *1 : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. *2 : Oscillator oscillation time is the time to 90 % of amplitude. For a crystal oscillator this is on the order of several milliseconds to tens of milliseconds. For a FAR/ceramic oscillator, this is several hundred microseconds to several milliseconds. For an external clock signal the value is 0 ms. • In stop mode tRSTL RST 0.2 Vcc X0 0.2 Vcc 90 % of amplitude Internal operating clock Oscillator oscillation time 4 tCP Oscillator stabilization wait time Instruction execution Internal reset 33 MB90980 Series (3) Power-on Reset Standards (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Power rise time Power down time Pin name Conditions tR VCC tOFF VCC Value Unit Remarks Min Max ⎯ 30 ms * 1 ⎯ ms In repeated operation ⎯ * : Power rise time requires VCC < 0.2 V. Notes: • The above standards are for the application of a power-on reset. • Within the device, the power-on reset should be applied by switching the power supply off and on again. tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Rapid fluctuations in power supply voltage may trigger a power-on reset in some cases. As shown below, when changing supply voltage during operation, it is recommended that voltage changes be suppressed and a smooth restart be applied. Main power supply voltage VCC Sub power supply voltage VSS 34 RAM data maintenance The slope of voltage increase should be kept within 50 mV/ms. MB90980 Series (4) UART Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin Serial clock cycle time tSCYC ⎯ SCK↓→SOT delay time tSLOV ⎯ Valid SIN→SCK↑ tIVSH ⎯ SCK↑→valid SIN hold time tSHIX ⎯ tSHSL ⎯ Serial clock “L” pulse width tSLSH ⎯ SCK↓→SOT delay time tSLOV ⎯ Valid SIN→SCK↑ tIVSH ⎯ SCK↑→valid SIN hold time tSHIX ⎯ Serial clock “H” pulse width Conditions Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL Value Max 8 tCP*2 ⎯ ns −80 +80 ns −120 +120 ns 100 ⎯ ns 200 ⎯ ns tCP*2 ⎯ ns CP 2 ⎯ ns CP 2 4t * ⎯ ns ⎯ 150 ns ⎯ 200 ns 60 ⎯ ns 120 ⎯ ns 60 ⎯ ns 120 ⎯ ns 4t * External shift clock mode output pins : CL*1 = 80 pF + 1 TTL Unit Min Remarks fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz *1 : CL is the load capacitance applied to pins for testing. *2 : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. Note : AC ratings are for CLK synchronized mode. 35 MB90980 Series • Internal shift clock mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL SCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN 36 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC MB90980 Series (5) Extended I/O Serial Interface Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Serial clock cycle time tSCYC ⎯ SCK↓→SOT delay time tSLOV ⎯ Valid SIN→SCK↑ tIVSH ⎯ SCK↑→valid SIN hold time tSHIX ⎯ tSHSL ⎯ Serial clock “L” pulse width tSLSH ⎯ SCK↓→SOT delay time tSLOV ⎯ Valid SIN→SCK↑ tIVSH ⎯ SCK↑→valid SIN hold time tSHIX ⎯ Parameter Serial clock “H” pulse width Conditions Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL Value Max 8 tCP*2 ⎯ ns −80 + 80 ns −120 + 120 ns 100 ⎯ ns 200 ⎯ ns tCP*2 ⎯ ns CP 2 ⎯ ns CP 2 4t * ⎯ ns ⎯ 150 ns ⎯ 200 ns 60 ⎯ ns 120 ⎯ ns 60 ⎯ ns 120 ⎯ ns 4t * External shift clock mode output pins : CL*1 = 80 pF + 1 TTL Unit Min Remarks fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz *1 : CL is the load capacitance applied to pins for testing. *2 : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. Notes : • AC ratings are for CLK synchronized mode. • Values on this table are target values. 37 MB90980 Series • Internal shift clock mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL SCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN 38 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC MB90980 Series (6) Timer Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Input pulse width Symbol Pin name Conditions tTIWH tTIWL TIN0, IN0, IN1, PWC0, PWC1 ⎯ Value Min Max 4 tCP* ⎯ Unit Remarks ns * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. 0.8 VCC TIN0 IN0, IN1 PWC0, PWC1 0.8 VCC 0.2 VCC tTIWH 0.2 VCC tTIWL (7) Timer Output Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Conditions CLK↑→Tout change time PPG0 to PPG3 change time OUT0 to OUT3 change time tTO TOT0, PPG0 to PPG3, OUT0 to OUT3 Load conditions 80 pF CLK TOUT PPG0 to PPG3 OUT0 to OUT3 Value Min Max 30 ⎯ Unit Remarks ns 0.7 VCC 0.7 VCC 0.3 VCC tTO 39 MB90980 Series (8) I2C Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol SCL clock frequency Condition tHDSTA “L” width of the SCL clock tLOW “H” width of the SCL clock tHIGH Set-up time (repeated) START condition SCL↑→SDA↓ tSUSTA Data hold time SCL↓→SDA↓↑ tHDDAT Data set-up time SDA↓↑→SCL↑ tSUDAT Set-up time for STOP condition SCL↑→SDA↑ tSUSTO Bus free time between a STOP and START condition tBUS Unit Min Max 0 100 kHz 4.0 ⎯ µs 4.7 ⎯ µs 4.0 ⎯ µs 4.7 ⎯ µs 0 3.45*3 µs When power supply voltage of external pull-up resistance is 5.5 V fCP*1 ≤ 20 MHz, R = 1.3 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V fCP*1 ≤ 20 MHz, R = 1.6 kΩ, C = 50 pF*2 250 ⎯ ns When power supply voltage of external pull-up resistance is 5.5 V fCP*1 > 20 MHz, R = 1.3 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V fCP*1 > 20 MHz, R = 1.6 kΩ, C = 50 pF*2 200 ⎯ ns 4.0 ⎯ µs 4.7 ⎯ µs fSCL Hold time (repeated) START condition SDA↓→SCL↓ Standard-mode When power supply voltage of external pull-up resistance is 5.5 V R = 1.3 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V R = 1.6 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 5.5 V R = 1.3 kΩ, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V R = 1.6 kΩ, C = 50 pF*2 *1 : fCP is internal operation clock frequency. Refer to “ (1) Clock Timing”. *2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. Note : VCC = VCC3 = VCC5 SDA tHDSTA tSUDAT tLOW tBUS SCL tHDSTA 40 tHDDAT tHIGH tSUSTA tSUSTO MB90980 Series (9) Trigger Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Conditions tTRGH, tTRGL ADTG, IRQ0 to IRQ7 ⎯ Input pulse width Value Unit Remarks ⎯ ns Normal operation ⎯ µs Stop mode Min Max 5 tCP* 1 * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. IRQ0 to IRQ7 ADTG 0.8 VCC 0.8 VCC 0.2 VCC tTRGH 0.2 VCC tTRGL (10) Up-down Counter Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Conditions Value Min Max Unit AIN input “H” pulse width tAHL 8 tCP* ⎯ ns AIN input “L” pulse width tALL 8 tCP* ⎯ ns BIN input “H” pulse width tBHL 8 tCP* ⎯ ns BIN input “L” pulse width tBLL 8 tCP* ⎯ ns AIN↑→BIN↑ rise time tAUBU 4 tCP* ⎯ ns BIN↑→AIN↓ fall time tBUAD 4 tCP* ⎯ ns 4 tCP* ⎯ ns 4 tCP* ⎯ ns AIN0, AIN1, BIN0, BIN1 Load conditions 80 pF AIN↓→BIN↑ rise time tADBD BIN↓→AIN↑ rise time tBDAU BIN↑→AIN↑ rise time tBUAU 4 tCP* ⎯ ns AIN↑→BIN↓ fall time tAUBD 4 tCP* ⎯ ns BIN↓→AIN↑ rise time tBDAD 4 tCP* ⎯ ns AIN↓→BIN↑ rise time tADBU 4 tCP* ⎯ ns ZIN input “H” pulse width tZHL 4 tCP* ⎯ ns ZIN input “L” pulse width tZLL 4 tCP* ⎯ ns ZIN0, ZIN1 Remarks * : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”. 41 MB90980 Series tAHL 0.8 VCC tALL 0.8 VCC AIN 0.2 VCC tAUBU tBUAD tADBD 0.8 VCC 0.2 VCC tBDAU 0.8 VCC BIN 0.2 VCC tBHL 0.8 VCC 0.2 VCC tBLL 0.8 VCC BIN 0.2 VCC tBUAU tAUBD tBDAD 0.2 VCC tADBU 0.8 VCC AIN 0.2 VCC 0.8 VCC ZIN 0.8 VCC tZHL tZLL 0.2 VCC 42 0.2 VCC MB90980 Series 5. A/D Converter Electrical Characteristics (VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH, TA = −40 °C to +85 °C) Parameter Symbol Pin name Value Min Typ Max Unit Resolution ⎯ ⎯ ⎯ ⎯ 10 bit Total error ⎯ ⎯ ⎯ ⎯ ±3.0 LSB Non-linear error ⎯ ⎯ ⎯ ⎯ ±2.5 LSB Differential linearity error ⎯ ⎯ ⎯ ⎯ ±1.9 LSB Zero transition voltage VOT AN0 to AN7 AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV Full scale transition voltage VFST AN0 to AN7 AVRH − 3.5 LSB AVRH − 1.5 LSB AVRH + 0.5 LSB mV Conversion time ⎯ ⎯ 3.68 *1 ⎯ ⎯ µs Analog port input current IAIN AN0 to AN7 ⎯ 0.1 10 µA Analog input voltage VAIN AN0 to AN7 AVSS ⎯ AVRH V ⎯ AVRH AVSS + 2.2 ⎯ AVCC V IA AVCC ⎯ 1.4 3.5 mA IAH AVCC ⎯ ⎯ 5 *2 µA IR AVRH ⎯ 94 150 µA 2 µA Reference voltage Power supply current Reference voltage supply current IRH AVRH ⎯ ⎯ 5* Offset between channels ⎯ AN0 to AN7 ⎯ ⎯ 4 Remarks LSB *1 : At machine clock frequency of 25 MHz. *2 : CPU stop mode current when A/D converter is not operating (at VCC = AVCC = AVRH = 3.0 V) . 43 MB90980 Series • About the external impedance of the analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. • Analog input circuit model R Analog input Comparator C During sampling : ON R C 2.5 kΩ (Max) 31.0 pF (Max) 1.9 kΩ (Max) 25.0 pF (Max) MB90982 MB90F983 Note: The values are reference values. • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. • The relationship between external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ) (External impedance = 0 kΩ to 100 kΩ) MB90F983 MB90982 MB90F983 20 90 External impedance [kΩ] External impedance [kΩ] 100 80 70 60 50 40 30 20 10 0 MB90982 18 16 14 12 10 8 6 4 2 0 0 5 10 15 20 25 30 Minimum sampling time [µs] 35 0 1 2 3 4 5 6 7 8 Minimum sampling time [µs] • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • About errors As |AVRH − AVSS| becomes smaller, values of relative errors grow larger. Note : Concerning sampling time, and compare time When 3.6 V ≥ AVCC ≥ 2.7 V, then Sampling time : 1.92 µs, compare time : 1.1 µs Settings should ensure that actual values do not go below these values due to operating frequency changes. 44 MB90980 Series • Flash Memory Program/Erase Characteristics Parameter Conditions Sector erase time TA = + 25 °C, VCC = 3.0 V Chip erase time Word (16-bit) programming time Value Unit Remarks Min Typ Max ⎯ 1 15 s Excludes 00H programming prior erasure ⎯ 7 ⎯ s Excludes 00H programming prior erasure ⎯ 16 3600 µs Excludes system-level overhead Program/Erase cycle ⎯ 10000 ⎯ ⎯ cycle Flash Memory Data hold time Average TA = + 85 °C 10 ⎯ ⎯ year * * : The value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) . • Use of the X0/X1, X0A/X1A pins When used with a crystal oscillator X1 Pull-up resistance 1 X0 X0A Damping resistance 1 C2 X1A Internal damping resistance 0 Damping resistance 2 C1 C3 C4 In normal use : Internal damping resistance 1 : Typ 600 kΩ Consult with the oscillator manufacturer. Pull-up resistance 1, Damping resistance 1, 2, C1 to C4 • Sample use with external clock input X0 OPEN MB90980 series X1 45 MB90980 Series ■ ORDERING INFORMATION Model MB90F983 MB90982 46 Package 64-pin plastic LQFP (FPT-64P-M03) Remarks MB90980 Series ■ PACKAGE DIMENSIONS 64-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 10.0 × 10.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32g Code (Reference) P-LFQFP64-10×10-0.50 (FPT-64P-M03) 64-pin plastic LQFP (FPT-64P-M03) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ * 10.00±0.10(.394±.004)SQ 48 0.145±0.055 (.006±.002) 33 49 32 Details of "A" part 0.08(.003) +0.20 1.50 –0.10 +.008 .059 –.004 INDEX 64 0˚~8˚ 17 (Mounting height) 0.10±0.10 (.004±.004) (Stand off) "A" LEAD No. 1 16 0.50(.020) C 2003 FUJITSU LIMITED F64009S-c-5-8 0.20±0.05 (.008±.002) 0.08(.003) M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values 47 MB90980 Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0604