HT24LC64 Absolute Maximum Ratings Operating Temperature (Commercial) ........................................................................................................ 0°C to 70°C Storage Temperature ............................................................................................................................ -50°C to 125°C Applied VCC Voltage with Respect to VSS .................................................................................VSS -0.3V to VSS+6.0V Applied Voltage on any Pin with Respect to VSS ................................................................................................VSS -0.3V to VCC+0.3V Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Ta=0°C to 70°C Test Conditions VCC Conditions ¾ Min. Typ. Max. Unit VCC Operating Voltage ¾ 2.4 ¾ 5.5 V ICC1 Operating Current 5V Read at 100kHz ¾ ¾ 2 mA ICC2 Operating Current 5V Write at 100kHz ¾ ¾ 5 mA VIL Input Low Voltage ¾ ¾ -1 ¾ 0.3VCC V VIH Input High Voltage ¾ ¾ 0.7VCC ¾ VCC+0.5 V VOL Output Low Voltage ¾ ¾ 0.4 V ILI Input Leakage Current 5V VIN=0 or VCC ¾ ¾ 1 mA ILO Output Leakage Current 5V VOUT=0 or VCC ¾ ¾ 1 mA ISTB1 Standby Current 5V VIN=0 or VCC ¾ ¾ 5 mA ISTB2 Standby Current 2.4V VIN=0 or VCC ¾ ¾ 4 mA CIN Input Capacitance (See Note) f=1MHz 25°C ¾ ¾ 6 pF COUT Output Capacitance (See Note) ¾ f=1MHz 25°C ¾ ¾ 8 pF 2.4V IOL=2.1mA ¾ Note: These parameters are periodically sampled but not 100% tested. A.C. Characteristics Symbol Ta=0°C to 70°C Parameter Remark Standard Mode* Min. Max. VCC=5V±10% Min. Max. Unit fSK Clock Frequency ¾ ¾ 100 ¾ 400 kHz tHIGH Clock High Time ¾ 4000 ¾ 600 ¾ ns tLOW Clock Low Time ¾ 4700 ¾ 1200 ¾ ns tR SDA and SCL Rise Time Note ¾ 1000 ¾ 300 ns tF SDA and SCL Fall Time Note ¾ 300 ¾ 300 ns tHD:STA START Condition Hold Time After this period, the first clock pulse is generated. 4000 ¾ 600 ¾ ns tSU:STA START Condition Setup Time Only relevant for repeated START condition. 4000 ¾ 600 ¾ ns tHD:DAT Data Input Hold Time ¾ 0 ¾ 0 ¾ ns tSU:DAT ¾ 100 ¾ ns ¾ 200 tSU:STO STOP Condition Setup Time ¾ 4000 ¾ 600 ¾ ns tAA ¾ ¾ 3500 ¾ 900 ns Rev. 1.00 Data Input Setup Time Output Valid from Clock 2 January 5, 2005 HT24LC64 Symbol Parameter Standard Mode* Remark tBUF Bus Free Time Time in which the bus must be free before a new transmission can start tSP Input Filter Time Constant (SDA and SCL Pins) Noise suppression time tWR Write Cycle Time Note: ¾ VCC=5V±10% Unit Min. Max. Min. Max. 4700 ¾ 1200 ¾ ns ¾ 100 ¾ 50 ns ¾ 5 ¾ 5 ms These parameters are periodically sampled but not 100% tested * The standard mode means VCC=2.4V to 5.5V For relative timing, refer to timing diagrams Functional Description · Serial clock (SCL) stable whenever the clock line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition. The SCL input is used for positive edge clock data into each EEPROM device and negative edge clock data out of each device. · Start condition · Serial data (SDA) A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition Timing diagram). The SDA pin is bidirectional for serial data transfer. The pin is open drain driven and may be wired-OR with any number of other open drain or open collector devices. · Stop condition A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram). · A0, A1, A2 The A2, A1 and A0 pins are device address inputs that are hard wired or left not connected for hardware compatibility with HT24LC64. When the pins are hardwired, as many as eight 64K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). These inputs must be tied to VCC or VSS, to establish the device select code. · Acknowledge All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. · Write protect (WP) D a ta a llo w e d to c h a n g e The HT24LC64 has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when the connection is grounded. When the write protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following table. WP Pin Status S D A S C L S ta rt c o n d itio n Protect Array A d d re s s o r a c k n o w le d g e v a lid N o A C K s ta te S to p c o n d itio n At VCC Full Array (64K) Device Addressing At VSS (floating) Normal Read/Write Operations The 64K EEPROM devices require an 8-bit device address word following a start condition to enable the chip for a read or write operation. The device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to the diagram showing the Device Address). This is common to all the EEPROM device. Memory Organization Internally organized with 8192 8-bit words, the 64K requires a 13-bit data word address for random word addressing. Device Operations The 64K EEPROM uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. · Clock and data transition Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain Rev. 1.00 3 January 5, 2005 HT24LC64 The data word address lower 5 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will ²roll over² and previous data will be overwritten. The 8th bit device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. If the comparison of the device address succeed the EEPROM will output a zero at ACK bit. If not, the chip will return to a standby state. 1 0 1 0 A 2 A 1 A 0 R /W D e v ic e A d d r e s s Device Address · Acknowledge polling To maximize bus throughput, one technique is to allow the master to poll for an acknowledge signal after the start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned. The master can send the next read/write command when the ACK signal has finally been received. Write Operations · Byte write A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the nonvolatile memory. All inputs are disabled during this write cycle and EEPROM will not respond until the write operation is completed (refer to Byte write timing). S e n d W r ite C o m m a n d S e n d S to p C o n d itio n to In itia te W r ite C y c le S e n d S ta rt S e n d C o n tro l B y te w ith R /W = 0 · Page write The 64K EEPROM is capable of a 32-byte page write. A page write is initiated in the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges the receipt of the first data word, the microcontroller can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Page write timing). Y e s N e x t O p e r a tio n Acknowledge Polling Flow F ir s t W o r d A d d r e s s S e c o n d W o rd A d d re s s S to p W r ite S ta rt D e v ic e A d d r e s s S D A L in e N o (A C K = 0 )? D a ta A 2 A 1 A 0 A C K A C K A C K A C K R /W D a ta (n ) D a ta (n + x ) Byte Write Timing F ir s t W o r d A d d r e s s ( n ) S e c o n d W o r d A d d r e s s ( n ) S to p W r ite S ta rt S D A L in e D e v ic e A d d r e s s A 2 A 1 A 0 A C K A C K A C K A C K A C K R /W N o t e : * = D o n 't c a r e b it s Page Write Timing Rev. 1.00 4 January 5, 2005 HT24LC64 · Write protect · Random read A random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller should respond with a ²no ACK² signal (high) followed by a stop condition (refer to Random read timing). The HT24LC64 has a write-protect function and programming will then be inhibited when the WP pin is connected to VCC. Under this mode, the HT24LC64 is used as a serial ROM. · Read operations The HT24LC64 supports three read operations, namely, current address read, random address read and sequential read. During read operation execution, the read/write select bit should be set to ²1². · Current address read The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address remains valid between operations as long as the chip power is maintained. The address will roll over during read from the last byte of the last memory page to the first byte of the first page. The address will roll over during write from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but generates a following stop condition (refer to Current read timing). Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The sequential read operation is terminated when the microcontroller does not respond with a zero but generates a following stop condition. S to p R e a d S ta rt D e v ic e a d d r e s s · Sequential read D a ta A 2 A 1 A 0 S D A L in e N o A C K A C K R /W Current Address Read Timing A 2 A 1 A 0 S to p D e v ic e A d d r e s s R e a d 1 s t, 2 n d W o rd A d d re s s (n ) S ta rt S D A L in e W r ite S ta rt D e v ic e A d d r e s s D a ta (n ) A 2 A 1 A 0 N o A C K A C K A C K A C K R /W D u m m y W r ite N o t e : * = D o n 't c a r e b it s Random Read Timing D a ta (n ) D a ta (n + 1 ) D a ta (n + 2 ) D a ta (n + x ) S to p R e a d D e v ic e A d d re s s S D A L in e N o A C K A C K A C K A C K A C K R /W Sequential Read Timing Rev. 1.00 5 January 5, 2005 HT24LC64 Timing Diagrams tF tR S C L tS S D A U :S T A tS tL O W tH D :S T A tH IG H tH tS D :D A T U :D A T P tA S D A A V a lid O U T tS U :S T O tB U F V a lid S C L S D A 8 th b it A C K W o rd n tW S to p c o n d itio n R S to p c o n d itio n Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command. Rev. 1.00 6 January 5, 2005 HT24LC64 Package Information 8-pin DIP (300mil) Outline Dimensions A 8 B 5 4 1 H C D = G E I F Symbol A Rev. 1.00 Dimensions in mil Min. Nom. Max. 355 ¾ 375 B 240 ¾ 260 C 125 ¾ 135 D 125 ¾ 145 E 16 ¾ 20 F 50 ¾ 70 G ¾ 100 ¾ H 295 ¾ 315 I 335 ¾ 375 a 0° ¾ 15° 7 January 5, 2005 HT24LC64 8-pin SOP (150mil) Outline Dimensions 5 8 A B 4 1 C C ' G H D E Symbol Rev. 1.00 = F Dimensions in mil Min. Nom. Max. A 228 ¾ 244 B 149 ¾ 157 C 14 ¾ 20 C¢ 189 ¾ 197 D 53 ¾ 69 E ¾ 50 ¾ F 4 ¾ 10 G 22 ¾ 28 H 4 ¾ 12 a 0° ¾ 10° 8 January 5, 2005 HT24LC64 Product Tape and Reel Specifications Reel Dimensions D T 2 A C B T 1 SOP 8N Symbol Description Dimensions in mm A Reel Outer Diameter 330±1.0 B Reel Inner Diameter 62±1.5 C Spindle Hole Diameter 13.0+0.5 -0.2 D Key Slit Width 2.0±0.15 T1 Space Between Flange 12.8+0.3 -0.2 T2 Reel Thickness 18.2±0.2 Rev. 1.00 9 January 5, 2005 HT24LC64 Carrier Tape Dimensions P 0 D P 1 t E F W C D 1 B 0 P K 0 A 0 SOP 8N Symbol Description Dimensions in mm W Carrier Tape Width 12.0+0.3 -0.1 P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 5.5±0.1 D Perforation Diameter 1.55±0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.4±0.1 B0 Cavity Width 5.20±0.1 K0 Cavity Depth 2.1±0.1 t Carrier Tape Thickness 0.3±0.05 C Cover Tape Width Rev. 1.00 9.3 10 January 5, 2005 HT24LC64 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 11 January 5, 2005