ACE24C128B Two-wire Serial EEPROM Description The ACE24C128B is a 128-Kbit I2C-compatible Serial EEPROM (Electrically Erasable Programmable Memory) device. It contains a memory array of 16 K * 8 bits, which is organized in 64-byte per page. Features Single Supply Voltage and High Speed Minimum operating voltage down to 1.7V 1 MHz clock from 2.5V to 5.5V 400kHz clock from 1.7V to 2.5V Low power CMOS technology Read current 400uA, maximum Write current 1.6mA, maximum Standby current 100nA, 2.5V, typical Schmitt Trigger, Filtered Inputs for Noise Suppression Sequential & Random Read Features 64 byte Page Write Modes, Partial Page Writes Allowed Write protect of the whole memory array Self-timed Write Cycle (5ms maximum) High Reliability Endurance: > 2 Million Write Cycles Data Retention: > 100 Years ESD Protection >4000V (HBM) on all pins LATCH UP Capability: +/- 200mA Absolute Maximum Ratings Operating Temperature -40℃ to 85℃ Storage Temperature -65℃ to 150℃ Maximum Operation Voltage 6.25V Voltage on Any Pin with Respect to Ground -1.0V to (Vcc+1.0V) DC Output Current 5.0mA Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. VER 1.3 1 ACE24C128B Two-wire Serial EEPROM Packaging Type DIP-8 / SOP-8 / TSSOP-8 / TDFN Pin Configurations Pin Name Type Functions E0 I/O Slave Address Setting E1 Input Slave Address Setting E2 Input Slave Address Setting GND Ground Ground SDA I/O Serial Data Input and Serial Data Output SCL Input Serial Clock Input WCB Input Write Control, Low Enable Write Vcc Power Power Ordering information ACE24C128B XX + X H Halogen-free U : Tube T : Tape and Reel Pb - free DP : DIP-8 FM : SOP-8 TM : TSSOP-8 DM : TDFN VER 1.3 2 ACE24C128B Two-wire Serial EEPROM Block Diagram Pin Descriptions Serial Clock (SCL): The SCL input is used to positive-edge clock data in and negative-edge clock data out of each device. Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. Device Addresses (E2, E1, E0): The E2, E1, and E0 pins are device address inputs. Typically, the E2, E1, and E0 pins are for hardware addressing and a total of 8 devices can be connected on a single bus system. If these pins are left floating, the E2, E1, and E0 pins will be internally pulled down to GND. Write Control (WCB): The Write Control input, when WCB is connected directly to VCC, all write operations to the memory are inhibited. When connected to GND, allows normal write operations. If the pin is left floating, the WCB pin will be internally pulled down to GND. VER 1.3 3 ACE24C128B Two-wire Serial EEPROM Pin Capacitance(1) Symbol Parameter Max Units Test Condition CI/O Input / Output Capacitance (SDA) 8 pF VI/O=GND CIN Input Capacitance (E0,E1,E2,WCB,SCL) 6 pF VIN=GND Note: Test Conditions: TA = 25°C, F=1MHz, Vcc=5.0V. DC Characteristics (Unless otherwise specified, VCC = 1.7V to 5.5V, TA = –40°C to 85°C) Symbol Vcc Parameter Supply Voltage Test Condition Min 1.7 Typ 1.0 3.0 0.4 Unit V uA uA uA mA 1.6 1.0 1.0 0.3 Vcc Vcc+0.5 mA μA μA V V IOL=1.5mA 0.2 V IOL=2.1mA 0.4 V Isb Standby Current Vcc = 2.5V, TA = 25°C Vcc = 2.5V, TA =85°C Vcc = 5.5V, TA = 85°C ICC1 Supply Current Vcc=5.5V, Read at 400Khz 0.2 ICC2 ILI ILO VIL VIH Supply Current Input Leakage Current Output Leakage Current Input Low Level Input High Level Output Low Level VCC = 1.7V (SDA) Output Low Level VCC = 3.0V (SDA) Vcc=5.5V Write at 400Khz VIN=VCC or GND VOUT=VCC or GND 0.8 0.1 0.05 VOL1 VOL2 -0.6 0.7 Vcc 0.1 Max 5.5 VER 1.3 4 ACE24C128B Two-wire Serial EEPROM AC Characteristics Unless otherwise specified, VCC=1.7V to 5.5V, TA=–40°C to 85°C, CL=100pF, Test Conditions are listed in Notes 1.7≤VCC<2.5 2.5≤VCC≤5.5 (2) Symbol Parameter fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low 1.3 0.4 µs tHIGH Clock Pulse Width High 0.6 0.4 µs tAA Clock Low to Data Out Valid 0.05 tI 1.3 0.5 µs tHD.STA Noise Suppression Time Time the bus must be free before a new transmission can start Start Hold Time 0.6 0.25 µs tSU.STA Start Setup Time 0.6 0.25 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DAT Data In Setup Time 0.1 0.1 µs tBUF tR Min 0.9 Min 0.05 0.1 Typ Max 1000 Units kHz 0.55 µs 0.05 µs (1) 0.3 0.3 µs (1) 0.3 0.1 µs Inputs Rise Time tF Typ Max 400 Inputs Fall Time tSU.STO Stop Setup Time 0.6 0.25 µs tDH Data Out Hold Time 0.05 0.05 µs tSU.WCB WCB pin Setup Time 1.2 0.6 µs tHD.WCB WCB pin Hold Time 1.2 0.6 µs tWR Write Cycle Time 5 5 ms Notes: 1. This parameter is ensured by characterization not 100% tested 2. AC measurement conditions: CC): 1.3k (2.5V, 5.5V), 10k (1.7V) CC to 0.7 VCC CC Reliability Characteristic(1) Symbol EDR (2) DRET Parameter Min Typ Max Unit Endurance 2,000,000 Write cycle Data retention 100 Years Note: 1.This parameter is ensured by characterization and is not 100% tested 2. Under the condition: 25°C, 3.3V, Page mode VER 1.3 5 ACE24C128B Two-wire Serial EEPROM Figure 1. Bus Timing Figure 2. Write Cycle Timing Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Device Operation Data Input The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see to Figure 3). Data changes during SCL high periods will indicate a start or stop condition as defined below. VER 1.3 6 ACE24C128B Two-wire Serial EEPROM Figure 3. Data Validity Start Condition A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see to Figure 4) Stop Condition A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the ACE24C128B in a standby power mode (see Figure 4). Figure 4. Start and stop definition Acknowledge (ACK) All addresses and data words are serially transmitted to and from the ACE24C128B in 8-bit words. The ACE24C128B sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle. VER 1.3 7 ACE24C128B Two-wire Serial EEPROM Figure 5. Output Acknowledge Standby Mode The ACE24C128B features a low-power standby mode which is enabled: (a) after a fresh power up, (b) after receiving a STOP bit in read mode, and (c) after completing a self-time internal programming operation Soft Reset After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (a) Create a start condition, (b) Clock nine cycles, and (c) create another start bit followed by stop bit condition, as shown below. The device is ready for the next communication after the above steps have been completed. Figure 6. Soft Reset Device Addressing The ACE24C128B requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure7). The device address word consists of a mandatory one-zero sequence for the first four most-significant bits, as shown. VER 1.3 8 ACE24C128B Two-wire Serial EEPROM Figure 7. Device Address The three E2, E1, and E0 device address bits to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The E2, E1, and E0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are floating. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the Chip will output a zero. If a compare is not made, the device will return to a standby state. Data Security ACE24C128B has a hardware data protection scheme that allows the user to write protect the whole memory when the WCB pin is at Vcc. Instructions Write Operations BYTE WRITE A write operation requires two 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the ACE24C128B will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the ACE24C128B will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. And then the ACE24C128B enters an internally timed write cycle, all inputs are disabled during this write cycle and the ACE24C128B will not respond until the write is complete (see Figure 8). Figure 8. Byte Write Note: x means don’t care. VER 1.3 9 ACE24C128B Two-wire Serial EEPROM Page Write A page write is initiated the same as a byte write, but the master does not send a stop condition after the first data word is clocked in. Instead, after the ACE24C128B acknowledges receipt of the first data word, the master can transmit more data words. The ACE24C128B will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition. Figure 9. Page Write The lower six bits of the data word address are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the ACE24C128B, the data word address will roll-over, and previous data will be overwritten. The address roll-over during write is from the last byte of the current page to the first byte of the same page. Acknowledge Polling Once the internally timed write cycle has started and the ACE24C128B inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the ACE24C128B respond with a “0”, allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: Current Address Read; Random Address Read and Sequential Read. Current Address Read The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address roll-over during read is from the last byte of the last memory page to the first byte of the first page. Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the ACE24C128B, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (see Figure 10). VER 1.3 10 ACE24C128B Two-wire Serial EEPROM Figure 10. Current Address Read Random Read A Random Read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the ACE24C128B, the microcontroller must generate another start condition. The microcontroller now initiates a Current Address Read by sending a device address with the read/write select bit high. The ACE24C128B acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 11). Figure 11. Random Read Sequential Read Sequential Reads are initiated by either a Current Address Read or a Random Address Read. After the microcontroller receives a data word, it responds with acknowledge. As long as the ACE24C128B receives acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll-over and the Sequential Read will continue. The Sequential Read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 12) VER 1.3 11 ACE24C128B Two-wire Serial EEPROM Figure 12. Sequential Read VER 1.3 12 ACE24C128B Two-wire Serial EEPROM Packaging information DIP-8 Symbol Dimensions In Millimeter Dimensions In Inches min max min max A 3.71 4.31 0.146 0.17 A1 0.51 0.02 b 0.38 0.57 0.015 0.022 b2 1.524 (BSC) 0.060 (BSC) C 0.204 0.36 0.008 0.014 D 9 9.4 0.354 0.37 E1 6.2 6.6 0.244 0.26 E 7.32 7.92 0.288 0.312 e 2.54 (BSC) 0.10 (BSC) L 3 3.6 0.118 0.142 eB 8.4 9 0.331 0.354 VER 1.3 13 ACE24C128B Two-wire Serial EEPROM Packaging information SOP-8 Symbol Dimensions In Millimeter Dimensions In Inches min max min max A 1.35 1.75 0.53 0.069 A1 0.1 0.25 0.004 0.01 b 0.33 0.51 0.013 0.02 c 0.17 0.25 0.006 0.01 D 4.7 5.1 0.185 0.2 E 3.8 4 0.15 0.157 E1 5.8 6.2 0.228 0.244 e L Θ 1.27 (BSC) 0.4 。 0 0.05 (BSC) 1.27 。 8 0.016 。 0 0.05 。 8 VER 1.3 14 ACE24C128B Two-wire Serial EEPROM Packaging information TSSOP-8 Symbol Dimensions In Millimeter Dimensions In Inches min max min max D 2.9 3.1 0.114 0.122 E 4.3 4.5 0.169 0.177 b 0.19 0.3 0.007 0.012 c 0.09 0.2 0.004 0.008 E1 6.25 6.55 0.246 0.258 A A1 1.2 0.05 E L 0.002 0.65 (BSC) 0.5 H Θ 0.15 0.047 0.026 (BSC) 0.7 0.02 0.25 (Typ) 。 1 0.006 0.028 0.01 (Typ) 。 7 。 1 。 7 VER 1.3 15 ACE24C128B Two-wire Serial EEPROM Packaging information TDFN Symbol Dimensions In Millimeter Dimensions In Inches min max min max A 0.7/0.8 0.8/0.9 0.028/0.031 0.031/0.035 A1 0 0.05 0 0.002 A3 0.203 REF 0.008 REF D 1.924 2.076 0.076 0.082 E 2.924 3.076 0.115 0.121 D2 1.4 1.6 0.055 0.063 E2 1.4 1.6 0.055 0.063 k b 0.200 MIN 0.2 e L 0.008 MIN 0.3 0.5 TYP 0.224 0.008 0.012 0.02 TYP 0.376 0.009 0.015 VER 1.3 16 ACE24C128B Two-wire Serial EEPROM Notes ACE does not assume any responsibility for use as critical components in life support devices or systems without the express written approval of the president and general counsel of ACE Electronics Co., LTD. As sued herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ACE Technology Co., LTD. http://www.ace-ele.com/ VER 1.3 17