ACE24C1024 Two-wire Serial EEPROM Description The ACE24C1024 provides wide voltage of 1,048,576 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 131,072 words of 8 bits each. The device can be connected in series to achieve the characteristics of the four devices to share a two-wire system addressable bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. Features Low Operation Voltage: Vcc = 1.7V to 5.5V Internally Organized: 131,072 x 8 (1024K) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol 1MHz (2.5V~5.5V) and 400 kHz (1.7V) Compatibility Write Protect Pin for Hardware Data Protection 256-byte Page Write Modes Partial Page Writes are Allowed Self-timed Write Cycle (5 ms max) High-reliability - Endurance: 1,000,000 Write Cycles - Data Retention: 40 Years Absolute Maximum Ratings Operating Temperature -55℃ to +125℃ Storage Temperature -65℃ to +150℃ Voltage on Any Pin with Respect to Ground -1.0V to +7.0V Maximum Operating Voltage 6.25V DC Output Current 5.0 mA *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VER 1.4 1 ACE24C1024 Two-wire Serial EEPROM Packaging Type Pin Configurations Pin Name A1~A2 Function Device Address Inputs SDA Serial Data Input / Output SCL Serial Clock Input WP Write Protect VCC Power Supply GND Ground NC Not Connect Block Diagram Figure 1 VER 1.4 2 ACE24C1024 Two-wire Serial EEPROM Ordering information ACE24C1024 XX + X H Halogen-free U : Tube T : Tape and Reel Pb - free DP : DIP-8 FM : SOP-8 TM : TSSOP-8 Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. Serial Data (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. Device/Page Addresses (A2, A1): The A2, A1 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other ACE24CXXX devices. When the pins are hardwired, as many as eight 1024K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).If the pins are left floating, the A2, A1 pins will be internally pulled down to GND if the capacitive coupling to the circuit board Vcc plane is < 3pF, if coupling is > 3pF recommends connecting the address pins to GND. Write Protect (WP): The ACE24C1024 has a Write Provides hardware data protection. The WP pin allows normal write operations when connected to ground (GND). When the Write Protect pin is connected to Vcc. All write operations to the memory are inhibited. Write Protect Description WP Pin Status Part of the Array Protected WP=VCC Full (1024K) Memory WP=GND Normal Read/Write Operations VER 1.4 3 ACE24C1024 Two-wire Serial EEPROM Memory Organization ACE24C1024, 1024K Serial EEPROM: Internally organized with 512 pages of 256 bytes each, the 1024K requires a 17-bit data word address for random word addressing. Pin Capacitance Applicable over recommended operating range from: TA = 25℃, f = 1.0 MHz, VCC = +1.7V. Symbol Test Condition Max Units Conditions 1 Input / Output Capacitance 8 pF V I/O = 0V 1 Input Capacitance 6 pF V IN = 0V C I/O C IN Note: 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +3.5V, (unless otherwise noted). Symbol Parameter Test Condition Min Typ 1.7 Max Units 5.5 V VCC Supply Voltage ICC1 Supply Current VCC = 5.0V, Read at 400K 0.4 1.0 mA ICC2 Supply Current VCC = 5.0V, Write at 400K 2.0 3.0 mA ISB Standby Current VIN = VCC/ VSS 1.0 20.0 µA ILI Input Leakage Current VIN = VCC/VSS 0.10 3.0 µA ILO Output Leakage Current VOUT = VCC/ VSS 0.05 3.0 µA VIL1 Input Low Level -0.6 VCCx0.3 V VIH1 Input High Level VCCx0.7 VCC+0.5 V VOL2 Output Low Level VCC = 1.7V, IOL = 0.15 mA 0.2 V VOL1 Output Low Level VCC = 3.0V, IOL = 2.1 mA 0.4 V Note: 1. VIL min and VIH max are reference only and are not tested. VER 1.4 4 ACE24C1024 Two-wire Serial EEPROM AC Characteristics Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note2. 1.7-volt 2.5-volt 5.5-volt Symbol Parameter fSCL Clock Frequency, SCL TLOW Clock Pulse Width Low 1300 400 400 ns THIGH Clock Pulse Width High 600 400 400 ns Ti1 Noise Suppression Time TAA Clock Low to Data Out Valid TBUF1 Time the bus must be free before a new transmission can Start Min Max Min Max Min Max 400 20 1000 100 50 900 20 550 1000 Units kHz 50 20 550 ns 1300 500 500 ns THD.STA Start Hold Time 600 250 250 ns TSU.STA Start Setup Time 600 250 250 ns THD.DAT Data In Hold Time 0 0 0 ns TSU.DAT Data In Setup Time 100 100 100 ns TR Inputs Rise Time 300 300 300 ns TF Inputs Fall Time 300 100 100 ns TSU.STO Stop Setup Time 600 250 250 ns TDH Data Out Hold Time 50 50 50 ns TWR Write Cycle Time Endurance1 3.3V, 25℃, Page Mode 5 5 1,000,000 5 ms Write Cycles Notes:1. This parameter is characterized and not 100% tested. 2.AC measurement conditions: RL (connects to Vcc): 1.3KΩ Input pulse voltages: 0.3 Vcc to 0.7 Vcc Input rise and fall times: ≦50 ns Input and output timing reference voltages: 0.5Vcc Device Operation Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Figure 4). Data changes during SCL high periods will indicate a start or stop condition as defined below. Start Condition: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Figure 5). VER 1.4 5 ACE24C1024 Two-wire Serial EEPROM Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Figure 5). Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. Standby Mode : The ACE24C1024 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the stop bit and the completion of any internal operations. Memory Reset : After an interruption in protocol power loss or system reset, any two-wire part can be protocol reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high and then. 3. Create a start condition as SDA is high. Bus Timing Figure 2．SCL: Serial Clock, SDA: Serial Data I/O VER 1.4 6 ACE24C1024 Two-wire Serial EEPROM Write Cycle Timing Figure 3．SCL: Serial Clock, SDA: Serial Data I/O Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Figure 4．Data Validity Figure 5．Start and Stop Definition VER 1.4 7 ACE24C1024 Two-wire Serial EEPROM Figure 6．Output Acknowledge Device Addressing The 1024K EEPROM device require an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 7). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The 1024K EEPROM use the three device address bits A2, A1 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hard-wired input pins. The A2,A1 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The seventh bit (P0) of the device address is a memory page address bit. This memory page address bit is the most significant bit of the data word address that follows. The module package device address word also consists of a mandatory one, zero sequence for the first four most significant bits. The next 3 bits are all zero. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state. Noise protection: Special internal circuitry place on the SDA and SCL pins prevent small noise spikes from activating the device. Date Security: The ACE24C1024 has a hardware data protect scheme that slows the user to write protect the entire memory when the WP pin is at Vcc. VER 1.4 8 ACE24C1024 Two-wire Serial EEPROM Write Operations Byte Write: A write operation requires two 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 8). Page Write: The 1024K EEPROM is capable of an 256-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 9). The data word address lower 8 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 256 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. Acknowledge Polling: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. Current Address Read: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 10). VER 1.4 9 ACE24C1024 Two-wire Serial EEPROM Random Read: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 11). Sequential Read: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 12). MSB 1 LSB 0 1 0 A2 A1 A0 R/W Figure 7．Device Address Figure 8．Byte Write VER 1.4 10 ACE24C1024 Two-wire Serial EEPROM Figure 9．Page Write Figure 10．Current Address Read Figure 11． Random Read VER 1.4 11 ACE24C1024 Two-wire Serial EEPROM Figure 12． Sequential Read VER 1.4 12 ACE24C1024 Two-wire Serial EEPROM Packaging information DIP-8 VER 1.4 13 ACE24C1024 Two-wire Serial EEPROM Packaging information SOP-8 VER 1.4 14 ACE24C1024 Two-wire Serial EEPROM Packaging information TSSOP-8 VER 1.4 15 ACE24C1024 Two-wire Serial EEPROM Notes ACE does not assume any responsibility for use as critical components in life support devices or systems without the express written approval of the president and general counsel of ACE Electronics Co., LTD. As sued herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ACE Technology Co., LTD. http://www.ace-ele.com/ VER 1.4 16