HOLTEK HT46RU67

HT46RU67/HT46CU67
A/D Type 8-Bit MCU with LCD
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
- HA0047E An PWM application example using the HT46 series of MCUs
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage:
· Watchdog Timer
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Buzzer output function
· Crystal, RC and 32768Hz crystal system oscillator
· 32 bidirectional I/O lines
option
· Two external interrupt inputs
· Power down and wake-up functions reduce power
· Dual 16-bit programmable timer/event counters with
consumption
Programmable Frequency Divider, PFD, function
· 16-level subroutine nesting
· Single 8-bit programmable timer/event counter with
· 8-channel 12-bit resolution A/D converter
source clock prescaler
· 4-channel PWM outputs shared with 4 I/O lines
· 47´3 or 46´4 segment LCD driver with logic
· SIO - Synchronous serial I/O - function
output option for SEG0~SEG23)
· Bit manipulation instruction
· 32K´16 program memory
· 16-bit table read instruction
· 768´8 data memory RAM
· Up to 0.5ms instruction cycle with 8MHz system clock
· Universal Asynchronous Receiver Transmitter
· 63 powerful instructions
-UART
· Instruction execution within 1 or 2 machine cycles
· PFD function for sound generation
· Low voltage reset/detector function
· Real Time Clock - RTC
· 52-pin QFP, 56-pin SSOP packages
· 8-bit RTC prescaler
100-pin QFP packages
General Description
The HT46RU67/HT46CU67 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D product applications that
interface directly to analog signals and which require an
LCD Interface. The HT46CU67, mask version device, is
fully pin and functionally compatible with its sister
HT46RU67 OTP device.
Converter, Pulse Width Modulation function, UART, serial I/O interface, Power Down and Wake-up functions,
in addition to a flexible and configurable LCD interface
enhance the versatility of these devices to control a
wide range of applications requiring analog signal processing and LCD interfacing, such as electronic metering, environmental monitoring, handheld measurement
tools, motor driving, etc. for both the industrial and home
appliance application areas.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, multi-channel A/D
Rev. 1.10
1
May 27, 2010
HT46RU67/HT46CU67
Block Diagram
In te rru p t
C ir c u it
P ro g ra m
E P R O M
M
T M R 2 C
T M R 2
P r e s c a le r
U
X
M
U
P r e s c a le r
X
In s tr u c tio n
R e g is te r
M
M P
U
D A T A
M e m o ry
X
T M R 1 C
T M R 1
P F D 1
M
U
P D 7 /T M R 1
fS
X
fS
M U X
In s tr u c tio n
D e c o d e r
M
W D T
S T A T U S
A L U
T im e B a s e
P W M
A C C
C 1
S
D
S
C 3
B P
P D
L C D
M e m o ry
U A R T
P C C
L C D D r iv e r
C O M 0 ~
C O M 2
P o rt D
S IO
P o rt C
P C
C O M 3 /
S E G 4 6
8 -C h a n n e l
A /D C o n v e rte r
S E G 0 ~
S E G 4 5
E N /D IS
P B C
P o rt B
P B
H A L T
P A C
L V D /L V R
P A
2
U
Y S
/4
O S C 3
O S C 4
R T C O S C
X
W D T O S C
S h ifte r
P D C
/4
Y S
3 2 7 6 8 H z
R T C
Rev. 1.10
Y S
P D 6 /T M R 0
P F D 0
O S
R E
V D
V S
O S
fS
T M R 2
IN T C
T M R 0 C
T M R 0
O S C 2
O S C 4
Y S
S T A C K
P ro g ra m
C o u n te r
T im in g
G e n e r a tio n
fS
P o rt A
P D 0
P D 4
P D 5
P D 6
P D 7
/P W
/IN
/IN
/T M
/T M
P C 0
P C 1
P C 2
P C 3
P C 4
P C 5
P C 6
P C 7
/T M
/S D
/S D
/S C
/S C
M 0 ~ P D 3 /P W M 3
T 0
T 1
R 0
R 1
R 2
I
O
K
S
/T X
/R X
P B 0 /A N 0 ~ P B 7 /A N 7
P A 0
P A 1
P A 2
P A 3
P A 4
/B Z
/B Z
/P F D
~ P A 7
May 27, 2010
HT46RU67/HT46CU67
Pin Assignment
1
5 6
R E S
P A 1 /B Z
2
5 5
O S C 1
P A 2
3
5 4
O S C 2
P A 3 /P F D
4
5 3
V D D
P A 4
5
5 2
O S C 3
P A 5
6
5 1
O S C 4
P A 6
7
5 0
S E G 1 6
P A 7
8
4 9
S E G 1 7
P C 6 /T X
9
4 8
S E G 1 8
P C 7 /R X
1 0
4 7
S E G 1 9
S E G
S E G
S E G
S E G
S E G
S E G
S E G
O S C
O S C
V D
V R E
A V D
O S C
O S C
R E
P A 0 /B
P A 1 /B
P A
P A 3 /P F
P A
P A 0 /B Z
D
D
D
S
Z
Z
F
1 4
4 3
S E G 2 3
V S S
1 5
4 2
S E G 2 4
P D 0 /P W M 0
1 6
4 1
S E G 2 5
P D 1 /P W M 1
1 7
4 0
S E G 2 6
P D 2 /P W M 2
1 8
3 9
S E G 2 7
P D 4 /IN T 0
1 9
3 8
S E G 2 8
P D 5 /IN T 1
2 0
3 7
S E G 2 9
P D 6 /T M R 0
2 1
3 6
S E G 3 0
V L C D
2 2
3 5
S E G 3 1
V M A X
2 3
3 4
S E G 3 2
V 1
2 4
3 3
S E G 3 3
V 2
2 5
3 2
S E G 3 4
C 1
2 6
3 1
C O M 3 /S E G 4 6
C 2
2 7
3 0
C O M 2
C O M 0
2 8
2 9
C O M 1
P
P
P
P
P
P
P
1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1
1
8 0
2
7 9
3
7 8
4
7 7
5
7 6
6
7 5
7
7 4
8
7 3
9
7 2
1 0
7 1
1 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
1 2
1 3
1 4
H T 4 6 R U 6 7 /H T 4 6 C U 6 7
1 0 0 Q F P -A
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
S E G
S E G
S E G
S E G
S E G
N C
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
C O M
C O M
C O M
C O M
C 2
C 1
V 2
V 1
V M A
V L C
H T 4 6 R U 6 7 /H T 4 6 C U 6 7
5 6 S S O P -A
6
P B 3 /A N 3
5
S E G 2 2
4
4 4
3
1 3
4
P B 2 /A N 2
2
1
0
S E G 2 1
3
S E G 2 0
4 5
2
4 6
1 2
1
1 1
P B 1 /A N 1
2
4
P B 0 /A N 0
P A 5
P A 6
P A 7
P C 4 /S C S
P C 5
P C 6 /T X
P C 7 /R X
P B 0 /A N 0
P B 1 /A N 1
P B 2 /A N 2
P B 3 /A N 3
P B 4 /A N 4
P B 5 /A N 5
P B 6 /A N 6
P B 7 /A N 7
V S S
A V S S
D 0 /P W M 0
D 1 /P W M 1
D 2 /P W M 2
D 3 /P W M 3
P D 4 /IN T 0
P D 5 /IN T 1
D 6 /T M R 0
D 7 /T M R 1
C 0 /T M R 2
P C 1 /S D I
P C 2 /S D O
P C 3 /S C K
N C
D
1
0
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
3 /S E G 4 6
2
X
S E G 1
S E G 1
O S C
O S C
V D
O S C
O S C
R E
P A 0 /B
P A 1 /B
P A
P A 3 /P F
P A
D
D
S
Z
Z
7
P D 0 /P
P D 1 /P
P D 2 /P
6
P
4
P
3
2
1
P
2
4
P
P C
P C
B 0
B 1
B 2
B 3
P A 5
P A 6
P A 7
6 /T X
7 /R X
/A N 0
/A N 1
/A N 2
/A N 3
V S S
W M 0
W M 1
W M 2
5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
1
3 9
2
3 8
3
3 7
4
3 6
5
3 5
6
H T 4 6 R U 6 7 /H T 4 6 C U 6 7
5 2 Q F P -A
7
8
9
1 0
1 1
1 2
1 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
S E G
S E G
S E G
C O M
C O M
C O M
C O M
V 1
V M A
V L C
P D 6
P D 5
P D 4
D
2
1
0
3 1
3 2
3 3
3 /S E G 4 6
X
/T M R 0
/IN T 1
/IN T 0
Rev. 1.10
3
May 27, 2010
HT46RU67/HT46CU67
Pin Description
Pin Name
PA0/BZ
PA1/BZ
PA2
PA3/PFD
PA4~PA7
PB0/AN0~
PB7/AN7
PC0/TMR2
PC1/SDI
PC2/SDO
PC3/SCK
PC4/SCS
PC5
PC6/TX
PC7/RX
PD0/PWM0
PD1/PWM1
PD2/PWM2
PD3/PWM3
PD4/INT0
PD5/INT1
PD6/TMR0
PD7/TMR1
I/O
Configuration
Option
Description
I/O
Pull-high
Wake-up
Buzzer
PFD
Bidirectional 8-bit input/output port. Each individual pin on this port can
be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input.
Configuration options determine which pins on the port have pull-high resistors. Pins PA0, PA1 and PA3 are pin-shared with BZ, BZ and PFD respectively, the function of which is chosen via configuration options.
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt Trigger input. Configuration options
determine which pins on the port have pull-high resistors. PB is
pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and
pull-high resistor functions are disabled automatically.
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt Trigger input. A Configuration option
determines if the port has pull-high resistors. Pin PC0 is pin-shared with
the timer input pin TMR2. Pins PC4, PC3, PC2 and PC1 are pin-shared
with SCS, SCK, SDO and SDI. Pins PC6 and PC7 are pin-shared with
the UART pins TX and RX.
Pull-high
PWM
Interrupt
Bidirectional 8-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt Trigger input. Configuration options
determine which pins on the port have pull-high resistors. PD0~PD3 are
pin-shared with PWM0~PWM3, the function of each pin is selected via a
configuration option. Pins PD4 and PD5 are pin-shared with external interrupt input pins INT0 and INT1 respectively. Configuration options determine the interrupt enable/disable and the interrupt low/high trigger
type. Pins PD6 and PD7 are pin-shared with the external timer input pins
TMR0 and TMR1 respectively.
I/O
I/O
I/O
OSC1
OSC2
I
O
Crystal or RC
OSC1 and OSC2 are connected to an external RC network or external
crystal, determined by configuration option, for the internal system clock.
For external RC system clock operation, OSC2 is an output pin where
the system frequency can be monitored, at a frequency of 1/4 system
clock. If an RTC oscillator on pins OSC3 and OSC4 is used as a system
clock, then the OSC1 and OSC2 pins should be left floating.
OSC3
OSC4
I
O
RTC or
System Clock
OSC3 and OSC4 are connected to a 32768Hz crystal to form a real time
clock for timing purposes or to form a system clock.
VLCD
¾
¾
LCD power supply
VMAX
¾
¾
IC maximum voltage, connect to VDD, VLCD or V1
V1, V2, C1, C2
I
¾
LCD voltage pump
SEG0~SEG7
O
SEG0~SEG7 or
CMOS Output
SEG8~SEG15
O
LCD driver outputs for LCD panel segments. A configuration option can
SEG8~SEG15 or
select all pins to be used as segment drivers or all pins to be used as
CMOS Output
CMOS outputs.
SEG16~SEG23
O
LCD driver outputs for LCD panel segments. Configuration options can
SEG16~SEG23
select each pin to be used as either a segment driver or each pin to be
or CMOS Output
used as a CMOS output.
SEG24~SEG45
O
Rev. 1.10
¾
LCD driver outputs for the LCD panel segments. A configuration option
can select all pins to be used as segment drivers or all pins to be used as
CMOS outputs.
LCD driver outputs for LCD panel segments
4
May 27, 2010
HT46RU67/HT46CU67
Pin Name
I/O
Configuration
Option
Description
An LCD duty-cycle configuration option determines if SEG46 is config1/3 or 1/4 Duty
ured as a segment driver or as a common output driver for the LCD
COM3 or SEG46
panel. COM0~COM2 are the LCD common outputs.
COM0~COM2
COM3/SEG46
O
VREF
I
¾
Reference voltage input pin.
RES
I
¾
Schmitt Trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
AVDD
I
¾
Positive analog power supply
AVSS
I
¾
Negative analog power supply, ground
Note:
Each pin on Port A can be programmed through a configuration option to have a wake-up function.
Pins V2, C1, C2 and segment pin SEG34 are not available on the 52-pin QFP package.
Segment pins SEG0~SEG15 and SEG35~SEG45 only exist on the 100-pin QFP package.
For the 52-pin QFP and 56-pin SSOP, the VREF, AVDD are bonded together VDD.
For the 52-pin QFP and 56-pin SSOP, the AVSS is bonded together VSS.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
VDD
Operating Voltage
Typ.
Max.
Unit
¾
fSYS=4MHz
2.2
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
3.0
¾
5.5
V
¾
1
2
mA
¾
3
5
mA
¾
1.5
3
mA
¾
3
6
mA
AVDD
Analog Operating Voltage
(see Note 5)
¾
VREF=AVDD
IDD1
Operating Current
(Crystal OSC, RC OSC)
3V
5V
No load, fSYS=4MHz,
ADC Off, UART Off
Operating Current
(Crystal OSC, RC OSC)
5V
IDD2
Min.
Conditions
3V
No load, fSYS=4MHz,
ADC Off, UART On
IDD3
Operating Current
(Crystal OSC, RC OSC)
5V
No load, fSYS=8MHz,
ADC Off, UART Off
¾
4
8
mA
IDD4
Operating Current
(Crystal OSC, RC OSC)
5V
No load, fSYS=8MHz,
ADC Off, UART On
¾
5
10
mA
IDD5
Operating Current
(fSYS=32768Hz)
¾
0.3
0.6
mA
¾
1
1.9
mA
¾
¾
1
mA
¾
¾
2
mA
ISTB1
Rev. 1.10
Standby Current
(*fS=T1)
3V
5V
3V
5V
No load, ADC Off,
UART Off
No load, system HALT,
LCD Off at HALT, UART Off
5
May 27, 2010
HT46RU67/HT46CU67
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
No load, system HALT,
LCD On at HALT, C type,
UART Off
¾
2.5
5
mA
¾
10
20
mA
No load, system HALT,
LCD On at HALT, C type,
UART Off
¾
2
5
mA
¾
6
10
mA
¾
17
30
mA
¾
34
60
mA
¾
13
25
mA
¾
28
50
mA
¾
14
25
mA
¾
26
50
mA
¾
10
20
mA
¾
19
40
mA
VDD
ISTB2
ISTB3
ISTB4
Standby Current
(*fS=RTC OSC)
3V
Standby Current
(*fS=WDT OSC)
3V
Standby Current
(*fS=RTC OSC)
5V
5V
3V
5V
ISTB5
Standby Current
(*fS=RTC OSC)
3V
5V
ISTB6
Standby Current
(*fS=WDT OSC)
3V
5V
ISTB7
Standby Current
(*fS=WDT OSC)
3V
5V
Conditions
No load, system HALT,
LCD On at HALT, R type,
1/2 bias, VLCD=VDD,
UART Off
(Low bias current option)
No load, system HALT,
LCD On at HALT, R type,
1/3 bias, VLCD=VDD,
UART Off
(Low bias current option)
No load, system HALT,
LCD On at HALT, R type,
1/2 bias, VLCD=VDD,
UART Off
(Low bias current option)
No load, system HALT,
LCD On at HALT, R type,
1/3 bias, VLCD=VDD,
UART Off
(Low bias current option)
VIL1
Input Low Voltage for I/O Ports,
TMR0, TMR1, INT0 and INT1
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR0, TMR1, INT0 and INT1
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
LVR 2.1V option
1.98
2.1
2.22
V
LVR 3.15V option
2.98
3.15
3.32
V
LVR 4.2V option
3.98
4.2
4.42
V
LVD voltage 2.2V option
2.1
2.2
2.31
V
LVD voltage 3.3V option
3.15
3.3
3.46
V
LVD voltage 4.4V option
4.2
4.4
4.62
V
52QFP, 56SSOP
0
¾
AVDD
V
80QFP, 100QFP
0
¾
VREF
V
AVDD=3V
1.3
¾
AVDD
V
AVDD=5V
1.5
¾
AVDD
V
6
12
¾
mA
10
25
¾
mA
-2
-4
¾
mA
-5
-8
¾
mA
VLVR
VLVD
VAD
VREF
IOL1
IOH1
Rev. 1.10
Low Voltage Reset Voltage
Low Voltage Detector Voltage
A/D Input Voltage
¾
¾
¾
ADC Input Reference Voltage
Range
¾
I/O Port Segment Logic Output
Sink Current
3V
I/O Port Segment Logic Output
Source Current
VOL=0.1VDD
5V
3V
VOH=0.9VDD
5V
6
May 27, 2010
HT46RU67/HT46CU67
Test Conditions
Symbol
Parameter
VDD
LCD Common and Segment
Current
IOL2
LCD Common and Segment
Current
IOH2
3V
Typ.
Max.
Unit
210
420
¾
mA
350
700
¾
mA
-80
-160
¾
mA
-180
-360
¾
mA
¾
20
60
100
kW
¾
10
30
50
kW
¾
0.5
1
mA
¾
1.5
3
mA
VOL=0.1VDD
5V
3V
VOH=0.9VDD
5V
Pull-high Resistance of I/O 3V
Ports
5V
and INT0, INT1
RPH
Min.
Conditions
3V
Additional Power Consumption
if A/D Converter is Used
5V
DNL
ADC Differential Non-Linear
5V
AVDD=5V, VREF=AVDD,
tAD=1ms
¾
¾
±2
LSB
INL
ADC Integral Non-Linear
5V
AVDD=5V, VREF=AVDD,
tAD=1ms
¾
±2.5
±4
LSB
¾
¾
12
Bits
IADC
RESOLU Resolution
Note:
tAD=1ms
¾
¾
1. ²*fS² refer to the WDT clock option
2. ISTB1=WDT disable, ISTB2~ISTB7=WDT enable
3. Voltage level of AVDD and VDD must be the same.
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
System Clock
(Crystal OSC, RC OSC)
fSYS1
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
2.2V~5.5V
¾
32768
¾
Hz
¾
32768
¾
Hz
fSYS2
System Clock
(32768Hz Crystal OSC)
¾
fRTCOSC
RTC Frequency
¾
fTIMER
Timer I/P Frequency
(TMR0/TMR1)
tWDTOSC Watchdog Oscillator Period
Min.
Conditions
¾
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Power-up or wake-up
from HALT
¾
1024
¾
tSYS
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
80
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
Note:
tSYS= 1/fSYS1 or 1/fSYS2
Rev. 1.10
7
May 27, 2010
HT46RU67/HT46CU67
Functional Description
Execution Flow
Program Counter - PC
The system clock is derived from either a crystal or an
RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
The program counter is 15 bits wide and controls the sequence in which the instructions stored in the program
ROM are executed. The contents of the PC can specify
a maximum of 32768´16 addresses.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
The pipelining scheme allows each instruction to be effectively executed in a cycle. If an instruction changes
the value of the program counter, two cycles are required to complete the instruction.
After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1.
The PC then points to the memory word containing the
next instruction code.
S y s te m
O S C 2 (R C
T 1
C lo c k
T 2
T 3
T 4
T 1
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,a subroutine call, interrupt or reset, etc., the
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*14 *13 *12 *11 *10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt 0 or
A/D Converter Interrupt
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt 1 or
Serial Interface Interrupt
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
UART Bus Interrupt or
Serial Interface Interrupt
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
Multi-function Interrupt
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
Skip
Program Counter + 2 (Within the current bank)
Loading PCL
*14 *13 *12 *11 *10
*9
*8
@7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch
BP.6 BP.5 #12 #11 #10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S14 S13 S12 S11 S10 S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*14~*0: Program counter bits
#12~#0: Instruction code bits
1 4 1 3 1 2
8 7
P ro g ra m
B P
.6
S14~S0: Stack register bits
@7~@0: PCL bits
0
C o u n te r
B P
.5
B a n k P o in te r (B P )
Rev. 1.10
8
May 27, 2010
HT46RU67/HT46CU67
Certain locations in the Program Memory are reserved
for special usage:
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
· Location 000H
Location 000H is reserved for program initialisation.
After a device reset, the program will jump to this location and begin execution.
· Location 004H
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writable register.
By transferring data directly into this register, a short program jump can be executed directly, however, as only
this low byte is available for manipulation, the jumps are
limited to the present page of memory, that is 256 locations. When such program jumps are executed it should
also be noted that a dummy cycle will be inserted.
Location 004H is reserved for the external interrupt or
the A/D converter interrupt, selected via configuration
option. If the INT0 input pin is activated or if an A/D
conversion has completed, the interrupt is enabled,
and the stack is not full, the program begins execution
at location 004H.
· Location 008H
Location 008H is also reserved for the external interrupt service program or serial interface interrupt, selected via configuration option. If the INT1 input pin is
activated, or 8-bit data have been received/transmitted successful from serial interface, the interrupt is enabled, and the stack is not full, the program will jump
to this location and begin execution.
As the Program Memory is stored in two Banks, the Bank
selection is under the control of bit 5 of the Bank Pointer.
It is this Bank Pointer bit that controls the highest address
bit of the Program Counter as shown in the diagram.
· Location 00CH
Program Memory
Location 00CH is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
The program memory is used to store the program instructions, which are to be executed. It also contains
data, table, and interrupt entries, and is organized into a
format of 32768´16 bits, which are addressed by the PC
and table pointer. The Program Memory is divided into
two banks, Bank0 and Bank1. Each bank has a capacity
of 8192´16 bits and is selected using bits BP.5 and PB.6
in the the bank pointer register. With BP = 000XXXXXB,
Bank 0 is selected and with BP = 001XXXXXB, Bank 1 is
selected, Bank 2 is selected and with BP = 010xxxxxB;
Bank 3 is selected and with BP = 011xxxxxB. The JMP
and CALL instructions provide only 13 bits of address to
allow branching within any 8K program memory bank.
When executing a JMP or CALL instruction, the user
must ensure that the bank pointer bit, BP.5, BP.6 is programmed so that the desired program memory bank is
addressed. If a return from a CALL instruction or interrupt is executed, the entire 14 bit PC is popped off the
stack. Therefore, manipulation of the BP.5 is not required when the RET or RETI instructions are executed.
0 0 0 H
D e v ic e in itia liz a tio n p r o g r a m
0 0 4 H
E x te rn a
A /D
E x te rn a
o r S e
0 0 8 H
0 0 C H
l in te r r u p t 0 s u b r o u tin e /
C o n v e rte r In te rru p t
l In te r r u p t 1 S u b r o u tin e
r ia l In te r fa c e In te r r u p t
T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e
0 1 0 H
T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e
0 1 4 H
U A R T B u s In te rru p t
o r S e r ia l In te r fa c e In te r r u p t
0 1 8 H
P ro g ra m
M e m o ry
(8 1 9 2
M u lti- F u n c tio n In te r r u p t
n 0 0 H
´
4 B a n k )
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
1 F 0 0 H
L o o k - u p ta b le ( 2 5 6 w o r d s )
1 F F F H
N o te : n ra n g e s fro m
1 6 b its
0 to 1 F
Program Memory
Instruction(s)
Table Location
*14~*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TBHP
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1111111
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*14~*0: Table location bits
@7~@0: Table pointer lower-order bits (TBLP)
Rev. 1.10
TBHP: Table pointer higher-order bits
9
May 27, 2010
HT46RU67/HT46CU67
· Location 010H
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer, known as SP, which is neither readable nor
writeable. At the start of a subroutine call or an interrupt
acknowledgment, the contents of the program counter
is pushed onto the stack. At the end of the subroutine or
interrupt routine, signaled by a return instruction, RET or
RETI, the contents of the program counter is restored to
its previous value from the stack. After a device reset,
the stack pointer will point to the top of the stack.
Location 010H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
· Location 014H
Location 014H is reserved for the UART Bus interrupt
service program or serial interface interrupt, selected
via configuration option. If the UART Bus interrupt resulting from a transmission flag or reception is completed, or 8-bit data have been received/transmitted
successful from serial interface, and if the interrupt is
enabled and the stack is not full, the program will jump
to this location and begin execution.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the acknowledge signal is still inhibited. Once the SP is decremented, using an RET or RETI instruction, the interrupt
is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a ²CALL² is subsequently
executed, a stack overflow occurs and the first entry is
lost as only the most recent 16 return addresses are
stored.
· Location 018H
This area is reserved for the Multi-function interrupt
service program. If a timer interrupt results from a
Timer/Event Counter 2 overflow, or the real time clock
time out, or Time base time out, and if the interrupt is
enabled and the stack is not full, the program will jump
to this location and begin execution.
Data Memory - RAM
· Table location
The Data Memory, RAM, has a structure of 812´8 bits,
and is divided into two functional groups, namely; special function registers, 44´8 bits, and general purpose
data memory (Bank 0: 192´8 bits, Bank 2: 192´8 bits,
Bank 3: 192´8 bits and Bank 4: 192´8 bits). Most of
these registers are readable and writeable, although
some are read only. The special function registers are
overlapped in any bank.
Any location in the Program Memory can be used as a
look-up table. The instructions ²TABRDC [m]² (page
specified by the TBHP) for the current page, 1
page=256 words) and ²TABRDL [m]² (the last page),
transfer the contents of the lower-order byte to the
specified data memory, and the contents of the
higher-order byte to the TBLH register. This is the Table Higher-order byte register (08H). Only the destination of the lower-order byte in the table is well-defined,
the other bits of the table word are all transferred to
the lower portion of the TBLH. The TBLH is read only,
the higher-order byte table pointer TBHP (1FH) and
the table pointer, TBLP, is a read/write register (07H),
indicating the table location. Before accessing the table, the location should be placed in the TBHP and
TBLP registers. All the table related instructions require 2 cycles to complete the operation. These areas
may function as a normal Program Memory depending upon the user¢s requirements.
The unused space before address 40H is reserved for
future expansion usage and reading these locations will
retrieve a value of ²00H². The space before 40H overlaps in each bank. The general purpose data memory,
addressed from 40H to FFH (Bank 0; BP=0, Bank 2;
BP=2, Bank 3; BP=3 or Bank 4; BP=4), is used for data
and control information under instruction commands. All
of the data memory areas can directly handle arithmetic,
logic, increment, decrement and rotate operations . Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i².
They are also indirectly accessible through the memory
pointer registers, MP0;01H and MP1;03H.
Stack Register - STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 16 levels and is neither part of the data
Rev. 1.10
10
May 27, 2010
HT46RU67/HT46CU67
0 0 H
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
R T C C
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
T M R 0 H
0 D H
T M R 0 L
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the Data Memory
pointed to by MP0 and MP1 respectively. Reading location 00H or 02H indirectly returns the result 00H. Writing
to it indirectly results to no operation.
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the Data Memory in combination with their corresponding indirect addressing registers. MP0 can only be
used to access data from Bank 0, while MP1 can be
used to access data from all banks.
Accumulator - ACC
The accumulator, ACC, is related to the ALU operations.
It is also mapped to location 05H of the Data Memory,
and is capable of operating with immediate data. The
data movement between two data memory locations
must pass through the ACC.
1 8 H
P D
1 9 H
P D C
1 A H
P W M 0
1 B H
P W M 1
1 C H
P W M 2
1 D H
P W M 3
1 E H
IN T C 1
1 F H
T B H P
Arithmetic and Logic Unit - ALU
S p e c ia l P u r p o s e
D a ta M e m o ry
This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ, etc.)
2 0 H
2 1 H
The ALU not only saves the results of a data operation
but also changes the status register.
2 2 H
2 3 H
2 4 H
A D R L
2 5 H
A D R H
2 6 H
A D C R
2 7 H
A C S R
2 8 H
S B C R
2 9 H
S B D R
Status Register - STATUS
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PDF), and a
watchdog time-out flag (TO). It also records the status
information and controls the operational sequence.
2 A H
2 B H
2 C H
2 D H
T M R 2
2 E H
T M R 2 C
2 F H
M F IC
3 0 H
U S R
3 1 H
U C R 1
3 2 H
U C R 2
3 3 H
T X R /R X R
3 4 H
3 5 H
B R G
3 F H
4 0 H
F F H
G e n e ra
D a ta
1 9 2 B
(4 B a n k s : B
B a n k 3
l P
M e
y te
a n
, B
u rp o s e
m o ry
s ´ 4
k 0 , B a n k 2 ,
a n k 4 )
Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to the other
registers. Data written into the status register does not
alter the TO or PDF flags. Operations related to the status register, however, may yield different results from
those intended. The TO and PDF flags can only be
changed by a Watchdog Timer overflow, device
power-up, or clearing the Watchdog Timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags
reflect the status of the latest operations.
On entering the interrupt sequence or executing a subroutine call, the status register will not be automatically
pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions to
save it properly.
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
Rev. 1.10
11
May 27, 2010
HT46RU67/HT46CU67
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction, otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
4
PDF
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is
set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
is set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Status (0AH) Register
Interrupts - INTC0, INTC1, MFIC
on pins INT0 or INT1 . A configuration option exists to
select one of three transition types, either high to low,
low to high or both. The related interrupt request flag,
EIF0; bit 4 of the INTC0 register and EIF1; bit 5 of the
INTC0 register, will be set when an external interrupt occurs. After the interrupt is enabled, the stack is not full,
and the external interrupt is active, a subroutine call to
location 04H or 08H occurs. The interrupt request flag,
EIF0 or EIF1 and the EMI bits are all cleared to disable
other maskable interrupts.
The device provides two external interrupts, an A/D converter interrupt, two Internal Timer/Event Counter (0/1)
interrupts, a UART Bus interrupt, SIO (Serial interface)
interrupt, and a Multi-function interrupt. The Multi-function interrupt includes the internal Timer/Event Counter
2 interrupt, the internal real time clock interrupt, and the
internal time base interrupt . The Interrupt Control register 0, INTC0;0BH, interrupt control register 1,
INTC1;1EH, and the Multi-Function interrupt control
register, MFIC;2FH, contain the interrupt control bits
that are used to set the enable/disable status and interrupt request flags.
The 04H vector, in addition to existing for the INT0 external interrupt, is also shared with the A/D converter interrupt. The interrupt selection for this vector is chosen
via configuration option. If the A/D converter interrupt is
chosen, then any trigger edge on pin INT0 will not generate an interrupt. In this case, when an A/D conversion
process has completed, if the EMI and EADI bits are enabled and, the stack is not full, a subroutine call to location 04H will occur.
Once an interrupt subroutine is serviced, other interrupts are all blocked automatically as the EMI bit is
cleared. This scheme may prevent any further interrupt
nesting. Other interrupt requests may take place during
this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the
service routine, the EMI bit and the corresponding bits in
the INTC0, INTC1 and MFIC registers may be set in order to allow interrupt nesting. Once the stack is full, the
interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the SP is decremented.
If immediate service is desired, the stack should be prevented from becoming full.
The internal Timer/Event Counter 0 interrupt is initialised by setting the Timer/Event Counter 0 interrupt request flag, T0F; bit 6 of the INTC0 register, which is
normally caused by a timer overflow. After the interrupt
is enabled, and the stack is not full, and the T0F bit is
set, a subroutine call to location 0CH occurs. The related interrupt request flag, T0F, is reset, and the EMI bit
is cleared to disable other maskable interrupts.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the program counter onto the
stack followed by a branch to a subroutine at the specified location in the Program Memory. Only the contents
of the program counter is pushed onto the stack. If the
contents of the register or the status register is altered
by the interrupt service program which corrupts the desired control sequence, the contents should be saved in
advance.
The Timer/Event Counter 1 and Timer/Event Counter 2
operates in the same manner, The Timer/Event Counter
1 related interrupt request flag is T1F, bit 4 of the INTC1
register, and its subroutine call location is 010H. The
Timer/Event Counter 2 related interrupt request flags
are MFF, bit 6 of the INTC1 register, and T2F, bit 4 of the
MFIC register, and its subroutine call location is 018H.
The related interrupt request flags, T1F and MFF, will be
reset and the EMI bit cleared to disable further interrupts. T2F, bit 4 of the MFIC register, will not be cleared
automatically, and should be cleared by the user.
External interrupts are triggered by an edge transition
Rev. 1.10
12
May 27, 2010
HT46RU67/HT46CU67
MFIC register, caused by a regular real time clock
time-out, RTF; bit 6 of the MFIC register or caused by a
time base time-out, TBF; bit5 of the MFIC register. After
the interrupt is enabled, EMFI=1, the stack is not full,
and the MFF bit is set, a subroutine call to location 018H
will occur. The related interrupt request flag, MFF, is reset and the EMI bit is cleared to disable further
maskable interrupts. T2F, TBF and RTF indicate that a
related interrupt has occurred. As these flags will not be
cleared automatically after reading, they should be
cleared by the user.
The UART Bus interrupt is initialized by setting the
UART Bus interrupt request flag, URF; bit 5 of the
INTC1 register, caused by transmit data register empty
(TXIF), received data available(RXIF), transmission idle
(TIDLE), Over run error (OERR) or Address detected.
When the interrupt is enabled, the stack is not full and
the TXIF, RXIF, TIDLE, OERR bit is set or an address is
detected, a subroutine call to location 014H will occur.
The related interrupt request flag, URF, will be reset and
the EMI bit cleared to disable further interrupts.
The Multi-Function Interrupt, MFI, is initialised by setting
the interrupt request flag, MFF; bit 6 of the INTC1 register, that is caused by a Timer 2 overflow, T2F; bit 4 of the
The serial interface interrupt is initialised by setting the
interrupt request flag (SIF; bit 5 of INTC0 and INTC1),
Bit No.
Label
0
EMI
Function
1
EEI0 or EADI
Controls the external interrupt 0 (1=enable; 0=disable) or
Control A/D interrupt (1=enable; 0=disable)
2
EEI1 or ESII
Controls the external interrupt 1 (1=enable; 0=disable) or
Control the serial interface interrupt (1=enable; 0=disable)
3
ET0I
4
EIF0 or ADF
External interrupt 0 request flag (1=active; 0=inactive) or
A/D converter request flag (1=active; 0=inactive)
5
EIF1 or SIF
External interrupt 1 request flag (1=active; 0=inactive) or
Serial interface data transferred/received interrupt request flag.
6
T0F
7
¾
Controls the master (global) interrupt (1=enable; 0= disable)
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC0 (0BH) Register
Bit No.
Label
0
ET1I
1
EURI or ESII
Control the UART Bus interrupt (1=enable; 0=disable)or
Control the serial interface interrupt (1=enable; 0=disable)
2
EMFI
Control the Multi-function interrupt (1=enable; 0=disable)
3, 7
¾
4
T1F
5
URF or SIF
6
MFF
Function
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
Unused bit, read as ²0²
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
UART Bus request flag (1=active; 0=inactive)or
Serial interface data transferred/received interrupt request flag.
Multi-function interrupt request flag (1=active; 0=inactive)
INTC1 (1EH) Register
Bit No.
Label
0
ET2I
Control the Timer/Event Counter 2 interrupt (1=enable; 0=disable)
Function
1
ETBI
Control the time base interrupt (1=enable; 0=disable)
2
ERTI
Control the real time clock interrupt (1=enable; 0=disable)
3, 7
¾
4
T2F
Unused bit, read as ²0²
Timer/Event Counter 2 interrupt request flag (1=active; 0=inactive)
5
TBF
Time base interrupt request flag (1=active; 0=inactive)
6
RTF
Real time clock interrupt request flag (1=active; 0=inactive)
MFIC (2FH) Register
Rev. 1.10
13
May 27, 2010
HT46RU67/HT46CU67
that is caused by a complete reception or transmission
of 8-bits of data from or to the serial interface. After the
interrupt is enabled, and the stack is not full and the SIF
bit is set, a subroutine call to location 08H or 14H, chosen via configuration options, will occur. The related interrupt request flag, SIF, will be reset and the EMI bit is
cleared to disable further maskable interrupt.
bit 4 of the MFIC register, the real time clock interrupt
flag, RTF; bit 6 of the MFIC register, the time base interrupt flag, TBF; bit 5 of the MFIC register, indicate that a
related interrupt has occurred. As these flags will not be
cleared automatically, they should be cleared by the
user. The enable control Timer 2 interrupt, ET2I, the enable time base interrupt, ETBI, the enable real time
clock interrupt, ERTI, constitute the Interrupt Control
Register 2, MFIC, which is located at 2FH in the Program Memory.
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the ²RETI² instruction is executed or the EMI bit and the
related interrupt control bit are set both to 1, if the stack
is not full. To return from the interrupt subroutine, a
²RET² or ²RETI² instruction may be executed. RETI sets
the EMI bit and enables an interrupt service, but RET
does not.
It is recommended that a program does not use the
²CALL² instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and the interrupt enabling is not well
controlled, the original control sequence may be damaged if a ²CALL² is executed.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Interrupt Source
Oscillator Configuration
The device provides three oscillator circuits for system
clocks. These are an RC oscillator, a crystal oscillator
and a 32768Hz crystal oscillator, the choice of which is
determined by a configuration option. The Power Down
mode will stop the system oscillator, if it is an RC or crystal oscillator type and will ignore external signals in order
to conserve power. If the 32768Hz crystal oscillator is
selected as the system oscillator, it will continue to run in
the Power Down mode, but the instruction execution will
be stopped. Since the 32768Hz oscillator is also designed for timing purposes, the internal timing (RTC,
time base, WDT) operation still runs even if the system
enters the Power Down mode.
Priority Vector
External Interrupt 0 or A/D Interrupt Selected Via Configuration Option
1
04H
External Interrupt 1 or
Serial Interface Interrupt
2
08H
Timer/Event Counter 0 Overflow
3
0CH
Timer/Event Counter 1 Overflow
4
10H
UART Bus Interrupt or
Serial Interface Interrupt
5
14H
Multi-function Interrupt
(Timer/Event Counter 2 / Real Time
Clock/Time Base Overflow)
6
18H
Of the three oscillators, if the RC oscillator is used, an
external resistor between OSC1 and VSS is required,
whose range should be within 24kW to 1MW. The system clock frequency divided by 4, can be monitored on
pin OSC2 if a pull-high resistor is added. This can be
used to synchronise external logic. The RC oscillator
provides the most cost effective solution. However, the
frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is
therefore, not suitable for timing sensitive operations
where accurate an oscillator frequency is desired.
The EMI, EEI0, EEI1, ET0I, ET1I, EURI, EADI, ESII and
EMFI bits are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from
being serviced. Once the interrupt request flags, EIF0,
EIF1, T0F, T1F, URF, ADF, ESII, MFF, are set, they will remain in the INTC0 and INTC1 registers until the interrupts
are serviced or cleared by a software instruction.
The Timer/Event Counter 2 overflow interrupt flag, T2F;
V
4 7 0 p F
O S C 1
O S C 1
O S C 3
O S C 4
3 2 7 6 8 H z C r y s ta l/R T C
D D
O S C 2
O s c illa to r
C r y s ta l O s c illa to r
fS
Y S
/4
O S C 2
R C
O s c illa to r
System Oscillator
Note:
32768Hz crystal enable condition: For WDT clock source or for system clock source.
The external resistor and capacitor components connected to the 32768Hz crystal are not necessary to provide oscillation. For applications where precise RTC frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances.
Rev. 1.10
14
May 27, 2010
HT46RU67/HT46CU67
give a time of about 2.1s~4.3s for the internal WDT oscillator. If the WDT oscillator is disabled, the WDT clock
may still come from the instruction clock. The WDT will
operate in the same manner except that in the Power
Down mode, the WDT will stop counting and lose its protecting purpose. In this situation the system can only be
restarted by external logic. If the device operates in a
noisy environment, using the on-chip WDT internal oscillator is strongly recommended, since the Power Down
mode will stop the system clock.
If the crystal oscillator is to be used, a crystal across
OSC1 and OSC2 is needed to provide the feedback and
phase shift required for oscillation, no other external
components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal
and to get a frequency reference, but two external capacitors must be be connected between OSC1, OSC2
and ground.
The other oscillator circuit is for the real time clock or
RTC, which has a fixed frequency of 32.768kHz. A
32.768kHz crystal oscillator should be connected between OSC3 and OSC4 for its implementation.
A WDT overflow under normal operation initialises a
²device reset² and sets the status bit ²TO². In the Power
Down mode, the overflow initialises a ²warm reset², and
only the program counter and stack pointer are reset to
zero. To clear the WDT contents, three methods can be
adopted. These are an external reset which is a low
level to RES, a software instruction, and a ²HALT² instruction. There are two types of software instructions;
the single ²CLR WDT² instruction and the instruction
pair - ²CLR WDT1² and ²CLR WDT2². Of these two
types of instruction, only one type of instruction can be
active at a time depending on the options - ²CLR WDT²
times selection option. If the ²CLR WDT² is selected,
i.e., CLR WDT times equal one, any execution of the
²CLR WDT² instruction clears the WDT. In the case that
²CLR WDT1² and ²CLR WDT2² are chosen, i.e., CLR
WDT times equal two, these two instructions have to be
executed to clear the WDT, otherwise, the WDT may reset the device due to a time-out.
The RTC oscillator circuit has a quick start up function
which can be activated by setting the ²QOSC² bit, which
is bit 4 of the RTCC register. It is recommended to turn
this bit on at power on, and then turn it off after 2 seconds to conserve power.
The WDT oscillator is a free running on-chip RC oscillator, which requires no external components. When the
system enters the power down mode, the system clock
will stop, but the WDT oscillator will continue to operate,
with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by a configuration option to conserve power.
Watchdog Timer - WDT
The WDT clock source can come from its own dedicated
internal WDT oscillator, from the instruction clock (system clock/4), or from the real time clock oscillator (RTC
oscillator). The timer is designed to prevent software
malfunctions or sequences from jumping to unknown locations with unpredictable results. The WDT can be disabled by a configuration option. If the WDT is disabled,
all executions related to the WDT result in no operation.
Multi-function Timer
The device provides a multi-function timer for the WDT,
time base and the RTC but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming
from the WDT OSC or RTC OSC or the instruction clock
(i.e., system clock divided by 4). The multi-function timer
also provides a selectable frequency signal (ranging
from fS/22 to fS/28) for the LCD driver circuits, and a
selectable frequency signal, ranging from fS/22 to fS/29,
for the buzzer output, setup by configuration options. It
is recommended to select a frequency as near to 4kHz
as possible for the LCD driver circuits for clarity.
The WDT clock source is divided by 212~215 , the actual
value chosen by a configuration option, to get the WDT
time-out period. For the WDT internal oscillator, the minimum WDT time-out period is about 300ms~600ms.
This time-out period may vary with temperature, VDD
and process variations. By using configuration options
to set the WDT prescaler, longer time-out periods can
be realised. If the WDT time-out is selected as 215, the
maximum time-out period is divided by 215~216. This will
S y s te m
R T C
O S C
W D T
O S C
C lo c k /4
3 2 7 6 8 H z
1 2 k H z
R O M
C o d e
O p tio n
fS
D iv id e r
fS /2
8
W D T
P r e s c a le r
M a s k O p tio n
C K
R
T
W D T C le a r
C K
R
T
T im e fS /2 15~
fS /2 14~
fS /2 13~
fS /2 12~
o u
fS
fS
fS
fS
t R e s e t
/2 16
/2 15
/2 14
/2 13
Watchdog Timer
Rev. 1.10
15
May 27, 2010
HT46RU67/HT46CU67
Time Base
Power Down Operation - HALT
The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period
ranges from 212/fS to 215/fS selected by options. If a time
base time-out occurs, the related interrupt request flags,
TBF; bit 5 of the MFIC register, and MFF; bit 6 of the
INTC1 register, will be set. If the interrupt is enabled,
and the stack is not full, a subroutine call to location 18H
occurs. The time base time-out signal can also be applied as a clock source for the Timer/Event Counter 1 to
obtain longer time-out periods.
The Power Down mode is initialised by the ²HALT² instruction and results in the following.
fs
D iv id e r
R O M
· The system oscillator turns off but the WDT oscillator
keeps running if the internal WDT oscillator or the real
time clock is selected.
· The contents of the on-chip RAM and of the registers
remain unchanged.
· The WDT is cleared and starts recounting, if the WDT
clock source comes from the WDT oscillator or the
real time clock oscillator.
· All I/O ports maintain their original status.
P r e s c a le r
· The LCD driver keeps running, if the WDT OSC or
R O M
C o d e
O p tio n
C o d e O p tio n
L C D D r iv e r ( fS /2 2 ~ fS /2 8 )
B u z z e r (fS /2 2~ fS /2 9)
· The PDF flag is set but the TO flag is cleared.
RTC OSC is selected.
The system leaves the Power Down mode by way of an
external reset, an interrupt, an external falling edge signal on port A, or a WDT overflow. An external reset
causes device initialisation, and a WDT overflow performs a ²warm reset². After examining the TO and PDF
flags, the reason behind the chip reset can be determined. The PDF flag is cleared by a system power-up or
by executing the ²CLR WDT² instruction, and is set by
executing the ²HALT² instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the program counter and stack pointer, and
leaves the other registers in their original state.
T im e B a s e In te r r u p t
fS /2 12~ fS /2 15
Time Base
Real Time Clock - RTC
The real time clock operates in the same manner as the
time base in that it is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215,
the actual value of which is setup by software programming. Writing data to the RT2, RT1 and RT0 bits in the
RTCC register, provides various time-out periods. If an
RTC time-out occurs, the related interrupt request flag,
RTF; bit 6 of the MFIC and MFF; bit 6 of the INTC1, is
set. If the interrupt is enabled, and the stack is not full, a
subroutine call to location 18H occurs. The real time
clock time-out signal can also be applied as a clock
source for Timer/Event Counter 0 in order to get longer
time-out period.
fS
D iv id e r
P r e s c a le r
R T 2
R T 1
R T 0
8 to 1 M U X
A Port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in
Port A can be independently selected to wake up the device via configuration options. Awakening from an I/O
port stimulus, the program resumes execution of the
next instruction. On the other hand, awakening from an
interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack
is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is
not full, the regular interrupt response takes place.
2 8/fS ~ 2 15/fS
R T C In te rru p t
When an interrupt request flag is set before entering the
²HALT² state, the system cannot be awakened using
that interrupt.
Real Time Clock
RT2
RT1
RT0
RTC Clock Divided Factor
0
0
0
2 8*
0
0
1
2 9*
0
1
0
210*
0
1
1
211*
1
0
0
212
1
0
1
213
1
1
0
214
1
1
1
215
If wake-up events occur, it takes 1024 tSYS (system
clock period) to resume normal operation. In other
words, a dummy period is inserted after a wake-up. If a
wake-up results from an interrupt acknowledge, the actual interrupt subroutine execution is delayed by more
than one cycle. However, if a wake-up results in the next
instruction execution, the execution will be performed
immediately after the dummy period has finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the Power Down
state.
Note: ²*² not recommended to be used
Rev. 1.10
16
May 27, 2010
HT46RU67/HT46CU67
The functional unit chip reset status is shown below.
Reset
There are several ways in which a reset may occur.
· RES is reset during normal operation
· Power on reset
· RES is reset during a Power Down
· WDT time-out is reset during normal operation
· WDT time-out during a Power Down
A WDT time-out when the device is in the Power Down
mode differs from the other reset conditions, as it performs a ²warm reset² that resets only the program counter and SP and leaves the other circuits in their original
state. Some registers remain unaffected during the
other reset conditions. Most registers are reset to their
initial condition once the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between the different types of resets.
TO
0
PDF
0
Program Counter
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT, RTC,
Time Base
Cleared. After a master reset,
the WDT starts counting
Timer/event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
V
1 0 0 k W
1 0 0 k W
R E S
RES reset during normal operation
0
1
RES Wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT Wake-up HALT
B a s ic
R e s e t
C ir c u it
Note:
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the system awakens from the Power Down mode or during
power up.
H A L T
H i-n o is e
R e s e t
C ir c u it
tS
S T
O S C 1
S S T T im e - o u t
W a rm
W D T
R e s e t
T im e - o u t
R e s e t
E x te rn a l
R E S
V D D
S S T
1 0 - b it R ip p le
C o u n te r
C o ld
R e s e t
P o w e r - o n D e te c tio n
R e s e t
Reset Timing Chart
Rev. 1.10
0 .1 m F
Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the
Hi-noise Reset Circuit.
W D T
R E S
1 0 k W
Reset Circuit
Note: ²u² stands for unchanged
C h ip
R E S
0 .1 m F
RES reset during power-up
u
D D
0 .0 1 m F
RESET Conditions
u
V
D D
Reset Configuration
17
May 27, 2010
HT46RU67/HT46CU67
The register states are summarized below:
Register
MP0
Reset
(Power On)
xxxx xxxx
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
uuuu uuuu
uuuu uuuu
RES Reset
(HALT)
WDT Time-out
(HALT)*
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
00u0 00uu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000H
0000H
0000H
0000H
0000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
RTCC
--00 0111
--00 0111
--00 0111
--00 0111
--uu uuuu
Program
Counter
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR0H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
0000 1---
0000 1---
0000 1---
0000 1---
uuuu u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PWM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM2
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM3
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
INTC1
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
SBCR
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
SBDR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRL
xxxx ----
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
1--- --00
1--- --00
1--- --00
---- --00
u--- --uu
TMR2
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR2C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
MFIC
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
USR
0000 1011
0000 1011
0000 1011
0000 1011
uuuu uuuu
Rev. 1.10
18
May 27, 2010
HT46RU67/HT46CU67
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
UCR1
0000 00x0
0000 00x0
0000 00x0
0000 00x0
uuuu uuuu
UCR2
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TXR/RXR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BRG
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
The event count mode is used to count external events,
which means that the clock source comes from the external, TMR0, TMR1 or TMR2 pin. The timer mode functions as a normal timer with the clock source coming
from the internally selected clock source. Finally, the
pulse width measurement mode can be used to count
the duration of a high or low level external signal on pin
TMR0, TMR1 or TMR2. The counting is based on the internally selected clock source.
Timer/Event Counter
Three timer/event counters are implemented in this
microcontroller. The Timer/Event Counter 0 contains a
16-bit programmable count-up counter whose clock
may come from an external or internal source. Its internal clock source comes from fSYS. The Timer/Event
Counter 1 contains a 16-bit programmable count-up
counter whose clock may come from an external or internal source. Its internal clock source comes from either fSYS/4 or the 32768Hz RTC oscillator selected via
configuration option. The Timer/Event Counter 2 contains an 8-bit programmable count-up counter whose
clock may come from an external or internal source. Its
internal clock source comes from fSYS. The external
clock input allows the user to count external events,
measure time intervals or pulse widths, or generate an
accurate time base.
In the event count or timer mode, the Timer/Event Counter 0 (1) starts counting at the current contents in the
timer/event counter and ends at FFFFH. Timer/Event
Counter 2 starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt request flag which are T0F; bit 6 of INTC0, T1F; bit 4 of
INTC1, T2F; bit 4 of MFIC and bit 6 of INTC1.
There are eight registers related to the Timer/Event
Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C
(0EH) and the Timer/Event Counter 1; TMR1H (0FH),
TMR1L (10H), TMR1C (11H) and the Timer/Event
Counter 2; TMR2 (2DH) TMR2C (2EH). Writing to
TMR0L (TMR1L) will only put the written data into an internal lower-order byte buffer (8-bit) while writing to
TMR0H (TMR1H) will transfer the specified data and the
contents of the lower-order byte buffer into the TMR0H
(TMR1H) and TMR0L (TMR1L) registers, respectively.
The Timer/Event Counter 1/0 preload register is
changed by each write operation to TMR0H (TMR1H).
Reading from the TMR0H (TMR1H) will latch the contents of the TMR0H (TMR1H) and TMR0L (TMR1L)
counters to the destination and the lower-order byte
buffer, respectively. Reading from TMR0L (TMR1L) will
read the contents of the lower-order byte buffer. Writing
to TMR2 places the start value into the Timer/Event
Counter 2 preload register, and reading from TMR2 retrieves the contents of the Timer/Event Counter 2. The
TMR0C (TMR1C,TMR2C) register is the Timer/Event
Counter 0 (1, 2) control register, which defines the operating mode, enable or disable function and the active
edge.
To enable the pulse width measurement mode, the operating mode select bits should both be set high. After
the TMR0/TMR1/TMR2 pin has received a transient
from low to high, or high to low if the T0E/T1E/T2E bit is
²0², it will start counting until the TMR0/TMR1/ TMR2 pin
returns to its original level a which point the
T0ON/T1ON/T2ON bit will be auomatically reset.
The measured result remains in the timer/event counter
even if the activated transient occurs again. In other
words, only a single shot measurement can be made.
Not until the T0ON/T1ON/T2ON bit is again set by the
program, can further pulse width measurements be
made. In this operation mode, the timer/event counter
begins counting not according to the logic level but to
the transient edges. In the case of counter overflows,
the counter is reloaded from the timer/event counter
register and issues an interrupt request, as in the other
two modes, i.e., event and timer modes.
To enable the counting operation, the Timer ON bit,
T0ON; bit 4 of TMR0C, T1ON; bit 4 of TMR1C, or T2ON;
bit 4 of TMR2C, should be set to 1. In the pulse width
measurement mode, the T0ON/T1ON/ T2ON is automatically cleared after a measurement cycle is comp l e t e d . B u t i n t h e o t h e r t w o m o d e s, t h e
T0ON/T1ON/T2ON can only be reset by instructions.
The T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C) and
T2M0, T2M1 (TMR2C) bits define the operational mode.
Rev. 1.10
19
May 27, 2010
HT46RU67/HT46CU67
ting the timer enable bit high together with a mode bit
modification, may lead to improper timer operation if executed as a single timer control register byte write instruction.
The overflow of the Timer/Event Counter 0/1/2 is one of
the wake-up sources. The Timer/Event Counter 0/1 can
also be applied to a PFD or Programmable Frequency
Divider whose output is on pin PA3 via a configuration
option. Only one PFD (PFD0 or PFD1) can be applied to
PA3 by options. No matter what the operation mode is,
writing a ²0² to ET0I, ET1I or ET2I disables the related
interrupt service. When the PFD function is selected, executing the ²SET [PA].3² instruction will enable the PFD
output and executing the ²CLR [PA].3² instruction will
disable the PFD output.
When the timer/event counter is read, the clock is
blocked to avoid errors. As this may results in a counting
error, blocking of the clock should be taken into account
by the programmer.
It is strongly recommended to load a desired value into
the TMR0/TMR1/TMR2 registers first, before turning on
the related timer/event counter, for proper operation
since the initial value of the TMR0/TMR1/TMR2 registers are unknown. Due to the timer/event counter
scheme, the programmer should pay special attention
to the instruction to enable then disable the timer for the
first time, whenever there is a need to use the
timer/event counter function, to avoid unpredictable result. After this procedure, the timer/event counter function can be operated normally.
If the timer/event counter is not running, writing data to
the timer/event counter preload register will also reload
that data to the timer/event counter. But if the
timer/event counter running, data written to the
timer/event counter is kept only in the timer/event counter preload register. The timer/event counter continues
to operate until an overflow occurs at which point the
new data will be loaded from the preload register into the
timer/event counter.
The bit0~bit2 of the TMR0C/TMR2C (T0PSC2~0/
T2PSC2~0) can be used to define the pre-scaling
stages of the internal clock sources of the timer/event
counter. The overflow signal of the timer/event counter
can be used to generate the PFD signal. The timer
prescaler is also used as the PWM counter.
After the timer has been initialised the timer can be
turned on and off by controlling the enable bit in the
timer control register. Note that setting the timer enable
bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. SetP W M
(6 + 2 ) o r (7 + 1 )
C o m p a re
fS
T o P D 0 /P D 1 /P D 2 /P D 3 C ir c u it
D a ta B u s
8 - s ta g e P r e s c a le r
Y S
f IN
8 -1 M U X
T 0 P S C 2 ~ T 0 P S C 0
L o w B y te
B u ffe r
T
T 0 M 1
T 0 M 0
T M R 0
1 6 - B it
P r e lo a d R e g is te r
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te
L o w
R e lo a d
O v e r flo w
B y te
to In te rru p t
1 6 - B it T im e r /E v e n t C o u n te r
P F D 0
Timer/Event Counter 0
D a ta B u s
fS Y S /4
3 2 7 6 8 H z
M U X
f IN
L o w B y te
B u ffe r
T
T 1 M 1
T 1 M 0
T 1 S
T M R 1
1 6 - B it
P r e lo a d R e g is te r
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te
L o w
R e lo a d
O v e r flo w
B y te
to In te rru p t
1 6 - B it T im e r /E v e n t C o u n te r
P F D 1
Timer/Event Counter 1
Rev. 1.10
20
May 27, 2010
HT46RU67/HT46CU67
fS
Y S
8 - s ta g e P r e s c a le r
f IN
8 -1 M U X
T 2 P S C 2 ~ T 2 P S C 0
(1 /1 ~ 1 /1 2 8 )
D a ta B u s
T
T 2 M 1
T 2 M 0
T M R 2
8 - B it T im e r /E v e n t
C o u n te r P r e lo a d R e g is te r
R e lo a d
T 2 E
T 2 M 1
T 2 M 0
T 2 O N
8 - B it T im e r /E v e n t
C o u n te r (T M R 2 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/Event Counter 2
P F D 0
M
P F D 1
U
T
X
P F D
Q
P A 3 D a ta C T R L
P F D S o u rc e
( O p tio n )
PFD Source Option
Bit No.
Label
Function
T0PSC0
T0PSC1
T0PSC2
Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
3
T0E
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T0ON
0
1
2
5
6
7
¾
T0M0
T0M1
Enables/disables the timer counting
(0=disable; 1=enable)
Unused bit, read as ²0²
Defines the operating mode, T0M1, T0M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH) Register
Rev. 1.10
21
May 27, 2010
HT46RU67/HT46CU67
Bit No.
0~2
Label
¾
3
T1E
4
T1ON
5
T1S
6
7
T1M0
T1M1
Function
Unused bit, read as ²0²
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enables/disables the timer counting (0=disable; 1=enable)
Defines the TMR1 internal clock source.
(0=fSYS/4; 1=32768Hz)
Defines the operating mode, T1M1, T1M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
Bit No.
Label
Function
T2PSC0
T2PSC1
T2PSC2
Defines the prescaler stages, T2PSC2, T2PSC1, T2PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
3
T2E
Defines the TMR2 active edge of the timer/event counter:
In Event Counter Mode (T2M1,T2M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T2M1,T2M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T2ON
0
1
2
5
6
7
¾
T2M0
T2M1
Enables/disables the timer counting (0=disable; 1=enable)
Unused bit, read as ²0²
Defines the operating mode, T2M1, T2M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR2C (2EH) Register
Rev. 1.10
22
May 27, 2010
HT46RU67/HT46CU67
Input/Output Ports
the pull-high configuration options. Each bit of these input/output latches can be set or cleared by the ²SET
[m].i² and ²CLR [m].i² bit manipulation instructions.
There are 32 bidirectional input/output lines in the device,
labeled as PA, PB, PC and PD, which are mapped to the
data memory of [12H], [14H], [16H] and [18H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction ²MOV A,[m]² (m=12H, 14H,
16H or 18H). For output operation, all the data is latched
and remains unchanged until the output latch is rewritten.
Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR [m].i²,
²CPL [m]², ²CPLA [m]² read the entire port states into the
CPU, execute the defined bit operations, and then write
the results back to the latches or the accumulator.
Each line of port A has the capability of waking-up the
device.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, a CMOS output or a Schmitt
Trigger input with or without pull-high resistor structures
can be reconfigured dynamically under software control.
To function as an input, the corresponding latch of the
control register must be setup as a ²1². The input source
also depends on the control register. If the control register bit is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will
move to the internal bus. The latter is possible in the
²read-modify-write² instruction.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor,
otherwise, there¢s none. Take note that a non-pull-high
I/O port operating in input mode will cause a floating
state.
PA0, PA1, PA3, PD4, PD5, PD6 and PD7 are pin-shared
with BZ, BZ, PFD, INT0, INT1, TMR0 and TMR1 pins respectively. The PC0, PC6 and PC7 pins are pin-shared
with TMR2, TX and RX.
PA0 and PA1 are pin-shared with the BZ and BZ signals,
respectively. If the BZ/BZ option is selected, the output
signal in output mode of PA0/PA1 will be the buzzer signal generated by the Multi-function timer. The input
mode always remain in its original functions. Once the
BZ/BZ option is selected, the buzzer output signals are
controlled by the PA0 data register only. The I/O functions of PA0/PA1 are shown below.
For an output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
After a device reset, these I/O lines will default to an input
state and will be either high or floating, depending upon
PAC Register
PAC0
PAC Register
PAC1
PA Data Register
PA0
PA Data Register
PA1
0
0
1
x
PA0=BZ, PA1=BZ
0
0
0
x
PA0=0, PA1=0
0
1
1
x
PA0=BZ, PA1=input
0
1
0
x
PA0=0, PA1=input
1
0
1
x
PA0=input, PA1=BZ
1
0
0
x
PA0=input, PA1=0
1
1
x
x
PA0=input, PA1=input
Note:
Output Function
²x² stands for don¢t care
²D² stands for Data ²0² or ²1²
PA3 is pin-shared with the signal. If the PFD option is selected and if PA3 is setup as an output, then the output signal
on the PA3 pin will be the PFD signal, generated by the timer/event counter overflow signal. If setup as an input it will
function as a normal input pin. Once the PFD option is selected, the PFD output signal is controlled by the PA3 data register only. Writing a ²1² to the PA3 data register will enable the PFD output function while writing a ²0² will force the PA3
pin to remain at ²0². The I/O functions of PA3 are shown below.
Note:
I/O Mode
I/P (Normal)
O/P (Normal)
I/P (PFD)
O/P (PFD)
PA3
Logical Input
Logical Output
Logical Input
PFD (Timer on)
The PFD frequency is the timer/event counter overflow frequency divided by 2.
Rev. 1.10
23
May 27, 2010
HT46RU67/HT46CU67
Port PB can also be used as A/D converter inputs. There is a PWM function shared with PD0/PD1/PD2/PD3. If the
PWM function is enabled, the PWM0/PWM1/PWM2/ PWM3 signal will appear on PD0/PD1/PD2/PD3, if PD0/ PD1/
PD2/PD3 are operating in output mode. Writing ²1² to the PD0~PD3 data register will enable the PWM output function
while writing ²0² will force the PD0~PD3 to remain at ²0². The I/O functions of the PD0/PD1/PD2/PD3 are shown below.
I/O Mode
I/P (Normal)
O/P (Normal)
I/P (PWM)
O/P (PWM)
PD0~PD3
Logical Input
Logical Output
Logical Input
PWM0~PWM3
It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid
consuming power under input floating state.
The definitions of the PFD control signal and PFD output frequency are listed in the following table.
Note:
Timer
Timer Preload Value
PA3 Data Register
PA3 Pad State
PFD Frequency
OFF
X
0
0
X
OFF
X
1
U
X
ON
N
0
0
X
ON
N
1
PFD
fTMR/[2´(M-N)]
²X² stands for unused
²U² stands for unknown
²M² is ²65536² for PFD0 or PFD1
²N² is the preload value for the timer/event counter
²fTMR² is input clock frequency for timer/event counter
V
P u ll- h ig h
O p tio n
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
C K
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
Q
S
M
P A 0 /P A 1 /P A 3 /P D 0 /P D 1 /P D 2 /P D 3
B Z /B Z /P F D /P W M 0 /P W M 1 /P W M 2 /P W M 3
M
R e a d D a ta R e g is te r
U
0 fo
1 fo
0 fo
1 fo
r P D
r P D
r P D
r P D
4 o n
5 o n
6 o n
7 o n
X
E N
X
S y s te m W a k e -u p
( P A o n ly )
IN T
IN T
T M R
T M R
U
D D
P A 0
P A 1
P A 2
P A 3
P A 4
P B 0
P C 0
P C 1
P C 2
P C 3
P D 4
P C 5
P D 0
P D 1
P D 2
P D 3
P D 4
P D 5
P D 6
P D 7
/B Z
/B Z
/P F
~ P A
/A N
/T M
/S D
/S D
/S C
/S C
/P W
/P W
/P W
/P W
/IN
/IN
/T M
/T M
D
7
0 ~ P B 7 /A N 7
R 2
I
O
K
S
M 0
M 1
M 2
M 3
T 0
T 1
R 0
R 1
W a k e - u p O p tio n s
ly
ly
ly
ly
Input/Output Ports
Rev. 1.10
24
May 27, 2010
HT46RU67/HT46CU67
V
C o n tr o l B it
D a ta B u s
Q
D
C K
W r ite C o n tr o l R e g is te r
D D
P u ll- h ig h
O p tio n
Q
S
C h ip R e s e t
P C 6 /T X
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
Q
S
M
F ro m
U A R T T X
M
R e a d D a ta R e g is te r
U
U
X
U A R T E N
X
& T X E N
PC6/TX Input/Output Ports
V
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
C K
D D
P u ll- h ig h
O p tio n
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P C 7 /R X
D a ta B it
Q
D
Q
C K
S
M
R e a d D a ta R e g is te r
U
X
T o U A R T R X
PC7/RX Input/Output Ports
Pulse Width Modulator
duty cycle of one modulation cycle of the output waveform, should be placed. To increase the PWM modulation frequency, each modulation cycle is subdivided into
two or four individual modulation subsections, known as
the 7+1 mode or 6+2 mode respectively. The device can
choose which mode to use by selecting the appropriate
configuration option. When a mode configuration option
is chosen, it applies to all PWM outputs on that device.
Note that when using the PWM, it is only necessary to
write the required value into the appropriate PWM register and select the required mode configuration option,
the subdivision of the waveform into its sub-modulation
cycles is done automatically within the microcontroller
hardware.
Each devices is provided with either three or four Pulse
Width Modulation (PWM) outputs, depending upon
which package type is selected. Useful for such applications such as motor speed control, the PWM function
provides outputs with a fixed frequency but with a duty
cycle that can be varied by setting particular values into
the corresponding PWM register.
A single register, located in the Data Memory is assigned to each PWM output. For devices with three
PWM outputs, these registers are known as PWM0,
PWM1 and PWM2. Devices with four PWM outputs require a further additional register known as PWM3. It is
here that the 8-bit value, which represents the overall
Rev. 1.10
25
May 27, 2010
HT46RU67/HT46CU67
For all devices, the PWM clock source is the system clock fSYS.
Package
Channels
PWM Mode
Output Pin
52/56-pin
3
6+2 or 7+1
PD0/PD1/PD2
PWM0/PWM1/PWM2
PD0/PD1/PD2/PD3
PWM0/PWM1/PWM2/PWM3
100-pin
4
6+2 or 7+1
PWM Register Name
PWM Function Table
four individual sub-cycles known as modulation cycle
0 ~ modulation cycle 3, denoted as ²i² in the table.
Each one of these four sub-cycles contains 64 clock
cycles. In this mode, a modulation frequency increase
of four is achieved. The 8-bit PWM register value,
which represents the overall duty cycle of the PWM
waveform, is divided into two groups. The first group
which consists of bit2~bit7 is denoted here as the DC
value. The second group which consists of bit0~bit1 is
known as the AC value. In the 6+2 PWM mode, the
duty cycle value of each of the four modulation
sub-cycles is shown in the following table.
This method of dividing the original modulation cycle
into a further 2 or 4 sub-cycles enables the generation of
higher PWM frequencies which allow a wider range of
applications to be served. As long as the periods of the
generated PWM pulses are less than the time constants
of the load, the PWM output will be suitable as such long
time constant loads will average out the pulses of the
PWM output. The difference between what is known as
the PWM cycle frequency and the PWM modulation frequency should be understood. As the PWM clock is the
system clock, fSYS, and as the PWM value is 8-bits wide,
the overall PWM cycle frequency is fSYS/256. However,
when in the 7+1 mode of operation the PWM modulation
frequency will be fSYS/128, while the PWM modulation
frequency for the 6+2 mode of operation will be fSYS/64.
PWM
Modulation Frequency
Parameter
i<AC
DC + 1
64
i³AC
DC
64
Modulation cycle i
(i=0~3)
6+2 Mode Modulation Cycle Values
fSYS/256
[PWM]/256
The following diagram illustrates the waveforms associated with the 6+2 mode PWM operation. It is important to note how the single PWM cycle is subdivided
into 4 individual modulation cycles, numbered from
0~3 and how the AC value is related to the PWM
value.
· 6+2 PWM mode
Each full PWM cycle, as it is controlled by an 8-bit
PWM register, has 256 clock periods. However, in the
6+2 PWM mode, each PWM cycle is subdivided into
Y S
Duty Cycle
PWM Cycle PWM Cycle
Frequency
Duty
fSYS/64 for (6+2) bits mode
fSYS/128 for (7+1) bits mode
fS
AC (0~3)
/2
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
(6+2) PWM Mode Output Waveform
b 7
b 0
P W M
R e g is te r
A C
v a lu e
D C
v a lu e
(6 + 2 ) M o d e
6+2 Mode PWM Register
Rev. 1.10
26
May 27, 2010
HT46RU67/HT46CU67
· 7+1 PWM mode
Parameter
Each full PWM cycle, as it is controlled by an 8-bit
PWM register, has 256 clock periods. However, in the
7+1 PWM mode, each PWM cycle is subdivided into
two individual sub-cycles known as modulation cycle 0
and modulation cycle 1, denoted as ²i² in the table.
Each one of these two sub-cycles contains 128 clock
cycles. In this mode, a modulation frequency increase
of two is achieved. The 8-bit PWM register value, which
represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which
consists of bit1~bit7 is denoted here as the DC value.
The second group which consists of bit0 is known as
the AC value. In the 7+1 PWM mode, the duty cycle
value of each of the two modulation sub-cycles is
shown in the following table.
fS
Y S
Modulation cycle i
(i=0~1)
AC (0~1)
i<AC
i³AC
Duty Cycle
DC + 1
128
DC
128
7+1 Mode Modulation Cycle Values
The following diagram illustrates the waveforms associated with the 7+1 mode PWM operation. It is important to note how the single PWM cycle is subdivided
into 2 individual modulation cycles, numbered 0 and 1
and how the AC value is related to the PWM value.
/2
[P W M ] = 1 0 0
P W M
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /1 2 8
P W M
m o d u la tio n p e r io d : 1 2 8 /fS
Y S
M o d u la tio n c y c le 0
M o d u la tio n c y c le 1
P W M
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
(7+1) PWM Mode Output Waveform
b 7
b 0
P W M
R e g is te r
A C
v a lu e
D C
v a lu e
(7 + 1 ) M o d e
7+1 Mode PWM Register
· PWM output control
able the PWM data to appear on the pin. Writing a ²0²
to the corresponding bit in the PD output data register
will disable the PWM output function and force the output low. In this way, the Port D data output register can
be used as an on/off control for the PWM function. Note
that if the configuration options have selected the PWM
function, but a ²1² has been written to its corresponding
bit in the PDC control register to configure the pin as an
input, then the pin can still function as a normal input
line, with pull-high resistor options.
On all devices, the PWM outputs are pin-shared with
the Port D I/O pins. To operate as PWM outputs and not
as I/O pins, the correct PWM configuration options
must be selected. A ²0² must also be written to the corresponding bits in the I/O port control register PDC to
ensure that the required PWM output pins are setup as
outputs. After these two initial steps have been carried
out, and of course after the required PWM value has
been written into the PWM register, writing a ²1² to the
corresponding bit in the PD output data register will en-
Rev. 1.10
27
May 27, 2010
HT46RU67/HT46CU67
The following sample program shows how the PWM outputs are setup and controlled, the corresponding PWM output configuration option must first be selected.
clr PDC.0
clr PDC.1
clr PDC.2
clr PDC.3
; set pin PD0 as output
; set pin PD1 as output
; set pin PD2 as output
; set pin PD3 as output
set pd.0
mov a,64h
mov pwm0,a
; PD.0=1; enable pin ²PD0/PWM0² to be the PWM channel 0
; PWM0=100D=64H
set pd.1
mov a,65h
mov pwm1,a
; PD.1=1; enable pin ²PD1/PWM1² to be the PWM channel 1
; PWM1=101D=65H
set pd.2
mov a,66h
mov pwm2,a
; PD.2=1; enable pin ²PD2/PWM2² to be the PWM channel 2
; PWM2=102D=66H
set pd.3
mov a,67h
mov pwm3,a
; PD.3=1; enable pin ²PD3/PWM3² to be the PWM channel 3
; PWM3=103D=67H
clr pd.0
clr pd.1
clr pd.2
clr pd.3
; disable PWM0 output - PD.0 will remain low
; disable PWM1 output - PD.1 will remain low
; disable PWM2 output - PD.2 will remain low
; disable PWM3 output - PD.3 will remain low
A/D Converter
are disabled and the A/D converter circuit is powered-on. The EOCB bit, bit6 of the ADCR is end of A/D
conversion flag. This bit can be monitored to know when
the A/D conversion has completed. The START bit in
the ADCR register is used to start the conversion process of the A/D converter. Giving the START bit a rising
edge and falling edge means that the A/D conversion
has started. In order to ensure that the A/D conversion is
completed, the START bit should remain at ²0² until the
EOCB flag is cleared to ²0² which indicates the end of
the A/D conversion.
An eight channel and 12 bits resolution A/D converter is
implemented in the microcontroller. The reference voltage is VDD. The A/D converter contains four special
registers which are; ADRL (24H), ADRH (25H), ADCR
(26H) and ACSR (27H). The ADRH and ADRL registers
are the A/D result register higher-order byte and
lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be
read to get the conversion result data. The ADCR is an
A/D converter control register, which defines the A/D
channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. To
start an A/D conversion, the PB configuration must first
be defined, the analog channel selected, after which the
START bit can supply a rising and falling edge
(0®1®0). At the end of A/D conversion, the EOCB bit is
cleared. The ACSR register is the A/D clock setting register, which is used to select the A/D clock source.
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
The EOCB bit is set to ²1² when the START bit is set
from ²0² to ²1².
Important Note for A/D initialisation:
Special care must be taken to initialise the A/D converter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialisation is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initialisation is not required.
The A/D converter control register is used to control the
A/D converter. Bit2~bit0 are used to select an analog input channel. There are a total of eight channels to select. Bit5~bit3 of the ADCR are used to set the PB
configurations. PB can be an analog input or setup as a
normal I/O line, the selected function is determined by
these 3 bits. Once a PB line is selected as an analog input, the I/O function and pull-high resistor of this I/O line
Rev. 1.10
28
May 27, 2010
HT46RU67/HT46CU67
Bit No.
Label
Function
Selects the A/D converter clock source
00=system clock/2
ADCS0
01=system clock/8
ADCS1 10=system clock/32
11=undefined
0
1
2~6
¾
Unused bit, read as ²0²
7
TEST
For test mode used only
ACSR (27H) Register
Bit No.
Label
Function
0
1
2
ACS0
ACS1
ACS2
ACS2, ACS1, ACS0: Select A/D channel
0, 0, 0: AN0
0, 0, 1: AN1
0, 1, 0: AN2
0, 1, 1: AN3
1, 0, 0: AN4
1, 0, 1: AN5
1, 1, 0: AN6
1, 1, 1: AN7
3
4
5
PCR0
PCR1
PCR2
Defines the Port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is
powered off to reduce power consumption.
6
EOCB
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialised by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialisation².
7
START Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
ADCR (26H) Register
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
AN0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
AN1
AN0
0
1
1
PB7
PB6
PB5
PB4
PB3
AN2
AN1
AN0
1
0
0
PB7
PB6
PB5
PB4
AN3
AN2
AN1
AN0
1
0
1
PB7
PB6
PB5
AN4
AN3
AN2
AN1
AN0
1
1
0
PB7
PB6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
1
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Port B Configuration
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADRL
D3
D2
D1
D0
¾
¾
¾
¾
ADRH
D11
D10
D9
D8
D7
D6
D5
D4
Note: D0~D11 is A/D conversion result data bit LSB~MSB.
ADRL (24H), ADRH (25H) Register
Rev. 1.10
29
May 27, 2010
HT46RU67/HT46CU67
The following programming example illustrates how to setup and implement an A/D conversion. The method of polling
the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete.
Example: using EOCB Polling Method to detect end of conversion
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov
ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
; reset A/D
clr
START
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp
polling_EOC
; continue polling
mov
a,ADRH
; read conversion result high byte value from the ADRH register
mov
adrh_buffer,a
; save result to user defined memory
mov
a,ADRL
; read conversion result low byte value from the ADRL register
mov
adrl_buffer,a
; save result to user defined memory
:
:
jmp
start_conversion
; start next A/D conversion
M in im u m
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D
tA
P C R 2 ~
P C R 0
s a m p lin g tim e
A /D
tA
D C S
0 0 0 B
s a m p lin g tim e
A /D
tA
D C S
1 0 0 B
1 0 0 B
s a m p lin g tim e
D C S
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
A /D
tA D
tA
c lo c k m u s t b e fS
= 3 2 tA D
= 8 0 tA D
C S
D C
Y S
/2 , fS
tA D C
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
Rev. 1.10
30
May 27, 2010
HT46RU67/HT46CU67
LCD Memory
and written to only by indirect addressing mode using
MP1. When data is written into the LCD display memory, it is automatically read by the LCD driver which then
generates the corresponding LCD driving signals. To
turn the display on or off, a ²1² or a ²0² is written to the
corresponding bit of the display memory, respectively.
The figure illustrates the mapping between the display
memory and LCD pattern for the device.
The device provides an area of embedded data memory
for LCD display. This area is located from 40H to 6EH of
the Bank 1 Data Memory . The bank pointer, BP, located
at position 04H in the Bank 1 Data Memory, is the switch
between the General Purpose Data Memory and the
LCD display memory. When the BP is set as ²1², any
data written into 40H~6EH will affect the LCD display.
When the BP is cleared to ²0², ²2² or ²3², any data written into 40H~6EH is mapped into the general purpose
data memory. The LCD display memory can be read
C O M
4 0 H
4 1 H
4 2 H
4 3 H
6 C H
6 D H
6 E H
0
LCD Driver Output
The output number of the device LCD driver can be 47´2
or 47´3 or 46´4 chosen via configuration option. This corresponds to, 1/2 duty, 1/3 duty or 1/4 duty. The bias type
LCD driver can be ²R² type or ²C² type. If the ²R² bias
type is selected, no external capacitor is required. If the
²C² bias type is selected, a capacitor mounted between
pins C1 and C2 is needed. The LCD driver bias voltage
can be 1/2 bias or 1/3 bias chosen via configuration option. If 1/2 bias is selected, a capacitor mounted between V2 pin and ground is required. If 1/3 bias is
selected, two capacitors are needed for pins V1 and V2.
Refer to the application diagram.
B it
0
1
1
2
2
3
3
S E G M E N T
0
1
2
3
4 4
4 5
4 6
Display Memory
LCD Segments as Logical Output
The SEG0~SEG23 pins can also can be used as logical outputs via a configuration option. Once an LCD segment is
optioned as a logical output, the contents of bit0 of the related segment address in the LCD RAM will appear on the segment.
SEG0~SEG7 are all byte optioned as logical outputs, SEG8~SEG15 are also byte optioned as logical outputs,
SEG16~SEG23 are individually bit optioned as logical outputs.
LCD Type
LCD Bias Type
VMAX
Rev. 1.10
R Type
1/2 bias
1/3 bias
C Type
1/2 bias
If VDD>VLCD, then VMAX connect to VDD,
else VMAX connect to VLCD
31
1/3 bias
3
If VDD> VLCD, then VMAX connect to VDD,
2
else VMAX connect to V1
May 27, 2010
HT46RU67/HT46CU67
D u r in g a R e s e t P u ls e
C O M 0 ,C O M 1 ,C O M 2
A ll L C D
d r iv e r o u tp u ts
N o r m a l O p e r a tio n M o d e
*
*
C O M 0
C O M 1
C O M 2 *
L C D s e g m e n ts O N
C O M 0 ,1 , 2 s id e s a r e u n lig h te d
O n ly L C D s e g m e n ts O N
C O M 0 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 1 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 2 s id e a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 , 2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 1 , 2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 , 2 s id e s a r e lig h te d
H A L T M o d e
C O M 0 , C O M 1 , C O M 2
A ll lc d d r iv e r o u tp u ts
N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D
*
V L
1 /2
V S
V L
1 /2
V S
C D
V L C D
S
C D
V L C D
S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
V L
1 /2
V S
V L
1 /2
V S
C D
V L C D
S
C D
V L C D
S
C D
C D
C D
C D
C D
C D
C D
C D
C D
C D
C D
is u s e d .
LCD Driver Output (1/3 Duty, 1/2 Byte, R/C Type)
Rev. 1.10
32
May 27, 2010
HT46RU67/HT46CU67
V A
V B
V C
C O M 0
V S S
V A
V B
V C
C O M 1
V S S
V A
V B
V C
C O M 2
V S S
V A
V B
C O M 3
V C
V S S
V A
V B
V C
L C D s e g m e n ts O N
C O M 2 s id e lig h te d
N o te : 1 /4 d u ty , 1 /3 b ia s , C
V S S
ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D
1 /4 d u ty , 1 /3 b ia s , R ty p e : " V A " V L C D , " V B " 2 /3 V L C D , " V C " 1 /3 V L C D
LCD Driver Output
Rev. 1.10
33
May 27, 2010
HT46RU67/HT46CU67
Low Voltage Reset/Detector Functions
There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in this microcontroller. These
two functions can be enabled/disabled by options. Once the LVD option is enabled, the user can use the RTCC.3 bit to
enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5, otherwise, the LVD function is
disabled.
The RTCC register definitions are listed below.
Bit No.
Label
0~2
RT0~RT2
3
LVDC*
LVD enable/disable (1/0)
4
QOSC
32768Hz OSC quick start-up oscillating
0/1: quick/slow start
5
LVDO
LVD detection output (1/0)
1: low voltage detected, read only
6, 7
¾
Note:
Function
8 to 1 multiplexer control inputs to select the real clock prescaler output
Unused bit, read as ²0²
²*² Once the LVD function is enabled the reference generator should be enabled; otherwise the reference generator is
controlled by LVR ROM code option. The relationship between LVR and LVD options and LVDC are as shown.
RTCC (09H) Register
The LVR has the same effect or function with the external RES signal which performs a chip reset. During
HALT state, both LVR and LVD are disabled.
The relationship between VDD and VLVR is shown below.
V D D
5 .5 V
V
O P R
5 .5 V
The LVR state requires the following specifications:
· The low voltage (0.9V~VLVR) has to be maintained for
more than 1ms, otherwise, the circuits remain in their
original state. If the low voltage state does not exceed
1ms, the LVR will ignore it and do not perform a reset
function.
V
L V R
3 .0 V
2 .2 V
· The LVR uses the ²OR² function with the external RES
0 .9 V
signal to perform a chip reset.
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
R e s e t
N o r m a l O p e r a tio n
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.
Rev. 1.10
34
May 27, 2010
HT46RU67/HT46CU67
which can also be used as a general purpose I/O pin,
if the pin is not configured as a receiver, which occurs
if the RXEN bit in the UCR2 register is equal to zero.
Along with the UARTEN bit, the TXEN and RXEN bits,
if set, will automatically setup these I/O pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on
the RX pin.
UART Bus Serial Interface
The HT46RU67/HT46CU67 devices contain an integrated full-duplex asynchronous serial communications
UART interface that enables communication with external devices that contain a serial interface. The UART
function has many features and can transmit and receive data serially by transferring a frame of data with
eight or nine data bits per transmission as well as being
able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own
internal interrupt which can be used to indicate when a
reception occurs or when a transmission terminates.
· UART data transfer scheme
The block diagram shows the overall data transfer
structure arrangement for the UART. The actual data
to be transmitted from the MCU is first transferred to
the TXR register by the application program. The data
will then be transferred to the Transmit Shift Register
from where it will be shifted out, LSB first, onto the TX
pin at a rate controlled by the Baud Rate Generator.
Only the TXR register is mapped onto the MCU Data
Memory, the Transmit Shift Register is not mapped
and is therefore inaccessible to the application program.
Data to be received by the UART is accepted on the
external RX pin, from where it is shifted in, LSB first, to
the Receiver Shift Register at a rate controlled by the
Baud Rate Generator. When the shift register is full,
the data will then be transferred from the shift register
to the internal RXR register, where it is buffered and
can be manipulated by the application program. Only
the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is
therefore inaccessible to the application program.
It should be noted that the actual register for data
transmission and reception, although referred to in the
text, and in application programs, as separate TXR
and RXR registers, only exists as a single shared register in the Data Memory. This shared register known
as the TXR/RXR register is used for both data transmission and data reception.
· UART features
The integrated UART function contains the following
features:
¨
Full-duplex, asynchronous communication
¨
8 or 9 bits character length
¨
Even, odd or no parity options
¨
One or two stop bits
¨
Baud rate generator with 8-bit prescaler
¨
Parity, framing, noise and overrun error detection
¨
Support for interrupt on address detect
(last character bit=1)
¨
Separately enabled transmitter and receiver
¨
2-byte Deep Fifo Receive Data Buffer
¨
Transmit and receive interrupts
¨
Interrupts can be initialized by the following
conditions:
-
Transmitter Empty
-
Transmitter Idle
-
Receiver Full
-
Receiver Overrun
-
Address Mode Detect
· UART status and control registers
There are five control registers associated with the
UART function. The USR, UCR1 and UCR2 registers
control the overall function of the UART, while the
BRG register controls the Baud rate. The actual data
to be transmitted and received on the serial interface
is managed through the TXR/RXR data registers.
· UART external pin interfacing
To communicate with an external serial interface, the
internal UART has two external pins known as TX and
RX. The TX pin is the UART transmitter pin, which can
be used as a general purpose I/O pin if the pin is not
configured as a UART transmitter, which occurs when
the TXEN bit in the UCR2 control register is equal to
zero. Similarly, the RX pin is the UART receiver pin,
T r a n s m itte r S h ift R e g is te r
M S B
R e c e iv e r S h ift R e g is te r
L S B
T X P in
C L K
T X R
R e g is te r
M S B
R X P in
L S B
C L K
B a u d R a te
G e n e ra to r
R X R R e g is te r
B u ffe r
M C U D a ta B u s
UART Data Transfer Scheme
Rev. 1.10
35
May 27, 2010
HT46RU67/HT46CU67
· USR register
RXIF flag is cleared when the USR register is read
with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available.
The USR register is the status register for the UART,
which can be read by the program to determine the
present status of the UART. All flags within the USR
register are read only.
Further explanation on each of the flags is given below:
¨
¨
¨
TXIF
The TXIF flag is the transmit data register empty
flag. When this read only flag is ²0² it indicates that
the character is not transferred to the transmit shift
registers. When the flag is ²1² it indicates that the
transmit shift register has received a character from
the TXR data register. The TXIF flag is cleared by
reading the UART status register (USR) with TXIF
set and then writing to the TXR data register. Note
that when the TXEN bit is set, the TXIF flag bit will
also be set since the transmit buffer is not yet full.
TIDLE
The TIDLE flag is known as the transmission complete flag. When this read only flag is ²0² it indicates
that a transmission is in progress. This flag will be
set to ²1² when the TXIF flag is ²1² and when there
is no transmit data, or break character being transmitted. When TIDLE is ²1² the TX pin becomes idle.
The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character,
or a break is queued and ready to be sent.
RXIF
The RXIF flag is the receive register status flag.
When this read only flag is ²0² it indicates that the
RXR read data register is empty. When the flag is
²1² it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt
is generated if RIE=1 in the UCR2 register. If one or
more errors are detected in the received word, the
appropriate receive-related flags NF, FERR, and/or
PERR are set within the same clock cycle. The
b 7
P E R R
¨
RIDLE
The RIDLE flag is the receiver status flag. When this
read only flag is ²0² it indicates that the receiver is
between the initial detection of the start bit and the
completion of the stop bit. When the flag is ²1² it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next
start bit, the RIDLE bit is ²1² indicating that the
UART is idle.
¨
OERR
The OERR flag is the overrun error flag, which indicates when the receiver buffer has overflowed.
When this read only flag is ²0² there is no overrun error. When the flag is ²1² an overrun error occurs
which will inhibit further transfers to the RXR receive
data register. The flag is cleared by a software sequence, which is a read to the status register USR
followed by an access to the RXR data register.
¨
FERR
The FERR flag is the framing error flag. When this
read only flag is ²0² it indicates no framing error.
When the flag is ²1² it indicates that a framing error
has been detected for the current character. The
flag can also be cleared by a software sequence
which will involve a read to the USR status register
followed by an access to the RXR data register.
¨
NF
The NF flag is the noise flag. When this read only
flag is ²0² it indicates a no noise condition. When
the flag is ²1² it indicates that the UART has detected noise on the receiver input. The NF flag is set
during the same cycle as the RXIF flag but will not
be set in the case of an overrun. The NF flag can be
cleared by a software sequence which will involve a
read to the USR status register, followed by an access to the RXR data register.
b 0
N F
F E R R
O E R R
R ID L E
R X IF
T ID L E
T X IF
U S R
R e g is te r
T r a n s m it d a ta r e g is te r e m p ty
1 : c h a r a c te r tr a n s fe r r e d to tr a n s m it s h ift r e g is te r
0 : c h a r a c te r n o t tr a n s fe r r e d to tr a n s m it s h ift r e g is te r
T r a n s m is s io n id le
1 : n o tr a n s m is s io n in p r o g r e s s
0 : tr a n s m is s io n in p r o g r e s s
R e c e iv e R X R r e g is te r s ta tu s
1 : R X R r e g is te r h a s a v a ila b le d a ta
0 : R X R r e g is te r is e m p ty
R e c e iv e r s ta tu s
1 : r e c e iv e r is id le
0 : d a ta b e in g r e c e iv e d
O v e rru n e rro r
1 : o v e rru n e rro r d e te c te d
0 : n o o v e rru n e rro r d e te c te d
F r a m in g e r r o r fla g
1 : fr a m in g e r r o r d e te c te d
0 : n o fr a m in g e r r o r
N o is e fla g
1 : n o is e d e te c te d
0 : n o n o is e d e te c te d
P a r ity e r r o r fla g
1 : p a r ity e r r o r d e te c te d
0 : n o p a r ity e r r o r d e te c te d
Rev. 1.10
36
May 27, 2010
HT46RU67/HT46CU67
¨
used, if the bit is equal to ²0² then only one stop bit is
used.
PERR
The PERR flag is the parity error flag. When this
read only flag is ²0² it indicates that a parity error
has not been detected. When the flag is ²1² it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode
(odd or even) is selected. The flag can also be
cleared by a software sequence which involves a
read to the USR status register, followed by an access to the RXR data register.
· UCR1 register
The UCR1 register together with the UCR2 register
are the two UART control registers that are used to set
the various options for the UART function, such as
overall on/off control, parity control, data transfer bit
length etc.
Further explanation on each of the bits is given below:
¨
TX8
This bit is only used if 9-bit data transfers are used,
in which case this bit location will store the 9th bit of
the transmitted data, known as TX8. The BNO bit is
used to determine whether data transfers are in
8-bit or 9-bit format.
¨
RX8
This bit is only used if 9-bit data transfers are used,
in which case this bit location will store the 9th bit of
the received data, known as RX8. The BNO bit is
used to determine whether data transfers are in
8-bit or 9-bit format.
¨
TXBRK
The TXBRK bit is the Transmit Break Character bit.
When this bit is ²0² there are no break characters
and the TX pin operates normally. When the bit is
²1² there are transmit break characters and the
transmitter will send logic zeros. When equal to ²1²
after the buffered data has been transmitted, the
transmitter output is held low for a minimum of a
13-bit length and until the TXBRK bit is reset.
¨
STOPS
This bit determines if one or two stop bits are to be
used. When this bit is equal to ²1² two stop bits are
b 7
U A R T E N
¨
PRT
This is the parity type selection bit. When this bit is
equal to ²1² odd parity will be selected, if the bit is
equal to ²0² then even parity will be selected.
¨
PREN
This is parity enable bit. When this bit is equal to ²1²
the parity function will be enabled, if the bit is equal
to ²0² then the parity function will be disabled.
¨
BNO
This bit is used to select the data length format,
which can have a choice of either 8-bits or 9-bits. If
this bit is equal to ²1² then a 9-bit data length will be
selected, if the bit is equal to ²0² then an 8-bit data
length will be selected. If 9-bit data length is selected then bits RX8 and TX8 will be used to store
the 9th bit of the received and transmitted data respectively.
¨
UARTEN
The UARTEN bit is the UART enable bit. When the
bit is ²0² the UART will be disabled and the RX and
TX pins will function as General Purpose I/O pins.
When the bit is ²1² the UART will be enabled and
the TX and RX pins will function as defined by the
TXEN and RXEN control bits. When the UART is
disabled it will empty the buffer so any character remaining in the buffer will be discarded. In addition,
the baud rate counter value will be reset. When the
UART is disabled, all error and status flags will be
reset. The TXEN, RXEN, TXBRK, RXIF, OERR,
FERR, PERR, and NF bits will be cleared, while the
TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2, and BRG registers will remain unaffected. If the UART is active and the
UARTEN bit is cleared, all pending transmissions
and receptions will be terminated and the module
will be reset as defined above. When the UART is
re-enabled it will restart in the same configuration.
b 0
B N O
P R E N
P R T
S T O P S
T X B R K
R X 8
T X 8
U C R 1 R e g is te r
T r a n s m it d a ta b it 8 ( w r ite o n ly )
R e c e iv e d a ta b it 8 ( r e a d o n ly )
T r a n s m it b r e a k c h a r a c te r
1 : tr a n s m it b r e a k c h a r a c te r s
0 : n o b re a k c h a ra c te rs
D e fin e s th e n u m b e r o f s to p b its
1 : tw o s to p b its
0 : o n e s to p b it
P a r ity ty p e b it
1 : o d d p a r ity fo r p a r ity g e n e r a to r
0 : e v e n p a r ity fo r p a r ity g e n e r a to r
P a r ity e n a b le b it
1 : p a r ity fu n c tio n e n a b le d
0 : p a r ity fu n c tio n d is a b le d
N u m b e r o f d a ta tr a n s fe r b its
1 : 9 - b it d a ta tr a n s fe r
0 : 8 - b it d a ta tr a n s fe r
U A R T e n a b le b it
1 : e n a b le U A R T , T X & R X p in s a s U A R T p in s
0 : d is a b le U A R T , T X & R X p in s a s I/O p o r t p in s
Rev. 1.10
37
May 27, 2010
HT46RU67/HT46CU67
· UCR2 register
to ²0² and if the MCU is in the Power Down Mode,
any edge transitions on the RX pin will not wake-up
the device.
The UCR2 register is the second of the two UART
control registers and serves several purposes. One of
its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver
as well as enabling the various UART interrupt
sources. The register also serves to control the baud
rate speed, receiver wake-up enable and the address
detect enable.
Further explanation on each of the bits is given below:
¨
ADDEN
The ADDEN bit is the address detect mode bit.
When this bit is ²1² the address detect mode is enabled. When this occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which
corresponds to RX8 if BNO=1, has a value of ²1²
then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be
generated each time the received word has the address bit set, which is the 8 or 9 bit depending on the
value of BNO. If the address bit is ²0² an interrupt
will not be generated, and the received data will be
discarded.
¨
TEIE
This bit enables or disables the transmitter empty
interrupt. If this bit is equal to ²1² when the transmitter empty TXIF flag is set, due to a transmitter
empty condition, the UART interrupt request flag
will be set. If this bit is equal to ²0² the UART interrupt request flag will not be influenced by the condition of the TXIF flag.
¨
¨
TIIE
This bit enables or disables the transmitter idle interrupt. If this bit is equal to ²1² when the transmitter
idle TIDLE flag is set, the UART interrupt request
flag will be set. If this bit is equal to ²0² the UART interrupt request flag will not be influenced by the
condition of the TIDLE flag.
BRGH
The BRGH bit selects the high or low speed mode
of the Baud Rate Generator. This bit, together with
the value placed in the BRG register, controls the
Baud Rate of the UART. If this bit is equal to ²1² the
high speed mode is selected. If the bit is equal to ²0²
the low speed mode is selected.
¨
¨
RIE
This bit enables or disables the receiver interrupt. If
this bit is equal to ²1² when the receiver overrun
OERR flag or receive data available RXIF flag is
set, the UART interrupt request flag will be set. If
this bit is equal to ²0² the UART interrupt will not be
influenced by the condition of the OERR or RXIF
flags.
¨
WAKE
This bit enables or disables the receiver wake-up
function. If this bit is equal to ²1² and if the MCU is in
the Power Down Mode, a low going edge on the RX
input pin will wake-up the device. If this bit is equal
RXEN
The RXEN bit is the Receiver Enable Bit. When this
bit is equal to ²0² the receiver will be disabled with
any pending data receptions being aborted. In addition the buffer will be reset. In this situation the RX
pin can be used as a general purpose I/O pin. If the
RXEN bit is equal to ²1² the receiver will be enabled
and if the UARTEN bit is equal to ²1² the RX pin will
be controlled by the UART. Clearing the RXEN bit
during a transmission will cause the data reception
to be aborted and will reset the receiver. If this occurs, the RX pin can be used as a general purpose
I/O pin.
b 7
T X E N
b 0
R X E N
B R G H
A D D E N
W A K E
R IE
T IIE
T E IE
U C R 2 R e g is te r
T r a n s m itte r e m p ty in te r r u p t e n a b le
1 : T X IF in te r r u p t r e q u e s t e n a b le
0 : T X IF in te r r u p t r e q u e s t d is a b le
T r a n s m itte r id le in te r r u p t e n a b le
1 : T ID L E in te r r u p t r e q u e s t e n a b le
0 : T ID L E in te r r u p t r e q u e s t d is a b le
R e c e iv e r in te r r u p t e n a b le
1 : R X IF in te r r u p t r e q u e s t e n a b le
0 : R X IF in te r r u p t r e q u e s t d is a b le
D e fin e s th e R X w a k e u p e n a b le
1 : R X w a k e u p e n a b le ( fa llin g e d g e )
0 : R X w a k e u p d is a b le
A d d re s s d e te c t m o d e
1 : e n a b le
0 : d is a b le
H ig h b a u d r a te s e le c t b it
1 : h ig h s p e e d
0 : lo w s p e e d
R e c e iv e r e n a b le b it
1 : r e c e iv e r e n a b le
0 : r e c e iv e r d is a b le
T r a n s m itte r e n a b le b it
1 : tr a n s m itte r e n a b le
0 : tr a n s m itte r d is a b le
Rev. 1.10
38
May 27, 2010
HT46RU67/HT46CU67
¨
TXEN
The TXEN bit is the Transmitter Enable Bit. When
this bit is equal to ²0² the transmitter will be disabled
with any pending transmissions being aborted. In
addition the buffer will be reset. In this situation the
TX pin can be used as a general purpose I/O pin. If
the TXEN bit is equal to ²1² the transmitter will be
enabled and if the UARTEN bit is equal to ²1² the
TX pin will be controlled by the UART. Clearing the
TXEN bit during a transmission will cause the transmission to be aborted and will reset the transmitter.
If this occurs, the TX pin can be used as a general
purpose I/O pin.
By programming the BRGH bit which allows selection
of the related formula and programming the required
value in the BRG register, the required baud rate can
be setup. Note that because the actual baud rate is
determined using a discrete value, N, placed in the
BRG register, there will be an error associated between the actual and requested value. The following
example shows how the BRG register value N and the
error value can be calculated.
Calculating the register and error values
For a clock frequency of 4MHz, and with BRGH set to
²0² determine the BRG register value N, the actual
baud rate and the error value for a desired baud rate
of 4800.
From the above table the desired baud rate BR
fSYS
=
[64 (N + 1)]
fSYS
Re-arranging this equation gives N =
-1
(BRx64)
4000000
- 1 = 12.0208
Giving a value for N =
(4800x 64)
· Baud rate generator
To setup the speed of the serial data communication,
the UART function contains its own dedicated baud
rate generator. The baud rate is controlled by its own
internal free running 8-bit timer, the period of which is
determined by two factors. The first of these is the
value placed in the BRG register and the second is the
value of the BRGH bit within the UCR2 control register. The BRGH bit decides, if the baud rate generator
is to be used in a high speed mode or low speed
mode, which in turn determines the formula that is
used to calculate the baud rate. The value in the BRG
register determines the division factor, N, which is
used in the following baud rate calculation formula.
Note that N is the decimal value placed in the BRG
register and has a range of between 0 and 255.
UCR2 BRGH Bit
Baud Rate
0
1
fSYS
[64 (N + 1)]
fSYS
[16 (N + 1)]
To obtain the closest value, a decimal value of 12
should be placed into the BRG register. This gives an
actual or calculated baud rate value of
4000000
= 4808
BR =
[64(12 + 1)]
Therefore the error is equal to
4 8 0 8
4 8 0 0
4 8 0 0
= 0.16%
The following tables show actual values of baud rate and error values for the two values of BRGH.
Baud Rates for BRGH=0
Baud Rate
K/BPS
fSYS=4MHz
fSYS=3.579545MHz
BRG
Kbaud
Error (%)
BRG
Kbaud
Error (%)
0.3
207
0.300
0.00
185
0.300
0.00
1.2
51
1.202
0.16
46
1.19
-0.83
2.4
25
2.404
0.16
22
2.432
1.32
4.8
12
4.808
0.16
11
4.661
-2.9
9.6
6
8.929
-6.99
5
9.321
-2.9
19.2
2
20.83
8.51
2
18.643
-2.9
38.4
1
¾
¾
1
¾
¾
57.6
0
62.5
8.51
0
55.93
-2.9
115.2
¾
¾
¾
¾
¾
¾
Baud Rates and Error Values for BRGH = 0
Rev. 1.10
39
May 27, 2010
HT46RU67/HT46CU67
Baud Rates for BRGH=1
Baud Rate
K/BPS
fSYS=4MHz
fSYS=3.579545MHz
BRG
Kbaud
Error (%)
BRG
Kbaud
Error (%)
0.3
¾
¾
¾
¾
¾
¾
1.2
207
1.202
0.16
185
1.203
0.23
2.4
103
2.404
0.16
92
2.406
0.23
4.8
51
4.808
0.16
46
4.76
-0.83
9.6
25
9.615
0.16
22
9.727
1.32
19.2
12
19.231
0.16
11
18.643
-2.9
38.4
6
35.714
-6.99
5
37.286
-2.9
57.6
3
62.5
8.51
3
55.930
-2.9
115.2
1
125
8.51
1
111.86
-2.9
250
0
250
0
¾
¾
¾
Baud Rates and Error Values for BRGH = 1
· Setting up and controlling the UART
¨
¨
Clearing the UARTEN bit will disable the TX and RX
pins and allow these two pins to be used as normal
I/O pins. When the UART function is disabled the
buffer will be reset to an empty condition, at the
same time discarding any remaining residual data.
Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF,
OERR, FERR, PERR and NF being cleared while
bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG
registers will remain unaffected. If the UARTEN bit
in the UCR1 register is cleared while the UART is
active, then all pending transmissions and receptions will be immediately suspended and the UART
will be reset to a condition as defined above. If the
UART is then subsequently re-enabled, it will restart
again in the same configuration.
Introduction
For data transfer, the UART function utilizes a
non-return-to-zero, more commonly known as
NRZ, format. This is composed of one start bit, eight
or nine data bits, and one or two stop bits. Parity is
supported by the UART hardware, and can be
setup to be even, odd or no parity. For the most
common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as
the default setting, which is the setting at power-on.
The number of data bits and stop bits, along with the
parity, are setup by programming the corresponding
BNO, PRT, PREN, and STOPS bits in the UCR1
register. The baud rate used to transmit and receive
data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received
LSB first. Although the UART¢s transmitter and receiver are functionally independent, they both use
the same data format and baud rate. In all cases
stop bits will be used for data transmission.
¨
Enabling/disabling the UART
The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1
register. As the UART transmit and receive pins, TX
and RX respectively, are pin-shared with normal I/O
pins, one of the basic functions of the UARTEN control bit is to control the UART function of these two
pins. If the UARTEN, TXEN and RXEN bits are set,
then these two I/O pins will be setup as a TX output
pin and an RX input pin respectively, in effect disabling the normal I/O pin function. If no data is being
transmitted on the TX pin then it will default to a
logic high value.
Rev. 1.10
40
Data, parity and stop bit selection
The format of the data to be transferred, is composed of various factors such as data bit length,
parity on/off, parity type, address bits and the number of stop bits. These factors are determined by
the setup of various bits within the UCR1 register.
The BNO bit controls the number of data bits which
can be set to either 8 or 9, the PRT bit controls the
choice of odd or even parity, the PREN bit controls
the parity on/off function and the STOPS bit decides
whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an
address character. The number of stop bits, which
can be either one or two, is independent of the data
length.
May 27, 2010
HT46RU67/HT46CU67
Start
Bit
Data
Bits
Address
Bits
Parity
Bits
Stop
Bit
¨
Example of 8-bit Data Formats
1
8
0
0
1
1
7
0
1
1
7
1
0
1
1
1
Example of 9-bit Data Formats
1
9
0
0
1
1
8
0
1
1
1
8
11
0
1
Transmitting data
When the UART is transmitting data, the data is
shifted on the TX pin from the shift register, with the
least significant bit first. In the transmit mode, the
TXR register forms a buffer between the internal
bus and the transmitter shift register. It should be
noted that if 9-bit data format has been selected,
then the MSB will be taken from the TX8 bit in the
UCR1 register. The steps to initiate a data transfer
can be summarized as follows:
-
Make the correct selection of the BNO, PRT,
PREN and STOPS bits to define the required
word length, parity type and number of stop bits.
-
Setup the BRG register to select the desired baud
rate.
-
Set the TXEN bit to ensure that the TX pin is used
as a UART transmitter pin and not as an I/O pin.
-
Access the USR register and write the data that is
to be transmitted into the TXR register. Note that
this step will clear the TXIF bit.
-
This sequence of events can now be repeated to
send additional data.
Transmitter Receiver Data Format
The following diagram shows the transmit and receive
waveforms for both 8-bit and 9-bit data formats.
· UART transmitter
Data word lengths of either 8 or 9 bits, can be selected
by programming the BNO bit in the UCR1 register.
When BNO bit is set, the word length will be set to 9
bits. In this case the 9th bit, which is the MSB, needs
to be stored in the TX8 bit in the UCR1 register. At the
transmitter core lies the Transmitter Shift Register,
more commonly known as the TSR, whose data is obtained from the transmit data register, which is known
as the TXR register. The data to be transmitted is
loaded into this TXR register by the application program. The TSR register is not written to with new data
until the stop bit from the previous transmission has
been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data
from the TXR register, if it is available. It should be
noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area
and as such is not available to the application program
for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN
bit is set, but the data will not be transmitted until the
TXR register has been loaded with data and the baud
rate generator has defined a shift clock source. However, the transmission can also be initiated by first
loading data into the TXR register, after which the
TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a
transfer to the TXR register will result in an immediate
transfer to the TSR. If during a transmission the TXEN
bit is cleared, the transmission will immediately cease
and the transmitter will be reset. The TX output pin will
then return to having a normal general purpose I/O pin
function.
It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the
following software sequence:
1. A USR register access
2. A TXR register write execution
The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is
empty and that other data can now be written into
the TXR register without overwriting the previous
data. If the TEIE bit is set then the TXIF flag will generate an interrupt.
During a data transmission, a write instruction to the
TXR register will place the data into the TXR register, which will be copied to the shift register at the
end of the present transmission. When there is no
data transmission in progress, a write instruction to
the TXR register will place the data directly into the
shift register, resulting in the commencement of
data transmission, and the TXIF bit being immediately set. When a frame transmission is complete,
which happens after stop bits are sent or after the
break frame, the TIDLE bit will be set. To clear the
TIDLE bit the following software sequence is used:
1. A USR register access
2. A TXR register write execution
Note that both the TXIF and TIDLE bits are cleared
by the same software sequence.
P a r ity B it
S ta r t B it
B it 0
B it 1
B it 2
B it 3
B it 4
B it 5
B it 6
B it 7
S to p B it
N e x t
S ta rt
B it
8 -B it D a ta F o r m a t
P a r ity B it
S ta r t B it
B it 0
B it 1
B it 2
B it 3
B it 4
B it 5
B it 6
B it 7
B it 8
S to p B it
N e x t
S ta rt
B it
9 -B it D a ta F o r m a t
Rev. 1.10
41
May 27, 2010
HT46RU67/HT46CU67
¨
-
Transmit break
If the TXBRK bit is set then break characters will be
sent on the next transmission. Break character
transmission consists of a start bit, followed by 13´
N ¢0¢ bits and stop bits, where N=1, 2, etc. If a break
character is to be transmitted then the TXBRK bit
must be first set by the application program, then
cleared to generate the stop bits. Transmitting a
break character will not generate a transmit interrupt. Note that a break condition length is at least 13
bits long. If the TXBRK bit is continually kept at a
logic high level then the transmitter circuitry will
transmit continuous break characters. After the application program has cleared the TXBRK bit, the
transmitter will finish transmitting the last break
character and subsequently send out one or two
stop bits. The automatic logic highs at the end of the
last break character will ensure that the start bit of
the next frame is recognized.
At this point the receiver will be enabled which will
begin to look for a start bit.
When a character is received the following sequence of events will occur:
- The RXIF bit in the USR register will be set when
RXR register has data available, at least one
more character can be read.
Introduction
The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length
will be set to 9 bits with the MSB being stored in the
RX8 bit of the UCR1 register. At the receiver core lies
the Receive Serial Shift Register, commonly known
as the RSR. The data which is received on the RX
external input pin, is sent to the data recovery block.
The data recovery block operating speed is 16 times
that of the baud rate, while the main receive serial
shifter operates at the baud rate. After the RX pin is
sampled for the stop bit, the received data in RSR is
transferred to the receive data register, if the register
is empty. The data which is received on the external
RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been
placed onto the RX pin. It should be noted that the
RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as
such is not available to the application program for
direct read/write operations.
¨
Receiving data
When the UART receiver is receiving data, the data
is serially shifted in on the external RX input pin,
LSB first. In the read mode, the RXR register forms
a buffer between the internal bus and the receiver
shift register. The RXR register is a two byte deep
FIFO data buffer, where two bytes can be held in the
FIFO while a third byte can continue to be received.
Note that the application program must ensure that
the data is read from RXR before the third byte has
been completely shifted in, otherwise this third byte
will be discarded and an overrun error OERR will be
subsequently indicated. The steps to initiate a data
transfer can be summarized as follows:
-
Make the correct selection of BNO, PRT, PREN
and STOPS bits to define the word length, parity
type and number of stop bits.
-
Setup the BRG register to select the desired baud
rate.
Rev. 1.10
-
When the contents of the shift register have been
transferred to the RXR register, then if the RIE bit
is set, an interrupt will be generated.
-
If during reception, a frame error, noise error, parity error, or an overrun error has been detected,
then the error flags can be set.
The RXIF bit can be cleared using the following software sequence:
1. A USR register access
2. An RXR register read execution
· UART receiver
¨
Set the RXEN bit to ensure that the RX pin is used
as a UART receiver pin and not as an I/O pin.
¨
¨
42
Receive break
Any break character received by the UART will be
managed as a framing error. The receiver will count
and expect a certain number of bit times as specified by the values programmed into the BNO and
STOPS bits. If the break is much longer than 13 bit
times, the reception will be considered as complete
after the number of bit times specified by BNO and
STOPS. The RXIF bit is set, FERR is set, zeros are
loaded into the receive data register, interrupts are
generated if appropriate and the RIDLE bit is set. If
a long break signal has been detected and the receiver has received a start bit, the data bits and the
invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking
for the next start bit. The receiver will not make the
assumption that the break condition on the line is
the next start bit. A break is regarded as a character
that contains only zeros with the FERR flag set. The
break character will be loaded into the buffer and no
further data will be received until stop bits are received. It should be noted that the RIDLE read only
flag will go high when the stop bits have not yet
been received. The reception of a break character
on the UART registers will result in the following:
-
The framing error flag, FERR, will be set.
-
The receive data register, RXR, will be cleared.
-
The OERR, NF, PERR, RIDLE or RXIF flags will
possibly be set.
Idle status
When the receiver is reading data, which means it
will be in between the detection of a start bit and the
reading of a stop bit, the receiver status flag in the
USR register, otherwise known as the RIDLE flag,
will have a zero value. In between the reception of a
stop bit and the detection of the next start bit, the
RIDLE flag will have a high value, which indicates
the receiver is in an idle condition.
May 27, 2010
HT46RU67/HT46CU67
¨
Receiver interrupt
The read only receive interrupt flag RXIF in the USR
register is set by an edge generated by the receiver.
An interrupt is generated if RIE=1, when a word is
transferred from the Receive Shift Register, RSR, to
the Receive Data Register, RXR. An overrun error
can also generate an interrupt if RIE=1.
rises at the same time as the RXIF bit which itself
generates an interrupt.
Note that the NF flag is reset by a USR register read
operation followed by an RXR register read
operation.
¨
Framing Error - FERR Flag
The read only framing error flag, FERR, in the USR
register, is set if a zero is detected instead of stop
bits. If two stop bits are selected, both stop bits must
be high, otherwise the FERR flag will be set. The
FERR flag is buffered along with the received data
and is cleared on any reset.
¨
Parity Error - PERR Flag
The read only parity error flag, PERR, in the USR
register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity
is enabled, PREN = 1, and if the parity type, odd or
even is selected. The read only PERR flag is buffered along with the received data bytes. It is
cleared on any reset. It should be noted that the
FERR and PERR flags are buffered along with the
corresponding word and should be read before
reading the data word.
· Managing receiver errors
Several types of reception errors can occur within the
UART module, the following section describes the
various types and how they are managed by the
UART.
¨
Overrun Error - OERR flag
The RXR register is composed of a two byte deep
FIFO data buffer, where two bytes can be held in the
FIFO register, while a third byte can continue to be
received. Before this third byte has been entirely
shifted in, the data should be read from the RXR
register. If this is not done, the overrun error flag
OERR will be consequently indicated.
In the event of an overrun error occurring, the
following will happen:
-
The OERR flag in the USR register will be set.
-
The RXR contents will not be lost.
-
The shift register will be overwritten.
· UART interrupt scheme
The UART internal function possesses its own internal interrupt and independent interrupt vector. Several
individual UART conditions can generate an internal
UART interrupt. These conditions are, a transmitter
data register empty, transmitter idle, receiver data
available, receiver overrun, address detect and an RX
pin wake-up. When any of these conditions are created, if the UART interrupt is enabled and the stack is
not full, the program will jump to the UART interrupt
vector where it can be serviced before returning to the
main program. Four of these conditions, have a corresponding USR register flag, which will generate a
UART interrupt if its associated interrupt enable flag in
the UCR2 register is set. The two transmitter interrupt
conditions have their own corresponding enable bits,
-
An interrupt will be generated if the RIE bit is set.
The OERR flag can be cleared by an access to the
USR register followed by a read to the RXR register.
¨
Noise Error - NF Flag
Over-sampling is used for data recovery to identify
valid incoming data and noise. If noise is detected
within a frame the following will occur:
-
The read only noise flag, NF, in the USR register
will be set on the rising edge of the RXIF bit.
-
Data will be transferred from the Shift register to
the RXR register.
-
No interrupt will be generated. However this bit
U C R 2 R e g is te r
U S R R e g is te r
0
T E IE
T r a n s m itte r E m p ty
F la g T X IF
1
IN T C 1
R e g is te r
U A R T In te rru p t
R e q u e s t F la g
U R F
0
T IIE
T r a n s m itte r Id le
F la g T ID L E
1
R e c e iv e r O v e r r u n
F la g O E R R
R e c e iv e r D a ta
A v a ila b le R X IF
E M I
0
R IE
O R
E U R I
IN T C 0
R e g is te r
1
0
A D D E N
1
0
1
R X P in
W a k e -u p
0
W A K E
R X 7 if B N O = 0
R X 8 if B N O = 1
1
U C R 2 R e g is te r
UART Interrupt Scheme
Rev. 1.10
43
May 27, 2010
HT46RU67/HT46CU67
mode is enabled, then to ensure correct operation, the
parity function should be disabled by resetting the parity enable bit to zero.
while the two receiver interrupt conditions have a
shared enable bit. These enable bits can be used to
mask out individual UART interrupt sources.
The address detect condition, which is also a UART
interrupt source, does not have an associated flag,
but will generate a UART interrupt when an address
detect condition occurs if its function is enabled by
setting the ADDEN bit in the UCR2 register. An RX pin
wake-up, which is also a UART interrupt source, does
not have an associated flag, but will generate a UART
interrupt if the microcontroller is woken up by a low
going edge on the RX pin, if the WAKE and RIE bits in
the UCR2 register are set. Note that in the event of an
RX wake-up interrupt occurring, there will be a delay
of 1024 system clock cycles before the system
resumes normal operation.
Note that the USR register flags are read only and
cannot be cleared or set by the application program,
neither will they be cleared when the program jumps
to the corresponding interrupt servicing routine, as is
the case for some of the other interrupts. The flags will
be cleared automatically when certain actions are
taken by the UART, the details of which are given in
the UART register section. The overall UART interrupt
can be disabled or enabled by the EURI bit in the
INTC1 interrupt control register to prevent a UART
interrupt from occurring.
ADDEN
0
1
0
Ö
1
Ö
0
X
1
Ö
ADDEN Bit Function
· UART operation in power down mode
When the MCU is in the Power Down Mode the UART
will cease to function. When the device enters the
Power Down Mode, all clock sources to the module
are shutdown. If the MCU enters the Power Down
Mode while a transmission is still in progress, then the
transmission will be terminated and the external TX
transmit pin will be forced to a logic high level. In a
similar way, if the MCU enters the Power Down Mode
while receiving data, then the reception of data will
likewise be terminated. When the MCU enters the
Power Down Mode, note that the USR, UCR1, UCR2,
transmit and receive registers, as well as the BRG
register will not be affected.
The UART function contains a receiver RX pin
wake-up function, which is enabled or disabled by the
WAKE bit in the UCR2 register. If this bit, along with
the UART enable bit, UARTEN, the receiver enable
bit, RXEN and the receiver interrupt bit, RIE, are all
set before the MCU enters the Power Down Mode,
then a falling edge on the RX pin will wake-up the
MCU from the Power Down Mode. Note that as it
takes 1024 system clock cycles after a wake-up, before normal microcontroller operation resumes, any
data received during this time on the RX pin will be ignored.
For a UART wake-up interrupt to occur, in addition to
the bits for the wake-up being set, the global interrupt
enable bit, EMI, and the UART interrupt enable bit,
EURI must also be set. If these two bits are not set
then only a wake up event will occur and no interrupt
will be generated. Note also that as it takes 1024 system clock cycles after a wake-up before normal
microcontroller resumes, the UART interrupt will not
be generated until after this time has elapsed.
· Address detect mode
Setting the Address Detect Mode bit, ADDEN, in the
UCR2 register, enables this special mode. If this bit is
enabled then an additional qualifier will be placed on
the generation of a Receiver Data Available interrupt,
which is requested by the RXIF flag. If the ADDEN bit
is enabled, then when data is available, an interrupt
will only be generated, if the highest received bit has a
high value. Note that the EURI and EMI interrupt enable bits must also be enabled for correct interrupt
generation. This highest address bit is the 9th bit if
BNO=1 or the 8th bit if BNO=0. If this bit is high, then
the received word will be defined as an address rather
than data. A Data Available interrupt will be generated
every time the last bit of the received word is set. If the
ADDEN bit is not enabled, then a Receiver Data Available interrupt will be generated each time the RXIF
flag is set, irrespective of the data last bit status. The
address detect mode and parity enable are mutually
exclusive functions. Therefore if the address detect
Rev. 1.10
Bit 9 if BNO=1, UART Interrupt
Bit 8 if BNO=0
Generated
44
May 27, 2010
HT46RU67/HT46CU67
Serial Interface
Serial interface function has four basic signals included. They are SDI (serial data input), SDO (serial data output), SCK
(serial clock) and SCS (slave select pin).
Note: SCS can be named SCS in the design note.
S C S
C L K
S D I
S D O
S B C R
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
C K S
M 1
M 0
S B E N
M L S
C S E N
W C O L
T R F
D E F A U L T
: S E R IA L B U S
0
1
1
0
0
0
0
0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
S B D R
U
U
U
U
U
U
U
U
D A T A R E G IS T E R
D E F A U L T
S B D R
S B C R
C O N T R O L R E G IS T E R
: S E R IA L B U S
N o te : "U " m e a n s u n c h a n g e d .
¨
Two registers (SBCR and SBDR) unique to serial interface provide control, status, and data storage.
· SBCR: Serial bus control register
Bit7 (CKS) clock source selection: fSIO=fSYS/4, select
as 0
Bit6 (M1), Bit5 (M0) master/slave mode and baud rate
selection
M1, M0: 00 ® MASTER MODE, BAUD RATE= fSIO
01 ® MASTER MODE, BAUD RATE= fSIO/4
10 ® MASTER MODE, BAUD RATE= fSIO/16
11 ® SLAVE MODE
· Bit4 (SBEN) ® serial bus enable/disable (1/0)
¨
· SBDR: Serial bus data register
Enable: (SCS dependent on CSEN bit)
Disable ® enable: SCK, SDI, SDO, SCS= 0
(SCKB= ²0²) and waiting for writing data to SBDR
(TXRX buffer)
Master mode: write data to SBDR (TXRX buffer)
start transmission/reception automatically
Master mode: when data has been transferred, set
TRF
Slave mode: when an SCK (and SCS dependent on
CSEN) is received, data in TXRX buffer is
shifted-out and data on SDI is shifted-in.
Rev. 1.10
Disable: SCK (SCK), SDI, SDO, SCS floating
Bit3 (MLS) ® MSB or LSB (1/0) shift first control bit
Bit2 (CSEN) ® serial bus selection signal enable/disable (SCS), when CSEN=0, SCSB is floating.
Bit1 (WCOL) ® this bit is set to 1 if data is written to
SBDR (TXRX buffer) when data is transferred,
writing will be ignored if data is written to SBDR
(TXRX buffer) when data is transferred.
Bit0 (TRF) ® data transferred or data received
used to generate an interrupt.
Note: data receiving is still working when the MCU
enters HALT mode.
Data written to SBDR ® write data to TXRX buffer
only
Data read from SBDR ® read from SBDR only
Operating Mode description:
Master transmitter: clock sending and data I/O started
by writing SBDR
Master clock sending started by writing SBDR
Slave transmitter: data I/O started by clock received
Slave receiver: data I/O started by clock received
45
May 27, 2010
HT46RU67/HT46CU67
Clock polarity= rising (CLK) or falling (CLK): 1 or 0 (mask option)
Modes
Operations
1.
Select CKS and select M1, M0 = 00,01,10
2.
Select CSEN, MLS (the same as the slave)
3.
Set SBEN
4.
Writing data to SBDR ® data is stored in TXRX buffer ® output CLK (and SCS) signals ® go to
step 5 ® (SIO internal operation ® data stored in TXRX buffer, and SDI data is shifted into TXRX
buffer ® data transferred, data in TXRX buffer is latched into SBDR)
Master
5.
Check WCOL; WCOL= 1 ® clear WCOL and go to step 4; WCOL= 0 ® go to step 6
6.
Check TRF or waiting for SBI (serial bus interrupt)
7.
Read data from SBDR
8.
Clear TRF
9.
Go to step 4
1.
CKS don¢t care and select M1, M0= 11
2.
Select CSEN, MLS (the same as the master)
3.
Set SBEN
4.
Writing data to SBDR ® data is stored in TXRX buffer ® waiting for master clock signal (and SCS):
CLK ® go to step 5 ® (SIO internal operations ® CLK (SCS) received ® output data in TXRX
buffer and SDI data is shifted into TXRX buffer ® data transferred, data in TXRX buffer is latched
into SBDR)
5.
Check WCOL; WCOL= 1 ® clear WCOL, go to step 4; WCOL= 0 ® go to step 6
6.
Check TRF or wait for SBI (serial bus interrupt)
7.
Read data from SBDR
8.
9.
Clear TRF
Go to step 4
Slave
Operation of Serial Interface
WCOL: master/slave mode, set while writing to SBDR
when data is transferring (transmitting or receiving) and
this writing will then be ignored. WCOL function can be
enabled/disabled by mask option. WCOL is set by SIO
and cleared by users.
SCS pin (master and slave) should be floating. CSEN
has 2 options: CSEN mask option is used to enable/disable software CSEN function. If CSEN mask option is
disabled, the software CSEN is always disabled. If
CSEN mask option is enabled, software CSEN function
can be used.
Data transmission and reception are still working when
the MCU enters the HALT mode.
SBEN= 1 ® serial bus standby; SCS (CSEN= 1) = 1;
SCS= floating (CSEN= 0); SDI= floating; SDO= 1; master CLK= output 1/0 (dependent on CPOL mask option),
slave CLK= floating
CPOL is used to select the clock polarity of CLK. It is a
mask option.
MLS: MSB or LSB first selection
SBEN= 0 ® serial bus disabled; SCS= SDI= SDO=
CLK= floating
CSEN: chip select function enable/disable, CSEN=1 ®
SCS signal function is active. Master should output SCS
signal before CLK signal is set and slave data transferring should be disabled (or enabled) before (after) SCS
signal is received. CSEN= 0, SCS signal is not needed,
Rev. 1.10
TRF is set by SIO and cleared by users. When data
transfer (transmission and reception) is completed, TRF
is set to generate SBI (serial bus interrupt).
46
May 27, 2010
HT46RU67/HT46CU67
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R
( if p u ll- h ig h e d )
S B E N = C S E N = 1 a n d w r ite d a ta to S B D R
S C S
C L K
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S D I
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S D O
C L K B
S B C R
D e fa u lt
S B D R
D e fa u lt
D 7
C K S
0
D 7
u
D 6
M 1
1
D 6
u
D 5
M 0
1
D 5
u
D 4
S B E N
0
D 4
u
D 3
M L S
0
D 3
u
D 2
C S E N
0
D 2
u
D 1
W C O L
0
D 1
u
D 0
T R F
0
D 0
u
N o te : "u " m e a n s u n c h a n g e d .
D a ta B u s
S B D R
( R e c e iv e d D a ta R e g is te r )
D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
M
S D O
U
X
B u ffe r
S B E N
M L S
M
In te r n a l B a u d R a te C lo c k
a n d , s ta rt
E N
C L K
a n d , s ta rt
C lo c k P o la r ity
S D I
U
X
M
S D O
U
X
T R F
C 0 C 1 C 2
M a s te r o r S la v e
A N D
In te r n a l B u s y F la g
S B E N
a n d , s ta rt
E N
W r ite S B D R
W r ite S B D R
S B E N
W C O L F la g
E n a b le /D is a b le
W r ite S B D R
S C S
M a s te r o r S la v e
S B E N
C S E N
W C O L : s e t b
C S E N : e n a b
1 . m a s te r
2 . s la v e m
S B E N : e n a b
1 . W h e n S
2 . W h e n S
T R F 1 : d a ta
C P O L 1 /0 : c
Rev. 1.10
y S IO c le a r e d b y u s e r s
le /d is a b le c h ip s e le c tio n fu n c tio
m o d e 1 /0 : w ith /w ith o u t S C S B o
o d e 1 /0 : w ith /w ith o u t S C S B in p
le /d is a b le s e r ia l b u s ( 0 : in itia liz
B E N = 0 , a ll s ta tu s fla g s s h o u ld
B E N = 0 , a ll S IO r e la te d fu n c tio
tr a n s m itte d o r r e c e iv e d , 0 : d a ta
lo c k p o la r ity r is in g /fa llin g e d g e
47
n p
u tp
u t
e a
b e
n p
is
: m
in
u t fu n c tio n
c o n tro l fu n
ll s ta tu s fla
in itia liz e d
in s s h o u ld
tr a n s m ittin
a s k o p tio n
c tio n
g s )
s ta y a t flo a tin g s ta te
g o r s till n o t r e c e iv e d
May 27, 2010
HT46RU67/HT46CU67
Options
The following shows the options in the device. All these options should be defined in order to ensure having a proper
functioning system.
Options
OSC type selection.
This option is to determine if an RC or crystal or 32768Hz crystal oscillator is chosen as system clock.
WDT, RTC and time base clock source selection.
There are three types of selections: system clock/4 or RTC OSC or WDT OSC.
WDT enable/disable selection.
WDT can be enabled or disabled by option.
WDT time-out period selection.
There are four types of selection: WDT clock source divided by 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS or
215/fS~216/fS.
CLR WDT times selection.
This option defines the method to clear the WDT by instruction. ²One time² means that the ²CLR WDT² can clear the
WDT. ²Two times² means only if both of the ²CLR WDT1² and ²CLR WDT2² have been executed, only then can the
WDT be cleared.
Time Base time-out period selection.
The Time Base time-out period ranges from clock/212 to clock/215. ²clock² means the clock source selected by options.
Buzzer output frequency selection.
There are eight types of frequency signals for the buzzer output: clock/22 ~ clock/29. ²clock² means the clock source
selected by options.
Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to
wake-up the chip from a HALT by a falling edge (bit option).
Pull-high selection.
This option is to determine whether the pull-high resistance is viable or not in the input mode of the I/O ports. PA, PB,
PC and PD can be independently selected (bit option).
I/O pins share with other function selections.
PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.
PA3/PFD: PA3 can be set as I/O pins or PFD output.
LCD common selection.
There are three types of selections: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4
common is selected, the segment output pin ²SEG46² will be set as a common output.
LCD bias power supply selection.
There are two types of selections: 1/2 bias or 1/3 bias
LCD bias type selection.
This option is to determine what kind of bias is selected, R type or C type (Low or high bias current option).
LCD driver clock frequency selection.
There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. ²fS² stands for the clock source selection by options.
LCD ON/OFF at HALT selection.
LCD Segments as logical output selection, (byte, byte, bit, bit, bit, bit, bit, bit, bit, bit option)
[SEG0~SEG7], [SEG8~SEG15], SEG16, SEG17, SEG18, SEG19, SEG20, SEG21, SEG22, or SEG23
LVR selection.
LVR has enable or disable options
LVD selection.
LVD has enable or disable options
Rev. 1.10
48
May 27, 2010
HT46RU67/HT46CU67
Options
PFD selection.
If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as
the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively.
PWM mode select: (7+1) or (6+2) mode
PD0: level output or PWM0 output
PD1: level output or PWM1 output
PD2: level output or PWM2 output
PD3: level output or PWM3 output
INT0 or INT1 triggering edge selection: disable; high to low; low to high; low to high or high to low.
INT0 trigger source selection.
There are two types of selection: INT0 pin or A/D conversion completed.
Interrupt vector selection.
08H: INT1, 14H: UART or
08H: SIO, 14H: UART or
08H: INT1, 14H: SIO
SIO selection.
SIO has enable a disable options
SIO WCOL selection.
SIO WCOL has enable or disable options.
SIO CSEN selection.
SIO CSEN has enable or disable options.
SIO CPOL selection.
SIO CPOL has enable or disable options.
Rev. 1.10
49
May 27, 2010
HT46RU67/HT46CU67
Application Circuits
V
D D
C O M 0 ~ C O M 2
C O M 3 /S E G 4 6
S E G 0 ~ S E G 4 5
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
L C D
P a n e l
V L C D
L C D
P o w e r S u p p ly
V M A X
L C D
H ig h V o lta g e
R E S
C 1
0 .1 m F
0 .1 m F
C 2
V S S
V 1
0 .1 m F
3 2 7 6 8 H z
V
D D
4 7 0 p F
V 2
O S C 3
O S C 4
~
P D 0 /P W M 0
P D 3 /P W M 3
P D 4 /IN T 0
P D 5 /IN T 1
0 .1 m F
P A 0 /B
P A 1 /B
P A
P A 3 /P F
P A 4 ~ P A
R
O S C
O S C 1
fS
C 1
Z
C 2
D
7
R 1
O S C 2
O S C 2
C r y s ta l/R e s o n a to r
S y s te m O s c illa to r
F o r R 1 , C 1 , C 2 s e e n o te
~
P B 0 /A N 0
P B 7 /A N 7
/4
O S C 1
Z
2
Y S
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
P D 6 /T M R 0
P D 7 /T M R 1
O S C
C ir c u it
O S C 1
O S C 2
P C 0 /T
P C 1 ~
P C
P C
M R
P C
6 /T
7 /R
O S C 1
X
2
X
5
O S C 2
H T 4 6 R U 6 7 /H T 4 6 C U 6 7
O S C
3 2 7 6 8 H z C ry s ta l S y s te m
O s c illa to r
O S C 1 a n d O S C 2 le ft
u n c o n n e c te d
C ir c u it
Note: 1. Crystal/resonator system oscillators
For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For
resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is not
necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator when
VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2 should be
selected in consultation with the crystal/resonator manufacturer specifications.
2. Reset circuit
The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of
the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.
3. For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information.
Rev. 1.10
50
May 27, 2010
HT46RU67/HT46CU67
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 1.10
51
May 27, 2010
HT46RU67/HT46CU67
Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.10
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
52
May 27, 2010
HT46RU67/HT46CU67
Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 1.10
53
May 27, 2010
HT46RU67/HT46CU67
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
Rev. 1.10
54
May 27, 2010
HT46RU67/HT46CU67
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.10
55
May 27, 2010
HT46RU67/HT46CU67
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.10
56
May 27, 2010
HT46RU67/HT46CU67
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.10
57
May 27, 2010
HT46RU67/HT46CU67
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.10
58
May 27, 2010
HT46RU67/HT46CU67
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.10
59
May 27, 2010
HT46RU67/HT46CU67
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.10
60
May 27, 2010
HT46RU67/HT46CU67
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.10
61
May 27, 2010
HT46RU67/HT46CU67
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.10
62
May 27, 2010
HT46RU67/HT46CU67
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.10
63
May 27, 2010
HT46RU67/HT46CU67
Package Information
52-pin QFP (14mm´14mm) Outline Dimensions
C
H
D
3 9
G
2 7
I
2 6
4 0
F
A
B
E
1 4
5 2
K
J
1
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
0.681
¾
0.689
B
0.547
¾
0.555
C
0.681
¾
0.689
D
0.547
¾
0.555
E
¾
0.039
¾
F
¾
0.016
¾
G
0.098
¾
0.122
H
¾
¾
0.134
I
¾
0.004
¾
J
0.029
¾
0.041
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
Rev. 1.10
1 3
Dimensions in mm
Min.
Nom.
Max.
A
17.30
¾
17.50
B
13.90
¾
14.10
C
17.30
¾
17.50
D
13.90
¾
14.10
E
¾
1.00
¾
F
¾
0.40
¾
G
2.50
¾
3.10
H
¾
¾
3.40
I
¾
0.10
¾
J
0.73
¾
1.03
K
0.10
¾
0.20
a
0°
¾
7°
64
May 27, 2010
HT46RU67/HT46CU67
56-pin SSOP (300mil) Outline Dimensions
2 9
5 6
B
A
2 8
1
C
C '
G
H
D
E
Symbol
A
F
Dimensions in inch
Min.
Nom.
Max.
0.395
¾
0.420
B
0.291
¾
0.299
C
0.008
¾
0.012
C¢
0.720
¾
0.730
D
0.089
¾
0.099
E
¾
0.025
¾
F
0.004
¾
0.010
G
0.025
¾
0.035
H
0.004
¾
0.012
a
0°
¾
8°
Symbol
Rev. 1.10
a
Dimensions in mm
Min.
Nom.
Max.
A
10.03
¾
10.67
B
7.39
¾
7.59
C
0.20
¾
0.30
C¢
18.29
¾
18.54
D
2.26
¾
2.51
E
¾
0.64
¾
F
0.10
¾
0.25
G
0.64
¾
0.89
H
0.10
¾
0.30
a
0°
¾
8°
65
May 27, 2010
HT46RU67/HT46CU67
100-pin QFP (14mm´20mm) Outline Dimensions
C
H
D
8 0
G
5 1
I
5 0
8 1
F
A
B
E
3 1
1 0 0
K
a
J
1
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
0.728
¾
0.756
B
0.547
¾
0.555
C
0.965
¾
0.992
D
0.783
¾
0.791
E
¾
0.026
¾
F
¾
0.012
¾
G
0.098
¾
0.122
H
¾
¾
0.134
I
¾
0.004
¾
J
0.039
¾
0.055
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
Rev. 1.10
3 0
Dimensions in mm
Min.
Nom.
Max.
A
18.50
¾
19.20
B
13.90
¾
14.10
C
24.50
¾
25.20
D
19.90
¾
20.10
E
¾
0.65
¾
F
¾
0.30
¾
G
2.50
¾
3.10
H
¾
¾
3.40
I
¾
0.1
¾
J
1.00
¾
1.40
K
0.10
¾
0.20
a
0°
¾
7°
66
May 27, 2010
HT46RU67/HT46CU67
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
67
May 27, 2010