HOLTEK HT82A525R

HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Features
·
·
Operating voltage:
fSYS=6MHz: 3.3V~5.5V
fSYS=12MHz: 4.5V~5.5V
Two oscillators:
External crystal -- HXT (6MHz or 12 MHz)
Internal RC -- HIRC (12MHz)
·
Fully integrated internal 12MHz oscillator requires no external components
·
4K´15 Program Memory
·
192´8 Data Memory RAM
USB 2.0 Full Speed Compatible
·
·
·
·
·
·
·
Single 16-bit programmable Timer/Event Counters with overflow interrupt
Single 8-bit programmable Timer/Event Counters with overflow interrupt
Two SPI interfaces shared with I/O lines
Support SPI serial DMA or 8-bit parallel DMA
Support serial clock for peripheral device
·
Software controlled 4-COM lines LCD driver with 1/2 bias
Watchdog Timer function
Power down and wake-up functions to reduce power consumption
3-channel 12-bit PWM output shared with three I/O lines
·
Up to 42 bidirectional I/O lines
·
Up to 0.33ms instruction cycle with 12MHz system clock at VDD=5V
·
·
4 endpoints supported (endpoint 0 included)
Support interrupt, control & bulk transfer
·
Total FIFO size is 208 bytes (8,8,64,64´2 for EP0~EP3)
·
6-level subroutine nesting
Bit manipulation instruction
Table read instructions
·
·
·
·
·
·
·
·
63 powerful instructions
All instructions executed in one or two instruction cycles
Low voltage reset function (2.2V±0.2V)
24-pin SSOP, 32-pin QFN, 48/64-pin LQFP packages
General Description
This HT82A525R is an 8-bit high performance RISC microcontroller designed for USB keyboard
mouse and fingerprint product applications.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options,
multi-channel Pulse Width Modulation function, Watchdog timer, dual SPI interfaces, SPI serial
DMA or 8-bit parallel DMA , Power Down and wake-up functions, combine to provide the device
with a huge range of functional options while still maintaining a high level of cost effectiveness. The
device includes a fully integrated system oscillator HIRC, which requires no external components.
While the DMA function opens up application possibilities such as fingerprint data processing, the
device is also suited for a range of other applications such as motor driving, industrial control,
consumer products, subsystem controllers, etc.
Rev. 1.30
1
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Block Diagram
The following block diagram illustrates the main functional blocks.
U S B D +
V 3 3 O
U S B D -
T M R 0 C
U S B 2 .0
F u ll S p e e d
P ro g ra m
R O M
P ro g ra m
C o u n te r
In s tr u c tio n
R e g is te r
M
M P
U
X
IN T C
T M R 1 C
D A T A
M e m o ry
P A
P B C
S T A T U S
P B
P C C
P C
P F 1 /O S C O
P F 0 /O
R E
V D
V S
H V D
A V S
V D D
S
D
S
S C I
S
U
fS
X
P o rt A
P o rt B
P o rt C
P D C
P D
P E C
P E
Rev. 1.30
2
P C 2 /T M R 1
M
W D T
P A 0
P A 1
P A 3
P A 5
U
fS
X
/P S
/P W
/P W
/P C
Y S
/4
W D T O S C
Y N
M
M
L K
C , V S Y N
0 , P A 2 /P
2 , P A 4 /H
, P A 6 ~ P
C
W M 1
S Y N C
A 7
P B 0 /S C L K
P B 1 ~ P B 7
P C 0 /IN T
P C 3
P C 6 /S D I2
P C 7 /S D O 2
P D 0 /D 0 ~ P D 7 /D 7
P o rt D
P o rt E
P D 0
P D 1
P D 2
P D 3
P D 4
/C O
/C O
/C O
/C O
~ P D
M 0
M 1
M 2
M 3
7
P E 4 ~ P E 7
P E 0 /S C S 1
P E 1 /S C K 1
S e r ia l
D M A
In te rfa c e 1
P F
/4
P C 5 /S C K 2
P a r a lle
D M A
In te rfa c e
P F C
Y S
P C 4 /S C S 2
S e r ia l
In te rfa c e 2
IO
/4
E N /D IS
A C C
D
Y S
P C 1 /T M R 0
W D T P r e s c a le r
S h ifte r
T im in g
G e n e ra to r
H IR C
X
W D T S
M U X
A L U
M
T M R 1
P A C
In s tr u c tio n
D e c o d e r
fS
U
T M R 0
In te rru p t
C ir c u it
S T A C K
M
P E 2 /S D I1
P E 3 /S D O 1
P o rt F
P F 0 /O S C I
P F 1 /O S C O
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Pin Assignment
2 4
P A 5
P A 2
3
2 2
P A 7
4
5
P F 0 /O S C I
P B 0 /S C L K
P E 3 /S D O 1
6
V S S
1 9
7
V D D IO /V D D
1 8
8
V 3 3 O
1 7
9
U S B D P
1 6
1 0
U S B D M
1 5
1 1
S Y N
M 0 /D
M 1 /D
M 2 /D
M 3 /D
/S C L
/S D O
2 /S D
C
2
3
2
K
I1
4
2 2
2 1
H T 8 2 A 5 2 5 R
3 2 Q F N -A
3
5
6
1
P D 5
P D 6
P D 7
R E S
P F 0
P F 1
H V D
V S S
2 4
2 3
1
2 0
1 9
7
8
1 8
9 1 0 1 1 1 2 1 3 1 4 1 5 1 6
1 7
/D 5
/D 6
/D 7
/O S C I
/O S C O
D
O
P E 0 /S C S 1
IO
D M
H T 8 2 A 5 2 5 R
2 4 S S O P -A
D P
S
/T M R 0
/S C K 1
1 3
3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5
1
0
A V S S
1 4
1 2
N C , V
0 /C O
1 /C O
2 /C O
3 /C O
P B 0
P E 3
P E
V D D
V D D
U S B
U S B
V 3 3
A V S
P C 1
P E 1
P E 2 /S D I1
P E 1 /S C K 1
H V D D
2 0
P F 1 /O S C O
P A 0 /P S Y
P D
P D
P D
P D
R E S
2 1
P A 0 /P S Y N C , V S Y N C
M 1
P A 1
P B 1
P A 6
2 3
M 0
2
P D 4 /D 4
P A 7
P A 6
L K
N C
M 2
1
P A 3
P A 5 /P C
P A 4 /H S Y
P A 3 /P W
P A 2 /P W
P A 1 /P W
P A 4
C , V
/C O
/C O
/C O
P D 5 /D
P D 4 /D
P A
P A
P A 5 /P C L
P A 4 /H S Y N
P A 3 /P W M
P A 2 /P W M
P A 1 /P W M
N
S Y N
M 3 /D
M 2 /D
M 1 /D
N
N
P A 0 /P S Y N
P D 3
P D 2
P D 1
P D
P F 0 /O
P D
P D
P D
2 8
1 0
2 7
1 1
2 6
1 2
2 5
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
5
2 9
4
2
3 0
7
4
3 1
6
7
9
5
3 2
K
H T 8 2 A 5 2 5 R
4 8 L Q F P -A
8
6
I2
6
0
P F 1
H V D
V S S
V D D
V D D
V 3 3
U S B
U S B
A V S
P C 0
P C 1
P C 2
/O S C O
D
N
P D 0 /C O M 0 /D
P B
P B
P B
P B
P C 7 /S D O
P C 6 /S D
P C 5 /S C K
P C 4 /S C S
P B
P B
P B
P B 0 /S C L
N
N
IO
O
D P
S
D M
/IN T
/T M R 0
/T M R 1
P E 5
P E 4
P E 0
P E 1
P E 2
P E 3
P B 0
P B 1
P B 2
P B 3
P C 4
P C 5
/S C
/S C
/S D
/S D
/S C
C
6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9
1
7
4 6
3
4 5
4
6
4 4
5
5
4
I2
2
2
3
2
1
K
C
C
2
4 8
4 7
2
0
6
7
8
9
1 0
H T 8 2 A 5 2 5 R
6 4 L Q F P -A
1 1
1 2
1 3
1 4
1 5
1 6
1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
N C
P D 6
P D 7
R E S
P F 0
P F 1
H V D
V S S
V D D
N C
V D D
V 3 3
U S B
U S B
N C
N C
/D 6
/D 7
/O S C I
/O S C O
D
O
IO
D P
D M
N C
A V
P C
P C
P C
P C
P E
P E
P E
P E
P E
P E
P E
P E
N C
N C
S 1
K 1
I1
O 1
L K
/S C S 2
/S C K 2
3
S S
0 /IN T
1 /T M R 0
2 /T M R 1
7
6
C S 1
C K 1
D I1
D O 1
3
5
4
0 /S
1 /S
2 /S
3 /S
Rev. 1.30
2
5
1
C
3 3
1
3 4
4
2
0
3
C
3 5
3
7
3 6
3
2
2
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
1
0
C
1
W M
Y N
3 /D
2 /D
1 /D
0 /D
P B
P B
P B
P B
P C 7 /S D O
P C 6 /S D
C
1 /P
, V S
O M
O M
O M
O M
C
P A
N C
3 /C
2 /C
1 /C
0 /C
C
S C I
R E S
7 /D 7
6 /D 6
5 /D 5
4 /D 4
P A 7
P A 6
L K
N C
M 2
M 1
P A 5 /P C
P A 4 /H S Y
P A 3 /P W
P A 2 /P W
P A 0 /P S Y
P D
P D
P D
P D
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Pin Description
Pin Name
PA0/PSYNC/VSYNC
PA1/PWM0
PA2/PWM1
PA3/PWM2
PA4/HSYNC
PA5/PCLK
PA6~PA7
PB0/SCLK
PB1~PB7
PC0/INT
PC1/TMR0
PC2/TMR1
PC3
PC4/SCS2
PC5/SCK2
PC6/SDI2
PC7/SDO2
PD0/COM0/D0
PD1/COM1/D1
PD2/COM2/D2
PD3/COM3/D3
PD4/D4~PD7/D7
PE0/SCS1
PE1/SCK1
PE2/SDI1
PE3/SDO1
PE4~PE7
I/O
I/O
Description
Pull-high
(bit option)
Wake-up
(bit option)
Bidirectional 8-bit input/output port. Each individual pin on this
port can be configured as a wake-up input by a configuration
option. Software instructions determine if the pin is a CMOS
output or Schmitt Trigger input. Configuration options determine
which pins on the port have pull-high resistors. The PSYNC/
VSYNC is pin shared with PA0 (dependent on PSYNC/VSYNC
option). PA1~PA3 are pin-shared with PWM0~PWM2.
HSYNC is pin shared with PA4 (dependent on HSYNC option).
PCLK is pin shared with PA5 (dependent on PCLK option).
The power supply for the I/O pins is sourced from the VDDIO pin.
I/O
Bidirectional 8-bit input/output port. Each nibble on this port can
be configured as a wake-up input by a configuration option.
Pull-high
Software instructions determine if the pin is a CMOS output or
(bit option)
Schmitt Trigger input. Configuration options determine which
CMOS/NMOS
pins on the port have pull-high resistors. PB0~PB7 have CMOS/
wake-up
NMOS options.
(nibble option)
SCLK is pin shared with PB0 (dependent on SCLK option).
The power supply for the I/O pins is sourced from the VDDIO pin.
I/O
Bidirectional I/O lines. Each nibble on this port can be configured
as a wake-up input by a configuration option. Software
instructions determine if the pin is a CMOS output or Schmitt
Pull-high
Trigger input. Configuration options determine which nibble on
(nibble option)
the port have pull-high resistors. INT, TMR0, TMR1 are pin
wake-up
shared with PC0, PC1, PC2 respectively. SCS2 is pin shared
(nibble option)
with PC4. SCK2 is pin shared with PC5. SDI2 is pin shared with
PC6. SDO2 is pin shared with PC7.
The power supply for the I/O pins is sourced from the VDDIO pin.
I/O
Bidirectional I/O lines. Each nibble on this port can be configured
as a wake-up input by a configuration option. Software
Pull-high
instructions determine if the pin is a CMOS output or Schmitt
(nibble option) Trigger input. Configuration options determine which nibble on
wake-up
the port have pull-high resistors.
(nibble option) PD0~PD3 are pin-shared with COM0~COM3. The parallel DMA
data D0~D7 lines are pin shared with PD0~PD7.
The power supply for the I/O pins is sourced from the VDDIO pin.
I/O
Bidirectional I/O lines. Each nibble on this port can be configured
as a wake-up input by a configuration option. Software
Pull-high
instructions determine if the pin is a CMOS output or Schmitt
(nibble option) Trigger input. Configuration options determine which nibble on
wake-up
the port have pull-high resistors.
(nibble option) SCS1 is pin shared with PE0. SCK1 is pin shared with PE1.
SDI1 is pin shared with PE2. SDO is pin shared with PE3.
The power supply for the I/O pins is sourced from the VDDIO pin.
I/O (PF0)
Pull-high
wake-up
I(OSCI)
¾
PF0/OSCI
Rev. 1.30
Options
Bidirectional I/O line. The pin can be configured as a wake-up
input by a configuration option. Software instructions determine
if the pin is a CMOS output or Schmitt trigger input. A
configuration option determines if the pin has a pull-high resistor.
The power supply for the I/O pins is sourced from the VDD pin.
External crystal connection
4
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Pin Name
I/O
Options
Description
I/O (PF1)
Pull-high
wake-up
Bidirectional I/O line. The pin can be configured as a wake-up
input by a configuration option. Software instructions determine
if the pin is a CMOS output or Schmitt trigger input. A
configuration option determines if the pin has a pull-high resistor.
The power supply for the I/O pins is sourced from the VDD pin.
O(OSCO)
¾
External crystal connection
RES
I
¾
Schmitt trigger reset input, active low
VSS
¾
¾
HIRC and digital negative power supply, ground
AVSS
¾
¾
Analog negative power supply, ground
VDDIO
¾
¾
Positive power supply, VDDIO is used for PA, PB, PC, PD, PE,
except PF. For 24-pin SSOP package, the VDDIO pin is double
bonding to VDD pin.
HVDD
¾
¾
HIRC Positive power supply
VDD
¾
¾
Analog and digital positive power supply
V33O
O
¾
3.3V regulator output, can be disabled by firmware
USBDP
I/O
¾
USB D+ or 3D PS2 data line.
USB function is controlled using software control registers.
PS2 function is controlled by the SELPS2 bit in USC register.
USBDM
I/O
¾
USB D- or 3D PS2 CLK line.
USB function is controlled using software control registers.
PS2 function is controlled by the SELPS2 bit in USC register.
PF1/OSCO
Absolute Maximum Ratings
Supply Voltage ...............................................................................................VSS-0.3V to VSS+6.0V
Storage Temperature .................................................................................................-50°C to 125°C
Input Voltage .................................................................................................VSS-0.3V to VDD+0.3V
Operating Temperature................................................................................................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme
conditions may affect device reliability.
Rev. 1.30
5
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSYS=6MHz
3.3
¾
5.5
V
fSYS=12MHz
4.5
¾
5.5
V
¾
3.3
¾
VDD
V
VDD
VDD
Operating Voltage
¾
Conditions
VDDIO
Operating Voltage for I/O Ports
¾
IDD1
Operating Current (6MHz Crystal)
5V
No load, fSYS=6MHz
¾
4
8
mA
IDD2
Operating Current
(12MHz Crystal and HIRC)
5V
No load, fSYS=12MHz
¾
7.5
16
mA
5V
No load, system HALT,
USB mode, LVR disable,
WDT disable,
Clr V33O [USC.4],
Clr PLL [USC.5],
Clr SELPS2 [USC.6],
Clr USBCKEN [UCC.3],
Set SUSP2 [UCC.4],
Set RCtrl [UCC.7],
Set CLK_adj [PSD.4]
¾
¾
350
mA
¾
¾
10
mA
ISTB1
Standby Current 1
ISTB2
Standby Current 2
5V
No load, system HALT,
PS2 (I/O) mode,
LVR disable,
WDT disable,
Clr V33O [USC.4],
Clr PLL [USC.5],
Set SELPS2 [USC.6],
Clr USBCKEN [UCC.3],
Set SUSP2 [UCC.4],
Clr RCtrl [UCC.7],
CLR CLK_adj [PSD.4]
VIL1
Input Low Voltage for I/O Ports
¾
¾
0
¾
0.3VDDIO
V
VIH1
Input High Voltage for I/O Ports
¾
¾
0.7VDDIO
¾
VDDIO
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
IOL1
I/O Port Sink Current for PA, PB, PC,
PD, PE
¾
VOL=0.1VDDIO,
VDDIO=3.3V
2
5
¾
mA
IOL2
I/O Port Sink Current for PF0, PF1
¾
VOL=0.1VDD, VDD=5V
2
5
¾
mA
IOH1
I/O Port Source Current for PA, PB,
PC, PD, PE
¾
VOH=0.9VDDIO,
VDDIO=3.3V
-2
-5
¾
mA
IOH2
I/O Port Source Current for PF0, PF1 5V
VOH=0.9VDD
-2
-5
¾
mA
RPH1
Pull-high Resistance for PA, PB,
PC, PD, PE
¾
VDDIO=3.3V
40
60
80
kW
RPH2
Pull-high Resistance for PF0, PF1
5V
¾
10
30
50
kW
VLVR
Low Voltage Reset Voltage
¾
¾
2.0
2.2
2.4
V
Rev. 1.30
6
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
LCDC. RSEL[1:0]=00
17.5
25.0
32.5
mA
LCDC. RSEL[1:0]=01
35
50
65
mA
LCDC. RSEL[1:0]=10
70
100
130
mA
LCDC. RSEL[1:0]=11
140
200
260
mA
0.475
0.500
0.525
VDDIO
VDD
ILCD_BIAS
VDDIO/2 Bias Current for LCD,
VDDIO=5V
VDDIO/2 Voltage for LCD COM Port,
VDDIO=5V
VCOM
Conditions
5V
5V
No load
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
¾
6000
¾
12000
kHz
4.5V~
5.5V
¾
11640
12000
12360
kHz
5V
¾
0
¾
fSYS
kHz
tWDTOSC Watchdog Oscillator Period
5V
¾
32
65
130
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
*tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
fPCLK
Parallel Frequency
5V
¾
2
¾
5
MHz
fSYS1
System Clock (Crystal OSC)
fSYS2
System Clock (HIRC OSC)
fTIMER
Timer I/P Frequency (TMR0/TMR1)
Note:
VDD
Conditions
5V
Power-up, reset or
wake-up from HALT
*tSYS=1/fSYS
*fT1=fSYS/4
Rev. 1.30
7
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to
the internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance.
The pipelining scheme is implemented in such a way that instruction fetching and instruction
execution are overlapped, hence instructions are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the
instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement,
branch decisions, etc. The internal data path is simplified by moving data through the Accumulator
and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of these registers along with additional
architectural features ensure that a minimum of external components is required to provide a
functional I/O control system with maximum reliability and flexibility.
Clocking and Pipelining
The main system clock, derived from a Crystal oscillator is subdivided into four internally generated
non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1
clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the
decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle.
Although the fetching and execution of instructions takes place in consecutive instruction cycles, the
pipelining structure of the microcontroller ensures that instructions are effectively executed in one
instruction cycle. The exception to this are instructions where the contents of the Program Counter
are changed, such as subroutine calls or jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one cycle
to first obtain the actual jump or call address and then another cycle to actually execute the branch.
The requirement for this extra cycle should be taken into account by programmers in timing sensitive
applications.
S y s te m
O S C 2 (R C
T 1
C lo c k
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
System Clocking and Pipelining
1
3
M O V A ,[1 2 H ]
C A L L D E L A Y
C P L [1 2 H ]
5
:
2
4
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
:
6
E x e c u te In s t. 2
F e tc h In s t. 3
N O P
D E L A Y :
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
Instruction Fetching
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I/O Type USB 8-Bit OTP MCU with SPI
Program Counter
During program execution, the Program Counter is used to keep track of the address of the next
instruction to be executed. It is automatically incremented by one each time an instruction is executed
except for instructions, such as ²JMP² or ²CALL², that demand a jump to a non-consecutive Program
Memory address. Note that the Program Counter width varies with the Program Memory capacity
depending upon which device is selected. However, it must be noted that only the lower 8 bits, known
as the Program Counter Low Register, are directly addressable by user.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by
loading the required address into the Program Counter. For conditional skip instructions, once the
condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writable register. By transferring data directly into
this register, a short program jump can be executed directly, however, as only this low byte is
available for manipulation, the jumps are limited to the present page of memory, that is 256 locations.
When such program jumps are executed it should also be noted that a dummy cycle will be inserted.
The lower byte of the Program Counter is fully accessible under program control. Manipulating the
PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on
the PCL register can be found in the Special Function Register section.
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
USB Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
Serial Interface 1 Interrupt
0
0
0
0
0
0
0
1
0
1
0
0
Serial Interface 2 Interrupt
0
0
0
0
0
0
0
1
1
0
0
0
@3
@2
@1
@0
Skip
Program Counter+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
PC11~PC8: Current Program Counter bits
#11~#0: Instruction code address bits
S11~S0: Stack register bits
@7~@0: PCL bits
Stack
This is a special part of the memory which is used to save the contents of the Program Counter only.
The stack has 6 levels and is neither part of the data nor part of the program space, and can neither be
read from nor written to. The activated level is indexed by the Stack Pointer, SP, which can also
neither be read from nor written to. At a subroutine call or interrupt acknowledge signal, the contents
of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value
from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
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If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be
executed which will result in a stack overflow. Precautions should be taken to avoid such cases, which
might cause unpredictable program branching.
P ro g ra m
T o p o f S ta c k
B o tto m
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
S ta c k L e v e l 3
o f S ta c k
C o u n te r
P ro g ra m
M e m o ry
S ta c k L e v e l 6
Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
·
Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
·
Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
·
Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
·
Increment and Decrement INCA, INC, DECA, DEC
·
Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code or program is stored. The device contains
One-Time Programmable, OTP, memory where users can program their application code into the
device. By using the appropriate programming tools, OTP devices offer users the flexibility to freely
develop their applications, which may be useful during debug or for products requiring frequent
upgrades or program changes. OTP devices are also applicable for use in applications that require low
or medium volume production runs.
Organisation
The Program Memory has a capacity of 4K by 15 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries. Table data, which
can be setup in any location within the Program Memory, is addressed by separate table pointer
registers.
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I/O Type USB 8-Bit OTP MCU with SPI
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and
interrupts.
·
Location 000H
Location 000H is reserved for program initialization.
After a chip reset, the program always begins execution at this location.
·
Location 004H
Location 004H is reserved for the external interrupt service program. If the INT input pin is
activated, and the interrupt is enabled, and the stack is not full, the program begins execution at
location 004H.
·
Location 008H
Location 008H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer
interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack
is not full, the program begins execution at location 008H.
·
Location 00CH
Location 00CH is reserved for the Timer/Event Counter 1 interrupt service program. If a timer
interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack
is not full, the program begins execution at location 00CH.
·
Location 010H
Location 010H is reserved for the USB interrupt service program. If the USB interrupt is activated,
the interrupt is enabled and the stack is not full, the program begins execution at location 010H.
·
Location 014H
Location 014H is reserved for the Serial Interface 1. When 8 bits data have been received or
transmitted successfully from this Serial Interface 1, the related interrupts are enabled, and the stack
is not full, the program begins execution at location 014H.
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r 0
In te r r u p t S u b r o u tin e
0 0 C H
T im e r /E v e n t C o u n te r 1
In te r r u p t S u b r o u tin e
0 1 0 H
U S B In te r r u p t S u b r o u tin e
0 1 4 H
S e r ia l In te r fa c e 1 In te r r u p t S u b r o u tin e
0 1 8 H
S e r ia l In te r fa c e 2 In te r r u p t S u b r o u tin e
n 0 0 H
n F F H
F 0 0 H
F F F H
P ro g ra m
M e m o ry
L o o k - u p T a b le ( 2 5 6 w o r d s )
L o o k - u p T a b le ( 2 5 6 w o r d s )
1 5 b its
N o te : n ra n g e s fro m 0 to F
Program Memory
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HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
·
Location 018H
Location 018H is reserved for the Serial Interface 2. When 8 bits data have been received or
transmitted successfully from Serial Interface 2, the related interrupts are enabled, and the stack is
not full, the program begins execution at location 018H.
·
Table location
Any location in the program memory can be used as a look-up tables. There are three methods to
read the ROM data using two table read instructions ²TABRDC² and ²TABRDL², transfer the
contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH
(08H).
The three methods are shown as follows:
¨ The instruction ²TABRDC [m]² (the current page, one page=256 words), where the table location
is defined by TBLP (07H) in the current page. The configuration option, TBHP, is disabled (default).
¨ The instructions ²TABRDC [m]², where the table location is defined by registers TBLP (07H) and
TBHP (01FH). The configuration option, TBHP, is enabled.
¨ The instruction ²TABRDL [m]², where the table locations is defined by registers TBLP (07H) in
the last page (0F00H~0FFFH).
Table Location
Instruction
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Note:
*11~*0: Table location bits
@7~@0: Table pointer bits
Table Location
P11~P8: Current program counter bits
Only the destination of the lower-order byte in the table is well-defined, the other bits of the table
word are transferred to the lower portion of TBLH. The Table Higher-order byte register (TBLH) is
read only and cannot be restored. The table pointer (TBLP, TBHP) is a read/write register (07H,
1FH), which indicates the table location. Before accessing the table, the location must be placed in
the TBLP and TBHP registers(If the configuration option TBHP is disabled, the value in TBHP has
no effect).
If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the
contents of the TBLH in the main routine is likely to be changed by the table read instruction used in
the ISR. As a result errors may occur. In other words, using the table read instruction in the main
routine and in the ISR simultaneously should be avoided. However, if the table read instruction has to
be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read
instruction.
It will not be enabled until the TBLH has been backed up. All table related instructions require two
cycles to complete the operation. These areas may function as normal program memory depending on
the requirements.
Once TBHP is enabled, the instruction ²TABRDC [m]² reads the ROM data as defined by TBLP and
TBHP register value. Otherwise, if the configuration option TBHP is disabled, the instruction
²TABRDC [m]² reads the ROM data as defined by TBLP and the current program counter bits.
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HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Data Memory - RAM
The data memory (RAM) is designed with 256´8 bits, and is divided into two functional groups,
namely; special function registers (64´8 bits) and general purpose data memory (192´8 bits) most of
which are readable/writeable, although some are read only.
The unused space before 40H is reserved for future expanded usage and reading these locations will
get ²00H². The general purpose data memory, addressed from 40H to FFH, is used for data and
control information under instruction commands. All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in
the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly
accessible through memory pointer registers (MP0;01H/MP1;03H).
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers that are not physically implemented. Any
read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1 (03H)
respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing into it,
indirectly leads to no operation.
The function of data movement between two indirect addressing registers is not supported. The
memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by
combining corresponding indirect addressing registers.
Accumulator - ACC
The accumulator is closely related to ALU operations. It is also mapped to location 05H of the RAM
and capable of operating with immediate data. The data movement between two data memory
locations must pass through the accumulator.
Status Register - STATUS
The status register (0AH) is 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a
zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a Watchdog time-out flag (TO). It
also records the status information and controls the operation sequence. Except for the TO and PDF
flags, bits in the status register can be altered by instructions similar to other registers. Data written into
the status register does not alter the TO or PDF flags. Operations related to the status register, however,
may yield different results from those intended. The TO and PDF flags can only be changed by a
Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the ²HALT²
instruction.
The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt
sequence or executing a subroutine call, the status register will not be automatically pushed onto the
stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status
register, the programmer should take precautions and save it properly.
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I/O Type USB 8-Bit OTP MCU with SPI
0 0 H
IA R 0
0 2 H
IA R 1
0 1 H
0 3 H
0 4 H
M P 0
M P 1
0 5 H
A C C
0 7 H
T B L P
0 6 H
P C L
0 8 H
T B L H
0 A H
S T A T U S
0 9 H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
IN T C 0
T M R 0
T M R 0 C
T M R 1 H
T M R 1 L
1 1 H
T M R 1 C
1 3 H
P A C
1 5 H
P B C
1 7 H
P C C
1 9 H
P D C
1 B H
P E C
1 D H
P F C
1 2 H
1 4 H
1 6 H
1 8 H
1 A H
1 C H
P A
P B
P C
S p e c ia l P u r p o s e
D a ta M e m o ry
P D
P E
P F
1 E H
IN T C 1
2 0 H
U S C
1 F H
2 1 H
2 2 H
2 3 H
T B H P
U S R
U C C
A W R
2 4 H
S T A L L
2 6 H
M IS C
2 5 H
S IE S
2 7 H
S E T IO
2 9 H
F IF O 1
2 8 H
2 A H
2 B H
F IF O 0
F IF O 2
F IF O 3
2 C H
S B C R 1
2 E H
S B C R 2
2 D H
2 F H
3 0 H
3 1 H
S B D R 1
S B D R 2
P W M B R 0
P W M 0 D R L
3 2 H
P W M 0 D R H
3 4 H
P W M 1 D R L
3 3 H
P W M B R 1
3 5 H
P W M 1 D R H
3 7 H
P W M 2 D R L
3 6 H
P W M B R 2
3 8 H
P W M 2 D R H
3 A H
P S D
3 9 H
3 B H
3 C H
3 F H
4 0 H
F F H
C L K
L C D C
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
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HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Bit No.
Label
Function
C
Carry flag
0: no carry-out
1: an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation.
C is also affected by a rotate through carry instruction.
1
AC
Auxiliary flag
0: no auxiliary carry
1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high
nibble into the low nibble in subtraction.
2
Z
3
OV
Overflow flag
0: no overflow
1: an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
4
PDF
Power down flag
0: After power up or executing the ²CLR WDT² instruction
1: By executing the ²HALT² instruction
5
TO
Watchdog Time-Out flag
0: After power up or executing the ²CLR WDT² or ²HALT² instruction
1: A watchdog time-out occurred.
6, 7
¾
Unused bit, read as ²0²
0
Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Status (0AH) Register
Interrupts
This device provides external interrupts (INT pin interrupt), USB interrupt, Serial Interface interrupt
and internal timer/event counter interrupts. The Interrupt Control Register0 (INTC0;0BH) and
interrupt control register1 (INTC1:1EH) both contain the interrupt control bits that are used to set the
enable/disable status and interrupt request flags.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI
bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur
during this interval but only the interrupt request flag is recorded. If a certain interrupt requires
servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or INTC1
may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be
acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If
immediate service is desired, the stack must be prevented from becoming full.
All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer
occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at
specified location in the program memory. Only the program counter is pushed onto the stack. If the
contents of the register or status register (STATUS) are altered by the interrupt service program which
corrupts the desired control sequence, the contents should be saved in advance.
External interrupts can are triggered by a falling edge transition of INT), and the related interrupt
request flag (EIF; bit4 of the INTC0) is set as well. After the interrupt is enabled, the stack is not full,
and the external interrupt is active (INT pin), a subroutine call at location 04H occurs. The interrupt
flag (EIF) and EMI bits are all cleared to disable other maskable interrupts.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0
interrupt request flag (bit 5 of the INTC0), caused by a Timer 0 overflow. When the interrupt is enabled,
the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related
interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts.
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The internal Timer/Event Counter 1 interrupt is initialized by setting the Timer/Event Counter 1
interrupt request flag (bit 6 of the INTC0), caused by a Timer 1 overflow. When the interrupt is enabled,
the stack is not full and the T1F is set, a subroutine call to location 0CH will occur. The related interrupt
request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts.
USB interrupts are triggered by the following USB events and the related interrupt request flag
(USBF; bit 4 of the INTC1) will be set.
·
The access of the corresponding USB FIFO from PC
·
The USB suspend signal from the PC
·
The USB resume signal from the PC
·
USB reset signal
Bit No.
Label
Function
0
EMI
Global interrupt control (1: enable; 0: disable)
1
EEI
External interrupt control (1: enable; 0: disable)
2
ET0I
Timer/Event Counter 0 interrupt control (1: enable; 0: disable)
3
ET1I
Timer/Event Counter 1 interrupt control (1: enable; 0: disable)
4
EIF
External interrupt request flag (1: active; 0: inactive)
5
T0F
Timer/Event Counter 0 interrupt request flag (1: active; 0: inactive)
6
T1F
Timer/Event Counter 1 interrupt request flag (1: active; 0: inactive)
7
¾
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
Label
Function
0
EUI
1
ES1II
Serial Interface 1 interrupt control (1: enable; 0: disable)
2
ES2II
Serial Interface 2 interrupt control (1: enable; 0: disable)
3
¾
4
USBF
USB interrupt request flag (1: active; 0: inactive)
5
SI1F
Serial interface 1 interrupt request flag (1: active; 0: inactive)
6
SI2F
Serial Interface 2 interrupt request flag (1: active; 0: inactive)
7
¾
USB interrupt control (1: enable; 0: disable)
Unused bit, read as ²0²
Unused bit, read as ²0²
INTC1 (1EH) Register
When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine
call to location 10H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts.
When PC Host access the FIFO of the HT82A525R, the corresponding request bit of USR is set, and
a USB interrupt is triggered when the corresponding interrupt is enabled. So user can easily
determine which FIFO is accessed. When the interrupt has been served, the corresponding bit should
be cleared by firmware. When the HT82A525R receives a USB Suspend signal from the Host PC, the
suspend line (bit0 of the USC) of the HT82A525R is set and a USB interrupt is also triggered.
Also when the HT82A525R receives a Resume signal from the Host PC, the resume line (bit3 of the
USC) of the HT82A525R is set and a USB interrupt is triggered.
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I/O Type USB 8-Bit OTP MCU with SPI
Whenever a USB reset signal is detected, a USB interrupt is triggered.
The serial interface interrupt is indicating by the interrupt flag (SI1F: bit 5 of INTC1 or SI2F: bit 6 of
INTC1), that is caused by received or transferred a complete 8-bit data between HT82A525R and
external device. The serial interface interrupt is controlled by setting the Serial interface interrupt
control bit (ES1II: bit 1 of INTC1 or ES2II: bit2 of INTC1). After the interrupt is enabled (by setting
SBEN; bit 4 of SBCR1 or SBCR2), and the stack is not full and the SIF is set, a subroutine call to
location 14H or 18H occurs.
During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the
²RETI² instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the
stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI
will set the EMI bit to enable an interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of
simultaneous requests the following table shows the priority that is applied. These can be masked by
resetting the EMI bit.
Interrupt Source
Priority
Vector
External Interrupt
1
04H
Timer/Event Counter 0 Overflow
2
08H
Timer/Event Counter 1 Overflow
3
0CH
USB Interrupt
4
10H
Serial Interface 1 Interrupt
5
14H
Serial Interface 2 Interrupt
6
18H
It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine.
Oscillator Configuration
Various oscillator options offer the user a wide range of functions according to their various
application requirements. Two types of system clocks and an internal 12kHz oscillator can be
selected while various clock source options for the Watchdog Timer are provided for maximum
flexibility. All oscillator options are selected through the configuration options.
The two methods of generating the system clock are:
·
External crystal oscillator
·
Internal RC oscillator
One of these two methods must be selected using the configuration options.
More information regarding the oscillator is located in Application Note HA0075E on the Holtek
website.
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HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
External Crystal Oscillator - HXT
The simple connection of a crystal across OSCI and OSCO will create the necessary phase shift and
feedback for oscillation, and will normally not require external capacitors. However, for some
crystals, to ensure oscillation and accurate frequency generation, it may be necessary to add two small
value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in
consultation with the crystal manufacturer¢s specification. The external parallel feedback resistor, RP,
is normally not required but in some cases may be needed to assist with oscillation start up.
C 1
O S C I
R p
C 2
R f
In te r n a l
O s c illa to r
C ir c u it
C a
C b
O S C O
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C I/O S C O
c a p a c ita n c e o f a r o u n d 7 p F .
T o in te r n a l
c ir c u its
p in s h a v e a p a r a s itic
Crystal Oscillator - HXT
Internal Ca, Cb, therefore Typical Values @ 5V, 25°C
Ca
Cb
Rf
11~13pF
13~15pF
800kW
Oscillator Internal Component Values
Internal RC Oscillator
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has a fixed frequency of 12MHz. Device trimming during the
manufacturing process and the inclusion of internal frequency compensation circuits are used to
ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25°C
degrees, the fixed oscillation frequency of 12MHz will have a tolerance within 3%. The HIRC has an
Automatic Clock adjust function which can be used to adjust the HIRC frequency and to minimise the
frequency deviation caused by temperature variation. This function is controlled by the CLK_adj and
CLR_RCP bits in the PSD register. Note that if this internal system clock option is selected, as it
requires no external pins for its operation, I/O pins PF0 and PF1 are free for use as normal I/O pins.
I/O
O S C I
I/O
O S C O
Internal RC Oscillator - HIRC
Rev. 1.30
18
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Bit No.
Label
R/W
Function
PS2_DAO
USBDM/DATA pin output control bit
0: output ²low²; 1: output ²high²
R/W
This control bit is used to generate the USBDM/DATA pin output signal in the 3D PS2
mouse mode. The default value is ²1².
1
PS2_CKO
USBDP/CLK pin output control bit
0: output ²low²; 1: output ²high²
R/W
This control bit is used to generate the USBDP/CLK pin output signal in the 3D PS2
mouse mode. The default value is ²1².
2
¾
¾
3
PU
R/W
0
Undefined bit, read as unknown
USBDP and USBDM internal 310kW pull-high resistor select bit
0: without pull up resistor; 1: with pull up resistor
4
CLK_adj
Automatic Clock adjustment control bit
0: disable (default); 1:enable
R/W This bit is used to adjust the HIRC mode system clock, to reduce the frequency
deviation due to temperature issue.
In the Power-down mode, this bit should be clear to reduce power consumption.
5
CLR_RCP
This bit is must enable and then disable by F/W to clear HIRC initial parameters after
R/W power on.
0: disable (default); 1:enable
6~7
¾
¾
Undefined bit, read as ²0²
PSD (3AH) Register
Internal 12kHz Oscillator - WDTOSC
The low frequency internal 12K RC oscillator (WDTOSC) is a free running on-chip RC oscillator,
and no external components are required. Although when the system enters the Halt mode, the system
clock stops, the WDT oscillator will still operate if this oscillator is selected. Its period is
approximately 83.3ms. The WDT oscillator can also be disabled to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated RC oscillator (WDTOSC) or the system clock
divided by 4 determined by a configuration option. The timer is designed to prevent a software
malfunction or sequence from jumping to an unknown location with unpredictable results. The
watchdog timer can be disabled by a configuration option. If the watchdog timer is disabled, all
executions related to the WDT results in no operation.
Once the internal WDT oscillator (RC oscillator with a period of 83.3ms , normally at 5V) is selected,
it is divided by 212~216 by configuration option to get the WDT time-out period. The WDT time-out
minimum period is about 340ms. This time-out period may vary with temperature, VDD and process
variations. By selection from the WDT option, longer time-out periods can be realized. If the WDT
time-out is selected as 215, the maximum time-out period is divided by 215, about 2.7s.
If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and
operates in the same manner except that in the HALT state the WDT may stop counting and lose its
protecting purpose. If the device operates in a noisy environment, using the on-chip RC oscillator
(WDTOSC) is strongly recommended, since the HALT instruction will stop the system clock.
The WDT overflow under normal operation will initialize a ²chip reset² and set the status bit ²TO².
Whereas in the HALT mode, the overflow will initialize a ²warm reset² and only the Program Counter and
Stack Pointer are reset to zero. To clear the contents of WDT, three methods are adopted; external reset (a
Rev. 1.30
19
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
low level to RES), software instructions, or a ²HALT² instruction. The software instructions include
²CLR WDT² and the other set -- ²CLR WDT1² and ²CLR WDT2². Of these two types of instruction,
only one can be active depending on the option -- ²CLR WDT² times selection option. If the ²CLR WDT²
is selected (i.e. CLR WDT times equal one), any execution of the ²CLR WDT² instruction will clear the
WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. ²CLRWDT² times equal two), these two
instructions must be executed to clear the WDT, otherwise, the WDT may reset the chip due to time-out.
There are two ²Timer out WDT clear² modes selected by configuration option. One is ²Half WDT clear²
and the other is ²Full WDT scale². The ²Half WDT clear² is only to clear the highest two bits of WDT
counter and the ²Full WDT clear² is to clear all bits of WDT counter.
S y s te m
F u ll W D T C le a r
C lo c k /4
C o n fig u r a tio n
O p tio n
W D T O S C
(1 2 k H z )
fW
D T
D iv id e r
fW
D T
/2
8
T im e r - o u t R e s e t
W D T P r e s c a le r
M a s k O p tio n
C K
R
T
C K
H a lf W D T C le a r
N o te : fS = fW
D T
R
T
H a lf W D T
2 12 ~ 2 1
2 13 ~ 2 1
2 14 ~ 2 1
2 15 ~ 2 1
6
5
4
3
C le a r
/ fs
/ fs
/ fs
/ fs
F u ll W D T C le a r
2 1 6 / fS
2 1 5 / fS
2 1 4 / fS
2 1 3 / fS
Watchdog Timer
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction and results in the following:
·
The system oscillator is turned off but the WDT oscillator keeps running (if the WDT oscillator is
selected).
·
The contents of the on-chip RAM and registers remain unchanged.
·
The WDT will be cleared and start recounting (if the WDT clock source is from the WDT oscillator).
·
All of the I/O ports maintain their original status.
·
The PDF flag is set and the TO flag is cleared.
The system can quit the HALT mode in many ways, by an external reset, an interrupt (except serial interface interrupt and serial interface 2 interrupt), an external falling edge or rising edge signal on I/O
ports or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a ²warm reset². After examining the TO and PDF flags, the cause for a chip reset can be determined. The PDF flag is cleared by a system power-up or by executing the ²CLR WDT² instruction and
is set when executing the ²HALT² instruction. On the other hand, the TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer; and
leaves the others in their original status.
The Port A wake-up and interrupt methods can be considered as a continuation of normal execution.
Each bit in Port A can be independently selected to wake-up the device by option. Awakening from an
I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an
interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but
the stack is full, the program will resume execution at the next instruction. But if the interrupt is
enabled and the stack is not full, a regular interrupt response takes place. When an interrupt request
flag is set to ²1² before entering the HALT mode, the wake-up function of the related interrupt will be
disabled. If a wake-up event occurs, it takes 1024 fSYS (system clock period) to resume normal
operation. In other words, a dummy period is inserted after wake-up. If the wake-up results from an
interrupt acknowledge, the actual interrupt subroutine execution is delayed by more than one cycle.
Rev. 1.30
20
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
However, if the wake-up results in the next instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should be carefully managed before entering the
HALT status.
Reset
There are three ways in which a reset may occur:
·
RES reset during normal operation
·
RES reset during HALT
·
WDT time-out reset during normal operation
The WDT time-out during HALT differs from other chip reset conditions, for it can perform a ²warm
reset² that resets only the program counter and stack pointer, leaving the other circuits in their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. Examining the PDF and TO flags, the
program can distinguish between different ²chip resets².
TO
PDF
0
0
RES reset during power-up
RESET Conditions
0
0
RES reset during normal operation
0
0
RES wake-up at HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up at HALT
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer)
provides an extra-delay of 1024 system clock pulses when the system awakes from the HALT state or
during power up.
Awaking from the HALT state or system power up, an SST delay is added. An extra SST delay is
added during power up period, and any wake-up from HALT may enable only the SST delay.
The functional unit chip reset status are shown below.
Program Counter
000H
Interrupt
Disable
Prescaler, Divider
Cleared
WDT
Clear. After master reset, WDT begins counting
Timer/event Counter Off
Rev. 1.30
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
21
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
H A L T
W D T
R E S
W D T
T im e - o u t
R e s e t
W a rm
0 .0 1 m F *
C o ld
R e s e t
R E S
1 0 k W
0 .1 m F *
P o w e r - o n D e te c tio n
Reset Circuit
Reset Configuration
Note:
V D D
R E S
D D
1 0 0 k W
E x te rn a l
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
V
R e s e t
tS
S T
+ tO
²*² Make the length of the wiring, which is
connected to the RES pin as short as possible,
to avoid noise interference.
P D
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
The registers states are summarized in the following table.
Reset
(Power On)
WDT
Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
USB Reset
(Normal)
USB Reset
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
Register
Program
Counter
STATUS
--00 xxxx
--1u uuuu
--00 uuuu
--00 uuuu
--11 uuuu
--uu uuuu
--01 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
-000 0000
-000 0000
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u u---
00-0 1000
00-0 1000
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
00-0 1---
00-0 1---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
Rev. 1.30
22
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Reset
(Power On)
WDT
Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
USB Reset
(Normal)
USB Reset
(HALT)
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PE
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PEC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PF
---- --11
---- --11
---- --11
---- --11
---- --uu
---- --11
---- --11
PFC
---- --11
---- --11
---- --11
---- --11
---- --uu
---- --11
---- --11
Register
INTC1
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
-000 -000
-000 -000
TBHP
---- xxxx
---- uuuu
---- uuuu
---- uuuu
---- uuuu
---- uuuu
---- uuuu
USC
1000 x00x
uuuu xuux
1000 x00x
1000 x00x
uuuu xuux
u-00 0100
u-00 0100
USR
0000 0000
0000 uuuu
0000 0000
0000 0000
0000 uuuu
0000 0000
0000 0000
UCC
-000 0000
-uuu uuuu
-000 0000
-000 0000
-uuu uuuu
-uu0 u000
-uu0 u000
AWR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
---- 1110
---- uuuu
---- 1110
---- 1110
---- uuuu
---- 1110
---- 1110
SIES
0x0x x000
uxux xxuu
0x0x x000
0x0x x000
uxux xxuu
0x0x x000
0x0x x000
MISC
0xx- -000
uxx- -uuu
0xx- -000
0xx- -000
uxx- -uuu
000- -000
000- -000
SETIO
---- 1110
---- uuuu
---- 1110
---- 1110
---- uuuu
---- 1110
---- 1110
FIFO0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO3
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
SBCR1
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
SBDR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
SBCR2
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
SBDR2
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PWMBR0
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PWM0DRL
0000 --00
0000 --00
0000 --00
0000 --00
uuuu --uu
0000 --00
0000 --00
PWM0DRH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PWMBR1
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PWM1DRL
0000 --00
0000 --00
0000 --00
0000 --00
uuuu --uu
0000 --00
0000 --00
PWM1DRH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PWMBR2
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PWM2DRL
0000 --00
0000 --00
0000 --00
0000 --00
uuuu --uu
0000 --00
0000 --00
PWM2DRH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
CLK
---00 0000
--uu uuuu
---00 0000
---00 0000
--uu uuuu
--uu uuuu
--uu uuuu
STALL
PSD
--00 0x11
--uu ux11
--00 0x11
--00 0x11
--uu ux11
--uu ux11
--uu ux11
LCDC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.30
23
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Timer/Event Counter
Two Timer/Event Counters (TMR0, TMR1) are implemented in the microcontroller. The
Timer/Event Counter 0 contains a 8-bit programmable count-up counter and the clock may come
from an external source or an internal clock source. An internal clock source comes from fSYS. The
Timer/Event Counter 1 contains a 16-bit programmable count-up counter and the clock may come
from an external source or an internal clock source. An internal clock source comes from fSYS/4. The
external clock input allows the user to count external events, measure time intervals or pulse widths,
or generate an accurate time base.
There are five registers related to the Timer/Event Counter 0; TMR0 (0DH), TMR0C (0EH) and the
Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). For 16bits timer to Write
data to TMR1L will only put the written data to an internal lower-order byte buffer (8-bit) and writing
TMR1H will transfer the specified data and the contents of the lower-order byte buffer to TMR1H
and TMR1L registers. The Timer/Event Counter 1 preload register is changed by each writing
TMR1H operations. Reading TMR1H will latch the contents of TMR1H and TMR1L counters to the
destination and the lower-order byte buffer, respectively. Reading the TMR1L will read the contents
of the lower-order byte buffer. The TMR0C (TMR1C) is the Timer/Event Counter 0 (1) control
register, which defines the operating mode, counting enable or disable and an active edge.
The T0M0, T0M1 (TMR0C) and T1M0, T1M1 (TMR1C) bits define the operation mode. The event
count mode is used to count external events, which means that the clock source is from an external
(TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from
the internal selected clock source. Finally, the pulse width measurement mode can be used to count
the high or low level duration of the external signal (TMR0, TMR1), and the counting is based on the
internal selected clock source.
In the event count or timer mode, the timer/event counter starts counting at the current contents in the
timer/event counter and ends at FFFFH (for 16 bits timer is FFFFH, bit 8 bits timer will be FFH).
Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and
generates an interrupt request flag (T0F; bit 5 of the INTC0, T1F; bit 6 of the INTC0).
In the pulse width measurement mode with the values of the T0ON/T1ON and T0E/T1E bits equal to
1, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the T0E/T1E
bit is ²0²), it will start counting until the TMR0 (TMR1) returns to the original level and resets the
T0ON/T1ON. The measured result remains in the timer/event counter even if the activated transient
occurs again. In other words, only 1-cycle measurement can be made until the T0ON/T1ON is set.
The cycle measurement will re-function as long as it receives further transient pulse. In this operation
mode, the timer/event counter begins counting not according to the logic level but to the transient
edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register
and issues an interrupt request, as in the other two modes, i.e., event and timer modes.
To enable the counting operation, the Timer ON bit (T0ON: bit 4 of the TMR0C; T10N: bit 4 of the
TMR1C) should be set to 1. In the pulse width measurement mode, the T0ON/T1ON is automatically
cleared after the measurement cycle is completed. But in the other two modes, the T0ON/T1ON can
only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up
sources. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related
interrupt service.
In the case of timer/event counter OFF condition, writing data to the timer/event counter preload
register also reloads that data to the timer/event counter. But if the timer/event counter is turned on,
data written to the timer/event counter is kept only in the timer/event counter preload register. The
timer/event counter still continues its operation until an overflow occurs.
Rev. 1.30
24
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as
this may results in a counting error. Blocking of the clock should be taken into account by the
programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 register first,
before turning on the related timer/event counter, for proper operation since the initial value of
TMR0/TMR1 is unknown. Due to the timer/event scheme, the programmer should pay special
attention on the instruction to enable then disable the timer for the first time, whenever there is a need
to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event
function can be operated normally.
Bit No.
Label
0~2
¾
3
T0E
4
T0ON
5
¾
6
7
T0M0
T0M1
Function
Unused bit, read as ²0²
Timer 0 active edge control bit
0: active on low to high
1: active on high to low
Timer 0 control bit
0: disable
1: enable
Unused bit, read as ²0²
T0M1, T0M0: Timer 0 operating mode control bits
00: Unused
01: Event counter mode (external clock)
10: Timer mode (internal clock)
11: Pulse width measurement mode
TMR0C (0EH) Register
Bit No.
Label
0~2
¾
3
T1E
4
T1ON
5
¾
6
7
T1M0
T1M1
Function
Unused bit, read as ²0²
Timer 1 active edge control bit
0: active on low to high
1: active on high to low
Timer 1 control bit
0: disable
1: enable
Unused bit, read as ²0²
T1M1, T1M0: Timer 1 operating mode control bits
00: Unused
01: Event counter mode ( external clock)
10: Timer mode ( internal clock)
11: Pulse width measurement mode
TMR1C (11H) Register
Rev. 1.30
25
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
D a ta B u s
T 0 M 1
fS
T M R 0
/4
Y S
T 0 M 0
P r e lo a d R e g is te r
R e lo a d
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T 0 E
T 0 O N
T im e r /E v e n t
C o u n te r
O v e r flo w
to In te rru p t
8 - B it T im e r /E v e n t C o u n te r
Timer/Event Counter 0
D a ta B u s
T 1 M 1
fS
T M R 1
Y S
/4
T 1 E
L o w B y te
B u ffe r
T 1 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T 1 O N
1 6 - B it
P r e lo a d R e g is te r
H ig h B y te
L o w
B y te
1 6 - b it T im e r /E v e n t C o u n te r
R e lo a d
O v e r flo w
to In te rru p t
Timer/Event Counter 1
Input/Output Ports
There are 42 bidirectional input/output lines in the microcontroller, labeled from PA to PF, which are
mapped to the data memory of [12H], [14H], [16H], [18H], [1AH] and [1CH] respectively. All of
these I/O ports can be used for input and output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]²
(m=12H, 14H, 16H, 18H, 1AH or 1CH). For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC, PCC, PDC, PEC, PFC) to control the
input/output configuration. With this control register, CMOS output or Schmitt trigger input with or
without pull-high resistor structures can be reconfigured dynamically under software control.
To function as an input, the corresponding latch of the control register must write a ²1². The input
source also depends on the control register. If the control register bit is ²1² the input will read the pad
state. If the control register bit is ²0² the contents of the latches will move to the internal bus. The
latter is possible in the ²Read-modify-write² instruction. For output function, CMOS is the only
configuration (except PB can be configured as CMOS output or NMOS output). These control
registers are mapped to locations 13H, 15H, 17H, 19H, 1BH and 1DH. PA0 is pin-shared with
PSYNC or VSYNC signal (dependent on PSYNC/VSYNC option). PB0 is pin-shared with SCLK
signal (dependent on SCLK option).
After a chip reset, these input/output lines remain at high levels or floating state (depending on the
pull-high options). Each bit of these input/output latches can be set or cleared by ²SET [m].i² and
²CLR [m].i² (m=12H, 14H, 16H, 18H , 1AH or 1CH ) instructions.
Some instructions first input data and then follow the output operations. For example, ²SET [m].i²,
²CLR [m].i², ²CPL [m]², ²CPLA [m]² read the entire port states into the CPU, execute the defined
operations (bit-operation), and then write the results back to the latches or the accumulator.
All the I/O ports have the capability of waking-up the device.
It is recommended that unused or not bonded out I/O lines should be set as output pins by software
instruction to avoid consuming power under input floating state.
Note that the I/O lines, from PA to PE, the power supply is from VDDIO pin, except PF, from VDD.
Rev. 1.30
26
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
D a ta B u s
D
W r ite C o n tr o l R e g is te r
C K
C h ip R e s e t
R e a d C o n tr o l R e g is te r
Q
Q
S
D a ta B it
W r ite D a ta R e g is te r
S C L K
S C L K E N
D
C K
S
Q
Q
M
P B 0
R e a d D a ta R e g is te r
S y s te m
V
P u ll- h ig h
O p tio n
C o n tr o l B it
W a k e -u p
IN T fo r P C 0
T M R 0 fo r P C 1
T M R 1 fo r P C 2
M
U
X
U
X
M a s k O p tio n
D D IO
(V
P A 0
P A 1
P A 3
P A 5
P B 0
P C 0
P C 2
P C 4
P C 6
P D 0
P D 1
P D 2
P D 3
P D 4
P E 0
P E 2
P E 4
P F 0
D D
fo r P F 0 ~ P F 1 )
/P S Y N C , V S Y N C
/P W M 0 , P A 2 /P W M 1
/P W M 2 , P A 4 /H S Y N C
/P C L K , P A 6 ~ P A 7
/S C L K , P B 1 ~ P B 7
/IN T , P C 1 /T M R 0
/T M R 1 , P C 3
/S C S 2 , P C 5 /S C K 2
/S D I2 , P C 7 /S D O 2
/C O M 0 /D 0
/C O M 1 /D 1
/C O M 2 /D 2
/C O M 3 /D 3
/D 4 ~ P D 7 /D 7
/S C S 1 , P E 1 /S C K 1
/S D I1 , P E 3 /S D O 1
~ P E 7
/O S C I, P F 1 /O S C O
M a s k O p tio n
Input/Output Ports
Low Voltage Reset - LVR
The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the
device. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery,
the LVR will automatically reset the device internally.
The LVR includes the following specifications:
·
The low voltage range (0.9V~VLVR) has to be maintained for over 1ms, otherwise, the LVR will
ignore it and do not perform a reset function.
·
The LVR uses the ²OR² function with the external RES signal to perform a chip reset.
SPI Serial Interface
This device includes two SPI Serial Interfaces, namely SPI1 and SPI2. The SPI interface is a full
duplex serial data link, originally designed by Motorola, which allows multiple devices connected to
the same SPI bus to communicate with each other. The devices communicate using a master/slave
technique where only the single master device can initiate a data transfer. A simple four line signal
bus is used for all communication and these pins are shared with normal I/O pins. The SPI function is
selected and controlled via configuration options and an SBCR register. The following table shows
the SPI pin-shared options.
Note that the SPIn stands for SPI1 and SPI2. The ²n², known as ²1² or ²2², is used to distinguish these
two SPIs in the following sections.
SPI Interface Communication
Four lines are used for SPIn communication known as SDIn - Serial Data Input, SDOn - Serial Data
Output, SCKn -Serial Clock and SCSn - Slave Select. Note that the condition of the Slave Select line
is conditioned by the CSENn bit in the SBCRn control register. If the CSENn bit is high then the
SCSn line is active while if the bit is low then the SCSn line will be a normal I/O pin. The following
timing diagram depicts the basic timing protocol of the SPIn bus.
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HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
D a ta B u s
S B D R n ( R e c e iv e d D a ta R e g is te r )
D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
M
X
M L S n
In te r n a l B a u d R a te C lo c k
a n d , s ta rt
E N
S C K n
a n d , s ta rt
C lo c k P o la r ity
M
S D In
U
B u ffe r
S D O n
S B E N n
X
M
U
X
M a s te r o r S la v e
S B E N n
a n d , s ta rt
E N
N o te : n = 0 o r 1
W C O L n : s e t
C S E N n : e n a
1 . m
2 . s
S B E N n : e n a
1 . W
2 . W
T R F n : d a ta
S P In _ C P O L
S D O
U
T R F n
C 0 C 1 C 2
In te r n a l B u s y F la g
S B E N n
W C O L n F la g
A N D
W r ite S B D R n
W r ite S B D R n E n a b le /D is a b le
W r ite S B D R n
S C S n
M a s te r o r S la v e
S B E N n
C S E N n
b y S
b le /d
a s te
la v e
b le /d
h e n
h e n
tra n s
1 /0 :
P In c le a r e d b y u s e r s
is a b le c h ip s e le c tio n fu n c tio n p in
r m o d e : 1 /0 = w ith /w ith o u t S C S n
m o d e : 1 /0 = w ith /w ith o u t S C S n in
is a b le s e r ia l b u s ( 0 : in itia lis e a ll s
S B E N n = 0 , a ll s ta tu s fla g s s h o u ld
S B E N n = 1 , a ll S P I r e la te d fu n c tio
m itte d o r r e c e iv e d , 0 : d a ta is tr a n
c lo c k p o la r ity r is in g /fa llin g e d g e :
o u tp u t fu n c tio n
p u t c o n tr o l fu n c tio n
ta tu s fla g s )
b e in itia lis e d
n p in s s h o u ld s ta y a t flo a tin g s ta te
s m ittin g o r s till n o t r e c e iv e d
c o n fig u r a tio n o p tio n
SPI Block Diagram
SPI pin-shared I/O Option Table
The following table shows how the SPIn pins are related to the SPIn configuration options and the
control bits in the SBCRn register.
Configuration Options
SPI_ENn
SPI_CSENn
Register Options
Pin-shared I/O Functions
SBENn
CSENn
SPIn or I/O
SCSn or I/O
Note
0
x
x
x
I/O
I/O
1
x
0
x
I/O
I/O
1
0
1
x
SPIn
I/O
SCSn not floating
1
1
1
0
SPIn
I/O
SCSn not floating
1
1
1
1
SPIn
SCSn
SPIn Registers
There are several registers associated with the SPIn Interface. These are the SBCRn register which is
the control register and the SBDRn which is the data register. The SBCRn register is used to setup the
required setup parameters for the SPIn bus and also used to store associated operating flags, while the
SBDRn register is used for data storage.
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HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
After Power on, the contents of the SBDRn register will be in an unknown condition while the
SBCRn register will default to the condition below:
CKSn
M1n
M0n
SBENn
MLSn
CSENn
WCOLn
TRFn
0
1
1
0
0
0
0
0
Note that data written to the SBDRn register will only be written to the TXRXn buffer, whereas data
read from the SBDRn register will actual be read from the register.
SPIn Bus Enable/Disable
To enable the SPIn bus, CSENn = 1, SCSn=0, then wait for data to be written to the SBDRn (TXRXn
buffer) register.
For the Master Mode, after data has been written to the (TXRXn buffer) register, then transmission or
reception will start automatically. When all the data has been transferred the TRFn bit should be set.
For the Slave Mode, when clock pulses are received on SCKn, data in the TXRXn buffer will be
shifted out or data on SDIn will be shifted in.
To Disable the SPIn bus SCKn, SDIn, SDOn, SCSn will enter I/O mode.
Bit No.
Label
Function
TRFn
SPIn Transmit/Receive Complete flag
0: data is being transferred; 1: SPIn data transmission is completed
The TRFn bit is the Transmit/Receive Complete flag and is set ²1² automatically when an
SPIn data transmission is completed, but must set to ²0² by the application program. It can
be used to generate an interrupt.
WCOLn
SPIn Write Collision flag
0: no collision; 1: collision
The WCOLn flag is used to detect if a data collision has occurred. If this bit is high it means
that data has been attempted to be written to the SIMDn register during a data transfer
operation. This writing operation will be ignored if data is being transferred. The bit can be
cleared by the application program. Note that using the WCOLn bit can be disabled or
enabled via configuration option.
2
CSENn
SPIn SCS pin Control
0: disable; 1: enable
The CSENn bit is used as an enable/disable for the SCSn pin. If this bit is low, then the
SCSBn pin will be disabled and placed into an I/O mode. If the bit is high the SCSBn pin will
be enabled and used as a select pin.
Note that using the CSENn bit can be disabled or enabled via configuration option.
3
MLSn
SPIn Data shift order
0: LSB; 1: MSB
This is the data shift select bit and is used to select how the data is transferred, either MSB or
LSB first. Setting the bit high will select MSB first and low for LSB first.
4
SBENn
0
1
5
6
M1n
M0n
7
CKSn
Serial Bus Control bit
0: disable; 1: enable
Depend upon CSENn bit.
Master/Slave/Baud rate control bits
00: Master, baud rate is fSIO
01: Master, baud rate is fSIO/4
10: Master, baud rate is fSIO/16
11: Slave mode
Clock Source Select bit
0: fSIO=fSYS/4; 1: fSIO=fSYS
Note: The TRFn flag will also generate an SPIn interrupt signal, for more information refer to the interrupt section.
SPIn Interface Control Register
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HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
SPIn Operation
All communication is carried out using the 4-line interface for both Master or Slave Mode which is
controlled by configuration options and the SBCRn register. The timing diagram shows the basic
operation of the bus. The CSENn bit in the SBCRn register and the SPIn_EN configuration option
control the overall function of the SPIn interface. Setting these two bits high, will enable the SPIn
interface by allowing the SCSn line to be active, which can then be used to control the SPIn interface.
Meanwhile, the PE0~PE3 or PC4~PC7 will be the SPIn function pins and the corresponding
pull-high resistor will be disabled by hardware.
If the CSENn bit is low, the SPIn interface will be disabled and the SCSn pins will be setup as normal
I/O pins and can therefore not be used for control of the SPIn interface. The SBENn bit in the SBCRn
register must also be high which will place the SDIn line in a floating condition and the SDOn line
high. If in Master Mode the SCKn line will be either high or low depending upon the clock polarity
configuration option. If in Slave Mode the SCKn line will be in a floating condition. If SBENn is low
then the bus will be disabled and SCSn, SDIn, SDOn and SCKn will all be in a I/O mode.
In the Master Mode the Master will always generate the clock signal. The clock and data transmission
will be initiated after data has been written to the SBDRn register.
In the Slave Mode, the clock signal will be received from an external master device for both data
transmission or reception. The following sequences show the order to be followed for data transfer in
both Master and Slave Mode.
Master Mode
Rev. 1.30
·
Step 1
Select the clock source using the CKSn bit in the SBCRn control register
·
Step 2
Setup the M0n and M1n bits in the SBCRn control register to select the Master Mode and the
required Baud rate. Values of 00, 01 or 10 can be selected.
·
Step 3
Setup the CSENn bit and setup the MLSn bit to choose if the data is MSB or LSB first, this must be
same as the Slave device.
·
Step 4
Setup the SBENn bit in the SBCRn control register to enable the SPIn interface.
·
Step 5
For write operations: write the data to the SBDRn register, which will actually place the data into the
TXRXn buffer. Then use the SCKn and SCSn lines to output the data.
Goto to step 6.For read operations: the data transferred in on the SDIn line will be stored in the
TXRXn buffer until all the data has been received at which point it will be latched into the SBDRn
register.
·
Step 6
Check the WCOLn bit, if set high then a collision error has occurred so return to step5. If equal to
zero then go to the following step.
·
Step 7
Check the TRFn bit or wait for an SBIn serial bus interrupt.
·
Step 8
Read data from the register.
·
Step 9
Clear TRFn.
·
Step10
Goto step 5.
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HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Slave Mode
·
Step 1
The CKSn bit has a don¢t care value in the slave mode.
·
Step 2
Setup the M0n and M1n bits to 11 to select the Slave Mode. The CKSn bit is don¢t care.
·
Step 3
Setup the CSENn bit and setup the MLS bit to choose if the data is MSB or LSB first, this must be
same as the Master device.
·
Step 4
Setup the SBENn bit in the SBCRn control register to enable the SPIn interface.
·
Step 5
For write operations: write data to the SBCRn register, which will actually place the data into the
TXRXn register, then wait for the master clock and SCSn signal. After this goto step 6.
For read operations: the data transferred in on the SDIn line will be stored in the TXRXn buffer until
all the data has been received at which point it will be latched into the SBDRn register.
·
Step 6
Check the WCOLn bit, if set high then a collision error has occurred so return to step5. If equal to
zero then go to the following step.
·
Step 7
Check the TRFn bit or wait for an SBI serial bus
interrupt.
·
Step 8
Read data from the SBDRn register.
·
Step 9
Clear TRFn
·
Step10
Goto step 5
SPIn Configuration Options
Several configuration options exist for the SPIn Interface function which must be setup during device
programming. One option is to enable the operation of the WCOLn, write collision bit, in the SBCRn
register. Another option exists to select the clock polarity of the SCKn line. A configuration option
also exists to disable or enable the operation of the CSENn bit in the SBCRn register. If the
configuration option disables the CSENn bit then this bit cannot be used to affect overall control of
the SPIn Interface.
Error Detection
The WCOLn bit in the SBCRn register is provided to indicate errors during data transfer. The bit is set
by the Serial Interface but must be cleared by the application program. This bit indicates a data
collision has occurred which happens if a write to the SBDRn register takes place during a data
transfer operation and will prevent the write operation from continuing. The bit will be set high by the
Serial Interface but has to be cleared by the user application program. The overall function of the
WCOLn bit can be disabled or enabled by a configuration option.
Programming Considerations
When the device is placed into the Power Down Mode note that data reception and transmission will
continue. The TRFn bit is used to generate an interrupt when the data has been transferred or
received.
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HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
There are two SPIn modes for different data output format, selected by a configuration option. The
following diagram illustrates these two data format, which are dependent on the SPIn_CPOL and
SPIn_mode options.
S P In _ m o d e = 0
S B E N n = 1 , C S E N n = 0 a n d w r ite d a ta to S B D R n ( C S in te r to IO
S B E N n = C S E N n = 1 a n d w r ite d a ta to S B D R n
S C S n
M o d e )
S C K n
(S P In _ C P O L = 1 )
S C K n
(S P In _ C P O L = 0 )
S D In
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S D O n
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S P In _ m o d e = 1
S B E N n = 1 , C S E N n = 0 a n d w r ite d a ta to S B D R n ( C S in te r to IO
S B E N n = C S E N n = 1 a n d w r ite d a ta to S B D R n
S C S n
M o d e )
S C K n
(S P In _ C P O L = 1 )
S C K n
(S P In _ C P O L = 0 )
S D In
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
S D O n
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
S B C R n
C K S n
M 1 n
M 0 n
S B E N n
M L S n
C S E N n
W C O L n
T R F n
D e fa u lt
0
1
1
0
0
0
0
0
S B D R n
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
D e fa u lt
X
X
X
X
X
X
X
X
S B C R n : S e r ia l B u s C o n tr o l R e g is te r
S B D R n : S e r ia l B u s D a ta R e g is te r
N o te : "X " m e a n s u n k n o w .
SPIn Bus Timing
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HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
If the PSYNC function is enabled, this device will generate an internal SYNC signal to synchronize
the received data in SDBR register, to indicate that the next receiving bit of data will be the MSB. The
following timing diagram illustrates the relationship between the SCK and PSYNC control signals in
slave mode. Note that if the SPI is working under master mode, the PSYNC function and the SYNC
will be ignored by hardware.
S C K
P S Y N C
S Y N C
( In te r n a l c o n tr o l s ig n a l)
A
S P I T ra n s fe r
M a s te r
M a s te r o r
S la v e
M 1 n M 0 n = 0 0 , 0 1 , 1 0
C o n fig u r e C K S n
W r ite D a ta in to
S B D R n
C le a r W C O L n
S la v e
Y e s
W C O L n = 1 ?
M 1 n M 0 n = 1 1
N o
N o
C o n fig u r e
C S E N n a n d M L S n
T r a n s m is s io n
C o m p le te d ?
(T R F n = 1 ? )
Y e s
S B E N n = 1
re a d d a ta fro m
S B D R n
A
c le a r T R F n
T ra n s fe r
F in is h e d ?
N o
Y e s
E N D
SPI Transfer Control Flowchart
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HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
DMA Function
The HT82A525R provides both serial and parallel interface DMA functions. The DMA serial
interface is implemented using one of the SPI interfaces, either SPI1 or SPI2. The parallel DMA is
implemented using Port D.
DMA Overview
For the serial DMA interface, the SPI1 related pins are pin shared with PE0~PE3, and the SPI 2
related pins are pin shared with PC4~PC7. The Parallel DMA data lines are pin shared with Port D,
HSYNC is pin shared with PA4 and the PCLK is pin shared with PA5. When the PDMA bit in the
CLK register is set high, the parallel DMA function will be selected and the data will be written to
FIFO2 directly. The FIFO2 size is 64´3 bytes for parallel DMA Mode. FIFO3 can¢t be use for parallel
DMA Mode.
PSYNC/VSYNC is pin shared with the PA0 pin. VSYNC is used to synchronise the Parallel DMA
data received data and PSYNC is used to synchronise the serial DMA received data. The SCLK is pin
shared with the PB0 pin and used as the clock output for serial or parallel DMA functions. The clock
output is controlled by the SCLKEN and CLKAUTOB bits in the CLK register. The clock output
frequency, 12, 16, 24, 6, 8, 4, 3, 2 MHz is selected by the FSCLK configuration option.
S D M A S E L
M C U
M U X
F IF O 2 o r F IF O 3
P D M A
S P I1
M U X
S P I2
P a r a lle l D M A
DMA Block Diagram
Bit No.
Label
R/W
Function
0
SCLKEN
R/W
SCLK pin output control bit
0: disable; 1: enable
1
CLKAUTOB
R/W
SCLK pin output halt control bit
0: when FIFO3 is full or SCLKEN is ²0² ; 1: when SCLKEN is ²0²
2
PDMA
R/W
Parallel DMA function control bit
0: disable; 1: enable
3
PDATA_SEL
R/W
Parallel DMA data format select bit
0: Receive odd Parallel DMA data only; 1: Receive all Parallel DMA data
4
PDMA_MOD
R/W
Parallel DMA function select bit
0: Fingerprint mode - for fingerprint application only
1: Normal mode, for general purpose application
Fingerprint frame pixel select bit
0: QVGA mode (320´240); 1: CIF mode (352´288)
This bit is used to select the Fingerprint frame pixel if the PDMA_MOD is cleared
to ²0².
5
FIG_PIX
R/W
6~7
¾
¾
Undefined bit, read as ²0²
This control bit is used to control the SCLK output no mater in serial or parallel DMA mode.
CLK Register
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HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
If the PDMA bit is cleared to zero and the SDMAEN bit in the MISC register is set high, then the
serial DMA function will be enabled. The SBDR1 data of the SPI1 or the SBDR2 data of the SPI2,
selected by the SDMSEL bit in the MISC register, will be written to FIFO3.
Serial DMA
In the Serial DMA mode, the SPI1 or SPI2 data, selected by SDMASEL bit, can be written to FIFO3
directly.
SCLK is pin shared with the PB0 pin and used as the clock output for serial or parallel DMA function.
The clock output function is controlled by the SCLKEN and CLKAUTOB bits in the CLK register.
The clock output frequency, (12, 16, 24, 6, 8, 4, 3, 2 MHz), is selected by the FSCLK by configuration
option.
If the SBEN, SDMAEN bits are set high, and PDMA is cleared to zero, the SPI interface DMA will
enter the master mode and start to send out the SCK clock. If the SPI is in the master mode and is used
as a receiver, the SCK clock will be stopped automatically when FIFO3 is full and will restart again
when FIFO3 is not full. If the SPI is in the slave mode and is used as a receiver, if FIFO3 is full, the
SPI will stop receiving data. It will restart again if FIFO3 is not full. The frequency of the SCK is
selected using the CKS, M1 and M0 bits in the SBCR register. Note that the SCK clock output will
stop at a low level if the CPOL bit is set high and stop at a high level if the CPOL bit is cleared to zero.
Each SPI interface can support both master or slave mode DMA. The direction of the SPI DMA is
determined by the SETIO3 bit. The corresponding buffer size of 8, 16, 32 or 64 bytes is determined by
bits DLEN 0~1 by configuration option.
Parallel DMA
In the Parallel DMA mode, HSYNC is pin shared with PA4, PCLK is pin shared with PA5 pin, the
VSYNC is pin shared with PA0 pin and the Parallel DMA data D0~D7 pins are pin shared with
PD0~PD7. HSYNC and the PCLK are used to synchronize the data of the parallel interface pins
which are pin shared with port D.
SCLK is pin shared with the PB0 pin and is used as the clock output for serial or parallel DMA
functions. The clock output function is controlled by the SCLKEN and CLKAUTOB bits in the CLK
register. The clock output frequency of 12, 16, 24, 6, 8, 4, 3 or 2 MHz is selected by the FSCLK
configuration option.
The parallel DMA function can be used in fingerprint mode or normal mode, which is selected using
the PDMA_MOD bit in the CLK register.
In the normal mode, the VSYNC signal of the parallel DMA received data will be ignored. In the
fingerprint mode, there are two frame pixel modes, the QVGA mode (320x240 pixels) or the CIF
mode (352x288 pixels). They are selected by the FIG_PIX bit in the CLK register.
If the PDMA bit is set high, the parallel DMA data will be written to FIFO2, the size of which is 64x3
bytes. There is only a slave mode for the parallel DMA and the data length can be selected as 5 bits or
8 bits by configuration option.
The FIFO2 buffers will start receiving data when HSYNC is set high and stop receiving data when
HSYNC is cleared to zero. If FIFO2 is not full and HSYNC is cleared to zero to stop receiving data,
then FIFO2 should not receive any incoming data. Only the received data in FIFO2 can be delivered
to the Endpoint. Not until the next HSYNC high signal can FIFO2 start receiving data from the next
buffer. If all buffers of the FIFO2 are full before HSYNC has a falling edge, this received data should
be ignored. There are two Parallel DMA data selections, to receive odd Parallel DMA data only or to
receive all Parallel DMA data, selected by the PDATA_SEL bit in the CLK register.
Rev. 1.30
35
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
If VSYNC is enabled, it can be used to synchronize the Parallel DMA data D0~D7. There are two
types of VSYNC control signal. The following diagram illustrates the Parallel DMA interface control
signals.
T 4
H S Y N C
T 3
P C L K
P C L K E = 0 ( o p tio n )
P C L K
P C L K E = 1 ( o p tio n )
D 7 ~ D 0
T 1
T 5
T 2
T 6
V S Y N C
(T y p e 1 )
T 7
V S Y N C
(T y p e 2 )
H S Y N C
D 7 ~ D 0
Symbol
Parameter
Min.
Max.
Unit
PCLK frequency
¾
4
MHz
PCLK duty cycle
45
55
%
T1
Data setup time to PCLK
5
¾
ns
T2
Data hold time to PCLK
7
¾
ns
T3
HSYNC ­ to PCLK delay
5
¾
ns
T4
Horizontal blank time (Thblank)
24
¾
TPCLK
T5
VSYNC(Tpye1) high pulse time
200
¾
ns
T6
VSYNC(Tpye1) ¯ to HSYNC delay time
500
¾
ns
T7
VSYNC(Tpye2) ­ to HSYNC delay time
700
¾
ns
Parallel DMA Data Timing Description
Rev. 1.30
36
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Suspend Wake-Up or Remote Wake-Up
If there is no signal on the signal bus for over 3ms, the HT82A525R will go into suspend mode. The
Suspend line (bit 0 of the USC) will be set to 1 and a USB interrupt is triggered to indicate that the
HT82A525R should jump to suspend state to meet the 500mA USB suspend current spec.
In order to meet the 500mA suspend current, the firmware should disable the USB clock by clearing
the USBCKEN (bit3 of the UCC) to ²0². The suspend current is about 300mA.
The user can also further decrease the suspend current by setting the SUSP2 (bit4 of the UCC). But if the
SUSP2 is set, user should make sure not to enable the LVR option, otherwise, the HT82A525R will be
reset. If user set the SUSP2 (bit4 of the UCC) In the USB mode, user must set Rctrl (bit7 of the UCC)
before set SUSP2 (bit4 of the UCC), otherwise, USB will disconnected.
When the resume signal is sent out by the host, the HT82A525R will wake-up the by USB interrupt
and the Resume line (bit 3 of the USC) is set. In order to make the HT82A525R work properly, the
firmware must set the USBCKEN (bit 3 of the UCC) to 1 and clear the SUSP2 (bit4 of the UCC). If
user set the Rctrl (bit7 of the UCC) and SUSP2 (bit4 of the UCC) In the USB suspend, when it will
wake-up user must clr Rctrl (bit7 of the UCC) before clr SUSP2 (bit4 of the UCC). Since the Resume
signal will be cleared before the Idle signal is sent out by the host and the Suspend line (bit 0 of the
USC) is going to ²0². So when the MCU is detecting the Suspend line (bit0 of USC), the Resume line
should be remembered and taken into consideration.
After finishing the resume signal, the suspend line will go inactive and a USB interrupt is triggered.
The following is the timing diagram:
S U S P E N D
U S B R e s u m e S ig n a l
U S B _ IN T
The device with remote wake-up function can wake-up the USB Host by sending a wake-up pulse
through RMWK (bit 1 of the USC). Once the USB Host receive the wake-up signal from the
HT82A525R, it will send a Resume signal to the device. The timing is as follow:
S U S P E N D
R M W K
U S B R e s u m e S ig n a l
M in . 1 U S B C L K
M in .2 .5 m s
U S B _ IN T
Rev. 1.30
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January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
USB Interface
The HT82A525R has 4 Endpoints (EP0~EP3). EP0~EP1 are support Interrupt transfer, EP2~EP3 is
support Bulk transfer.
There are 12 registers, including USC (20H), USR (21H), UCC (22H), AWR (address+remote
wake-up 23H), STALL (24H), SIES (25H), MISC (26H), SETIO (27H), FIFO0 (28H), FIFO1 (29H),
FIFO2 (2AH) and FIFO3 (2BH) used for the USB function.
The FIFO size of each FIFO is 8 byte (FIFO0), 8 byte (FIFO1), 64 byte (FIFO2) and 128 byte
(FIFO3), and total of 208 bytes.
URD (bit7 of the USC) is USB reset signal control function definition bit.
Bit No.
0
1
2
Label
SUSP
R/W
Function
R
USB suspend indication flag
0: not in suspend mode
1: in suspend mode
When this bit is set to ²1² (set by SIE), it indicates that the USB bus enters the suspend
mode. The USB interrupt is also triggered on any changes of this bit.
RMWK
USB remote wake-up command
0: disable
1: enable
R/W
It is set by the MCU to force the USB host leaving the suspend mode. Set RMWK bit to
²1² to enable remote wake-up. When this bit is set to ²1², a 2ms delay for clearing this
bit to ²0² is needed to insure that the RMWK command is accepted by the SIE.
URST
USB reset indication bit
0: no USB reset
R/W 1: USB reset
This bit is set or cleared by USB SIE. When the URST is set to ²1², this indicates that a
USB reset has occurred and a USB interrupt will be initialized.
3
RESUME
4
V33O
5
PLL
6
¾
7
URD
R
USB resume indication bit
0: in suspend mode
1: resume
When the USB leaves the suspend mode, this bit is set to ²1²
(set by SIE). This bit will appear for 20ms, waiting for the MCU to detect it. When the
RESUME is set by SIE, an interrupt will be generated to wake-up the MCU. In order to
detect the suspend state, MCU should set the USBCKEN and SUSP2 (in the SCC
register) to enable the SIE detect function. The RESUME will be cleared while the
SUSP is set to ²0². When MCU detects the SUSP, the RESUME (which causes MCU
to wake-up) should be remembered and token into consideration.
V33O enable control bit
R/W 0: turn off
1: turn on
PLL enable control bit
R/W 0: turn on
1: turn off
¾
Unused bit, read as ²0²
USB reset signal control function definition
R/W 1: Will reset the MCU
0: Cannot reset the MCU
USC (20H) Definitions
Rev. 1.30
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January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is
accessed. The endpoint request flags (EP0IF, EP1IF, EP2IF and EP3IF) are used to indicate which
endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to ²1²,
and then the USB interrupt takes place or not will depend on the ²Endpoint 0~3 interrupt function² via
the configuration option. If the ²Endpoint 0~3 interrupt function² is configured as ²Disable², then the
USB interrupt will occur (if the USB interrupt is enabled, the corresponding interrupt is enabled and
the stack is not full). If the ²Endpoint 0~3 interrupt function² is configured as ²Enable², the USB
interrupt will need to be managed by the Endpoint Interrupt control bits, EEP0I~EEP3I, in the USR
register as well. The Endpoint Interrupt control bits are used to control which endpoint is accessed and
generate interrupt. Only when the related Endpoint Interrupt control bits are selected as ²Enable², then
the related USB interrupt will take place, otherwise, the USB interrupt will not occur. When the active
endpoint request flag is served, the endpoint request flag has to be cleared to ²0².
Bit No.
Label
R/W
EP0IF
The endpoint 0 interrupt request flag
0: inactive
1: active
R/W
When this bit is set to ²1² (set by SIE), it indicates that the endpoint 0 is accessed and a
USB interrupt will occur. When the interrupt has been served, this bit should be cleared
by firmware.
EP1IF
The endpoint 1 interrupt request flag
0: inactive
1: active
R/W
When this bit is set to ²1² (set by SIE), it indicates that the endpoint 1 is accessed and a
USB interrupt will occur. When the interrupt has been served, this bit should be cleared
by firmware.
EP2IF
The endpoint 2 interrupt request flag
0: inactive
1: active
R/W
When this bit is set to ²1² (set by SIE), it indicates that the endpoint 2 is accessed and a
USB interrupt will occur. When the interrupt has been served, this bit should be cleared
by firmware.
3
EP3IF
The endpoint 3 interrupt request flag
0: inactive
1: active
R/W
When this bit is set to ²1² (set by SIE), it indicates that the endpoint 3 is accessed and a
USB interrupt will occur. When the interrupt has been served, this bit should be cleared
by firmware.
4
EEP0I
The endpoint 0 interrupt enable
R/W 0: disable
1: enable
5
EEP1I
The endpoint 1 interrupt enable
R/W 0: disable
1: enable
6
EEP2I
The endpoint 2 interrupt enable
R/W 0: disable
1: enable
7
EEP3I
The endpoint 3 interrupt enable
R/W 0: disable
1: enable
0
1
2
Function
USR (21H) Definitions
Rev. 1.30
39
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
There is a system clock control register implemented to select the clock used in the MCU. This
register consists of USB clock control bit (USBCKEN), second suspend mode control bit (SUSP2)
and system clock selection (SYSCLK).
If HIRC oscillator is used and for USB mode should enable CLK_adj bit for PSD register to adjust
system clock for temperature.
The following table defines which endpoint FIFO is selected, EPS2, EPS1 and EPS0.
Bit No.
0
1
2
3
Label
R/W
Function
EPS0
EPS1
EPS2
Accessing endpoint FIFO selection.
EPS2, EPS1, EPS0:
000: Select endpoint 0 FIFO
001: Select endpoint 1 FIFO
010: Select endpoint 2 FIFO
R/W 011: Select endpoint 3 FIFO
100: Reserved for future expansion, cannot be used
101: Reserved for future expansion, cannot be used
110: Reserved for future expansion, cannot be used
111: Reserved for future expansion, cannot be used
If the selected endpoints do not exist, the related functions are not available.
USB clock Control bit
USBCKEN R/W 0: disable
1: enable
4
SUSP2
5
¾
6
SYSCLK
7
RCtrl
Suspend mode control bit
0: Normal Mode
R/W 1: HALT Mode
This bit is used to reduce power consumption in suspend mode. In normal mode, clear
this bit to ²0². In HALT mode, set this bit to ²1² to reduce power consumption.
¾
Unused bit, read as ²0²
System clock oscillator frequency control bit
0: 12MHz
1: 6MHz
R/W
This bit is used to specify the system clock oscillator frequency used by the MCU. If a
6MHz crystal oscillator or resonator is used, this bit should be set to ²1². If a 12MHz
crystal oscillator or resonator is used, this bit should be cleared to ²0² .
7.5kW resistor between USBDP and Vbus select bit
R/W 0: without resistor
1: with resistor
UCC (22H) Definitions
The AWR register contains the current address and the remote wake-up function control bit. The initial value of the AWR is ²000H²0. The address value extracted from the USB command is not to be
loaded into this register until the SETUP stage is finished.
Bit No.
Label
R/W
Function
0
WKEN
R/W
Remote wake-up enable/disable
0: disable
1: enable
1~7
AD0~AD6
R/W
USB device address
AWR (23H) Definitions
Rev. 1.30
40
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
The STALL register shows whether the corresponding endpoint works properly or not. As soon as
the endpoint works improperly, the related bit in the STALL has to be set to ²1². The STALL will be
cleared by the USB reset signal.
Bit No.
Label
R/W
0~3
STL0~
STL3
R/W
4~7
¾
¾
Function
stalled USB endpoints control
Undefined bit, read as ²0²
STALL (24H) Definitions
This bit is used to configure the USB SIE to automatically change the device address with the value
of the Address+Remote_WakeUp Register (42H). When this bit is set to 1 by F/W, the USB SIE will
update the device address with the value of the Address+Remote_WakeUp Register (42H) after the
PC Host has successfully read the data from the device by the IN operation. The USB SIE will clear
the bit after updating the device address.
Otherwise, when this bit is cleared to 0, the USB SIE will update the device address immediately after
an address is written to the Address+Remote_WakeUp Register (42H).
The SIES Register is used to indicate the present signal state which the USB SIE received and also
determines whether the USB SIE has to change the device address automatically.
Bit No.
0
Label
Adr_set
R/W
Function
R/W
Device address configuration bit
0: update device address immediately
1: update by the IN operation
accessed FIFO0 errors indication bit
0: no errors
1: some errors
This bit is set by the USB SIE and cleared by F/W.
1
F0_ERR
R/W
2~6
¾
¾
Unused bit, read as ²0²
7
NMI
R/W
NAK interrupt mask bit
0: not mask
1: mask
SIES Function Table
Rev. 1.30
41
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
MISC register combines a command and status to control the desired endpoint FIFO action and to
show the status of the desired endpoint FIFO. The MISC will be cleared by USB reset signal.
Bit No.
0
1
2
Label
REQUEST
TX
CLEAR
R/W
Function
R/W
FIFO request control bit
0: not requested; 1: requested
After selecting the desired endpoint, FIFO can be requested by setting this bit as high
active. Afterwards, this bit must be set low.
R/W
The direction and transition end indication bit
0: read data from FIFO; 1: write data to FIFO
This indicates the direction and transition end which the MCU accesses. When set
as logic ²1², the MCU writes data to FIFO. Afterwards, this bit must be set to logic ²0²
before terminating request to indicate transition end. For reading action, this bit must
be set to logic 0 to indicate that the MCU wants to read and must be set to logic ²1²
afterwards.
R/W
Clear requested FIFO control bit
0: not clear; 1: clear
This indicates an MCU clear requested FIFO, even if the FIFO is not ready. After
clearing the FIFO, USB interface will send force_tx_err to tell Host that data
under-run if Host wants to read data.
3
SDMAEN
R/W
Serial DMA control bit
0: disable; 1: enable
This bit is used to control the enable or disable the SBDR of the serial interfaces
(which is pin-shared with port E or port C) being written to FIFO3 directly.
SPI interfaces can be controlled by MCU and MCU can transmit or receive data by
writing or reading SBDR. It is allowed changing from 1 to 0 when the FIFO is not full.
4
SDMASEL
R/W
Serial DMA interface selection bit
0: Serial interface 1 (pin-shared with port E)
1: Serial interface 2 (pin-shared with port C)
5
SETCMD
R/W
FIFO command data indication bit
0: not SETCMD token; 1: SETCMD token
6
READY
R
7
LEN0
R/W
FIFO ready indication bit
0: not ready to work; 1: ready to work
Host sent 0-sized packet indication bit
0: not 0-sized packet; 1: 0-sized packet
MISC (26H) Definitions
There are some timing constrains and usages illustrated here. By setting the MISC register, MCU
can perform reading, writing and clearing actions. There are some examples shown in the following
table for endpoint FIFO reading, writing and clearing.
Actions
MISC Setting Flow and Status
Read FIFO0 sequence
00H®01H®delay 2ms, check 41H®read* from FIFO0 register and
check not ready (01H)®03H®02H
Write FIFO0 sequence
02H®03H®delay 2ms, check 43H®write* to FIFO0 register and
check not ready (03H)®01H®00H
Check whether FIFO0 can be read or not
00H®01H®delay 2ms, check 41H (ready) or 01H (not ready)®00H
Check whether FIFO0 can be written or not
02H®03H®delay 2ms, check 43H (ready) or 03H (not ready)®02H
Write 0-sized packet sequence to FIFO0
02H®03H®delay 2ms, check 43H®01H®00H
Clear FIFO0 sequence
01H®delay 2ms®05H®delay 2ms®00H
Note: *: There are 2ms existing between 2 reading action or between 2 writing ® action.
Read or Write FIFO Table
Rev. 1.30
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January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
R e q .
R e q .
T x
T x
R e a d y
R e a d y
R e a d F IF O
Bit No.
Label
R/W
0
¾
¾
1~3
SETIO1~3**
R/W
4~7
¾
¾
T im in g
W r ite F IF O
T im in g
Function
Undefined bit, read as ²0²
endpoints input or output pile selection bit
0: output pipe; 1: input pipe
Undefined bit, read as ²0²
SETIO (27H) Register, USB Endpoint 1~Endpoint3 Set IN/OUT Pipe Register
Note:
*USB definition: when the host sends a ²set Configuration², the Data pipe should send the DATA0 (Data
toggle) first. So, when the device receives a ²set configuration² setup command, user needs to toggle this bit
so the next data will send a Data0 first.
**Needs to set the data pipe as an input pile or output pile. The purpose of this function is to avoid the host from
abnormally sending only an IN or OUT token and disables the endpoint.
Label
R/W
Function
FIFOi
R/W
EPi accessing register (i = 0~3). When an endpoint is disabled, the corresponding accessing
register should be disabled.
FIFO0~FIFO3 (28H~2BH) Register, USB Endpoint Accessing Registers Definitions
Bit No.
Label
R/W
Function
0
PS2_DAO
R/W
USBDM/DATA pin output control bit
0: output ²low²; 1: output ²high²
This control bit is used to generate the USBDM/DATA pin output signal in the 3D PS2
mouse mode. The default value is ²1².
1
PS2_CKO
USBDP/CLK pin output control bit
0: output ²low²; 1: output ²high²
R/W
This control bit is used to generate the USBDP/CLK pin output signal in the 3D PS2
mouse mode. The default value is ²1².
2
¾
¾
3
PU
R/W
Undefined bit, read as unknown
USBDP and USBDM internal 310kW pull-high resistor select bit
0: without pull up resistor; 1: with pull up resistor
4
CLK_adj
Automatic Clock adjustment control bit
0: disable (default); 1:enable
R/W This bit is used to adjust the HIRC mode system clock, to reduce the frequency
deviation due to temperature issue.
In the Power-down mode, this bit should be clear to reduce power consumption.
5
CLR_RCP
This bit is must enable and then disable by F/W to clear HIRC initial parameters after
R/W power on.
0: disable (default); 1:enable
6~7
¾
¾
Undefined bit, read as ²0²
PSD (3AH) Register
Rev. 1.30
43
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Pulse Width Modulator
The device contains three Pulse Width Modulation PWM outputs. Useful for such applications such
as motor speed control, the PWM function provides an output with a variable frequency, and with a
duty cycle that can be varied by setting particular values into the corresponding register pair.
Channel
PWM Mode
Output Pin
Register Names
0
8+4
PA1
PWM0DRL~
PWM0DRH
1
8+4
PA2
PWM1DRL~
PWM1DRH
2
8+4
PA3
PWM2DRL~
PWM2DRH
PWM Registers
Three register, located in the Data Memory are assigned to each Pulse Width Modulator output and
are known as the PWM registers. It is in each register pair that the 12-bit value, which represents the
overall duty cycle of one modulation cycle of the output waveform, should be placed. The PWM
registers also contain the enable/disable control bit for the PWM outputs. To increase the PWM
modulation frequency, each modulation cycle is modulated into sixteen individual modulation
sub-sections, known as the 8+4 mode. Note that it is only necessary to write the required modulation
value into the corresponding PWM register as the subdivision of the waveform into its
sub-modulation cycles is implemented automatically within the microcontroller hardware.
This method of dividing the original modulation cycle into a further 16 sub-cycles enables the
generation of higher PWM frequencies, which allow a wider range of applications to be served. As
long as the periods of the generated PWM pulses are less than the time constants of the load, the
PWM output will be suitable as such long time constant loads will average out the pulses of the PWM
output. The difference between what is known as the PWM cycle frequency and the PWM
modulation frequency should be understood.
As the PWM clock is defined by register PWMBR and the system clock fSYS or fSYS/4 (chosen via the
PWMn_S bit), and as the PWM value is 12-bits wide, the overall PWM cycle frequency ( fPWM ) as the
following equation and the corresponding PWM modulation frequency for 8+4 mode is fPWM /256 .
1
, when PWMn_S=0
(1/ fSYS)x(PWMBRn + 1)
1
fPWM=
, when PWMn_S=1
(4 / fSYS)x(PWMBRn + 1)
fPWM=
where PWMBRn=0~255 and fSYS may be 6MHz, 12MHz , n=0~2 , according register whether it is
PWM0, PWM1 or PWM2
Rev. 1.30
PWM Modulation
Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
fPWM/256
fPWM/4096
(PWM register value)/4096
44
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
8+4 PWM Mode Modulation
Each full PWM cycle, as it is 12-bits wide, has 4096 clock periods. However, in the 8+4 PWM mode,
each PWM cycle is subdivided into sixteen individual sub-cycles known as modulation cycle 0 ~
modulation cycle 15, denoted as ²i² in the table. Each one of these sixteen sub-cycles contains 256 clock
cycles. In this mode, a modulation frequency increase of sixteen is achieved. The 12-bit PWM register
value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The
first group which consists of bit4~bit11 is denoted here as the DC value. The second group which
consists of bit0~bit3 is known as the AC value. In the 8+4 PWM mode, the duty cycle value of each of
the two modulation sub-cycles is shown in the following table.
Parameter
Modulation cycle i
(i=0~15)
AC (0~15)
DC (Duty Cycle)
i < AC
DC+1
256
i ³ AC
DC
256
8+4 Mode Modulation Cycle Values
The accompanying diagram illustrates the waveforms associated with the 8+4 mode of PWM
operation. It is important to note how the single PWM cycle is subdivided into 16 individual
modulation cycles, numbered 0~15 and how the AC value is related to the PWM value.
PWM Output Control
The three outputs, PWM0, PWM1, and PWM2 are shared with pins PA1, PA2 and PA3. To operate as
a PWM output and not as an I/O pin, bit 0 of the relevant PWM low byte register bit must be set high.
A zero must also be written to the corresponding bit in the PAC port control register, to ensure that the
PWM0~2 output pin is setup as an output. After these two initial steps have been carried out, and of
course after the required PWM 12-bit value has been written into the PWM register pair register,
setting the corresponding bit in the PA data register high will enable the PWM data to appear on the
pin. Writing a zero to the bit will disable the PWM output function and force the output low. In this
way, the Port A data output register bits, can also be used as an on/off control for the PWM function.
Note that if the enable bit in the PWM register is set high to enable the PWM function, but if the
corresponding bit in the PAC control register is high to configure the pin as an input, then the pin can
still function as a normal input line, with pull-high resistor selections.
Rev. 1.30
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January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
PWM Programming Example
The following sample program shows how the output is setup and controlled.
mov
mov
clr
clr
set
set
:
:
clr
fP
a,64h
pwm0h,a
pwm0l
pac.1
pwm0en
pa.1
:
:
pa.1
;
;
;
;
;
;
setup PWM0 value to 1600 decimal which is 640H
setup PWM0H register value
setup PWM0L register value
setup pin PA1 as an output
set the PWM0 enable bit
Enable the PWM0 output
; PWM0 output disabled - PA1 will remain low
W M
[P W M ] = 1 6 0 0
P W M
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 1 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 1 /2 5 6
1 0 1 /2 5 6
1 0 1 /2 5 6
1 0 0 /2 5 6
1 0 0 /2 5 6
1 0 1 /2 5 6
1 0 0 /2 5 6
1 0 1 /2 5 6
[P W M ] = 1 6 0 1
P W M
[P W M ] = 1 6 0 2
P W M
[P W M ] = 1 6 1 5
P W M
1 0 1 /2 5 6
P W M
1 0 1 /2 5 6
m o d u la tio n p e r io d : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
1 0 1 /2 5 6
M o d u la tio n c y c le 1
M o d u la tio n c y c le 2
c y c le : 4 0 9 6 /fP
P W M
M o d u la tio n c y c le 1 5
M o d u la tio n c y c le 0
W M
8+4 PWM Mode
P W M 0 D R H ~ P W M 2 D R H
H ig h B y te R e g is te r s
b 7
1 1
1 0
9
8
7
6
5
P W M 0 D R L ~ P W M 2 D R L
L o w B y te R e g is te r s
b 0
4
b 7
3
2
1
0
P W M n _ S
b 0
P W M n _ E N
P W M R e g is te r s
P W M O n /O ff C o n tro l
1 : P W M e n a b le
0 : I/O p in e n a b le
P W M n b a s e p e r io d r e g is te r fr e q u e n c y s o u r c e
1 : fS Y S /4
0 : fS Y S ( d e fa u lt)
N o t im p le m e n te d , r e a d a s " 0 "
P W M A C
b its 0 ~ 3
V a lu e
P W M D C V a lu e
b its 4 ~ 1 1
PWM Register Pairs
Bit
R/W
7~0
R/W
Description
Used to define the base period of the PWM
Range =1 ~ 256 ´ (1/fSYS or 4/fSYS chosen via the PWMn_S bit)
where PWMBRn=0~255 (n= 0~2)
PWM Base Period Register PWMBR0 ~ PWMBR2
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COM Function for LCD
The devices have the capability of driving external LCD panels. The common pins for LCD driving,
COM0~COM3, are pin shared with certain pin on the PD0~ PD3 port. The LCD signals (COM and
SEG) are generated using the application program.
LCD Operation
An external LCD panel can be driven using this device by configuring the PD0~PD3 pins as common
pins and using other output ports lines as segment pins. The LCD driver function is controlled using
the LCDC register which in addition to controlling the overall on/off function also controls the bias
voltage setup function. This enables the LCD COM driver to generate the necessary
VDDIO/2 voltage levels for LCD 1/2 bias operation. The LCDEN bit in the LCDC register is the
overall master control for the LCD Driver, however this bit is used in conjunction with the COMnEN
bits to select which Port D pins are used for LCD driving. Note that the Port Control register does not
need to first setup the pins as outputs to enable the LCD driver operation. If the parallel DMA
function is disabled, PDMA control bit is set to ²0², and the COMnEN bits is set to ²1² will enable the
corresponding LCD COM driving waveform to Port D pins.
V
D D IO
C O M
V
D D IO
o p e r a tin g c u r r e n t
/2
C O M 0 ~ C O M 3
C O M n E N
L C D E N
LCD COM Circuit
LCDEN
COMnEN
Pin Function
O/P Level
0
X
I/O
0 or 1
1
0
I/O
0 or 1
1
1
COMn
VDDIO/2
Output Control
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I/O Type USB 8-Bit OTP MCU with SPI
LCD Bias Control
The LCD COM driver enables two kinds of selection to be provided to suit the requirement of the
LCD panel which is being used. The bias resistor choice is implemented using the RSEL0 and
RSEL1 bits in the LCDC register.
Bit No.
Label
R/W
Function
0
COM0EN
R/W
PD3 or COM0 selection
0: GPIO
1: COM3
1
COM1EN
R/W
PD3 or COM1 selection
0: GPIO
1: COM3
2
COM2EN
R/W
PD3 or COM2 selection
0: GPIO
1: COM3
3
COM3EN
R/W
PD3 or COM3 selection
0: GPIO
1: COM3
4
LCDEN
R/W
COM module control
0: disable
1: enable
5
6
RSEL0
RSEL1
R/W
Select SCOM typical bias current (VDD=5V)
00: 25mA
01: 50mA
10: 100mA
11: 200mA
7
¾
R/W
Reserved bit
0: correct level, bit must be reset to zero for correct operation
1: unpredictable operation, bit must not be set high
LCDC Register (3BH)
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Options
The following table shows all kinds of OTP option in the microcontroller. All of the OTP options
must be defined to ensure proper system functioning. The default values of the options are ²0².
No.
Option
I/O Options
1
PA0~PA7 wake-up function: enable or disable -- bit option
2
PA0~PA7 pull-high resistor function: enable or disable -- bit option
3
PB0~PB7 pull-high resistor function: enable or disable -- bit option
4
PB0~PB7 wake-up function: enable or disable -- nibble option
5
PB0~PB7 output structure option: CMOS or NMOS -- bit option
6
PC0~PC7 pull-high resistor option: enable or disable -- nibble option
7
PC0~PC7 wake-up function: enable or disable -- nibble option
8
PD0~PD7 pull-high resistor function: enable or disable -- nibble option
9
PD0~PD7 wake-up function: enable or disable -- nibble option
10
PE0~PE7 pull-high resistor function: enable or disable -- nibble option
11
PE0~PE7 wake-up function: enable or disable -- nibble option
12
PF0~PF1 pull-high resistor function: enable or disable -- nibble option
13
PF0~PF1 wake-up function: enable or disable -- nibble option
Oscillator Option
14
OSC, OSC mode selection: external crystal or internal RC OSC
SPI Options
15
SCLK function: enable or disable
16
FSCLK; SCLK frequency selection: 12MHz, 16MHz, 24MHz, 6MHz, 8MHz, 4MHz, 3MHz, 2MHz
17
SPI1 function: enable or disable
18
SPI1 WCOL function: enable or disable
19
SPI1 CSEN function: enable or disable
20
SPI1 Clock polarity selection: Rising or Falling edge
21
SPI1 data output mode option
22
SPI2 data output mode option
23
PCLK function: enable or disable
24
SPI2 function: enable or disable
25
SPI2 WCOL function: enable or disable
26
SPI2 CSEN function: enable or disable
27
SPI2 clock polarity selection: rising or falling edge
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I/O Type USB 8-Bit OTP MCU with SPI
No.
Option
DMA Options
28
PSYNC/VSYNC function: enable or disable
29
Parallel DMA data length option: 8bit or 5bit
30
DLEN;SPI DMA FIFO output data length option: 64 bytes, 32 bytes, 16 bytes, 8 bytes
31
HSYNC function: enable or disable
32
PCLKE clock polarity option: rising or falling edge
WDT Options
33
WDT function: enable or disable
34
WDT clock source option: fSYS/4 or WDTOSC
35
WDT timeout period option: 213/fS, 214/fS, 215/fS, 216/fS
36
Timer out WDT clear mode option: half WDT clear or full WDT clear
USB Options
37
EP1, EP2, EP3 data pipe function: enable or disable
38
Endpoint 0~3 interrupt function: enable or disable
LVR Option
39
LVR enable or disable
Other Options
40
TBHP enable or disable
41
VSEL; LCD COM voltage option (ICE only): 3.3V or 5.0V
Application Circuits
V D D
H V D D
A V D D
V D D IO
0 .1 m F *
V D D
U S B -
1 0 m F *
U S B +
1 0 0 k W
0 .1 m F * *
V S S
P A 0 ~ P A 7
P B 0 ~ P B 7
P C 0 ~ P C 7
P D 0 ~ P D 7
O S C I/P F 0
P E 0 ~ P E 7
V 3 3 O
X 1
O S C O /P F 1
0 .1 m F
1 0 k W
R E S
A V S S
V S S
U S B D M
U S B D P
1 .5 k W
0 .1 m F
3 3 W
3 3 W
H T 8 2 A 5 2 5 R
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that VDD is
stable and remains within a valid operating voltage range before bringing RES high.
X1 can use 6MHz or 12MHz, X1 as close OSCI & OSCO as possible.
* These capacitors should be placed close to the USB connector.
** This capacitor should be placed close to the MCU.
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I/O Type USB 8-Bit OTP MCU with SPI
Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case of
Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5ms and branch or call instructions would be implemented within
1ms. Although instructions which require one more cycle to implement are generally limited to the
JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be ²CLR PCL² or ²MOV PCL, A². For the case of skip instructions, it must be noted that if the
result of the comparison involves a skip operation then this will also take one more cycle, if no skip is
involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used operations.
Making use of three kinds of MOV instructions, data can be transferred from registers to the
Accumulator and vice-versa as well as being able to move specific immediate data directly into the
Accumulator. One of the most important data transfer applications is to receive data from the input
ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
Logical and Rotate Operations
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving data
manipulation, data must pass through the Accumulator which may involve additional programming
steps. In all logical data operations, the zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC
and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions
exist depending on program requirements. Rotate instructions are useful for serial port programming
applications where data can be rotated from an internal register into the Carry bit from where it can be
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I/O Type USB 8-Bit OTP MCU with SPI
examined and the necessary serial bit set high or low. Another application where rotate data
operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction or
to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine
call, the program must return to the instruction immediately when the subroutine has been carried out.
This is done by placing a return instruction RET in the subroutine which will cause the program to
jump back to the address right after the CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is no requirement to jump back to the original
jumping off point as in the case of the CALL instruction. One special and extremely useful set of
branch instructions are the conditional branches. Here a decision is first made regarding the condition
of a certain data memory or individual bits. Depending upon the conditions, the program will
continue with the next instruction or skip over it and jump to the following instruction. These
instructions are the key to decision making and branching within the program perhaps determined by
the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the ²SET [m].i² or ²CLR [m].i²
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the
Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory
to be setup as a table where data can be directly stored. A set of easy to use instructions provides the
means by which this fixed data can be referenced and retrieved from the Program Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as the
²HALT² instruction for Power-down operations and instructions to control the operation of the
Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
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Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.
Table conventions:
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles Flag Affected
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
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Mnemonic
Description
Cycles Flag Affected
Bit Operation
CLR [m].i
SET [m].i
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (locate by TBLP and TBHP) to data memory and TBLH
Read ROM code (current page) to data memory and TBLH
Read table (last page) to TBLH and Data Memory
2Note
2Note
2Note
None
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m](4)
TABRDC [m](5)
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and ²CLR WDT2² instructions
are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
4. Configuration option ²TBHP option² is enabled
5. Configuration option ²TBHP option² is disabled
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result
is stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical
AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto
the stack. The specified address is then loaded and the program continues execution
from this new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2
will have no effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1
will have no effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement).
Bits which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement).
Bits which previously contained a 1 are changed to 0 and vice versa. The complemented
result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater
than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the
low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set,
then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is
performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag
conditions. Only the C flag may be affected by this instruction which indicates that if the
original BCD sum is greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared.
The power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.30
57
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a
dummy instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.30
58
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR
operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be
processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into
bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into
bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.30
59
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit
7 replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated
into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit.
Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.30
60
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if
the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result
is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Data Memory. Note that if
the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result
is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0
the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0
the program proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0,
the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a
dummy instruction while the next instruction is fetched, it is a two cycle instruction. If
the result is not 0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.30
61
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0,
the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0
the program proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0,
the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a
dummy instruction while the next instruction is fetched, it is a two cycle instruction. If
the result is not 0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C
flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to
1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C
flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to
1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag
will be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.30
62
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped.
As this requires the insertion of a dummy instruction while the next instruction is
fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the
following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is
not 0 the program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP)
is moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.30
63
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
TABRDC [m]
Move the ROM code (locate by TBLP and TBHP) to TBLH and data memory (ROM
code TBHP is enabled)
Description
The low byte of ROM code addressed by the table pointers (TBLP and TBHP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR
operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical
XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.30
64
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Package Information
24-pin SSOP (150mil) Outline Dimensions
1 3
2 4
A
B
1
1 2
C
C '
G
D
E
Symbol
a
F
Dimensions in inch
Min.
Nom.
Max.
A
0.228
¾
0.244
B
0.150
¾
0.157
C
0.008
¾
0.012
C¢
0.335
¾
0.346
D
0.054
¾
0.060
E
¾
0.025
¾
F
0.004
¾
0.010
G
0.022
¾
0.028
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
Dimensions in mm
Min.
Nom.
Max.
5.79
¾
6.20
B
3.81
¾
3.99
C
0.20
¾
0.30
C¢
8.51
¾
8.79
D
1.37
¾
1.52
E
¾
0.64
¾
F
0.10
¾
0.25
G
0.56
¾
0.71
H
0.18
¾
0.25
a
0°
¾
8°
A
Rev. 1.30
H
65
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
SAW Type 32-pin (5mm´5mm) QFN Outline Dimensions
D
2 5
D 2
3 2
2 4
b
1
E
E 2
e
1 7
8
1 6
A 1
A 3
L
9
K
A
Symbol
Nom.
Max.
A
0.028
¾
0.031
A1
0.000
¾
0.002
A3
¾
0.008
¾
b
0.007
¾
0.012
D
¾
0.197
¾
E
¾
0.197
¾
e
¾
0.020
¾
D2
0.049
¾
0.128
E2
0.049
¾
0.128
L
0.012
¾
0.020
K
¾
¾
¾
Symbol
Rev. 1.30
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
0.70
¾
0.80
A1
0.00
¾
0.05
A3
¾
0.20
¾
b
0.18
¾
0.30
D
¾
5.00
¾
E
¾
5.00
¾
e
¾
0.50
¾
D2
1.25
¾
3.25
E2
1.25
¾
3.25
L
0.30
¾
0.50
K
¾
¾
¾
66
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
48-pin LQFP (7mm´7mm) Outline Dimensions
C
3 6
D
2 5
3 7
A
G
H
I
2 4
F
B
E
4 8
1 3
1
Symbol
a
1 2
Dimensions in inch
Min.
Nom.
Max.
A
0.350
¾
0.358
B
0.272
¾
0.280
C
0.350
¾
0.358
D
0.272
¾
0.280
E
¾
0.020
¾
F
¾
0.008
¾
G
0.053
¾
0.057
H
¾
¾
0.063
I
¾
0.004
¾
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
A
Rev. 1.30
K
Dimensions in mm
Min.
Nom.
Max.
8.90
¾
9.10
B
6.90
¾
7.10
C
8.90
¾
9.10
D
6.90
¾
7.10
E
¾
0.50
¾
F
¾
0.20
¾
G
1.35
¾
1.45
H
¾
¾
1.60
I
¾
0.10
¾
J
0.45
¾
0.75
K
0.10
¾
0.20
a
0°
¾
7°
67
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
64-pin LQFP (7mm´7mm) Outline Dimensions
C
D
4 8
G
3 3
H
I
3 2
4 9
F
A
B
E
6 4
1 7
K
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.350
¾
0.358
B
0.272
¾
0.280
C
0.350
¾
0.358
D
0.272
¾
0.280
E
¾
0.016
¾
F
0.005
¾
0.009
G
0.053
¾
0.057
H
¾
¾
0.063
I
0.002
¾
0.006
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
A
Rev. 1.30
J
1 6
1
a
Dimensions in mm
Min.
Nom.
Max.
8.90
¾
9.10
B
6.90
¾
7.10
C
8.90
¾
9.10
D
6.90
¾
7.10
E
¾
0.40
¾
F
0.13
¾
0.23
G
1.35
¾
1.45
H
¾
¾
1.60
I
0.05
¾
0.15
J
0.45
¾
0.75
K
0.09
¾
0.20
a
0°
¾
7°
68
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Reel Dimensions
D
T 2
A
C
B
T 1
SSOP 24S (150mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.30
13.0
+0.5/-0.2
2.0±0.5
16.8
+0.3/-0.2
22.2±0.2
69
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
D 1
P
B 0
C
K 0
A 0
R e e l H o le
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SSOP 24S (150mil)
Symbol
Description
Dimensions in mm
16.0
+0.3/-0.1
W
Carrier Tape Width
P
Cavity Pitch
E
Perforation Position
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.5
D1
Cavity Hole Diameter
1.50
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
9.5±0.1
K0
Cavity Depth
2.1±0.1
8.0±0.1
1.75±0.10
7.5±0.1
+0.1/-0.0
+0.25/-0.00
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
Rev. 1.30
70
January 14, 2011
HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
71
January 14, 2011