HOLTEK HT83B60

Voice Mask MCU
HT83B60
Revision: V1.00
Date: �����������������
December 19, 2011
HT83B60
Voice Mask MCU
Table of Contents
Features............................................................................................................. 5
General Description.......................................................................................... 5
Block Diagram................................................................................................... 6
Pin Assignment................................................................................................. 6
Pin Description................................................................................................. 7
Absolute Maximum Ratings............................................................................. 8
D.C. Characteristics.......................................................................................... 8
A.C. Characteristics........................................................................................ 10
Power-on Reset Characteristics.................................................................... 10
Characteristics Curves....................................................................................11
R vs. F (External RC) Chart Characteristics Curve at 25°C....................................................11
T vs. F (External RC) Chart Characteristics Curve.................................................................11
V vs. F (HIRC) Chart Characteristics Curve at 25°C − Trimmed at 5V.................................. 12
System Architecture....................................................................................... 13
Clocking and Pipelining.......................................................................................................... 13
Program Counter.................................................................................................................... 14
Stack...................................................................................................................................... 15
Arithmetic and Logic Unit − ALU............................................................................................ 15
Program Memory............................................................................................ 16
Structure................................................................................................................................. 16
Special Vectors...................................................................................................................... 16
Look-up Table......................................................................................................................... 17
Table Program Example......................................................................................................... 18
Data Memory................................................................................................... 19
Structure................................................................................................................................. 19
General Purpose Data Memory............................................................................................. 20
Special Purpose Data Memory.............................................................................................. 20
Special Function Registers............................................................................ 20
Indirect Addressing Registers − IAR0.................................................................................... 20
Memory Pointers − MP0........................................................................................................ 22
Accumulator − ACC................................................................................................................ 22
Program Counter Low Register − PCL................................................................................... 23
Look-up Table Registers - TBLP, TBLH.................................................................................. 23
Watchdog Timer Register - WDTS......................................................................................... 23
Status Register − STATUS..................................................................................................... 23
Interrupt Control Register - INTC, INTCH.............................................................................. 24
Timer Registers...................................................................................................................... 24
Input/Output Ports and Control Registers.............................................................................. 25
Port C Pull-high Control Register - PCPHC........................................................................... 25
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December 19, 2011
HT83B60
Voice Mask MCU
Voice Control and Audio output Registers - DAL, DAH, VOL................................................. 25
Pulse Width Modulator Registers - PWMC, PWML, PWMH.................................................. 25
Serial Interface Module (SIM) Registers - SIMC0A/B, SIMC1A/B, SIMC2A/B,
SIMARA/B, SIMDRA/B........................................................................................................... 25
Input/Output Ports.......................................................................................... 26
Pull-high Resistors................................................................................................................. 26
Port A Wake-up...................................................................................................................... 26
I/O Port Control Registers...................................................................................................... 26
Pin-shared Functions............................................................................................................. 28
Programming Considerations................................................................................................. 28
Timers.............................................................................................................. 29
Configuring the Timer Input Clock Source............................................................................. 29
Timer Registers - TMR0, TMR1............................................................................................. 29
Timer Control Registers - TMR0C, TMR1C........................................................................... 30
Configuring the Timer............................................................................................................. 31
Prescaler................................................................................................................................ 31
Programming Considerations................................................................................................. 31
Timer Program Example........................................................................................................ 32
Time Base........................................................................................................ 33
Time Base Operation............................................................................................................. 33
Time Base Example............................................................................................................... 33
Serial Interface................................................................................................ 34
SPI Interface.......................................................................................................................... 34
I2C Interface........................................................................................................................... 40
Voice ROM Access.......................................................................................... 47
Voice ROM SPI Modes.......................................................................................................... 47
Voice ROM Read Commands................................................................................................ 48
Voice Output.................................................................................................... 50
Voice Control.......................................................................................................................... 50
Audio Output and Volume Control - DAL, DAH, VOL............................................................. 50
Pulse Width Modulation Output.................................................................... 51
Pulse Width Modulator Operation.......................................................................................... 51
Interrupts......................................................................................................... 53
Interrupt Register................................................................................................................... 53
Interrupt Operation................................................................................................................. 54
Interrupt Priority...................................................................................................................... 55
Time Base Interrupt................................................................................................................ 55
Timer Interrupt........................................................................................................................ 55
Serial Interface Module - SIM - Interrupt................................................................................ 55
Programming Considerations................................................................................................. 56
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HT83B60
Voice Mask MCU
Reset and Initialisation................................................................................... 56
Reset Functions..................................................................................................................... 57
Reset Initial Conditions.......................................................................................................... 58
Oscillator......................................................................................................... 60
External Crystal/Resonator Oscillator.................................................................................... 60
External RC Oscillator............................................................................................................ 61
Internal RC Oscillator............................................................................................................. 61
Watchdog Timer Oscillator..................................................................................................... 61
Power Down Mode and Wake-up................................................................... 62
Power Down Mode................................................................................................................. 62
Entering the Power Down Mode............................................................................................ 62
Standby Current Considerations............................................................................................ 62
Wake-up................................................................................................................................. 63
Low Voltage Reset - LVR................................................................................ 63
Low Voltage Detector - LVD........................................................................... 64
Operation............................................................................................................................... 64
Watchdog Timer.............................................................................................. 64
Configuration Options.................................................................................... 66
Application Circuits........................................................................................ 67
Instruction Set................................................................................................. 68
Introduction............................................................................................................................ 68
Instruction Timing................................................................................................................... 68
Moving and Transferring Data................................................................................................ 68
Arithmetic Operations............................................................................................................. 68
Logical and Rotate Operations............................................................................................... 69
Branches and Control Transfer.............................................................................................. 69
Bit Operations........................................................................................................................ 69
Table Read Operations.......................................................................................................... 69
Other Operations.................................................................................................................... 69
Instruction Set Summary........................................................................................................ 70
Instruction Definition...................................................................................... 72
Package Information...................................................................................... 81
28-pin SOP (300mil) Outline Dimensions.............................................................................. 81
Reel Dimensions.................................................................................................................... 82
Carrier Tape Dimensions........................................................................................................ 83
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HT83B60
Voice Mask MCU
Features
• Operating voltage: 2.2V~5.5V
• System clock: 4MHz~12MHz
• Three oscillators:
♦♦
External Crystal-HXT
♦♦
External RC-ERC
♦♦
Internal RC-HIRC
• Fully integrated internal HIRC 4MHz, 8MHz and 12MHz oscillators require no external
components
• Up to 15 I/O pins
• Serial Interface Module- SIM for SPI or I2C, shared with PB
• Mask ROM: 2Kx16
• Data Memory: 208x8
• Voice ROM: 8M bits
• Two 8-bit programmable timer counter with 8-stage prescaler and one time base counter
• 12-bit high quality voltage type D/A output
• PWM circuit can directly drive speaker
• Watchdog Timer function
• 8-level subroutine nesting
• 2.7V Low voltage detection, tolerance 5%
• 2.2V Low voltage reset, tolerance 5%
• Power-down function and wake-up functions reduce power consumption
• 63 powerful instructions
• 28-pin SOP package
General Description
The HT83B60 is the Mask version of the HT83F02 but also includes an integrated 8M bits of Voice
ROM, connected to the MCU by an internal SPI Serial Interface. This 8-bit high performance
microcontroller includes a wide range of functions and special audio features which include a voice
synthesizer and tone generator.
This device is designed for applications which require multiple I/Os and sound effects, such as
voice and melody. It also includes an integrated high quality, voltage type DAC as well as a PWM
generator.
This device will form an excellent solution for versatile voice and sound effect product applications
with their efficient MCU instructions providing the user with programming capability for powerful
custom applications. The system frequency can be up to 12MHz at an operating voltage of 5V and
includes power-down functions to reduce power consumption. A full choice of oscillator functions
are provided including a fully integrated system oscillator which requires no external components
for its implementation.
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HT83B60
Voice Mask MCU
Block Diagram
The following block diagram illustrates the main functional blocks.
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P A 1
1
2 8
P A 2
P A 0
2
2 7
P A 3
P B 0 /S D O B /S D A B
3
2 6
P A 4
P B 1 /S C K B /S C L B
4
2 5
P A 5
P B 2 /S D IB
5
2 4
P A 6
* P B 4 /S D O A /S D A A
6
2 3
P A 7
* P B 5 /S C K A /S C L A
7
2 2
V S S
* P B 6 /S D IA
8
2 1
V D D
* P B 7 /S C S A
9
2 0
V D D _ P B IO
P C 1 /O S C 1
1 0
1 9
P C 0 /R E S
P C 2 /O S C 2
1 1
1 8
V S S P
V S S A
1 2
1 7
P W M 2
A U D
1 3
1 6
P W M 1
V D D A
1 4
1 5
V D D P
*: Note that the pins, SDOA, SDIA, SCKA and SCSAB, are dedicated for control of the internal
voice memory and should not be used for other functions. Care should be taken regarding these pinshared I/O pin settings and no external connections should be made to these pins.
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HT83B60
Voice Mask MCU
Pin Description
Pin Name
PA0~PA7
PB0/SDOB/SDAB
Function
OPT
I/T
O/T
Description
PAn
CO
ST
CMOS
General purpose I/O. Configuration option
determined pull-high resistors and wake up
function.
PB0
CO
ST
CMOS
General purpose I/O. Configuration option
determined pull-high resistors.
SDOB
CO
-
CMOS
SIMB SPI data output pin
SDAB
CO
ST
CMOS
SIMB I2C data pin
PB1
CO
ST
CMOS
General purpose I/O. Configuration option
enabled pull-up. Software instructions
determine if the pin is a CMOS output or
Schmitt trigger input.
SCKB
CO
ST
CMOS
SIMB SPI clock pin
SCLB
CO
ST
CMOS
SIMB I2C clock pin
PB2
CO
ST
CMOS
General purpose I/O. Configuration option
enabled pull-up. Software instructions
determine if the pin is a CMOS output or
Schmitt trigger input.
SDIB
CO
ST
-
PB4
CO
ST
CMOS
SDOA
CO
-
CMOS
SDAA
CO
STI
CMOS
PB5
CO
ST
CMOS
SCKA
CO
ST
CMOS
SCLA
CO
ST
CMOS
PB6
CO
ST
CMOS
SDIA
CO
ST
-
PB7
CO
ST
CMOS
SCSAB
CO
ST
-
PC0
PCPHC
ST
CMOS
RES
CO
ST
-
PB1/SCKB/SCLB
PB2/SDIB
PB4/SDOA/SDAA
PB5/SCKA/SCLA
PB6/SDIA
PB7/SCSAB
PC0/RES
PC1/OSC1
PC2/OSC2
AUD
PWM1,PWM2
VDD_PBIO
Rev. 1.00
PC1
PCPHC
ST
CMOS
OSC1
CO
HXT
-
SIMB SPI data input pin
Internal voice memory control pin. PB4
should be selected as input pin by software
instructions and disable the internal pull up by
configuration option and select as SIMA SPIA
data output pin, SDOA.
Should be left no external connection.
Internal voice memory control pin. PB5
should be selected as input pin by software
instructions and enable the internal pull up by
configuration option and select SIMA SPI clock
output pin, SCKA.
Should be left no external connection.
Internal voice memory control pin. PB6
should be selected as input pin by software
instructions and enable the internal pull up by
configuration option and select SIMA SPI data
input pin, SDIA.
Should be left no external connection.
Internal voice memory control pin. PB7
should be selected as input pin by software
instructions and enable the internal pull up
by configuration option and select SIMA SPI
Slave select pin, SCSAB.
Should be left no external connection.
General purpose I/O. Register enabled pull-up.
Reset pin
General purpose I/O. Register enabled pull-up
PC2
PCPHC
ST
CMOS
OSC2
CO
-
HXT
DAC output
-
-
CMOS
DAC output
PWMn
PB power
supply
-
-
CMOS
-
PWR
-
PWM circuit direct drive speaker
PB I/O external positive power supply,
determine by option.
7
General purpose I/O. Register enabled pull-up
December 19, 2011
HT83B60
Voice Mask MCU
Pin Name
Function
OPT
I/T
O/T
VDDA
DAC power
supply
-
PWR
-
Positive DAC circuit Power supply
VDDP
PWM power
supply
-
PWR
-
PWM positive power supply
VSSA
Ground
-
PWR
-
Negative DAC circuit power supply, ground
VSSP
PWM
ground
-
PWR
-
PWM negative power supply, ground
Note:
Description
I/T: Input type
O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power
CO: Configuration option
ST: Schmitt Trigger input
CMOS: CMOS output
Absolute Maximum Ratings
Supply Voltage ......................... VSS-0.3V to VSS +6.0V
Storage Temperature ........................... -50°C to 125°C
Input Voltage ............................VSS-0.3V to VDD +0.3V
Operating Temperature ......................... -40°C to 85°C
IOL Total..............................................................100mA
IOH Total............................................................ -100mA
Total Power Dissipation����������������������������������� 500mV
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings”
may cause substantial damage to the device. Functional operation of this device at other conditions beyond
those listed in the specification is not implied and prolonged exposure to extreme conditions may affect
device reliability.
D.C. Characteristics
Ta=25°C
Symbol
VDD1
VDD2
VDD3
VDD
Operating Voltage
(Crystal OSC)
Test Conditions
Conditions
fSYS=8MHz
—
fSYS=10MHz
Operating Voltage
(External RC OSC)
—
Operating Voltage (High
Frequency Internal RC OSC)
—
Parameter
3V
5V
IDD1
Operating Current
(Crystal OSC, fSYS=fH)
3V
5V
3V
5V
Rev. 1.00
Min.
Typ.
Max.
Unit
2.2
—
5.5
V
2.7
—
5.5
V
fSYS=12MHz
3.3
—
5.5
V
fSYS=6MHz
2.2
—
5.5
V
fSYS=8MHz
2.7
—
5.5
V
fSYS=12MHz
2.7
—
5.5
V
V
fSYS=8MHz
2.2
—
5.5
fSYS=12MHz
2.7
—
5.5
V
No load, fH=8MHz,
WDT enable
—
1.0
2.0
mA
—
2.7
4.5
mA
—
1.2
2.5
mA
—
3.3
6.5
mA
—
1.4
3.5
mA
—
3.9
10.0
mA
No load, fH=10MHz,
WDT enable
No load, fH=12MHz,
WDT enable
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December 19, 2011
HT83B60
Voice Mask MCU
Symbol
Parameter
VDD
3V
5V
IDD2
Operating Current
(ERC OSC, fSYS=fH)
3V
5V
3V
5V
3V
5V
IDD3
Operating Current
(HIRC OSC, fSYS=fH)
3V
5V
3V
5V
ISTB1
Standby Current (Idle)
(Crystal, ERC, HIRC OSC)
3V
ISTB2
Standby Current (Idle)
(Crystal, ERC, HIRC OSC)
3V
IOL1
IOH1
IOL2
I/O Port Sink Current
I/O Port Source Current
PWM1/PWM2 Sink Current
5V
5V
3V
5V
3V
5V
3V
5V
3V
Test Conditions
Conditions
Min.
Typ.
Max.
Unit
—
0.9
2.0
mA
—
2.2
4.0
mA
No load, fH=8MHz,
WDT enable
—
1.1
2.5
mA
—
2.9
6.5
mA
No load, fH=12MHz,
WDT enable
—
1.5
3.5
mA
—
4.1
8.0
mA
No load, fH=4MHz,
WDT enable
—
0.7
2.0
mA
—
1.6
3.5
mA
No load, fH=8MHz,
WDT enable
—
1.2
2.5
mA
—
3.2
7.0
mA
No load, fH=12MHz,
WDT enable
—
1.8
4.0
mA
—
4.3
8.5
mA
No load, system HALT,
WDT enable, fSYS=12MHz
—
1.2
5.5
μA
—
4.5
11.0
μA
No load, system HALT,
WDT disable, fSYS=12MHz
—
0.2
1.0
μA
No load, fH=6MHz,
WDT enable
VOL=0.1VDD
VOH=0.9VDD
VOL=0.1VDD
—
0.6
2.0
μA
5.5
10
—
mA
9.5
20
—
mA
-2.5
-5
—
mA
-10
-15
—
mA
60
85
—
mA
135
195
—
mA
-38
-55
—
mA
-80
-115
—
mA
IOH2
PWM1/PWM2 Source
Current
VIL1
Input Low Voltage for I/O
Ports
—
—
0
—
0.3VDD
VIH1
Input High Voltage for I/O
Ports
—
—
0.7VDD
—
VDD
VIL2
Input Low Voltage(RES)
—
—
0
—
0.4VDD
VIH2
Input High Voltage(RES)
—
—
0.9VDD
—
VDD
V
30
100
170
kW
10
35
60
kW
RPH
Pull-high Resistance
5V
VOH=0.9VDD
3V
—
5V
V
V
V
3V
VOH=0.9VDD
—
-4.5
—
mA
5V
VOH=0.9VDD
—
-10
—
mA
IAUD
AUD current source
VLVR
Low Voltage Reset Voltage
—
LVR 2.2V option
2.090
2.2
2.310
V
VLVD
Low Voltage Reset Voltage
—
LVD 2.7V option
2.565
2.7
2.835
V
Rev. 1.00
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December 19, 2011
HT83B60
Voice Mask MCU
A.C. Characteristics
Ta=25°C
Symbol
fSYS1
Parameter
VDD
System clock (Crystal OSC)
Test Conditions
Conditions
—
—
2
2.7~5.5V
—
2
—
Max.
Unit
8
MHz
10
MHz
12
MHz
2
—
-2%×Typ.
8
+2%×Typ. MHz
-2%×Typ.
8
+2%×Typ. MHz
1
—
—
µs
—
1024
—
tSYS
fSYS=ERC or HIRC OSC
—
15~16
—
tSYS
—
1
—
—
tSYS
tSUB
fSYS2
System clock (External RC OSC)
5.0V
Ta=25°C,
External RERC=120kΩ*
fSYS3
System clock (HI RC OSC)
5.0V
Ta=25°C
tRES
External Reset Low Pulse Width
tINT
Typ.
2.2~5.5V
3.3~5.5V
tSST
Min.
—
—
fSYS=XTAL
System Start-up time Period
(Wake-up from HALT)
—
Interrupt Pulse Width
—
—
7
—
8
tLVR
Low Voltage Width to Reset
—
—
350
880
1300
µs
tLVD
LVD Time
—
—
15
—
—
µs
Note: tSYS=1/fSYS; tSUB=1/fSUB
Power-on Reset Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure
Power-on Reset
—
—
—
—
100
mV
RRVDD
VDD Rise Rate to Ensure
Power-on Reset
—
—
0.035
—
—
V/ms
tPOR
Minimum Time for VDD to Remain
at VPOR to Ensure Power-on Reset
—
—
1
—
—
ms
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December 19, 2011
HT83B60
Voice Mask MCU
Characteristics Curves
R vs. F (External RC) Chart Characteristics Curve at 25°C
1 4
F re q u e n c y (M H z )
1 2
1 0
V
8
D D
= 5 .0 V
6
4
2
8 2
1 0 0
1 2 0
1 6 8
2 4 0
R (k )
T vs. F (External RC) Chart Characteristics Curve
Rev. 1.00
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December 19, 2011
HT83B60
Voice Mask MCU
V vs. F (HIRC) Chart Characteristics Curve at 25°C − Trimmed at 5V
Rev. 1.00
12
December 19, 2011
HT83B60
Voice Mask MCU
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to the internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance.
The pipelining scheme is implemented in such a way that instruction fetching and instruction
execution are overlapped, hence instructions are effectively executed in one cycle, with the
exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations
of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment,
decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and
can be directly or indirectly addressed. The simple addressing methods of these registers along
with additional architectural features ensure that a minimum of external components is required to
provide a functional I/O control system with maximum reliability and flexibility.
Clocking and Pipelining
The main system clock, derived from either a Crystal, ERC or IRC oscillator, is subdivided into
four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at
the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the
contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the
instruction will take one more instruction cycle to execute.
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
   
 
  
System Clocking and Pipelining
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HT83B60
Voice Mask MCU
     
  
Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the next
instruction to be executed. It is automatically incremented by one each time an instruction is
executed except for instructions, such as "JMP" or "CALL" that demand a jump to a non-consecutive
Program Memory address. Note that the Program Counter width varies with the Program Memory
capacity depending upon which device is selected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are directly addressable by user.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writable register. By transferring data directly
into this register, a short program jump can be executed directly, however, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory, that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle will
be inserted.
The lower byte of the Program Counter is fully accessible under program control. Manipulating the
PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information
on the PCL register can be found in the Special Function Register section.
Mode
Program Counter Bits
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
Timer Base Overflow
0
0
0
0
0
0
0
0
1
0
0
Timer Counter 0 overflow
0
0
0
0
0
0
0
1
0
0
0
Timer Counter 1 overflow
0
0
0
0
0
0
0
1
1
0
0
SIMA Interrupt
0
0
0
0
0
0
1
0
0
0
0
SIMB Interrupt
0
0
0
0
0
0
1
0
0
0
0
@0
Skip
Program Counter+2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
Jump, call branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return (RET, RETI)
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
Rev. 1.00
*10~*0: Program Counter bits
@[email protected]: PCL bits
#11~#0: Instruction code address bits
S10~S0: Stack register bits
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Stack
This is a special part of the memory which is used to save the contents of the Program Counter only.
The stack has 8 levels and is neither part of the data nor part of the program space, and can neither
be read from nor written to. The activated level is indexed by the Stack Pointer, SP, which can also
neither be read from nor written to. At a subroutine call or interrupt acknowledge signal, the contents
of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value
from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
P ro g ra m
T o p o f S ta c k
S ta c k
P o in te r
B o tto m
o f S ta c k
C o u n te r
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k L e v e l 3
P ro g ra m
M e m o ry
S ta c k L e v e l 8
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still
be executed which will result in a stack overflow. Precautions should be taken to avoid such cases,
which might cause unpredictable program branching.
Arithmetic and Logic Unit − ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
• Logic operations AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
• Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
• Increment and Decrement INCA, INC, DECA, DEC Branch decision JMP, SZ, SZA, SNZ, SIZ,
SDZ, SIZA, SDZA, CALL, RET, RETI
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Program Memory
The Program Memory is the location where the user code or program is stored. For this device, the
Program Memory is Mask type.
Structure
The Program Memory has a capacity of 2K by 16 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries. Table data, which
can be setup in any location within the Program Memory, is addressed by separate table pointer
registers.

Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and
interrupts.
Reset Vector
This vector is reserved for use by the device reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
External Interrupt Vector
This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the
program will jump to this location and begin execution if the external interrupt is enabled and the
stack is not full.
Timer Counter 0 Interrupt Vector
This vector is used by the 8-bit Timer 0. If a overflow occurs, the program will jump to this location
and begin execution if the timer interrupt is enabled and the stack is not full.
Timer Counter 1 Interrupt Vector
This vector is used by the 8-bit Timer 1. If a overflow occurs, the program will jump to this location
and begin execution if the timer interrupt is enabled and the stack is not full.
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SIMA Interrupt Vector
This vector is used by the SIMA Bus interrupt service program. If the SIMA Bus interrupt resulting
from a slave address is matched or if 8 bits of data have been received or transmitted successfully
from the I2C interface, or 8 bits of data have been received or transmitted successful from SPI
interface, the program will jump to this location and begin execution if the interrupt is enabled and
the stack is not full.
SIMB Interrupt Vector
This vector is used by the SIMB Bus interrupt service program. If the SIMB Bus interrupt resulting
from a slave address is matched or if 8 bits of data have been received or transmitted successfully
from the I2C interface, or 8 bits of data have been received or transmitted successful from SPI
interface, the program will jump to this location and begin execution if the interrupt is enabled and
the stack is not full.
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers
can store fixed data. To use the look-up table, the table pointers are used to setup the address of the
data that is to be accessed from the Program Memory. However, as some devices possess only a
low byte table pointer and other devices possess both a high and low byte pointer it should be noted
that depending upon which device is used, accessing look-up table data is implemented in slightly
different ways.
There are two Table Pointer Registers known as TBLP and TBHP in which the lower order and
higher order address of the look-up data to be retrieved must be respectively first written. The
additional TBHP register allows the complete address of the look-up table to be defined and
consequently allow table data from any address and any page to be directly accessed. For this
device, after setting up both the low and high byte table pointers, the table data can then be retrieved
from any area of Program Memory using the "TABRDC [m]" instruction or from the last page
of the Program Memory using the "TABRDL [m]" instruction. When either of these instructions
are executed, the lower order table byte from the Program Memory will be transferred to the user
defined Data Memory register [m] as specified in the instruction. The higher order table data byte
from the Program Memory will be transferred to the TBLH special register.
Any unused bits in this transferred higher order byte will be read as "0".
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The following diagram illustrates the addressing/data flow of the look-up table.
P ro g ra m C o u n te r
H ig h B y te
P ro g ra m
M e m o ry
T B L P
T B L H
S p e c ifie d b y [m ]
H ig h B y te o f T a b le C o n te n ts
L o w B y te o f T a b le C o n te n ts
Look-up Table
Table Program Example
The following example shows how the table pointer and table data is defined and retrieved from the
devices. This example uses raw table data located in the last page which is stored there using the
ORG statement. The value at this ORG statement is "700H" which refers to the start address of the
last page within the 2048x16-bit Program Memory of the microcontroller. The table pointer is setup
here to have an initial value of "06H" This will ensure that the first data read from the data table will
be at the Program Memory address "706H" or 6 locations after the start of the last page.
Note that the value for the table pointer is referenced to the first address of the present page if the
"TABRDC[m]" instruction is being used. The high byte of the table data which in this case is equal
to zero will be transferred to the TBLH register automatically when the "TABRDL [m]" instruction
is executed.
Instruction
Table Location Bits
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
PC10
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *10~*0: Current Program ROM table
P10~P8: Write P12~P8 to TBHP pointer register
@[email protected]: Write @[email protected] to TBLP pointer register
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Table Read Program Example
tempreg1 db ?
tempreg2 db ?
:
:
; temporary register #1
; temporary register #2
mov a,06h
; initialise table pointer - note that this address is referenced
mov tblp,a
:
:
; to the last page or present page
tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempregl
; data at prog. memory address "706H" transferred to tempreg1 and TBLH
dec tblp
; reduce value of table pointer by one
tabrdl tempreg2
:
:
;
;
;
;
;
org 700h
; sets initial address of the last page
transfers value in table referenced by table pointer to tempreg2
data at prog.memory address "705H" transferred to tempreg2 and TBLH
in this example the data "1AH" is transferred to
tempreg1 and data "0FH" to register tempreg2
the value "00H" will be transferred to the high byte register TBLH
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored. Divided into two sections, the first of these is an area of RAM
where special function registers are located. These registers have fixed locations and are necessary
for correct operation of the device. Many of these registers can be read from and written to directly
under program control, however, some remain protected from user manipulation. The second area of
RAM Data Memory is reserved for general purpose use. All locations within this area are read and
write accessible under program control.
Structure
The Data Memory has a bank, known as Bank, which is implemented in 8-bit wide RAM. The RAM
Data Memory is located in Bank 0 which is also subdivided into two sections, the Special Purpose
Data Memory and the General Purpose Data Memory. The length of these sections is dictated by the
type of microcontroller chosen.
The start address of the RAM Data Memory for all devices is the address "00H" and the last Data
Memory address is "FFH" Registers which are common to all microcontrollers, such as ACC, PCL,
etc., have the same Data Memory address.
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0 0 H
2 F H
3 0 H
S p e c ia l P u r p o s e
D a ta M e m o ry
G e n e ra l P u rp o s e
D a ta M e m o ry
(2 0 8 B y te s )
F F H
RAM Data Memory Structure
Note: Most of the Data Memory bits can be directly manipulated using the “SET [m].i” and “CLR
[m].i” with the exception of a few dedicated bits. The Data Memory can also be accessed
through the memory pointer registers.
General Purpose Data Memory
All microcontroller programs require an area of read/write memory where temporary data can be
stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose
Data Memory. This area of Data Memory is fully accessible by the user program for both read and
write operations. By using the "SET [m].i" and "CLR [m].i" instructions individual bits can be set
or reset under program control giving the user a large range of flexibility for bit manipulation in the
Data Memory.
Special Purpose Data Memory
This area of Data Memory, is located in Bank, where registers, necessary for the correct operation
of the microcontroller, are stored. Most of the registers are both readable and writable but some are
protected and are readable only, the details of which are located under the relevant Special Function
Register section. Note that for locations that are unused, any read instruction to these addresses will
return the value "00H".
Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in
the Data Memory area. These registers ensure correct operation of internal functions such as timers,
interrupts, etc., as well as external functions such as I/O data control. The location of these registers
within the Data Memory begins at the address "00H". Any unused Data Memory locations between
these special function registers and the point where the General Purpose Memory begins is reserved
and attempting to read data from these locations will return a value of "00H".
Indirect Addressing Registers − IAR0
The Indirect Addressing Registers, IAR0, although having their locations in normal RAM register
space, do not actually physically exist as normal registers. The method of indirect addressing for
RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast
to direct memory addressing, where the actual memory address is specified. Actions on the IAR0
registers will result in no actual read or write operation to these registers but rather to the memory
location specified by their corresponding Memory Pointer, MP0. As the Indirect Addressing
Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will
return a result of "00H" and writing to the registers indirectly will result in no operation.
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Special Purpose Data Memory Structure
Rev. 1.00
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Indirect Addressing Program Example
The following example shows how to clear a section of four Data Memory locations already defined
as locations adres1 to adres4.
data .section 'data'
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 code
org00h
start:
mov
mov
mov
mov
a,04h; setup size of block
block,a
a,offset adres1 ; Accumulator loaded with first RAM address
mp0,a ; setup memory pointer with first RAM address
loop:
clr
inc
sdz
jmp
IAR0 ; clear the data at address defined by MP0
mp0; increment memory pointer
block ; check if last memory location has been cleared
loop
continue:
The important point to note here is that in the example shown above, no reference is made to specific
Data Memory addresses.
Memory Pointers − MP0
For all devices, two Memory Pointers, known as MP0 is provided. These Memory Pointers are
physically implemented in the Data Memory and can be manipulated in the same way as normal
registers providing a convenient way with which to address and track data. When any operation to
the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller
is directed to, is the address specified by the related Memory Pointer.
Accumulator − ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
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Program Counter Low Register − PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Look-up Table Registers - TBLP, TBLH
These two special function registers are used to control operation of the look-up table, which is
stored in the Program Memory. TBLP is the table pointer and indicates the location where the table
data is located. Its value must be setup before any table read commands are executed. Its value
can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data
pointing and reading. TBLH is the location where the high order byte of the table data is stored
after a table read data instruction has been executed. Note that the lower order table data byte is
transferred to a user defined location.
Watchdog Timer Register - WDTS
The Watchdog feature of the microcontroller provides an automatic reset function giving the
microcontroller a means of protection against spurious jumps to incorrect Program Memory
addresses. To implement this, a timer is provided within the microcontroller which will issue a reset
command when its value overflows. To provide variable Watchdog Timer reset times, the Watchdog
Timer clock source can be divided by various division ratios, the value of which is set using the
WDTS register. By writing directly to this register, the appropriate division ratio for the Watchdog
Timer clock source can be setup. Note that only the lower 3 bits are used to set division ratios
between 1 and 128.
Status Register − STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing
the "HALT" or "CLR WDT" instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the interrupt routine can change the status register, precautions must be taken to correctly save it.
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STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
TO
PDF
OV
Z
AC
C
R/W
—
—
R
R
R/W
R/W
R/W
R/W
POR
—
—
0
0
x
x
x
x
“X” unknown
Bit 7, 6
Unimplemented, read as "0"
Bit 5
TO: Watchdog Time-Out flag
0: After power up or executing the "CLR WDT" or "HALT" instruction
1: A watchdog time-out occurred.
Bit 4
PDF: Power down flag
0: After power up or executing the "CLR WDT" instruction
1: By executing the "HALT" instruction
Bit 3
OV: Overflow flag
0: no overflow
1: an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Bit 2
Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1
AC: Auxiliary flag
0: no auxiliary carry
1: an operation results in a carry out of the low nibbles in addition, or no borrow
from the high nibble into the low nibble in subtraction
Bit 0
C: Carry flag
0: no carry-out
1: an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation
C is also affected by a rotate through carry instruction.
Interrupt Control Register - INTC, INTCH
Two 8-bit register, known as the INTC and INTCH registers, controls the operation of both external
and internal timer interrupts. By setting various bits within these registers using standard bit
manipulation instructions, the enable/disable function of the external and timer interrupts can be
independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global
enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an
interrupt routine is entered to disable further interrupt and is set by executing the "RETI" instruction.
Note: In situations where other interrupts may require servicing within present interrupt service
routines, the EMI bit can be manually set by the program after the present interrupt service
routine has been entered.
Timer Registers
All devices contain two 8-bit Timers whose associated registers are known as TMR0 and TMR1
which is the location where the associated timer's 8-bit value is located. Their associated control
registers, known as TMR0C and TMR1C, contain the setup information for these timers.
Note that all timer registers can be directly written to in order to preload their contents with fixed
data to allow different time intervals to be setup.
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Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O registers and their associated control registers
play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB
and PC. These labeled I/O registers are mapped to specific addresses within the Data Memory as
shown in the Data Memory table, which are used to transfer the appropriate output or input data on
that port. With each I/O port there is an associated control register labeled PAC, PBC and PCC, also
mapped to specific addresses with the Data Memory. The control register specifies which pins of
that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding
bit of the control register must be set high, for an output it must be set low. During program
initialization, it is important to first setup the control registers to specify which pins are outputs and
which are inputs before reading data from or writing data to the I/O ports. One flexible feature of
these registers is the ability to directly program single bits using the "SET [m].i" and "CLR [m].
i" instructions. The ability to change I/O pins from output to input and vice versa by manipulating
specific bits of the I/O control registers during normal program operation is a useful feature of these
devices.
Port C Pull-high Control Register - PCPHC
Port C pull-high control register, PCPHC, is used to set the Port C pull high function.
b 7
b 0
P C P H C 2
P C P H C 1
P C P H C 0
C o n tr o l th e P o r t C P u ll- H ig h
1 : e n a b k e
0 : d is a b le - d e fa u lt
N o t im p le m e n te d , r e a d a s " 0 "
Voice Control and Audio output Registers - DAL, DAH, VOL
The devices include a single 12-bit current type DAC function for driving an external 8W speaker
through an external NPN transistor or Power Amplifier. The programmer must writer the voice data
to these DAL/DAH registers. The programmer can control the DAC volume with 8-levels via the
VOL register.
Pulse Width Modulator Registers - PWMC, PWML, PWMH
Each device contains a single 12-bit PWM function for driving an external 8W speaker. The
programmer must writer the voice data to PWML/PWMH register. The programmer can control the
PWM volume with 9-levels via the VOL register.
Serial Interface Module (SIM) Registers - SIMC0A/B, SIMC1A/B, SIMC2A/B,
SIMARA/B, SIMDRA/B
Each SIM contains SPI and I2C function for communicating with other microcontroller or SPI Flash
Memory. All devices contain an integrated I2C and SPI bus which interfaces to the external shared
pins SDA, SCL and SCSB, SCK, SDI, SDO with PB on the microcontroller. The I2C correct setup
and data transfer operation of this 2-line bidirectional bus utilizes 4 special function registers. The
SIMARA/B register sets the slave address of the device while the SIMC0A/B is the control register
that enables or disables the device as well as select whether it is in I2C or SPI mode. The SIMC1A/
B register is the I2C status register while the SIMDRA/B register is the input/output data register.
The SPI correct setup and data transfer operation of this 3-line bidirectional bus utilizes 3 special
function registers. The SIMC0A/B is the control register that enables or disables the device as well
as select whether it is in I2C or SPI mode. The SIMC2A/B register is the SPI status register while the
SIMDRA/B register is the input/output data register.
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Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high options for all ports and wakeup options on certain pins, the user is provided with an I/O structure to meet the needs of a wide
range of application possibilities.
Depending upon which device or package is chosen, the microcontroller range provides from 15
bidirectional input/output lines labeled with port names PA, PB, PC etc. These I/O ports are mapped
to the Data Memory with specific addresses as shown in the Special Purpose Data Memory table.
All of these I/O ports can be used for input and output operations. For input operation, these ports
are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV
A,[m]" where m denotes the port address. For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as an input have the capability of being connected to an internal pull-high resistor. These
pull-high resistors are selectable via configuration or software options and are implemented using a
weak PMOS transistor. Note that if the pull-high option is selected, then all I/O pins on that port will
be connected to pull-high resistors, individual pins can be selected for pull-high resistor options.
Port A Wake-up
Each device has a HALT instruction enabling the microcontroller to enter a Power Down Mode and
preserve power, a feature that is important for battery and other low-power applications. Various
methods exist to wake-up the microcontroller, one of which is to change the logic condition on
one of the Port A pins from high to low. After a "HALT" instruction forces the microcontroller
into entering a HALT condition, the processor will remain idle or in a low-power state until the
logic condition of the selected wake-up pin on Port A changes from high to low. This function is
especially suitable for applications that can be woken up via external switches. Note that each pin on
Port A can be selected individually to have this wake-up feature.
I/O Port Control Registers
Each I/O port has its own control register PAC, PBC and PCC, to control the input/output
configuration. With this control register, each CMOS output or input with or without pull-high
resistor structures can be reconfigured dynamically under software control. Each pin of the I/O
ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as
an input, the corresponding bit of the control register must be written as a "1". This will then allow
the logic state of the input pin to be directly read by instructions. When the corresponding bit of the
control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently
setup as an output, instructions can still be used to read the output register. However, it should be
noted that the program will in fact only read the status of the output data latch and not the actual
logic status of the output pin.
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Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but by
supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the
chosen function of the multi-function I/O pins is set by configuration options while for others the
function is set by application program control.
Serial Interface Module
The device pins, PB0~PB3, are pin-shared with pins SDAB, SCLB, SCSB, SCKB, SDIB, SDOB.
The choice of which function is used is selected using the SIMC0B register.
Serial Interface Module
The device pins, PB4~PB7, are pin-shared with pins SDAA, SCLA, SCSA, SCKA, SDIA, SDOA.
The choice of which function is used is selected using the SIMC0A register.
This Serial interface module should be selected as SPI function which is used for the internal Voice
ROM access control, and should be left no external connection.
I/O Pin Structures
The following diagrams illustrate the I/O pin internal structures. As the exact logical construction
of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the
functional understanding of the I/O pins.
Note also that the specified pins refer to the largest device package, therefore not all pins specified
will exist on all devices.
Programming Considerations
Within the user program, one of the first things to consider is port initialization. After a reset, all of
the I/O data and port control registers will be set high. This means that all I/O pins will default to
an input state, the level of which depends on the other connected circuitry and whether pull-high
options have been selected. If the port control registers, PAC, PBC, PCC etc., are then programmed
to setup some pins as outputs, these output pins will have an initial high output value unless the
associated port data registers, PA, PB, PC etc., are first programmed. Selecting which pins are inputs
and which are outputs can be achieved byte-wide by loading the correct values into the appropriate
port control register or by programming individual bits in the port control register using the "SET [m].
i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modifywrite operation takes place. The microcontroller must first read in the data on the entire port, modify
it to the required new bit values and then rewrite this data back to the output ports.
Read/Write Timing
Port A has the additional capability of providing wake-up functions. When the device is in the
Power Down Mode, various methods are available to wake the device up. One of these is a high to
low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this
function.
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Voice Mask MCU
Timers
The provision of timers form an important part of any microcontroller, giving the designer a means
of carrying out time related functions. These devices contain two count up timers of 8-bit capacity.
The provision of an internal prescaler to the clock circuitry of the timer gives added range to the
timer.
There are two types of register related to each Timer. The first is the register that contains the actual
value of the timer and into which an initial value can be preloaded. Reading from this register
retrieves the contents of the Timer. All devices can have the timer clock configured to come from the
internal clock source.
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Configuring the Timer Input Clock Source
The clock source for the 8-bit timers is the system clock divided by four. The 8-bit timer clock
source is also first divided by a, the division ratio of which is conditioned by the three lower bits of
the associated timer control register.
Timer Registers - TMR0, TMR1
The timer registers are special function registers located in the special purpose Data Memory and is
the place where the actual timer value is stored. All devices contain two 8-bit timers, whose registers
are known as TMR0 and TMR1. The value in the timer registers increases by one each time an
internal clock pulse is received. The timer will count from the initial value loaded by the preload
register to the full count of FFH for the 8-bit timer at which point the timer overflows and an internal
interrupt signal is generated. The timer value will then be reset with the initial preload register value
and continue counting.
Note that to achieve a maximum full range count of FFH for the 8-bit timer, the preload registers
must first be cleared to all zeros. It should be noted that after power-on, the preload registers will be
in an unknown condition. Note that if the Timer Counters are in an OFF condition and data is written
to their preload registers, this data will be immediately written into the actual counter. However, if
the counter is enabled and counting, any new data written into the preload data register during this
period will remain in the preload register and will only be written into the actual counter the next
time an overflow occurs. Note also that when the timer registers are read, the timer clock will be
blocked to avoid errors, however, as this may result in certain timing errors, programmers must take
this into account.
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Voice Mask MCU
Timer Control Registers - TMR0C, TMR1C
Each timer has its respective timer control register, known as TMR0C and TMR1C. It is the timer
control register together with their corresponding timer registers that control the full operation of the
timers. Before the timers can be used, it is essential that the appropriate timer control register is fully
programmed with the right data to ensure its correct operation, a process that is normally carried
out during program initialization. Bits 7 and 6 of the Timer Control Register, must be set to the
required logic levels. Bit 6 of the registers must always be written with a "1", and bit 7 must always
be written with a "1". The timer-on bit, which is bit 4 of the Timer Control Register and known
as T0ON/T1ON, depending upon which timer is used, provides the basic on/off control of the
respective timer. setting the bit high allows the timer to run, clearing the bit stops the timer. For the
8-bit timers, which have prescalers, bits 0~2 of the Timer Control Register determines the division
ratio of the input clock prescaler.
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Voice Mask MCU
Configuring the Timer
The Timer is used to measure fixed time intervals, providing an internal interrupt signal each time
the Timer overflows. To do this the Operating Mode Select bit pair in the Timer Control Register
must be set to the correct value as shown.
Control Register Operating Mode
Select Bits
Bit7
Bit6
1
0
The internal clock, fSYS, is used as the Timer clock. However, this clock source is further divided by
a prescaler, the value of which is determined by the Prescaler Rate Select bits, which are bits 0~2
in the Timer Control Register. After the other bits in the Timer Control Register have been setup,
the enable bit, which is bit 4 of the Timer Control Register, can be set high to enable the Timer to
run. Each time an internal clock cycle occurs, the Timer increments by one. When it is full and
overflows, an interrupt signal is generated and the Timer will reload the value already loaded into
the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer
Interrupt Enable bit in the Interrupt Control Register, INTC, is reset to zero.
Timer Mode Timing Diagram
Prescaler
All of the 8-bit timers possess a prescaler. Bits 0~2 of their associated timer control register, define
the pre-scaling stages of the internal clock source of the Timer. The Timer overflow signal can be
used to generate signals for the Timer interrupt.
Programming Considerations
The internal system clock is used as the timer clock source and is therefore synchronized with the
overall operation of the microcontroller. In this mode, when the appropriate timer register is full, the
microcontroller will generate an internal interrupt signal directing the program flow to the respective
internal interrupt vector.
When the Timer is read, the clock is blocked to avoid errors, however as this may result in a
counting error, this should be taken into account by the programmer. Care must be taken to ensure
that the timers are properly initialized before using them for the first time. The associated timer
enable bits in the interrupt control register must be properly set otherwise the internal interrupt
associated with the timer will remain inactive. The edge select, timer mode and clock source control
bits in timer control register must also be correctly set to ensure the timer is properly configured
for the required application. It is also important to ensure that an initial value is first loaded into the
timer registers before the timer is switched on; this is because after power-on the initial values of the
timer registers are unknown. After the timer has been initialized the timer can be turned on and off
by controlling the enable bit in the timer control register.
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Voice Mask MCU
Timer Program Example
The following example program section is based on the device, which contain two 8-bit timers.
Programming the timer for other devices is conducted in a very similar way. The program shows
how the timer registers are setup along with how the interrupts are enabled and managed. Points to
note in the example are how, for the 8-bit timer. Note how the timer is turned on by setting bit 4 of
the respective timer control register. The timer can be turned off in a similar way by clearing the
same bit. This example program sets the timer to be in the timer mode which uses the internal fSYS as
their clock source, and produce a timer 0 interrupt per 1ms.
#include HT83B60.inc
jmpbegin
:
org
04h;
reti
org
08h;
jmp tmr0int ;
org 0Ch
reti
org 10h
reti
org 14h
reti
:
;
Tmr0int:
:
;
:
reti
:
begin:
;
mov a,06h ;
mov tmr0,a ;
mov a,094 ;
mov tmr0c,a ;
;
mov a,05h ;
mov intc,a ;
Rev. 1.00
time base vector
timer 0 interrupt vector
jump here when timer 0 overflows every 1ms
internal timer 0 interrupt routine
timer 0 main program placed here
setup timer 0 registers
setup timer 0 low byte
flow byte must be setup before high byte
setup timer 0 control register
setup timer mode and clock source is fsys/32 prescaler
setup interrupt register
enable global interrupt
enable timer 0 interrupt
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Voice Mask MCU
Time Base
The Time Base function will generate a regular interrupt signal synchronised to the system clock
which can be used by the application as a time base signal.
Time Base Operation
The Time Base operation is a very simple function for the generation of a regular time signal. This
is implemented by generating a regular interrupt signal whose enable/disabled and request flags are
in the INTC register. The clock source for the time base is the internal fSYS/4 clock source, which
is then divided internally by a value of 1024. It is this divided signal that generates the internal
interrupt. The Time Base Interrupt is enabled by the ETBI bit in the INTC register and interrupt
request flag is the TBF flag in the same register. A time base of 1ms will therefor be generated from
a system clock of 4MHz and a time base of 0.5ms will be generated from a system clock source of
8MHz.
Time Base Example
The following example program section is based on the device. The program shows how the Time
Base registers are setup along with how the interrupts are enabled and managed. The points to note
in the example are how the Time Base is turned on by setting bit 4 of the INTC register. The Time
Base can be turned off in a similar way by clearing the same bit. This example program sets the
Time Base which uses the internal system clock as their clock source, and produces a time base
interrupt every 0.5ms from a system source clock of 8MHz.
#include HT83B60.inc
jmp begin
:
org 04h
;
jmp time_base_int ;
org 08h
reti
org 0Ch
reti
org 10h
reti
org 14h
reti
:
;
time_base_int:
:
;
:
reti
:
begin:
;
mova,03h;
movintc,a;
Rev. 1.00
time base vector
jump here when time base overflows per 0.5ms
time base interrupt routine
time base main program placed here
setup interrupt register
enable global and time base interrupt
enable time base
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HT83B60
Voice Mask MCU
Serial Interface
The device contains both SPI and I2C serial interface functions, which allows two methods of easy
communication with external peripheral hardware. As the SPI and I2C function share the same
external pins and internal registers their function must first be chosen by selecting the correct
configuration option.
SPI Interface
The SPI interface is often used to communicate with external peripheral devices such as sensors,
Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI
interface is a synchronous serial data interface that has a relatively simple communication protocol
simplifying the programming requirements when communicating with external hardware devices.
SPI Interface Operation
The SPI interface is a full duplex synchronous serial data link. Communication between devices
connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations
being implemented by the master. Multiple slave devices can be connected to the SPI serial bus with
each device controlled using its slave select line. The SPI is a four line interface with pin names SDI,
SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK
is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with
segment pins and with the I2C function pins, the SPI interface must first be enabled by selecting the
correct configuration option. After the SPI configuration option has been selected it can then also be
selected using the SIMEN bit in the SIMC0 register.
The SPI function in this device offers the following features:
• Full duplex synchronous data transfer
• Both Master and Slave modes
• LSB first or MSB first data transmission modes
• Transmission complete flag
Several other configuration options also exist to setup various SPI interface options as follows:
• SPI pin enabled
• WCOL bit enabled or disabled
• CSEN bit enabled or disabled
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Voice Mask MCU
The status of the SPI interface pins is determined by a number of factors, whether the device is in
master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN.
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Master/Salve
(SIMEN=0)
Master (=1)
CSEN=1
Slave (=1)
CSEN=0
CSEN=0
SCS line=0
(CSEN=1)
SCS line=1
(CSEN=1)
SCS
Z
L
Z
Z
I, Z
I, Z
SDO
Z
O
O
O
O
Z
SDI
Z
I, Z
I, Z
I, Z
I, Z
Z
Z
L(CPOL=1)
H(CPOL=0)
L(CPOL=1)
H(CPOL=0)
I, Z
I, Z
Z
SCK
"Z" floating, "H" output high, "L"output low, "I"Input, "O" output level,
"I,Z" input floating (no pull-high)
SPI Interface Pin Status
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Voice Mask MCU
SPI Registers
The SIMDR A/B register is used to store the data being transmitted and received. There are two
control registers associated with the SPI interface, SIMC0 A/B and SIMC2 A/B and one data register
known as SIMDRA/B. The SIMC1 A/B register is not used by the SPI function. Register SIMC0
A/B is used to control the enable/disable function, the power down control and to set the data
transmission clock frequency. Register SIMC2 A/B is used for other control functions such as LSB/
MSB selection, write collision flag etc.
The following gives further explanation of each bit:
• SIMEN A/B
The A/B bit is the overall on/off control for the SPI interface. When the A/B bit is cleared to
zero to disable the SPI interface, the SDI, SDO A/B, SCK A/B and SCS A/B lines will be in a
floating condition and the SPI operating current will be reduced to <0.1mA at 5V. When the bit is
high the SPI interface is enabled. Note that when the SIMEN A/B bit changes from low to high
the contents of the SPI control registers will be in an unknown condition and should therefore be
initialised by the application program.
• SIM0 A/B~SIM2 A/B
These three bits control the Master/Slave selection and also setup the SPI interface clock speed
when in the Master Mode. The SPI clock is a function of the system clock whether it be RC type
or Crystal type. If the Slave Mode is selected then the clock will be supplied by the external
Master device.
The following gives further explanation of each bit:
Rev. 1.00
♦♦
TRF A/B
The TRF A/B bit is the Transmit/Receive Complete flag and is cleared by the application
program and can be used to generate an interrupt. When the bit is high the data has been
transmitted or received. If the bit is low the data is being transmitted or has not yet been
received.
♦♦
WCOL A/B
The WCOL A/B bit is used to detect if a data collision has occurred. If this bit is high it means
that data has been attempted to be written to the SMDR A/B register during a data transfer
operation. This writing operation will be ignored if data is being transferred. The bit can be
cleared by the application program. Note that using the CSEN A/B bit can be disabled or
enabled via configuration option.
♦♦
CSEN A/B
The CSEN A/B bit is used as an on/off control for the SCS A/B pin. If this bit is low then the
SCS A/B pin will be disabled and placed into a floating condition. If the bit is high the SCS A/B
pin will be enabled and used as a select pin.
♦♦
MLS A/B
The MLS A/B is used to select how the data is transferred, either MSB or
L S B firs t. S ettin g the bit high w ill s e le c t M SB firs t a nd low for LSB firs t.
Note that the SIMC2 A/B register is the same as the SIMAR A/B register used by the I2C
interface.
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Voice Mask MCU
• SPI Communication
After the SPI interface is enabled by setting the SIMEN A/B bit high, then in the Master
Mode, when data is written to the SIMDR A/B register, transmission/reception will begin
simultaneously. When the data transfer is complete, the TRF A/B flag will be set automatically. In
the Slave Mode, when the clock signal from the master has been received, any data in the SIMDR
register will be transmitted and any data on the SDI A/B pin will be shifted into the SIMDR A/B
register. The master should output an SCS A/B signal before a clock signal is provided and slave
data transfers should be enabled/disabled before/after an SCS A/B signal is received.
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Rev. 1.00
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HT83B60
Voice Mask MCU
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Rev. 1.00
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HT83B60
Voice Mask MCU
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Rev. 1.00
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HT83B60
Voice Mask MCU
I2C Interface
The I2C bus is a bidirectional 2-line communication interface originally developed by Philips.
The possibility of transmitting and receiving data on only 2 lines offers many new application
possibilities for microcontroller based applications.
I2C Interface Operation
As the I2C interface pins are pin-shared with segment pins and with the SPI function pins, the I2C
interface must first be enabled by selecting the correct configuration option.
There are two lines associated with the I2C bus, the first is known as SDA and is the Serial Data line,
the second is known as SCL line and is the Serial Clock line. As many devices may be connected
together on the same bus, their outputs are both open drain types. For this reason it is necessary that
external pull-high resistors are connected to these outputs. Note that no chip select line exists, as
each device on the I2C bus is identified by a unique address which will be transmitted and received
on the I2C bus.
When two devices communicate with each other on the bidirectional I2C bus, one is known as the
master device and one as the slave device. Both master and slave can transmit and receive data,
however, it is the master device that has overall control of the bus. For this device, which only
operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit
mode and the slave receive mode.
I2C Registers
There are three control registers associated with the I2C bus, SIMC0A/B, SIMC1A/B and SIMARA/
B and one data register, SIMDRA/B.
The SIMDRA/B register is used to store the data being transmitted and received on the I2C bus.
Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be
placed in the SIMDRA/B register. After the data is received from the I2C bus, the microcontroller
can read it from the SIMDRA/B register. Any transmission of data to the I2C bus or reception of data
from the I2C bus must be made via the SIMDRA/B register.
The SIMARA/B register is the location where the slave address of the microcontroller is stored. Bits
1~7 of the SIMARA/B register define the microcontroller slave address. Bit 0 is not defined. When
a master device, which is connected to the I2C bus, sends out an address, which matches the slave
address in the SIMARA/B register, the microcontroller slave device will be selected.
Note that the SIMARA/B register is the same register as SIMC2A/B which is used by the SPI
interface.
The SIMC0A/B register is used for the I2C overall on/off control.
  Slave Address Register - SIMARA/B
Rev. 1.00
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HT83B60
Voice Mask MCU
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Rev. 1.00
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HT83B60
Voice Mask MCU
I2C Configuration Option
There are several configuration options associated with the I2C interface. One of these is to
enable the RNICA/B bit function which selects the RNICA/B bit in SIMC1A/B register. Another
configuration option determines the debounce time of the I2C interface. This add a debounce delay
time to the external clock to reduce the possibility of glitches on the clock line causing erroneous
operation. The debounce time if selected can be chosen to be either 1 or 2 system clocks.
The following gives further explanation of each bit:
• SIMENA/B
The SIMENA/B bit determines if the I2C bus is enabled or disabled. If data is to be transferred or
received on the I2C bus then this bit must be set high.
The following gives further explanation of each bit:
• HCFA/B
The HCFA/B flag is the data transfer flag. This flag will be zero when data is being transferred.
Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated.
• HASSA/B
The HASSA/B flag is the address match flag. This flag is used to determine if the slave device
address is the same as the master transmit address. If the addresses match then this bit will be
high, if there is no match then the flag will be low.
• HBBA/B
The HBBA/B flag is the I2C busy flag. This flag will be high when the I2C bus is busy which will
occur when a START signal is detected. The flag will be reset to zero when the bus is free which
will occur when a STOP signal is detected.
• HTXA/B
The HTXA/B flag is the transmit/receive mode bit. This flag should be set high to set the transmit
mode and low for the receive mode.
• TXAKA/B
The TXAKA/B flag is the transmit acknowledge flag. After the receipt of 8-bits of data, this bit
will be transmitted to the bus on the 9th clock. To continue receiving more data, this bit has to be
reset to zero before further data is received.
• SRWA/B
The SRWA/B bit is the Slave Read/Write bit. This bit determines whether the master device
wishes to transmit or receive data from the I2C bus. When the transmitted address and slave
address match, that is when the HAASA/B bit is set high, the device will check the SRWA/B bit
to determine whether it should be in transmit mode or receive mode. If the SRWA/B bit is high,
the master is requesting to read data from the bus, so the device should be in transmit mode.
When the SRWA/B bit is zero, the master will write data to the bus, therefore the device should
be in receive mode to read this data.
• RNICA/B
The RNICA/B bit is used as I2C running clock from Internal or external clock. If this bit is low
then I2C running using internal clock and it will not wake-up when I2C interrupts in the Power
Down Mode. If the bit is high I2C running using external clock and it will wake-up when I2C
interrupts in the Power Down Mode.
Rev. 1.00
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HT83B60
Voice Mask MCU
• RXAKA/B
The RXAKA/B flag is the receive acknowledge flag. When the RXAKA/B bit has been reset to
zero it means that a correct acknowledge signal has been received at the 9th clock, after 8 bits
of data have been transmitted. When in the transmit mode, the transmitter checks the RXAKA/
B bit to determine if the receiver wishes to receive the next byte. The transmitter will therefore
continue sending out data until the RXAKA/B bit is set to "1". When this occurs, the transmitter
will release the SDAA/B line to allow the master to send a STOP signal to release the bus.
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I2C Bus Communication
Communication on the I2C bus requires four separate steps, a START signal, a slave device address
transmission, a data transmission and finally a STOP signal. When a START signal is placed on the
I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data
on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB.
If the address of the microcontroller matches that of the transmitted address, the HAAS bit in the
SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service
routine, the microcontroller slave device must first check the condition of the HAAS bit to determine
whether the interrupt source originates from an address match or from the completion of an 8-bit
data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the
following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit.
This bit will be checked by the microcontroller to determine whether to go into transmit or receive
mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus,
the following are steps to achieve this:
Step 1
Write the slave address of the microcontroller to the I2C bus address register SIMAR.
Step 2
Set the SIMEN bit in the SIMC0 register to "1" to enable the I2C bus.
Step 3
Rev. 1.00
Set the EHI bit of the interrupt control register to enable the I2C bus interrupt.
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Voice Mask MCU
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• Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not
by the microcontroller, which is only a slave device. This START signal will be detected by
all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and
therefore the HBB bit will be set. A START condition occurs when a high to low transition on the
SDA line takes place when the SCL line remains high.
• Slave Address
The transmission of a START signal by the master will be detected by all devices on the I2C
bus. To determine which slave device the master wishes to communicate with, the address of the
slave device will be sent out immediately following the START signal. All slave devices, after
receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address
sent out by the master matches the internal address of the microcontroller slave device, then an
internal I2C bus interrupt signal will be generated. The next bit following the address, which is
the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register.
The device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The
microcontroller slave device will also set the status flag HAAS when the addresses match.
As an I2C bus interrupt can come from two sources, when the program enters the interrupt
subroutine, the HAAS bit should be examined to see whether the interrupt source has come from
a matching slave address or from the completion of a data byte transfer. When a slave address is
matched, the device must be placed in either the transmit mode and then write data to the SIMDR
register, or in the receive mode where it must implement a dummy read from the SIMDR register
to release the SCL line.
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Voice Mask MCU
• SRW Bit
The SRW bit in the SIMC1 register defines whether the microcontroller slave device wishes
to read data from the I2C bus or write data to the I2C bus. The microcontroller should examine
this bit to determine if it is to be a transmitter or a receiver. If the SRW bit is set to "1" then this
indicates that the master wishes to read data from the I2C bus, therefore the microcontroller slave
device must be setup to send data to the I2C bus as a transmitter. If the SRW bit is "0" then this
indicates that the master wishes to send data to the I2C bus, therefore the microcontroller slave
device must be setup to read data from the I2C bus as a receiver.
• Acknowledge Bit
After the master has transmitted a calling address, any slave device on the I2C bus, whose
own internal address matches the calling address, must generate an acknowledge signal. This
acknowledge signal will inform the master that a slave device has accepted its calling address. If
no acknowledge signal is received by the master then a STOP signal must be transmitted by the
master to end the communication. When the HAAS bit is high, the addresses have matched and
the microcontroller slave device must check the SRW bit to determine if it is to be a transmitter
or a receiver. If the SRW bit is high, the microcontroller slave device should be setup to be a
transmitter so the HTX bit in the SIMC1 register should be set to "1" if the SRW bit is low then
the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1
register should be set to "0".
• Data Byte
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged
receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB
last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the transmitter does not receive an acknowledge bit
signal from the receiver, then it will release the SDA line and the master will send out a STOP
signal to release control of the I2C bus. The corresponding data will be stored in the SIMDR
register. If setup as a transmitter, the microcontroller slave device must first write the data to be
transmitted into the SIMDR register. If setup as a receiver, the microcontroller slave device must
read the transmitted data from the SIMDR register.
Data Timing Diagram
• Receive Acknowledge Bit
When the receiver wishes to continue to receive the next data byte, it must generate an
acknowledge bit, known as TXAK, on the 9th clock. The microcontroller slave device, which is
setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send
another data byte, if not then it will release the SDA line and await the receipt of a STOP signal
from the master.
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Voice Mask MCU
        I2C Bus ISR Flow Chart
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I2C Bus Initialisation Flow Chart
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HT83B60
Voice Mask MCU
Voice ROM Access
The device provides two serial interface modules, called SIMA and SIMB. SIMA is dedicated to
access the internal voice ROM while SIMB can be used as an independent SPI or I2C function to
communicate with external devices. As SIMA communicates with the Voice ROM using its SPI
interface, it must be setup to activate the SPIA function by the SIMC0A register. The PB4~PB7 pins
are pin shared with the SPIA interface, SDOA, SCKA, SDIA and SCSA pins respectively. In order
not to interfere SPIA function, the pin-shared I/O pins, PB4~PB7, should be set as input pins using
the application program, while PB5, PB6 and PB7 should also have pull high resistors enabled using
configuration option. The accompanying diagram illustrates the SPI interface with the Voice ROM
block diagram.
SDOA
SDIA
SCKA
SPI to Voice ROM
Interface
Voice ROM
SCSA
SIMA SPI Interface with Voice ROM
Voice ROM SPI Modes
The device provides the SPI mode 0 and mode 3 to access the internal voice ROM. The difference
between these two modes is the setting on the SPI clock edge and polarity selections. The designer
should follow the Voice ROM SPI modes to select the SPIA clock pin, namely SCKA, input edge
and polarity by the CKPOLA and CKEGA bits in the SIMC2A register. The following diagram
illustrates the timing diagram.
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Voice Mask MCU
Voice ROM Read Commands
The device has READ and FAST_READ commands to access data from the internal Voice ROM.
The READ command code is "03H" while the FAST_READ command code is “0BH”. Both of the
READ and FAST_READ commands can be used to read one byte or bulk data from the Voice ROM.
The FAST_READ command is used to access the Voice ROM data using a higher speed SPI clock
rate. The clock rate can be up to 85MHz, however, as the maximum system clock is 12MHz, these
two commands will have the same performance.
READ Command
The READ command is used to read data from the Voice ROM. The address is latched on the
rising edge of the SPI clock pin, namely SCKA, and the data will be shifted out on the falling
edge of SCKA. The first address byte can point to any location in the Voice ROM. The address
is automatically incremented to the next address after each byte data is shifted out, so the whole
memory can be read out using a single READ command. The address will roll over to 0 when the
highest address has been reached. The accompanying flowchart and diagram illustrate the READ
data command setting procedure and the timing diagram.
READ Command
Procedure
Clear SCSAB pin =0
Send READ command
code= 03 to SDOA pin
Send 3 bytes address to
SDOA pin
Read data on SDIA pin
Set SCSAB pin=1
End
READ Command Procedure
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HT83B60
Voice Mask MCU
SCSA
SCKA
0
1
�
3
4
5
6
7
8
Command
SDOA
�8 �� 30 31 3� 33 34 35 36 37 38 3�
� 10
�4-Bit Address
�3 �� �1
03
3
�
1
0
MSB
SDIA
Data Out 1
Hign-Z
7
6
5
4
3
Data Out �
�
1
0
7
MSB
READ Command Procedure Timing Diagram
FAST_READ Command
The FAST_READ command provides a higher speed to access the Voice ROM data. The address
is latched on the rising edge of the SPI clock pin, namely SCKA, and each bit of the data will be
shifted out on the falling edge of SCKA. The first address byte can point to any location in the voice
ROM. The address is automatically incremented to the next address after each byte data is shifted
out, so the whole memory can be read out by a single FAST_READ command. The address will
roll over to 0 when the highest address has been reached. The accompanying flowchart and diagram
illustrate the FAST_READ data instruction setting procedure and the timing diagram.
FAST_READ
Command Procedure
Clear SCSAB pin =0
Send FAST_READ
command code= 0BH
to SDOA pin
Send 3 bytes address to
SDOA pin
Send 1 byte dummy byte
address to SDOA pin
Read data on SDIA pin
Set SCSAB pin=1
End
FAST_READ Command Procedure
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HT83B60
Voice Mask MCU
SCSA
0
SCKA
1
�
3
4
5
6
7
8
Command
SDOA
�8 �� 30 31
� 10
�4-Bit Address
�3 �� �1
0B
3
�
1
0
Hign-Z
SDIA
SCSA
3� 33 34 35 36 37 38 3� 40 41 4� 43 44 45 46 47
SCKA
Command
SDOA
7
6
5
4
3
�
1
0
Data Out 1
SDIA
7
6
5
4
3
�
Data Out �
1
0
MSB
7
6
5
4
3
�
1
MSB
0
7
MSB
FAST_READ Command Procedure Timing Diagram
Voice Output
The device contains an internal 12-bit DAC function which can be used for audio signal generation.
Voice Control
Two internal registers DAL and DAH contain the 12-bit digital value for conversion by the internal
DAC. There is also a DAC enable/disable control bit in the PWMC control register for overall on/
off control of the DAC circuit. If the DAC circuit is not enabled, the DAH/DAL value outputs will
be invalid. Writing a "1" to the DAC bit in bit1 of PWMC will enable the enable DAC circuit, while
writing a "0" to the DAC bit will disable the DAC circuit.
Audio Output and Volume Control - DAL, DAH, VOL
The audio output is 12-bits wide whose highest 8-bits are written into the DAH register and whose
lowest four bits are written into the highest four bits of the DAL register. Bits 0~3 of the DAL
register are always read as zero. There are 8 levels of volume which are setup using the VOL
register. Only the lowest 3-bits of this register are used for volume control.

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­ € ‚ ­ € ‚ ­ € ‚     Rev. 1.00
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HT83B60
Voice Mask MCU
VOL[2:0]
DAC Volume Control
111
High Volume
↑
110
101
100
011
010
001
↓
Low Volume
000
Pulse Width Modulation Output
All devices include a single 12-bit PWM function which can directly drive external audio
components such as speakers.
Pulse Width Modulator Operation
The PWM output is provided on two complimentary outputs on the PWM1 and PWM2 pins,
providing a differential output pair and thus capable of higher drive power. These two pins can
directly drive a piezo buzzer or an 8 ohm speaker without using external components. The PWM
outputs can also be used single ended, where the signal is provided on the PWM1 output, and
again can also be used by itself alone to drive a piezo buzzer or an 8 ohm speaker without external
components. This single end output drive type is chosen using the SINGLE_PWM bit in the PWMC
register.
If the MSB_SIGN bit is low, then the signal that is provided on PWM1and PWM2 will obtain a
GND level voltage after setting the PWMCC bit high. If the MSB_SIGN bit is high, then the signal
that is provided on PWM2 and PWM1 will have a GND level voltage when the PWMCC bit is set
high.
The two PWM outputs will initially be at low levels, and if the PWM function is stopped will also
return to a low level. If the PWMCC bit changes from low to high then the PWM function will start
running and latch new data. If the data is not updated then the old value will remain. If the PWMCC
bit changes from high to low, at the end of the duty cycle, the PWM output will stop.
VOL[3:0]
PWM Volume Control
1xxx
High Volume
0111
↑
0110
0101
0100
0011
0010
Rev. 1.00
0001
↓
0000
Low Volume
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HT83B60
Voice Mask MCU

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HT83B60
Voice Mask MCU
Interrupts
Interrupts are an important part of any microcontroller system. When an internal function such as
a Time Base or Timer requires microcontroller attention, their corresponding interrupt will enforce
a temporary suspension of the main program allowing the microcontroller to direct attention to
their respective needs. Each device contains a Time Base interrupt and two internal timer interrupt
functions. The Time Base interrupt is controlled by bit 1 of INTC register, while the internal
interrupt is controlled by the Timer Counter overflow.
  
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 Interrupt Structure
Interrupt Register
Overall interrupt control, which means interrupt enabling and flag setting, is controlled using two
registers, known as INTC and INTCH, which are located in the Data Memory. By controlling the
appropriate enable bits in these registers each individual interrupt can be enabled or disabled. Also
when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The
global enable flag if cleared to zero will disable all interrupts.
   
Interrupt Control Register
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HT83B60
Voice Mask MCU
 
   
  INTCH Register
Interrupt Operation
A timer or Time Base overflow or by setting their corresponding request flag, if their appropriate
interrupt enable bit is set. When this happens, the Program Counter, which stores the address of
the next instruction to be executed, will be transferred onto the stack. The Program Counter will
then be loaded with a new address which will be the value of the corresponding interrupt vector.
The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at
this vector will usually be a JMP statement which will take program execution to another section
of program which is known as the interrupt service routine. Here is located the code to control the
appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which
retrieves the original Program Counter address from the stack and allows the microcontroller to
continue with normal execution at the point where the interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
accompanying diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will
be cleared automatically. This will prevent any further interrupt nesting from occurring. However,
if other interrupt requests occur during this interval, although the interrupt will not be immediately
serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the
program is already in another interrupt service routine, the EMI bit should be set after entering the
routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service
is desired, the stack must be prevented from becoming full.
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Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the accompanying table shows the priority that is applied.
Interrupt Source
Interrupt Vector
HT83B60 Priority
Time Base Interrupt
04H
1
Timer 0 Overflow
08H
2
Timer 1 Overflow
0CH
3
SIM A Interrupt
10H
4
SIM B Interrupt
14H
5
Suitable masking of the individual interrupts using the INTC and INTCH registers can prevent
simultaneous occurrences.
Time Base Interrupt
Each device contains a Time Base whose corresponding interrupt enable bits are known as ETBI
and is located in the INTC register. For a Time Base generated interrupt to occur, the corresponding
Time Base interrupt enable bit must be first set. Time Base also has a corresponding Time Base
interrupt request flag, which is known as TBF, also located in the INTC register. When the master
interrupt and corresponding timer interrupt enable bits are enabled, the stack is not full, and when
the corresponding timer overflows a subroutine call to the corresponding Time Base interrupt vector
will occur. The corresponding Program Memory vector locations for the Time Base is 04H. After
entering the interrupt execution routine, the corresponding interrupt request flag, TBF will be reset
and the EMI bit will be cleared to disable other interrupts.
Timer Interrupt
For a timer generated interrupt to occur, the corresponding timer interrupt enable bit must be first
set. Each device contains two 8-bit timers whose corresponding interrupt enable bits are known
as ET0 and ET1and are located in the INTC register. Each timer also has a corresponding timer
interrupt request flag, which are known as T0F and T1F, also located in the INTC register. When the
master interrupt and corresponding timer interrupt enable bits are enabled, the stack is not full, and
when the corresponding timer overflows a subroutine call to the corresponding timer interrupt vector
will occur. The corresponding Program Memory vector locations for Timer 0 and Timer1 are 08H
and 0CH. After entering the interrupt execution routine, the corresponding interrupt request flags,
T0F or T1F will be reset and the EMI bit will be cleared to disable other interrupts.
Serial Interface Module - SIM - Interrupt
SIMA/B Interrupts include both the SPI and I2C Interrupts. The SIMA/B Mode is determined by the
SIM2A/B, SIM1A/B and SIM0A/B bits in the SIMC0A/B register.
For a SPI Interrupt to occur, the global interrupt enable bit, EMI, and the corresponding SIMA/
B interrupt enable bit, ESII, must be first set. The SIMENA/B bit in the SIMC0A/B register must
also be set. An actual SPI Interrupt will take place when the flag, SIFA/B, is set, a situation that will
occur when 8-bits of data are transferred or received from either of the SPI interfaces. When the
interrupt is enabled, the stack is not full and an SIMA/B interrupt occurs, a subroutine call to the
SIMA/B interrupt vector at location 10H, will take place. When the interrupt is serviced, the SPIA/
B interrupt request flag, SIFA/B, will be automatically reset and the EMI bit will be automatically
cleared to disable other interrupts.
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Voice Mask MCU
For an I2C interrupt to occur, the corresponding interrupt enable bit ESIIA/B must be first set. An
actual I2C interrupt will be initialized when the SIMA/B interrupt request flag, SIFA/B, is set, a
situation that will occur when a matching I2C slave address is received or from the completion of
an I2C data byte transfer. When the interrupt is enabled, the stack is not full and a SIMA/B interrupt
occurs, a subroutine call to the SIMA/B interrupt vector at location 14H, will take place When an
I2C interrupt occurs, the interrupt request flag SIFA/B will be reset and the EMI bit will be cleared to
disable other interrupts.
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced,
however, once an interrupt request flag is set, it will remain in this condition in the INTC or INTCH
register until the corresponding interrupt is serviced or until the request flag is cleared by a software
instruction.
It is recommended that programs do not use the "CALL subroutine" instruction within the interrupt
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately
in some applications. If only one stack is left and the interrupt is not well controlled, the original
control sequence will be damaged once a "CALL subroutine" is executed in the interrupt subroutine.
All of these interrupts have the capability of waking up the processor when in the Power Down
Mode. Only the Program Counter is pushed onto the stack. If the contents of the register or
status register are altered by the interrupt service program, which may corrupt the desired control
sequence, then the contents should be saved in advance.
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
In addition to the power-on reset, situations may arise where it is necessary to forcefully apply
a reset condition when the microcontroller is running. One example of this is where after power
has been applied and the microcontroller is already running, the RES line is forcefully pulled low.
In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with normal operation after the reset line is
allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the
microcontroller. All types of reset operations result in different register conditions being setup.
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Voice Mask MCU
Reset Functions
There are five ways in which a microcontroller reset can occur, through events occurring both
internally and externally.
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all pins will be first set to inputs.
Although the microcontroller has an internal RC reset function, if the VDD power supply rise time
is not fast enough or does not stabilise quickly at power-on, the internal reset function may be
incapable of providing proper reset operation. For this reason it is recommended that an external
RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin
remains low for an extended period to allow the power supply to stabilise. During this time delay,
normal operation of the microcontroller will be inhibited. After the RES line reaches a certain
voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the
microcontroller will begin normal operation. The abbreviation SST in the figures stands for System
Start-up Timer.
Power-On Reset Timing Chart
For most applications a resistor connected between VDD and the RES pin and a capacitor connected
between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to
the RES pin should be kept as short as possible to minimise any stray noise interference.
Basic Reset Circuit
For applications that operate within an environment where more noise is present the Enhanced Reset
Circuit shown is recommended.
Enhanced Reset Circuit
More information regarding external reset circuits is located in Application Note HA0075E on the
Holtek website.
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Voice Mask MCU
RES Pin Reset
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully
pulled low by external hardware such as an external switch. In this case as in the case of other reset,
the Program Counter will reset to zero and program execution initiated from this point.
RES Reset Timing Chart
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset
except that the Watchdog time-out flag TO will be set to "1".
WDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during Power Down
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most
of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be
cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details.
WDT Time-out Reset during Power Down Timing Chart
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the
table:
TO
PDF
RESET Conditions
0
0
RES reset during power-on
u
u
RES or LVR reset during normal operation
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Note: "u" stands for unchanged
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Voice Mask MCU
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer
All Timer will be turned off
Prescaler
The Timer Prescaler will be cleared
Input/Output Ports
I/O ports will be setup as inputs
Stack Pointer
Stack Pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers. Note that where
more than one package type exists the table will reflect the situation for the larger package type.
Register
MP0
ACC
PCL
TBLP
TBLH
WDTS
STATUS
INTC
TMR0
TMR0C
TMR1
TMR1C
PA
PAC
PB
PBC
PC
PCC
INTCH
DAL
DAH
PWMC
PWML
PWMH
VOL
SIMC0A
SIMC1A
SIMDRA
SIMARA/
SIMC2A
SIMC0B
SIMC1B
SIMDRB
SIMARB/
SIMC2B
PCPHC
Reset
(Power-on)
xxxx
xxxx
0000
xxxx
xxxx
0000
−−00
−000
0000
0100
0000
0100
1111
1111
1111
1111
−−−−
−−−−
−−00
xxxx
xxxx
0−−−
xxxx
xxxx
xxxx
111x
100x
xxxx
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
xxxx
xxxx
0000
xxxx
xxxx
0111
xxxx
0000
0000
0000
0000
0000
1111
1111
1111
1111
−111
−111
−−00
−−−−
xxxx
0000
−−−−
xxxx
−xxx
xx0−
x0x1
xxxx
uuuu
uuuu
0000
uuuu
uuuu
0000
−− 1u
−000
0000
0100
0000
0100
1111
1111
1111
1111
−−−−
−−−−
−−00
uuuu
uuuu
0−−−
uuuu
uuuu
uuuu
111x
100x
xxxx
uuuu
uuuu
0000
uuuu
uuuu
0111
uuuu
0000
0000
0000
0000
0000
1111
1111
1111
1111
−111
−111
−−00
−−−−
uuuu
0000
−−−−
uuuu
−uuu
xx0−
x0x1
xxxx
uuuu
uuuu
0000
uuuu
uuuu
0000
−−uu
−000
0000
0100
0000
0100
1111
1111
1111
1111
−−−−
−−−−
−−00
uuuu
uuuu
0−−−
uuuu
uuuu
uuuu
111x
100x
xxxx
uuuu
uuuu
0000
uuuu
uuuu
0111
uuuu
0000
0000
0000
0000
0000
1111
1111
1111
1111
−111
−111
−−00
−−−−
uuuu
0000
−−−−
uuuu
−uuu
xx0−
x0x1
xxxx
RES Reset
(HALT)
uuuu
uuuu
0000
uuuu
uuuu
0000
−− 01
−000
0000
0100
0000
0100
1111
1111
1111
1111
−−−−
−−−−
−−00
uuuu
uuuu
0−−−
uuuu
uuuu
uuuu
111x
100x
xxxx
WDT Time-out
from HALT
uuuu
uuuu
0000
uuuu
uuuu
0111
uuuu
0000
0000
0000
0000
0000
1111
1111
1111
1111
−111
−111
−−00
−−−−
uuuu
0000
−−−−
uuuu
−uuu
xx0−
x0x1
xxxx
uuuu
uuuu
0000
uuuu
uuuu
uuuu
−−11
−uuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
−−−−
−−−−
−−uu
uuuu
uuuu
u−−−
uuuu
uuuu
uuuu
uuux
uuux
xxxx
uuuu
uuuu
0000
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
−uuu
−uuu
−−uu
−−−−
uuuu
uuuu
−−−−
uuuu
−uuu
xxu−
xuxu
xxxx
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
111x xx0−
100x x0x1
xxxx xxxx
111x xx0−
100x x0x1
xxxx xxxx
111x xx0−
100x x0x1
xxxx xxxx
111x xx0−
100x x0x1
xxxx xxxx
uuux xxu−
uuux xuxu
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
−−−− −000
−−−− −000
−−−− −000
−−−− −000
−−−− −uuu
Note: "u" stands for unchanged
"x" stands for unknown
"-" stands for undefined
Rev. 1.00
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Voice Mask MCU
Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements. Three types of system clocks can be selected while various clock source
options for the Watchdog Timer are provided for maximum flexibility. All oscillator options are
selected through the configuration options.
The three methods of generating the system clock are:
• External crystal/resonator oscillator
• External RC oscillator
• Internal RC oscillator
One of these three methods must be selected using the configuration options.
More information regarding the oscillator is located in Application Note HA0075E on the Holtek
website.
External Crystal/Resonator Oscillator
The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift
and feedback for oscillation, and will normally not require external capacitors. However, for some
crystals and most resonator types, to ensure oscillation and accurate frequency generation, it may
be necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2
should be selected in consultation with the crystal or resonator manufacturer┬ specification. The
external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to
assist with oscillation start up.
Internal Ca, Cb, Rf Typical Values @ 5V, 25°C
Ca
Cb
Rf
11~13pF
13~15pF
800kΩ
Oscillator Internal Component Values
      Crystal/Resonator Oscillator
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Voice Mask MCU
External RC Oscillator
Using the external system RC oscillator requires that a resistor, with a value between 150kW and
300kW, is connected between OSC1 and VSS. The generated system clock divided by 4 will be
provided on OSC2 as an output which can be used for external synchronization purposes. Note that
as the OSC2 output is an NMOS open-drain type, a pull high resistor should be connected if it to
be used to monitor the internal frequency. Although this is a cost effective oscillator configuration,
the oscillation frequency can vary with VDD, temperature and process variations and is therefore
not suitable for applications where timing is critical or where accurate oscillator frequencies are
required. For the value of the external resistor ROSC refer to the Holtek website for typical RC
Oscillator vs. Temperature and VDD characteristics graphics. Note that it is the only microcontroller
internal circuitry together with the external resistor, that determine the frequency of the oscillator.
The external capacitor shown on the diagram does not influence the frequency of oscillation.
External RC Oscillator
Internal RC Oscillator
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz selected
by configuration options. Device trimming during the manufacturing process and the inclusion of
internal frequency compensation circuits are used to ensure that the influence of the power supply
voltage, temperature and process variations on the oscillation frequency are minimised. As a result,
at a power supply of either 3.3V or 5V and at a temperature of 25° degrees, the fixed oscillation
frequency of 4MHz, 8MHz or 12MHz will have a tolerance within 2%. Note that if this internal
system clock option is selected, as it requires no external pins for its operation, I/O pins PC1 and
PC2 are free for use as normal I/O pins.
Internal RC Oscillator -- HIRC
Watchdog Timer Oscillator
The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period
of 65ms at 5V requiring no external components. When the device enters the Power Down Mode,
the system clock will stop running but the WDT oscillator continues to free-run and to keep the
watchdog active. However, to preserve power in certain applications the WDT oscillator can be
disabled via a configuration option.
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Voice Mask MCU
Power Down Mode and Wake-up
Power Down Mode
All of the Holtek microcontrollers have the ability to enter a Power Down Mode, also known as the
"HALT" Mode or Sleep Mode. When the device enters this mode, the normal operating current, will
be reduced to an extremely low standby current level. This occurs because when the device enters
the Power Down Mode, the system oscillator is stopped which reduces the power consumption
to extremely low levels, however, as the device maintains its present internal condition, it can
be woken up at a later stage and continue running, without requiring a full reset. This feature is
extremely important in application areas where the MCU must have its power supply constantly
maintained to keep the device in a known condition but where the power supply capacity is limited
such as in battery applications.
Entering the Power Down Mode
There is only one way for the device to enter the Power Down Mode and that is to execute the
"HALT" instruction in the application program. When this instruction is executed, the following will
occur:
• The system oscillator will stop running and the application program will stop at the "HALT"
instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting if the WDT clock source is selected to come from
the WDT oscillator. The WDT will stop if its clock source originates from the system clock.
• The I/O ports will maintain their present condition.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Standby Current Considerations
As the main reason for entering the Power Down Mode is to keep the current consumption of the
MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are
other considerations which must also be taken into account by the circuit designer if the power
consumption is to be minimized. Special attention must be made to the I/O pins on the device. All
high-impedance input pins must be connected to either a fixed high or low level as any floating input
pins could create internal oscillations and result in increased current consumption. Care must also
be taken with the loads, which are connected to I/Os, which are setup as outputs. These should be
placed in a condition in which minimum current is drawn or connected only to external circuits that
do not draw current, such as other CMOS inputs. Also note that additional standby current will also
be required if the configuration options have enabled the Watchdog Timer internal oscillator.
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Voice Mask MCU
Wake-up
After the system enters the Power Down Mode, it can be woken up from one of various sources
listed as follows:
• An external reset
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset,
however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated.
Although both of these wake-up methods will initiate a reset operation, the actual source of the
wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog Timer instructions and is set when executing the
"HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and Stack Pointer, the other flags remain in their original status.
Each pin on Port A can be setup via an individual configuration option to permit a negative transition
on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume
execution at the instruction following the "HALT" instruction.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where
the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the
program will resume execution at the instruction following the "HALT" instruction. In this situation,
the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced
later when the related interrupt is finally enabled or when a stack level becomes free. The other
situation is where the related interrupt is enabled and the stack is not full, in which case the regular
interrupt response takes place. If an interrupt request flag is set to "1" before entering the Power
Down Mode, the wake-up function of the related interrupt will be disabled.
No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period
equal to 1024 system clock periods will be required before normal system operation resumes.
However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution
will be delayed by an additional one or more cycles. If the wake-up results in the execution of the
next instruction following the "HALT" instruction, this will be executed immediately after the 1024
system clock period delay has ended.
Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of
the device, which is selected via a configuration option. If the supply voltage of the device drops
to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will
automatically reset the device internally.
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Voice Mask MCU
Low Voltage Detector - LVD
This Low Voltage Detect internal function provides a means for the user to monitor when the
power supply voltage falls below a certain fixed level as specified in the DC characteristics. Bit 2
of PWMC register and Low Voltage Detector option are used to control the overall function of the
LVD. Low Voltage Detector option is the enable/disable control bit, when select disable the overall
function of the LVD will be disabled.
Bit 2 is the LVD detector output bit and is known as LVDF. Under normal operation, and when the
power supply voltage is above the specified VLVD value in the DC characteristic section, the LVDF
bit will remain at a zero value. If the power supply voltage should fall below this VLVD value then
the LVDF bit will change to a high value indicating a low voltage condition. Note that the LVDF
bit is a read-only bit. By polling the LVDF bit in the PWMC register, the application program can
therefore determine the presence of a low voltage condition.
Operation
The Low Voltage Detector must first be enabled using a configuration option.
The LVD control bit is bit 2 of the PWMC regsiter and is known as LVDF. Under normal operation,
and when the power supply voltage is above the specified VLVD value in the DC characteristic
section, the LVDF bit will remain at a zero value. If the power supply voltage should fall below this
VLVD value then the LVDF bit will change to a high value indicating a low voltage condition. Note
that the LVDF bit is a read-only bit. By polling the LVDF bit in the PWMC register, the application
program can therefore determine the presence of a low voltage condition.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise. It operates
by providing a device reset when the WDT counter overflows. The WDT clock is supplied by one
of two sources selected by configuration option: its own self-contained dedicated internal WDT
oscillator, or the instruction clock which is the system clock divided by 4. Note that if the WDT
configuration option has been disabled, then any instruction relating to its operation will result in no
operation.
The internal WDT oscillator has an approximate period of 65ms at a supply voltage of 5V. If
selected, it is first divided by 256 via an 8-stage counter to give a nominal period of 17ms. Note
that this period can vary with VDD, temperature and process variations. For longer WDT timeout periods the WDT prescaler can be utilized. By writing the required value to bits 0, 1 and 2 of
the WDTS register, known as WS0, WS1 and WS2, longer time-out periods can be achieved. With
WS0, WS1 and WS2 all equal to 1, the division ratio is 1:128 which gives a maximum time-out
period of about 2.1s.
A configuration option can select the instruction clock, which is the system clock divided by 4, as
the WDT clock source instead of the internal WDT oscillator. If the instruction clock is used as the
clock source, it must be noted that when the system enters the Power Down Mode, as the system
clock is stopped, then the WDT clock source will also be stopped. Therefore the WDT will lose
its protecting purposes. In such cases the system cannot be restarted by the WDT and can only be
restarted using external signals. For systems that operate in noisy environments, using the internal
WDT oscillator is therefore the recommended choice.
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Voice Mask MCU
Under normal program operation, a WDT time-out will initialise a device reset and set the status bit
TO. However, if the system is in the Power Down Mode, when a WDT time-out occurs, only the
Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents
of the WDT and the WDT prescaler. The first is an external hardware reset, which means a low level
on the RES pin, the second is using the watchdog software instructions and the third is via a "HALT"
instruction.
There are two methods of using software instructions to clear the Watchdog Timer, one of which
must be chosen by configuration option. The first option is to use the single "CLR WDT" instruction
while the second is to use the two commands "CLR WDT1" and "CLR WDT2". For the first option,
a simple execution of "CLR WDT" will clear the WDT while for the second option, both "CLR
WDT1" and "CLR WDT2" must both be executed to successfully clear the WDT. Note that for this
second option, if "CLR WDT1" is used to clear the WDT, successive executions of this instruction
will have no effect, only the execution of a "CLR WDT2" instruction will clear the WDT. Similarly,
after the "CLR WDT2" instruction has been executed, only a successive "CLR WDT1" instruction
can clear the Watchdog Timer.
b 7
W S 2
b 0
W S 1
W S 0
W D T p r e s c a le r r a te s e le c t
W D T
W S 0
W S 1
W S 2
1
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
:1
R a te
:2
:4
:8
:1 6
:3 2
:6 4
:1 2 8
N o t u s e d
Watchdog Timer Register
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€ ‚ ƒ   ­ €    ‚ ƒ     Watchdog Timer
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HT83B60
Voice Mask MCU
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device
during the programming process. During the development process, these options are selected using
the HT-IDE software development tools. As these options are programmed into the device using the
hardware programming tools, once they are selected they cannot be changed later by the application
software.
No.
Options
I/O Options
1
PA0~PA7: wake-up enable or disable
2
PA0~PA7: pull-high enable or disable
3
PB0~PB7: pull-high enable or disable
Oscillator Options
4
OSC type selection: ERC, crystal or HIRC
HIRC Options
5
HIRC option: 4MHz, 8MHz, 12MHz
Watchdog Options
6
WDT: enable or disable
7
WDT clock source: WDTOSC or T1
PB I/O Port Output Voltage Options
8
VDD_PBIO/VDD type selection: VDD_PBIO or VDD for Port B, SPI, I2C I/O per bit
LVR Option
9
LVR function: enable or disable
LVD Option
10
LVD function: enable or disable
Reset Options
11
Reset function: PC0 or reset pin
SIMA Options
12
SIMA Function: enable or disable
13
SPIA S/W CSEN: enable or disable
14
SPIA S/W WCOL: enable or disable
15
I2CA RNIC: enable or disable
16
I2CA debounce time: 0/1/2 system clocks
SIMB Options
17
SIMB Function: enable or disable
18
SPIB S/W CSEN: enable or disable
19
SPIB S/W WCOL: enable or disable
20
I2CB RNIC: enable or disable
21
I2CB debounce time: 0/1/2 system clocks
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Voice Mask MCU
Application Circuits
VDD
Power Circuit
VDD1
R11
VDD2
10
SW24
OFF 3
D2
2
VDD
POWER SWITCH
1N5817
R9
C2
330
0.1u
HT7233
VIN
VOUT
BT1
BATTERY
+ C1
100u
D1
Power LED
V33
3
1
Mini USB CON
10u
U3
2
GND
ON 1
1
2
3
4
5
VDD
USBUSB+
VSS
VSS
1
JA1
C12
C19
C20
0.1u
10u
2
VSS
R12
0
VSS1
Power Amplifier
U1
VDD2
VSS1
AUD
VDD2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PA2
PA3
PA4
PA5
PA6
PA7
VSS
RESB
VSS1
PWM2
PWM1
VDD1
V33
VDD
VDD
AUD
VDD1
3
PA2
PA1
PA3
PA0
PA4
PB0
PA5
PB1
PB2
PA6
PB4/SDOA
PA7
VSS
PB5/SCLKA
VDD
PB6/SDIA
PB7/SCSA VDD_PBIO
PC0/RES
PC1/OSC1
VSSP
PC2/OSC2
PWM2
VSSA
AUD
PWM1
VDDA
VDDP
R5
100K
50K
2 VOL
VR1
C10
0.1uF
VDD1
C25
C22
C3
0.1u
0.1u
0.1u
C11
C9
0.01u
10uF
SP-
1
AUD_IN
2
VREF
3
VSS1
4
U2
OUTN
VDD
AUDIN OUTP
Vref
NC
VSS
CEB
HT82V739
8-SOP (150 mil)
8
7
SP+
6
5
PB2
C8
C23
100uF
0.1u
2
HT83B60
SW9
RESET
1
PB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
PA1
PA0
VSS1
VSS1
LED & KEY
VDD
R8
330
D4
PLAY
LED
PB2
Rev. 1.00
SW1
S1 KEY1
2
PA0
1
PA1
S2 KEY2
2
1
PA2
1
S3 KEY3
2
PA3
1
S4 KEY4
2
PA4
1
S5 KEY5
2
PA5
S6 KEY6
2
1
PA6
1
S7 KEY7
2
PA7
1
S8 KEY8
2
67
PWM1
1
SP+
3
PWM2
4
SP-
6
2
5
LS1
SPEAKER
December 19, 2011
HT83B60
Voice Mask MCU
Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5µs and branch or call instructions would be implemented within
1µs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be ″CLR PCL″ or ″MOV PCL, A″. For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
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Logical and Rotate Operations
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
where rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction or
to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine
call, the program must return to the instruction immediately when the subroutine has been carried
out. This is done by placing a return instruction RET in the subroutine which will cause the program
to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is no requirement to jump back to the original
jumping off point as in the case of the CALL instruction. One special and extremely useful set
of branch instructions are the conditional branches. Here a decision is first made regarding the
condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and jump to the following instruction. These
instructions are the key to decision making and branching within the program perhaps determined
by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the ″SET [m].i″ or ″CLR [m].i″
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be setup as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the ″HALT″ instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
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Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.
Table conventions:
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
1Note
1Note
1Note
1
1
1
1Note
1
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
1
1Note
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
1
Bit Operation
CLR [m].i
SET [m].i
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Voice Mask MCU
Mnemonic
Description
Cycles
Flag Affected
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no
skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ″CLR WDT1″ and ″CLR WDT2″ instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ″CLR WDT1″ and ″CLR WDT2″
instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.00
71
December 19, 2011
HT83B60
Voice Mask MCU
Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C
ADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C
Add Data Memory to ACC
ADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C
ADD A,x
Description
Operation
Affected flag(s)
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C
ADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C
AND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
AND A,x
Description
Operation
Affected flag(s)
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
ANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
Rev. 1.00
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December 19, 2011
HT83B60
Voice Mask MCU
CALL addr
Description
Operation
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Affected flag(s)
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT1
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in
conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have
effect. Repetitively executing this instruction without alternately executing CLR WDT2 will
have no effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT2
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction
with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect.
Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
Rev. 1.00
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HT83B60
Voice Mask MCU
CPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
DAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
HALT
Description
Operation
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
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HT83B60
Voice Mask MCU
JMP addr
Description
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
OR A,x
Description
Operation
Affected flag(s)
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
ORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
RET
Description
Operation
Affected flag(s)
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
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December 19, 2011
HT83B60
Voice Mask MCU
RET A,x
Description
Operation
Affected flag(s)
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
RETI
Description
Operation
Affected flag(s)
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Program Counter ← Stack
EMI ← 1
None
RL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i = 0~6)
[m].0 ← [m].7
None
RLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i = 0~6)
ACC.0 ← [m].7
None
RLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i = 0~6)
[m].0 ← C
C ← [m].7
C
RLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i = 0~6)
ACC.0 ← C
C ← [m].7
C
RR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i = 0~6)
[m].7 ← [m].0
None
Rev. 1.00
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December 19, 2011
HT83B60
Voice Mask MCU
RRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i = 0~6)
ACC.7 ← [m].0
None
RRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i = 0~6)
[m].7 ← C
C ← [m].0
C
RRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i = 0~6)
ACC.7 ← C
C ← [m].0
C
SBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C
SBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C
SDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m] = 0
None
Rev. 1.00
77
December 19, 2011
HT83B60
Voice Mask MCU
SDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC = 0
None
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m] = 0
None
SIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC = 0
None
SNZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is not 0
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
SUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C
Rev. 1.00
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HT83B60
Voice Mask MCU
SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C
SUB A,x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7 ~ [m].4
None
SWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3 ~ ACC.0 ← [m].7 ~ [m].4
ACC.7 ~ ACC.4 ← [m].3 ~ [m].0
None
SZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m] = 0
None
SZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m] = 0
None
SZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i = 0
None
Rev. 1.00
79
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HT83B60
Voice Mask MCU
TABRDC [m]
Description
Operation
Affected flag(s)
Read table (current page) to TBLH and Data Memory
The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
XOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
XORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
XOR A,x
Description
Operation
Affected flag(s)
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
Rev. 1.00
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HT83B60
Voice Mask MCU
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website
(http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package
information.
28-pin SOP (300mil) Outline Dimensions
MS-013
Symbol
Nom.
Max.
A
0.393
―
0.419
B
0.256
―
0.300
C
0.012
―
0.020
C'
0.697
―
0.713
D
―
―
0.104
E
―
0.050
―
F
0.004
―
0.012
G
0.016
―
0.050
H
0.008
―
0.013
α
0°
―
8°
Symbol
A
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
9.98
―
10.64
7.62
B
6.50
―
C
0.30
―
0.51
C'
17.70
―
18.11
2.64
D
―
―
E
―
1.27
―
F
0.10
―
0.30
G
0.41
―
1.27
H
0.20
―
0.33
α
0°
―
8°
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HT83B60
Voice Mask MCU
Reel Dimensions
SOP 28W (300mil)
Symbol
A
Rev. 1.00
Description
Reel Outer Diameter
Dimensions in mm
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0
D
Key Slit Width
T1
Space Between Flang
T2
Reel Thickness
+0.5/-0.2
2.0±0.5
24.8
+0.3/-0.2
30.2±0.2
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HT83B60
Voice Mask MCU
Carrier Tape Dimensions
 SOP 28W (300mil)
Symbol
Rev. 1.00
Description
Dimensions in mm
W
Carrier Tape Width
24.00±0.30
P
Cavity Pitch
12.00±0.10
E
Perforation Position
1.75±0.10
F
Cavity to Perforation(Width Direction)
D
Perforation Diameter
1.50
11.50±0.10
+0.10/-0.00
D1
Cavity Hole Diameter
1.50
+0.25/-0.00
P0
Perforation Pitch
P1
Cavity to Perforation(Length Direction)
A0
Cavity Length
10.85±0.10
B0
Cavity Width
18.34±0.10
K0
4.0±0.1
2.0±0.1
Cavity Depth
2.97±0.10
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
21.3±0.1
83
December 19, 2011
HT83B60
Voice Mask MCU
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright© 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication.
However, Holtek assumes no responsibility arising from the use of the specifications described.
The applications mentioned herein are used solely for the purpose of illustration and Holtek makes
no warranty or representation that such applications will be suitable without further modification,
nor recommends the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical components in life
support devices or systems. Holtek reserves the right to alter its products without prior notification. For
the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
84
December 19, 2011