PRELIMINARY Integrated Circuit Systems, Inc. ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS840004-01 is a 4 output LVCMOS/LVTTL Synthesizer optimized to generate Ethernet HiPerClockS™ reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 156.25MHz, 125MHz, and 62.5MHz. The ICS840004-01 uses ICS’ 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Ethernet jitter requirements. The ICS840004-01 is packaged in a small 20-pin TSSOP package. • Four LVCMOS/LVTTL outputs, 15Ω typical output impedance • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input ICS • Output frequency Range: 56MHz - 175MHz • VCO Range: 560MHz - 700MHz • RMS phase jitter at 156.25MHz (1.875MHz - 20MHz): 0.52ps (typical) design target Phase noise: Offset Noise Power 100Hz ............... -94.9 dBc/Hz 1kHz ............. -119.6 dBc/Hz 10kHz ............. -128.9 dBc/Hz 100kHz ............. -129.2 dBc/Hz • Full 3.3V or 3.3V core/2.5V output supply mode • 0°C to 70°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages FREQUENCY SELECT FUNCTION TABLE F_SEL1 F_SEL0 0 0 FOR ETHERNET FREQUENCIES Inputs M Divider N Divider Value Value 25 4 Output Frequency (25MHz Ref.) M/N Ratio Value 6.25 156.25 0 1 25 5 5 125 1 0 25 10 2.5 62.5 1 1 25 5 5 12 5 BLOCK DIAGRAM OE PIN ASSIGNMENT Pullup 2 F_SEL1:0 Pullup:Pullup nPLL_SEL Pulldown nXTAL_SEL XTAL_IN Pulldown 25MHz OSC F_SEL1:0 0 1 00 01 10 11 XTAL_OUT TEST_CLK Pulldown 1 Phase Detector VCO 0 N ÷4 ÷5 ÷10 ÷5 Q0 Q1 MR 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 F_SEL1 GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT ICS840004-01 20-Lead TSSOP Q2 M = ÷25 (fixed) F_SEL0 nc nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA nc VDD Q3 6.5mm x 4.4mm x 0.92mm package body G Package Top View Pulldown The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 840004AG-01 www.icst.com/products/hiperclocks.html 1 REV. B JANUARY 3, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1 F_SEL0 Input Type Description 2, 9 nc Unused 3 nXTAL_SEL Input Pulldown 4 TEST_CLK Input Pulldown 5 OE Input Pullup 6 MR Input Pulldown 7 nPLL_SEL Input Pulldown 8 VDDA Power No connect. Selects between the cr ystal or TEST_CLK inputs as the PLL reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Single-ended LVCMOS/LVTTL clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the otuputs to go low. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. Analog supply pin. 10 11, 12 13, 19 14, 15 17, 18 16 VDD XTAL_OUT, XTAL_IN GN D Q3, Q2, Q1, Q0 VDDO Power Core supply pin. Input Cr ystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. Power Power supply ground. Single-ended clock outputs. LVCMOS/LVTTL interface levels. 15Ω typical output impedence. Output supply pin. 20 F_SEL1 Pullup Output Power Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP Input Pullup Resistor RPULLDOWN ROUT 8400042AG-01 Test Conditions Minimum Typical Maximum Units 4 pF VDD, VDDA, VDDO = 3.465V TBD pF VDD, VDDA = 3.465V, VDDO = 2.625V TBD pF 51 kΩ Input Pulldown Resistor 51 kΩ Output Impedance 15 Ω www.icst.com/products/hiperclocks.html 2 REV. B JANUARY 3, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol VDD Parameter Core Supply Voltage VDDA Analog Supply Voltage Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 Units V 3.135 3.3 3.465 V 3.135 3.3 3.465 V 2.375 2.5 2.625 VDDO Output Supply Voltage IDD Power Supply Current 90 mA IDDA IDDO Analog Supply Current Output Supply Current 8 5 mA mA V TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V Input High Current VDD = VIN = 3.465V 5 µA IIH VDD = VIN = 3.465V 150 µA IIL Input Low Current VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 OE, F_SEL0, F_SEL1 nPLL_SEL, MR, nXTAL_SEL, TEST_CLK OE, F_SEL0, F_SEL1 VDD = 3.465V, VIN = 0V -150 µA nPLL_SEL, MR, nXTAL_SEL, TEST_CLK VDD = 3.465V, VIN = 0V -5 µA VDDO = 3.3V±5% 2.6 V VDDO = 2.5V±5% 1.8 V VDDO = 3.3V or 2.5V±5% 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuits. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Mode of Oscillation Minimum Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW NOTE: Characterized using an 18pF parallel resonant cr ystal. 840004AG-01 www.icst.com/products/hiperclocks.html 3 REV. B JANUARY 3, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency Range t sk(o) Output Skew; NOTE 1, 3 t jit(Ø) RMS Phase Jitter (Random); NOTE 2 tL PLL Lock Time tR / tF Output Rise/Fall Time Test Conditions Minimum Typical 56 156.25MHz @ Integration Range: 1.875MHz - 20MHz 125MHz @ Integration Range: 1.875MHz - 20MHz 62.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Maximum Units 175 MHz TBD ps 0.52 ps 0.65 ps 0.55 ps TBD ms 400 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. % TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency Range t sk(o) Output Skew; NOTE 1, 3 t jit(Ø) RMS Phase Jitter (Random); NOTE 2 tL PLL Lock Time tR / tF Output Rise/Fall Time Test Conditions Minimum Typical 56 156.25MHz @ Integration Range: 1.875MHz - 20MHz 125MHz @ Integration Range: 1.875MHz - 20MHz 62.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% www.icst.com/products/hiperclocks.html 4 Units 175 MHz TBD ps 0.48 ps 0.59 ps 0.53 ps TBD ms 450 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 8400042AG-01 Maximum % REV. B JANUARY 3, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 62.5MHZ @3.3V ➤ 0 -10 -20 1Gb Ethernet Filter -40 62.5MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.55ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ NOISE POWER dBc Hz -30 -120 -130 -140 -150 ➤ -160 -170 Phase Noise Result by adding 1Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 62.5MHZ @2.5V 0 ➤ -10 -20 1Gb Ethernet Filter NOISE POWER dBc Hz -30 -40 62.5MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.53ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ -120 -130 -140 -150 ➤ -160 -170 Phase Noise Result by adding 1Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 840004AG-01 www.icst.com/products/hiperclocks.html 5 REV. B JANUARY 3, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 125MHZ @3.3V 0 ➤ -10 -20 10Gb Ethernet Filter -40 125MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.65ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -30 -120 -130 -140 -150 ➤ -160 -170 Phase Noise Result by adding 10Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 125MHZ @2.5V 0 ➤ -10 -20 10Gb Ethernet Filter -40 125MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.59ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ NOISE POWER dBc Hz -30 -120 -130 -140 -150 ➤ -160 -170 Phase Noise Result by adding 10Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 8400042AG-01 www.icst.com/products/hiperclocks.html 6 REV. B JANUARY 3, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 156.25MHZ @3.3V 0 ➤ -10 -20 10Gb Ethernet Filter -40 156.25MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.52ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -30 -120 -130 -140 -150 ➤ -160 -170 Phase Noise Result by adding 10Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 156.25MHZ @2.5V 0 ➤ -10 -20 10Gb Ethernet Filter -40 156.25MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.48ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -30 -120 -130 -140 -150 ➤ -160 -170 Phase Noise Result by adding 10Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 840004AG-01 www.icst.com/products/hiperclocks.html 7 REV. B JANUARY 3, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2.05V±5% 1.25V±5% 1.65V±5% SCOPE VDD, VDDA, VDDO Qx LVCMOS SCOPE VDD, VDDA VDDO Qx LVCMOS GND GND -1.25V±5% -1.65V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT Noise Power Phase Noise Plot V DDO Qx 2 Phase Noise Mask V DDO Qy Offset Frequency f1 f2 2 tsk(o) RMS Jitter = Area Under the Masked Phase Noise Plot OUTPUT SKEW RMS PHASE JITTER V DDO 80% 80% 2 Q0:Q3 t PW Clock Outputs t 20% 20% tR PERIOD tF odc = t PW x 100% t PERIOD OUTPUT RISE/FALL TIME 8400042AG-01 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 8 REV. B JANUARY 3, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840004-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VDDA. 3.3V or 2.5V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS840004-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 ICS840004-01 Figure 2. CRYSTAL INPUt INTERFACE 840004AG-01 www.icst.com/products/hiperclocks.html 9 REV. B JANUARY 3, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the TEST_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LAYOUT GUIDELINE C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1KΩ pullup or pulldown resistors can be used for the logic control input pins. Figure 3 shows a schematic example of the ICS840004-01. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF parallel resonant 25MHz crystal is used. The C1=22pF and Logic Control Input Examples Set Logic Input to '1' 3.3V Set Logic Input to '0' 3.3V RU1 1K R3 36 RU2 Not Install To Logic Input pins To Logic Input pins RD1 Not Install U1 LVCMOS RD2 1K 3.3V VDDA R2 10 C3 10uF 3.3V C4 0.01u Zo = 50 Ohm 1 2 3 4 5 6 7 8 9 10 F_SEL0 nc nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA nc VDD F_SEL1 GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT 20 19 18 17 16 15 14 13 12 11 3.3V C6 0.1u R4 36 C5 0.1u Zo = 50 Ohm LVCMOS ICS840004-01 XTAL_OUT C2 22pF X1 XTAL_IN C1 22pF FIGURE 3. ICS840004-01 SCHEMATIC EXAMPLE 8400042AG-01 www.icst.com/products/hiperclocks.html 10 REV. B JANUARY 3, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS840004-01 is: 3085 840004AG-01 www.icst.com/products/hiperclocks.html 11 REV. B JANUARY 3, 2006 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER 20 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 8400042AG-01 www.icst.com/products/hiperclocks.html 12 REV. B JANUARY 3, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS840004-01 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS840004AG-01 ICS840004A01 20 Lead TSSOP tube 0°C to 70°C ICS840004AG-01T ICS840004A01 20 Lead TSSOP tape & reel 0°C to 70°C ICS840004AG-01LF ICS40004A01L 20 Lead "Lead-Free" TSSOP tube 0°C to 70°C ICS840004AG-01LFT ICS40004A01L 20 Lead "Lead-Free" TSSOP tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an LF suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840004AG-01 www.icst.com/products/hiperclocks.html 13 REV. B JANUARY 3, 2006