PRELIMINARY Integrated Circuit Systems, Inc. ICS840001-34 FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS840001-34 is a two output LVCMOS/ LVTTL Synthesizer and a member of the HiPerClockS™ HiPerClocks TM family of high performance devices from ICS. One output is the LVCMOS/ LVTTL main synthesized clock output (Q) and one output is a three-state LVCMOS/LVTTL reference clock (REF_CLK) output at the frequency of the crystal oscillator. The device can accept crystal from 15.3125MHz to 42.67MHz and can synthesize outputs from 81.67MHz to 213.33MHz.The ICS840001-34 has excellent <1ps phase jitter performance over the 637kHz – 10MHz integration range. The ICS840001-34 is packaged in a 3mm x 3mm 16-pin VFQFN, making it ideal for use on space constrained boards. • (2) LVCMOS/LVTTL outputs, 20Ω typical output impedence (1) Main clock output (Q) (1) Three-state reference clock output (REF_CLK) ICS • Crystal oscillator interface can accept crystals from 15.3125MHz to 42.67MHz, 18pF parallel resonant crystal • Output frequency range: 81.67MHz to 213.33MHz • VCO range: 490MHz to 640MHz • RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.38ps (typical) • 3.3V operating supply • 0°C to 70°C ambient operating temperature COMMON APPLICATION CONFIGURATION TABLE Inputs Crystal M Divider VCO (MHz) N Divider Output Frequency (MHz) 40 15 600 6 100 26.5625 24 637.5 6 106.25 Application Serial Attached (SCSI), PCI Express™, Processor Clock Fibre Channel 40 15 600 4 150 26.5625 24 637.5 3 212.5 Serial ATA (SATA), Processor Clock 25 25 62 5 5 125 25 25 62 5 4 156.25 10 Gigabit Ethernet 22.5 25 562.5 3 187.5 12 Gigabit Ethernet 19.44 32 622.08 4 155.52 SONET Fibre Channel 2 Ethernet 490MHz - 640MHz 11 = ÷15 (default) 10 = ÷24 01 = ÷25 00 = ÷32 M1 M0 Q XTAL_IN 2 11 VDDO XTAL_OUT 3 10 GND M0 4 9 VDD 5 6 7 8 N1 VCO 16 15 14 13 12 N0 OSC XTAL_OUT Phase Detector OE 1 nc XTAL_IN 00 = ÷3 01 = ÷4 10 = ÷5 11 = ÷6 (default) nc REF_CLK nc VDDA (Pullup) M1 OE PIN ASSIGNMENT REF_CLK BLOCK DIAGRAM Q ICS840001-34 16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View (Pullup) (Pullup) N1 (Pullup) (Pullup) N0 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 840001AK-34 www.icst.com/products/hiperclocks.html REV. A MAY 6, 2005 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS840001-34 FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1 OE Type Input 4, 5 XTAL_OUT, XTAL_IN M0, M1 6, 14, 15 nc Unused 7, 8 N0, N1 Input 2,3 Pullup Input Input Pullup Description Output enable pin. When HIGH, REF_CLK output is enabled. When LOW, forces REF_CLK to HiZ state. LVCMOS/LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. M divider inputs. LVCMOS/LVTTL interface levels. See Table 3B. 9 VDD Power No connect. Determines output divider value as defined in Table 3C. LVCMOS/LVTTL interface levels. Core supply pin. 10 GND Power Power supply ground. 11 VDDO Power 12 Q Output 13 REF_CLK Output 16 VDDA Power Output supply pin. Single-ended clock output. LVCMOS/LVTTL interface levels. 20Ω typical output impedance. Single-ended three-state reference clock output. LVCMOS/LVTTL interface levels. 20Ω typical output impedance. Analog supply pin. Pullup NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP ROUT Minimum Typical Maximum Units 4 pF 8 pF Input Pullup Resistor 51 kΩ Output Impedance 20 Ω VDD, VDDA, VDDO = 3.465V TABLE 3A. CONTROL FUNCTION TABLE Control Inputs Output OE REF_CLK 0 Hi-Z 1 Active TABLE 3B. M DIVIDER FUNCTION TABLE Control Inputs M1 M0 0 0 TABLE 3C. N DIVIDER FUNCTION TABLE Control Inputs Feedback Divider Ratio Output Divider Ratio N1 N0 ÷32 0 0 ÷3 0 1 ÷25 0 1 ÷4 1 0 ÷24 1 0 ÷5 1 1 ÷15 (default) 1 1 ÷6 (default) 840001-34AK www.icst.com/products/hiperclocks.html 2 REV. A MAY 6, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840001-34 FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 51.5°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 70 mA IDDA Analog Supply Current 6 mA IDDO Output Supply Current 27 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage Test Conditions VIL Input Low Voltage IIH Input High Current OE, M1:0, N1:0 VDD = VIN = 3.465V IIL Input Low Current OE, M1:0, N1:0 VDD = 3.465V, VIN = 0V VOH Output High Voltage; NOTE 1 Minimum Maximum Units 2 Typical VDD + 0.3 V -0.3 0.8 V 5 µA -150 µA 2.6 V Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit". 0.5 V Maximum Units 42.67 MHz TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 15.3125 Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW 840001AK-34 www.icst.com/products/hiperclocks.html 3 REV. A MAY 6, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840001-34 FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol fOUT tjit(Ø) t R / tF Parameter Test Conditions Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time 100MHz, Integration Range: 637kHz to 10MHz 106.25MHz, Integration Range: 637kHz to 10MHz 20% to 80% odc Output Duty Cycle All parameters are characterized @ 100MHz and 106.25MHz. NOTE 1: Please refer to the Phase Noise Plot. 840001-34AK www.icst.com/products/hiperclocks.html 4 Minimum Typical Maximum Units 100 MHz 106.25 MHz 0.54 ps 0.38 ps 470 ps 50 % REV. A MAY 6, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840001-34 FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 1.65V ± 5% Noise Power Phase Noise Plot SCOPE VDD, VDDA, VDDO Qx LVCMOS Phase Noise Mask GND Offset Frequency f1 -1.65V ± 5% f2 RMS Jitter = Area Under the Masked Phase Noise Plot 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER V DD 80% 2 Q0 80% t PW t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 840001AK-34 OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 5 REV. A MAY 6, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840001-34 FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840001-34 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01μF 10 Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS840001-34 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 26.5625MHz, 18pF par- allel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 2. CRYSTAL INPUt INTERFACE 840001-34AK www.icst.com/products/hiperclocks.html 6 REV. A MAY 6, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840001-34 FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN θJA at 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 51.5°C/W TRANSISTOR COUNT The transistor count for ICS840001-34 is: 2805 840001AK-34 www.icst.com/products/hiperclocks.html 7 REV. A MAY 6, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - K SUFFIX FOR ICS840001-34 FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER 16 LEAD VFQFN TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 16 N A 0.80 1.0 A1 0 0.05 0.25 Reference A3 b 0.18 0.30 e 0.50 BASIC ND 4 NE 4 3.0 D D2 0.25 1.25 3.0 E E2 0.25 1.25 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 840001-34AK www.icst.com/products/hiperclocks.html 8 REV. A MAY 6, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840001-34 FEMTOCLOCKS™CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS840001AK-34 1A34 16 Lead VFQFN tray 0°C to 70°C ICS840001AK-34 1A34 16 Lead VFQFN 2500 tape & reel 0°C to 70°C PCI Express™ is a trademark of PCI-SIG Corporation. All trademarks mentioned are the property of their respective owners. The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840001AK-34 www.icst.com/products/hiperclocks.html 9 REV. A MAY 6, 2005