ICS525-01/02/11/12 User Configurable Clock Description Features The ICS525-01/02/11/12 are the most flexible way to generate a high-quality, high-accuracy, high-frequency clock output from an inexpensive crystal or clock input. The user can configure the device to produce nearly any output frequency from any input frequency by grounding or floating the select pins. Neither microcontroller, software, nor device programmer are needed to set the frequency. Using Phase-Locked Loop (PLL) techniques, the device accepts a standard fundamental mode, inexpensive crystal to produce output clocks up to 250 MHz. It can also produce a highly accurate output clock from a given input clock, keeping them frequency locked together. • Packaged as 28-pin SSOP (150 mil body) • Industrial and commercial versions available in Pb For similar capability with a serial interface, use the ICS307. For simple multipliers to produce common frequencies, refer to the ICS50x family of parts, which are smaller and more cost effective. These products are intended for clock generation. They have low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For applications which require defined input to output timing, use the ICS527-01. (lead) free package • User determines the output frequency by setting all • • • • • • • • • • • • internal dividers Eliminates need for custom oscillators No software needed Online calculator determines register settings Pull-ups on all select inputs Input crystal frequency of 5 - 27 MHz Input clock frequency of 2 - 50 MHz Very low jitter Duty cycle of 45/55 up to 200 MHz Operating voltage of 3.0 V or 5.5 V Ideal for oscillator replacement Industrial temperature version available For Zero Delay, refer to the ICS527 Block Diagram VDD 2 PD X1/ICLK Crystal or clock input X2 VCO Output Divider VCO Divider Optional crystal capacitors 7 R6:R0 9 V8:V0 REF 2 3 S2:S0 GND 1 MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc. CLK Phase Comparator, Charge Pump, and Loop Filter Reference Divider Crystal Oscillator ● 525 Race Street, San Jose, CA 95126 Revision 101105 ● tel (408) 297-1201 ● www.icst.com ICS525-01/02/11/12 User Configurable Clock Pin Assignment R5 1 28 R4 R6 2 27 R3 S0 3 26 R2 S1 4 25 R1 S2 5 24 R0 VDD 6 23 VDD X1/ICLK 7 22 REF X2 8 21 CLK GND 9 20 GND V0 10 19 PD V1 11 18 V8 V2 12 17 V7 V3 13 16 V6 V4 14 15 V5 ICS525-01/-02/-11/-12 Pin Descriptions Pin Number Pin Name Pin Type 1, 2, 24-28 R5, R6, R0-R4 I(PU) Reference divider word input pins determined by user. Forms a binary number from 0 to 127. 3, 4, 5 S0, S1, S2 I(PU) Select pins for output divider determined by user. See table on page 3 6, 23 VDD Power Connect to VDD. 7 X1/ICLK X1 Crystal connection. Connect to a parallel resonant fundamental crystal or input clock. 8 X2 X2 Crystal connection. Connect to a crystal or leave unconnected for clock. 9, 20 GND Power Connect to ground. 10 - 18 V0 - V8 I(PU) VCO divider word input pins determined by user. Forms a binary number from 0 to 511. 19 PD Input Power-down. Active low. Turns off entire chip when low. Clock outputs stop low. 21 CLK Output Output clock determined by status of R0-R6, V-V8, S0-S2, and input frequency. 22 REF Output Reference output. Buffered crystal oscillator (or clock ) output. Pin Description KEY: I(PU) = Input with internal pull-up resistor; X1, X2 = crystal connections 2 MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 101105 ● tel (408) 297-1201 ● www.icst.com ICS525-01/02/11/12 User Configurable Clock ICS525-01 Output Frequency and Output Divider Table S2 S1 S0 CLK Output Pin 5 Pin 4 Pin 3 Divider Output Frequency Range (MHz) VDD = 5 V VDD = 3.3 V 0 - 70°C -40 to +85°C 0 - 70°C -40 to +85°C 3–26 3–23 3–18 3–16 0 0 0 10 0 0 1 2 15–160 15–140 15–100 15–90 0 1 0 8 3.75–40 3.75–36 3.75–25 3.75–22 0 1 1 4 7.5–80 7.5–72 7.5–50 7.5–45 1 0 0 5 6–50 6–45 6–34 6–30 1 0 1 7 4–40 4–36 4–26 4–23 1 1 0 9 3.3–33.3 3.3–30 3.3–20 3.3–18 1 1 1 6 5–53 5–47 5–27 5–24 ICS525-02 Output Frequency and Output Divider Table Output Frequency Range (MHz) S2 S1 S0 CLK Output Pin 5 Pin 4 Pin 3 Divider VDD = 5 V VDD = 3.3 V -40 to +85°C -40 to +85°C 5–67 5–40 0 0 0 6 0 0 1 2 15–200 15–120 0 1 0 8 3.75–50 3.75–30 0 1 1 4 7.5–100 7.5–60 1 0 0 5 6–80 6–48 1 0 1 7 4–57 4–34 1 1 0 1 30–250 30–200 1 1 1 3 10–133 10–80 ICS525-11 Output Frequency and Output Divider Table Output Frequency Range (MHz) S2 S1 S0 CLK Output Pin 5 Pin 4 Pin 3 Divider VDD = 5 V VDD = 3.3 V 0 - 70°C -40 to +85°C 0 - 70°C -40 to +85°C 0.75–4.5 0.75–4 0 0 0 10 0.75–6.5 0.75–5.75 0 0 1 2 3.75–40 3.75–35 3.75–25 3.75–22.5 0 1 0 8 0.94–10 0.94–9 0.94–6.25 0.94–5.5 0 1 1 4 1.875–20 1.875–18 1.875–12.5 1.875–11.25 1 0 0 5 1.5–12.5 1.5–11.25 1.5–8.5 1.5–7.5 1 0 1 7 1–10 1–9 1–6.5 1–5.75 1 1 0 9 0.83–8.33 0.83–7.5 0.83–5 0.83–4.5 1 1 1 6 1.25–13.25 1.25–11.75 1.25–6.75 1.25–6 3 MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 101105 ● tel (408) 297-1201 ● www.icst.com ICS525-01/02/11/12 User Configurable Clock ICS525-12 Output Frequency and Output Divider Table S2 S1 S0 CLK Output Pin 5 Pin 4 Pin 3 Divider Output Frequency Range (MHz) VDD = 5 V VDD = 3.3 V -40 to +85°C -40 to +85°C 1.25–16.75 1.25–10 0 0 0 6 0 0 1 2 3.75–50 3.75–30 0 1 0 8 0.94–12.5 0.94–7.5 0 1 1 4 1.875–25 1.875–15 1 0 0 5 1.5–20 1.5–12 1 0 1 7 1–14.25 1–8.5 1 1 0 1 7.5–62.5 7.5–50 1 1 1 3 2.5–33.25 2.5–20 4 MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 101105 ● tel (408) 297-1201 ● www.icst.com ICS525-01/02/11/12 User Configurable Clock ( VDW + 8 ) ( RDW + 2 ) • OD External Components/Crystal Selection CLK Frequency = Input Frequency × 2x --------------------------------------------- Where: Decoupling Capacitors The ICS525-01/02/11/12 requries two 0.01µF decoupling capacitors to be connected between VDD and GND, one on each side of the chip. The capacitor must be connected close to the device to minimize lead inductance. External Resistors A 33Ω series termination resistor should be used on the CLK and REF pins. Crystal Load Capacitors The approximate total on-chip capacitance for a crystal is 16 pF, so a parallel resonant, fundamental mode crystal with this value of load (correlation) capacitance should be used. For crystals with a specified load capacitance greater than 16 pF, crystal capacitors may be connected from each of the pins X1 and X2 to Ground as shown in the block diagram. The value (in pF) of these crystal caps should be (CL -16)*2, where CL is the crystal load capacitance in pF. These external capacitors are only required for applications where the exact frequency is critical. For a clock input, connect to X1 and leave X2 unconnected (no capacitors on either). Reference Divider Word (RDW) = 0 to 127 (0 not permitted for ICS525-01/-11) VCO Divider Word (VDW) = 0 to 511 (0, 1, 2, 3 not permitted for ICS525-01/-11) Output Divider (OD) = values on pages 3-4 Also, the following operating ranges should be observed: 1. The output frequency must be in the ranges listed on pages 3-4. 2. The phase detector frequency must be above 200 kHz. InputFrequency 200kHz < ----------------------------------------------( RDW + 2 ) Since all of the inputs have pull-up resistors, it is only necessary to ground the pins that need to be set to zero. Which Part to Use? The ICS525-01 is the original configurable clock. The ICS525-02 has a higher maximum output grequency and a slightly different set of output dividers. The ICS525-11 has the same divider set as the -01 but is optimized for low frequency operation. Determining the Output Frequency Users have full control in setting the desired output frequency over the range shown in the tables on pages 3-4. To replace a standard oscillator, users should connect the divider select input pins directly to ground (or VDD, although this is not required because of internal pull-ups) during Printed Circuit Board layout. The ICS525 will automatically produce the correct frequency when all components are soldered. It is also possible to connect the inputs to parallel I/O ports to switch frequencies. By choosing divides carefully, the number of inputs which need to be changed can be minimized. Observe the restrictions on allowed values of VDW and RDW. The ICS525-12 has the same divider set as the -02 but is optimized for low frequency operation. To determine the best combination of VCO, reference, and output divide, use the ICS525 Calculator on our web site. Configuration Pin Settings The output of the ICS525 can be determined by the following simple equation: 5 MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 101105 ● tel (408) 297-1201 ● www.icst.com ICS525-01/02/11/12 User Configurable Clock Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS525-01/02/11/12. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature, Commercial 0 to +70°C Ambient Operating Temperature, Industrial -40 to +85°C Storage Temperature -65°C to 150°C Junction Temperature 125°C Soldering Temperature 260°C (max. of 10 seconds) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V Parameter Symbol Conditions Min. Typ. Max. Units 5.5 V Operating Voltage VDD Operating Supply Current IDD 60 MHz out, no load, 15 MHz crystal, ICS525-01/02 only 8 mA Operating Supply Current IDD 40 MHz out, 15 MHz crystal, ICS525-11/12 only 6 mA Operating Supply Current, Power-down IDD Pin 19 = 0, Note 1 4 µA Input High Voltage VIH Input Low Voltage VIL Input High Voltage, X1/ICLK only VIH ICLK (pin7) Input Low Voltage, X1/ICLK only VIL ICLK (pin7) Output High Voltage VOH IOH = -12 mA Output Low Voltage VOL IOL = 12 mA 2 V 0.8 VDD/2+1 VDD/2 VDD/2 ● 525 Race Street, San Jose, CA 95126 V V VDD/2-1 V V VDD-0.4 0.4 6 MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc. 3.0 V Revision 101105 ● tel (408) 297-1201 ● www.icst.com ICS525-01/02/11/12 User Configurable Clock Parameter Symbol Short Circuit Current Conditions Min. Typ. Max. Units CLK and REF outputs ±55 mA Input Capacitance CIN V, R, S pins and pin 19 4 pF On-chip Pull-up Resistor RPU V, R, S pins and pin 19 270 kΩ AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V Parameter Symbol Input Frequency Conditions FIN Min. Typ. Max. Units Crystal input 5 27 MHz Clock input 2 50 MHz Output Clock Rise Time 0.8 to 2.0 V 1 ns Output Clock Fall Time 2.0 to 0.8 V 1 ns Output Clock Duty Cycle, OD = 2, 4, 6, 8, or 10 At VDD/2 45 Output Clock Duty Cycle, OD = 3, 5, 7, or 9 At VDD/2 Output Clock Duty Cycle, OD = 1 (-02 and -12 only) At VDD/2 49 to 51 55 % 40 60 % 35 65 Power-down Time, PD low to clocks stopped 50 ns Power-up Time, PD high to clocks stable 10 ms Absolute Clock Period Jitter, ICS525-01, Note 2 tja Deviation from mean One Sigma Clock Period Jitter, ICS525-01, Note 2 tjs Absolute Clock Period Jitter, ICS525-02, Note 2 ±140 ps One Sigma 45 ps tja Deviation from mean ±85 ps One Sigma Clock Period Jitter, ICS525-02, Note 2 tjs One Sigma 30 ps Absolute Clock Period Jitter, ICS525-11, Note 2 tja Deviation from mean ±160 ps One Sigma Clock Period Jitter, ICS525-11, Note 2 tjs One Sigma 40 ps Absolute Clock Period Jitter, ICS525-12, Note 2 tja Deviation from mean ±160 ps One Sigma Clock Period Jitter, ICS525-12, Note 2 tjs One Sigma 40 ps 7 MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 101105 ● tel (408) 297-1201 ● www.icst.com ICS525-01/02/11/12 User Configurable Clock NOTE 1: Phase relationship between input and output can change at power-up. For a fixed phase relationship, see the ICS527. NOTE 2: For 16 MHz, 100 MHz output. Use the -02 for lowest jitter. Package Outline and Package Dimensions (28-pin SSOP, 150 mil Body) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 Millimeters Inches* 28 Symbol E1 Min A A1 A2 b C D E E1 e L α aaa E INDEX AREA 1 2 D Max Min 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 9.80 10.00 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0° 8° -0.10 Max .053 .069 .0040 .010 -.059 .008 .012 .007 .010 .386 .394 .228 .244 .150 .157 0.025 Basic .016 .050 0° 8° -0.004 *For reference only. Controlling dimensions in mm. A 2 A A 1 c -Ce SEATING PLANE b L aaa C 8 MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 101105 ● tel (408) 297-1201 ● www.icst.com ICS525-01/02/11/12 User Configurable Clock Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS525-01R ICS525-01R Tubes 28-pin SSOP 0 to +70°C ICS525-01RT ICS525-01R Tape and Reel 28-pin SSOP 0 to +70°C ICS525-01RLF ICS525-01RLF Tubes 28-pin SSOP 0 to +70°C ICS525-01RLFT ICS525-01RLF Tape and Reel 28-pin SSOP 0 to +70°C ICS525-01RI ICS525-01RI Tubes 28-pin SSOP -40 to +85°C ICS525-01RIT ICS525-01RI Tape and Reel 28-pin SSOP -40 to +85°C ICS525-01RILF ICS525-01RILF Tubes 28-pin SSOP -40 to +85°C ICS525-01RILFT ICS525-01RILF Tape and Reel 28-pin SSOP -40 to +85°C ICS525R-02I ICS525R-02I Tubes 28-pin SSOP -40 to +85°C ICS525R-02IT ICS525R-02I Tape and Reel 28-pin SSOP -40 to +85°C ICS525R-02ILF ICS525R-02ILF Tubes 28-pin SSOP -40 to +85°C ICS525R-02ILFT ICS525R-02ILF Tape and Reel 28-pin SSOP -40 to +85°C ICS525R-11 ICS525R-11 Tubes 28-pin SSOP 0 to +70°C ICS525R-11T ICS525R-11 Tape and Reel 28-pin SSOP 0 to +70°C ICS525R-11LF ICS525R-11LF Tubes 28-pin SSOP 0 to +70°C ICS525R-11LFT ICS525R-11LF Tape and Reel 28-pin SSOP 0 to +70°C ICS525RI-11 ICS525RI-11 Tubes 28-pin SSOP -40 to +85°C ICS525RI-11T ICS525RI-11 Tape and Reel 28-pin SSOP -40 to +85°C ICS525RI-11LF ICS525RI-11LF Tubes 28-pin SSOP -40 to +85°C ICS525RI-11LFT ICS525RI-11LF Tape and Reel 28-pin SSOP -40 to +85°C ICS525RI-12 ICS525RI-12 Tubes 28-pin SSOP -40 to +85°C ICS525RI-12T ICS525RI-12 Tape and Reel 28-pin SSOP -40 to +85°C ICS525RI-12LF ICS525RI-12LF Tubes 28-pin SSOP -40 to +85°C ICS525RI12LFT ICS525RI-12LF Tape and Reel 28-pin SSOP -40 to +85°C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments 9 MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 101105 ● tel (408) 297-1201 ● www.icst.com