ICS V386GLF

V386
8-BIT LVDS RECEIVER FOR VIDEO
General Description
Features
The V386 is an ideal LVDS receiver that converts 4-pair
LVDS data streams into parallel 28 bits of CMOS/TTL
data with bandwidth up to 2.38 Gbps throughput or
297.5 Mbytes per second.
• Pin and function compatible with the National
This chip is an ideal means to solve EMI and cable size
problems associated with wide, high-speed TTL
interfaces through very low-swing LVDS signals.
ICS manufactures a large variety of video application
devices. Consult ICS for all of your video application
requirements.
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VCC
RxOUT21
RxOUT20
RxOUT19
GND
RxOUT18
RxOUT17
RxOUT16
VCC
RxOUT15
RxOUT14
RxOUT13
GND
RxOUT12
RxOUT11
RxOUT10
VCC
RxOUT9
RxOUT8
RxOUT7
GND
RxOUT6
RxOUT5
RxOUT4
RxOUT3
VCC
RxOUT2
RxOUT1
• Converts 4-pair LVDS data streams into parallel 28
bits of CMOS/TTL data
•
•
•
•
•
•
•
•
•
•
Fully spread spectrum compatible
Wide clock frequency range from 20 MHz to 85 MHz
Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
On-chip PLL requires no external components
Low-power CMOS design
Falling edge clock triggered outputs
Power-down control function
Compatible with TIA/EIA-644 LVDS standards
Packaged in a 56-pin TSSOP (Pb free available)
Block Diagram
RxIN0+
8
RxIN0-
8
GREEN
RxIN1+
8
BLUE
RxIN1RxIN2+
LVDS to TTL
De-serializer
RED
HSYNC
RxIN2-
VSYNC
RxIN3+
DATA ENABLE
RxIN3-
CONTROL
RxCLKIN+
PLL
RxCLKIN-
RxOUT0..27
RxOUT22
RxOUT23
RxOUT24
GND
RxOUT25
RxOUT26
RxOUT27
LVDS_GND
RxIN0RxIN0+
RxIN1RxIN1+
LVDS_VCC
LVDS_GND
RxIN2RxIN2+
RxCLKINRxCLKIN+
RxIN3RxIN3+
LVDS_GND
PLL_GND
PLL_VCC
PLL_GND
PWRDWN
RxCLKOUT
RxOUT0
GND
DS90CF386, THine THC63LVDF84, TI
SN65LVDS94
RxCLKOUT
PWRDWN
V386
56-pin TSSOP
V386
V386 Datasheet
1
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Pin Descriptions
Pin
Pin name
Type
Description
1
RxOUT22
OUT
Data outputs on pins (RxOUT0..27)
2
RxOUT23
OUT
Data outputs on pins (RxOUT0..27)
3
RxOUT24
OUT
Data outputs on pins (RxOUT0..27)
4
GND
5
RxOUT25
OUT
Data outputs on pins (RxOUT0..27)
6
RxOUT26
OUT
Data outputs on pins (RxOUT0..27)
7
RxOUT27
OUT
Data outputs on pins (RxOUT0..27)
8
LVDS_GND
Ground
Analog ground
9
RxIN0-
LVDS IN
LVDS input (-)
10
RxIN0+
LVDS IN
LVDS input (+)
11
RxIN1-
LVDS IN
LVDS input (-)
12
RxIN1+
LVDS IN
LVDS input (+)
13
LVDS_VCC
Power
Analog power
14
LVDS_GND
Ground
Analog ground
15
RxIN2-
LVDS IN
LVDS input (-)
16
RxIN2+
LVDS IN
LVDS input (+)
17
RxCLKIN-
LVDS IN
LVDS input (-)
18
RxCLKIN+
LVDS IN
LVDS input (+)
19
RxIN3-
LVDS IN
LVDS input (-)
20
RxIN3+
LVDS IN
LVDS input (+)
21
LVDS_GND
Ground
Analog ground
22
PLL_GND
Ground
PLL ground
23
PLL_VCC
Power
PLL power
24
PLL_GND
Ground
PLL ground
25
PWRDWN
IN
26
RxCLKOUT
OUT
Clock output
27
RxOUT0
OUT
Data outputs on pins (RxOUT0..27)
28
GND
29
RxOUT1
OUT
Data outputs on pins (RxOUT0..27)
30
RxOUT2
OUT
Data outputs on pins (RxOUT0..27)
31
VCC
32
RxOUT3
OUT
Data outputs on pins (RxOUT0..27)
33
RxOUT4
OUT
Data outputs on pins (RxOUT0..27)
V386 Datasheet
Ground
Ground
Power
Digital ground
Power-down control input.
H: Nomal
L: Power down, all ouputs are pulled low.
Digital ground
Digital power
2
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Pin
Pin name
Type
Description
34
RxOUT5
OUT
Data outputs on pins (RxOUT0..27)
35
RxOUT6
OUT
Data outputs on pins (RxOUT0..27)
36
GND
37
RxOUT7
OUT
Data outputs on pins (RxOUT0..27)
38
RxOUT8
OUT
Data outputs on pins (RxOUT0..27)
39
RxOUT9
OUT
Data outputs on pins (RxOUT0..27)
40
VCC
41
RxOUT10
OUT
Data outputs on pins (RxOUT0..27)
42
RxOUT11
OUT
Data outputs on pins (RxOUT0..27)
43
RxOUT12
OUT
Data outputs on pins (RxOUT0..27)
44
GND
45
RxOUT13
OUT
Data outputs on pins (RxOUT0..27)
46
RxOUT14
OUT
Data outputs on pins (RxOUT0..27)
47
RxOUT15
OUT
Data outputs on pins (RxOUT0..27)
48
VCC
49
RxOUT16
OUT
Data outputs on pins (RxOUT0..27)
50
RxOUT17
OUT
Data outputs on pins (RxOUT0..27)
51
RxOUT18
OUT
Data outputs on pins (RxOUT0..27)
52
GND
53
RxOUT19
OUT
Data outputs on pins (RxOUT0..27)
54
RxOUT20
OUT
Data outputs on pins (RxOUT0..27)
55
RxOUT21
OUT
Data outputs on pins (RxOUT0..27)
56
VCC
Ground
Power
Ground
Power
Ground
Power
Digital ground
Digital power
Digital ground
Digital power
Digital ground
Digital power
.
V386 Datasheet
3
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the V386. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VCC
-0.3 V to +4 V
CMOS/TTL Output Voltage
-0.3 V to (VCC+0.3 V)
LVDS Receiver Input Voltage
-0.3 V to (VCC+0.3 V)
Ambient Operating Temperature
0 to +70°C
Storage Temperature
-65 to +150°C
Junction Temperature
150°C
Soldering Temperature (10 seconds max.)
260°C
Maximum Package Power
1.61 W (V386)
Package Derating
12.4 mW/°C above +25°C
15 mW/°C above +25°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Units
0
25
70
°C
3.3 V Supply Voltage (VCC)
3
3.3
Receiver Input Range (VIN)
0
Ambient Operating Temperature (Ta)
Supply Noise Voltage (VN)
3.6
V
2.4
V
100
mVpp
Electrical Characteristics
VDD=3.3 V ±10%, Ambient temperature 0 to 70°C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
CMOS/TTL DC Specifications
Input High Voltage
VIH
2.0
VCC
V
Input Low Voltage
VIL
GND
0.8
V
Output High Voltage
VOH
IOH = -0.4 mA
3.3
VCC
V
Output Low Voltage
VOL
IOL = 2 mA
0.06
0.3
V
Input Clamp Voltage
VCL
ICL = -18mA
-0.79
-1.5
V
±15
µA
Input Current
V386 Datasheet
IIN
2.7
VCC
4
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Parameter
Output Short Circuit Current
Symbol
Conditions
Min.
Typ.
Max.
Units
0V
±10
IOS
VOUT = 0V
-60
mA
VCM = +1.2 V
+100
mV
LVDS Receiver DC Specifications
Differential Input High Threshold
VTH
Differential Input Low Threshold
VTL
Input Current
IIN
-100
mV
VIN = +2.4 V, VCC = 3.6 V
±10
µA
VIN = 0V, VCC = 3.6 V
±15
µA
CL = 8 pF, f = 65 MHz, worst
case pattern
220
mA
CL = 8 pF, f = 85 MHz, worst
case pattern
240
mA
CL= 8 pF, f = 65 MHz, 16
Grayscale pattern
125
mA
CL= 8 pF, f = 85 MHz, 16
Grayscale pattern
140
mA
140
400
µA
Receiver Supply Current
Receiver Supply Current (worst case)
Receiver Supply Current (16
Grayscale)
ICCRW
ICCRG
ICCRZ
Power_Down = Low,
Receiver outputs stay low
during Power-down mode
CMOS/TTL Low-to-High Transition
Time
CLHT
20% to 80% VCC, CL= 8 pF
2
3.5
ns
CMOS/TTL High-to-Low Transition
Time
CHLT
80% to 20% VCC, CL= 8 pF
1.8
3.5
ns
CLKOUT period
RCOP
11.76
T
50
ns
CLKOUT High Time
RCOH
f = 85 MHz
4.5
5
7
ns
CLKOUT Low Time
RCOL
f = 85 MHz
4
5
6.5
ns
Data Setup to CLKOUT
RSRC
f = 85 MHz
2.0
ns
Data Hold to CLKOUT
RHRC
f = 85 MHz
3.5
ns
RCK+/- to CLKOUT Delay
RCCD
25°C / 3.3 V
8
Receiver PLL Setup Time
RPLLS
Receiver Supply Current (Power
Down)
Receiver Switching Characteristics
14
20
ns
10
ms
1
µs
Receiver Input Strobe Position for
Bit0
RSPos0
f = 85 MHz, T = 11.76 ns
0.49
0.84
1.19
ns
Receiver Input Strobe Position for
Bit1
RSPos1
f = 85 MHz, T = 11.76 ns
2.17
2.52
2.87
ns
Receiver Input Strobe Position for
Bit2
RSPos2
f = 85 MHz, T = 11.76 ns
3.85
4.2
4.55
ns
Receiver Input Strobe Position for
Bit3
RSPos3
f = 85 MHz, T = 11.76 ns
5.53
5.88
6.23
ns
Receiver Input Strobe Position for
Bit4
RSPos4
f = 85 MHz, T = 11.76 ns
7.21
7.56
7.91
ns
Receiver Power Down Delay
V386 Datasheet
RPDD
5
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Min.
Typ.
Max.
Units
Receiver Input Strobe Position for
Bit5
Parameter
Symbol
RSPos5
f = 85 MHz, T = 11.76 ns
Conditions
8.89
9.24
9.59
ns
Receiver Input Strobe Position for
Bit6
RSPos6
f = 85 MHz, T = 11.76 ns
10.57
10.92
11.27
ns
RxIn Skew Margin (see note and
Figure 8)
Rskm
f = 85 MHz, T = 11.76 ns
300
ps
f = 65 MHz, T = 15.38 ns
500
ps
Note: The skew margins mean the maximum timing tolerance between the clock and data channel when the
receiver still works well. This margin takes into acount the receiver input setup and hold time, and internal clock
jitter (i.e., internal data sampling window - RSPos). Thyis margin allows for LVDS transmitter pulse position,
interconnect skew, inter-symbol interference and intrinsic channel mismatch which will cause the skew between
clock (RC+ and RCK-) and data (RX[n]+ and RX[n]- ; n =0, 1, 2, 3) channels.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
V386 Datasheet
Symbol
Conditions
Min.
Typ.
Max.
Units
θJA
Still air
84
°C/W
θJA
1 m/s air flow
76
°C/W
θJA
3 m/s air flow
67
°C/W
50
°C/W
θJC
6
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Timing Diagrams
CLKIN/CLKOUT
ODD Data In/Data Out
EVEN Data In/Data Out
T
Figure 1a. “Worst Case” Test Pattern
CLKOUT
D0, 8, 16
D1, 9, 17
D2, 10, 18
D3, 11, 19
D4-7, 12-15, 20-23
D24-27
Figure 1b. 16-Grayscale Test-Pattern Waveforms
CMOS/TTL Output
80%
80%
20%
8pF
20%
CLHT
CHLT
V386 CMO/TTL Output Load and Transition Times
Figure 2. V386 CMOS/TTL Output Load and Transition Time
V386 Datasheet
7
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
RCOP
2.0 V
2.0 V
CLKOUT
0.8 V
2.0 V
0.8 V
RCOH
RCOL
RSRC
RHRC
D0 – D27 Out
2.0 V
SETUP
2.0 V
HOLD
Figure 3. V386 SETUP/HOLD and High/Low Times
RCK
Vdiff=0V
RCCD
1.5V
CLKOUT
Figure 4. V386 Clock In to Clock Out Delay
2.0 V
3.6 V
PWRDWN
3.0 V
VCC
RPLLS
RCK
CLKOUT
Figure 5. V386 Phase Lock Loop Set Time
1.5 V
PWRDWN
RCK IN
RPDD
Low
Figure 6. V386 Power Down Delay
V386 Datasheet
8
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
TCLK
Clock
Previous Cycle
Next Cycle
Data
Rspos0 Min
Rspos0 Max
Rspos1 Min
Rspos1 Max
Rspos2 Min
Rspos2 Max
Rspos3 Min
Rspos3 Max
Rspos4 Min
Rspos4 Max
Rspos5 Min
Rspos5 Max
Rspos6 Min
Rspos6 Max
Figure 7. V386 LVDS Input Strobe Position
RCK+/RCKSkew Margin
RX[n]+/RX[n]N = 0, 1, 2, 3
Figure 8. Receiver Input Skew Margin
V386 Datasheet
9
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Package Outline and Package Dimensions (56-pin TSSOP)
Package dimensions are kept current with JEDEC Publication No. 95
56
Millimeters
Symbol
E1
INDEX
AREA
A
A1
A2
b
C
D
E
E1
e
L
a
aaa
E
1 2
D
A
2
Max
—
1.20
0.05
0.15
0.80
1.05
0.17
0.27
0.09
0.20
13.90
14.10
8.10 BASIC
6.00
6.20
0.50 BASIC
0.45
0.75
8°
0°
—
0.10
A
1
Max
—
0.047
0.002
0.006
0.032
0.041
0.007
0.011
0.0035
0.008
0.547
0.555
0.319 BASIC
0.236
0.244
0.020 BASIC
0.018
0.030
0°
8°
—
0.004
c
-CSEATING
PLANE
b
Min
* For reference only. Controlling dimensions in mm.
A
e
Min
Inches*
L
aaa C
Ordering Information
Part / Order Number
V386G
V386GT
V386GLF
V386GLFT
Marking
V386G
V386G
V386GLF
V386GLF
Shipping Packaging
Package
Temperature
Tubes
56-pin TSSOP
0 to +70°C
Tape and Reel
56-pin TSSOP
0 to +70°C
Tubes
56-pin TSSOP
0 to +70°C
Tape and Reel
56-pin TSSOP
0 to +70°C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit
Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of
third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice.
ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
V386 Datasheet
10
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m