TI SN74ABT16601

SN54ABT16601, SN74ABT16601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS210C – JUNE 1992 – REVISED JANUARY 1997
D
D
D
D
D
D
D
SN54ABT16601 . . . WD PACKAGE
SN74ABT16601 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
UBT  (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
Flow-Through Architecture Optimizes PCB
Layout
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
These 18-bit universal bus transceivers combine
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, clocked, and
clock-enabled modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. The clock can be controlled by the
clock-enable (CLKENAB and CLKENBA) inputs.
For A-to-B data flow, the device operates in the
transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held
at a high or low logic level. If LEAB is low, the
A data is stored in the latch/flip-flop on the
low-to-high transition of CLKAB. Output enable
OEAB is active low. When OEAB is low, the
outputs are active. When OEAB is high, the
outputs are in the high-impedance state.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CLKENAB
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
CLKENBA
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16601 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16601 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABT16601, SN74ABT16601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS210C – JUNE 1992 – REVISED JANUARY 1997
FUNCTION TABLE†
INPUTS
LEAB
CLKAB
A
OUTPUT
B
H
X
X
X
Z
L
H
X
L
L
CLKENAB
OEAB
X
X
X
L
H
X
H
H
H
L
L
X
X
H
L
L
X
X
B0‡
B0‡
L
L
L
↑
L
L
L
L
L
↑
H
L
L
L
L
X
H
B0‡
B0§
† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA.
‡ Output level before the indicated steady-state input conditions were
established
§ Output level before the indicated steady-state input conditions were
established, provided that CLKAB was low before LEAB went low
L
2
L
L
POST OFFICE BOX 655303
H
X
• DALLAS, TEXAS 75265
SN54ABT16601, SN74ABT16601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS210C – JUNE 1992 – REVISED JANUARY 1997
logic diagram (positive logic)
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
CE
3
1D
C1
CLK
54
B1
CE
1D
C1
CLK
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT16601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT16601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABT16601, SN74ABT16601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS210C – JUNE 1992 – REVISED JANUARY 1997
recommended operating conditions (see Note 3)
SN54ABT16601
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t/∆v
Input transition rise or fall rate
High-level input voltage
SN74ABT16601
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
TA
Operating free-air temperature
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
–55
0
V
V
0.8
VCC
–24
UNIT
VCC
–32
V
V
mA
48
64
mA
10
10
ns/V
85
°C
125
–40
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
VCC = 4
4.5
5V
MIN
MIN
–1.2
MAX
SN74ABT16601
MIN
–1.2
Control inputs
A or B ports
ICEX
IO‡
IOZH§
IOZL§
A or B ports
–1.2
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
IOL = 64 mA
0.55
Ci
Control inputs
Cio
A or B ports
±1
±1
±1
±20**
±100
±20
VI = VCC or GND
VCC = 0,
VCC = 5.5 V,
VO = 5.5 V
VI or VO ≤ 4.5 V
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.5 V
VO = 2.7 V
VCC = 5.5 V,
VO = 0.5 V
Outputs high
1.9
3
2
3
Outputs low
28
36
35
36
Outputs disabled
1.6
3
2
±100
Outputs high
50
–100
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
–180
50
–50
–180
–50
µA
±100
µA
50
µA
–180
mA
10
10
10
µA
–10
–10
–10
µA
50
1.5
mA
3
50
µA
mA
3
pF
9
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
** This limit applies only to the SN74ABT16601.
† All typical values are at VCC = 5 V.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§ The parameters IOZH and IOZL include the input leakage current.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
POST OFFICE BOX 655303
V
mV
VCC = 5
5.5
5V
V,
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
V
V
0.55
0.55*
–50
UNIT
2
0.55
VCC = 5.5 V,, One input at 3.4 V,,
Other inputs at VCC or GND
∆ICC¶
4
MAX
100
Ioff
ICC
SN54ABT16601
2.5
Vhys
II
TA = 25°C
TYP†
MAX
• DALLAS, TEXAS 75265
SN54ABT16601, SN74ABT16601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS210C – JUNE 1992 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT16601
fclock
tw
Clock frequency
Pulse duration
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB↑ or B before CLKBA↑
tsu
th
Setup time
Hold time
MIN
MAX
0
150
SN74ABT16601
MIN
MAX
0
150
2.5
2.5
3
3
4.6
4
CLK high
2.5
2.5
CLK low
1.3
1
CLKEN before CLK↑
2.9
2.5
A after CLKAB↑ or B after CLKBA↑
0.4
0
A after LEAB↓ or B after LEBA↓
2.8
2
0
0
A before LEAB↓ or B before LEBA↓
CLKEN after CLK↑
UNIT
MHz
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54ABT16601
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
LEAB or LEBA
B or A
CLKAB or CLKBA
B or A
OEAB or OEBA
B or A
OEAB or OEBA
B or A
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• DALLAS, TEXAS 75265
VCC = 5 V,
TA = 25°C
MIN
MAX
MIN
TYP
150
200
1.5
2.5
4.1
1
4.6
1.5
3.4
4.7
1
5.1
2
3.4
4.7
1
5.6
2
3.7
5
1
5.5
1.5
3.2
4.5
1
5.2
1.5
3.2
4.4
1
5
UNIT
MAX
150
MHz
2
4
5
1
5.7
2
4.2
5.6
1
6
2
4.5
5.8
1
6.8
1.5
3.4
5.3
1
6.3
ns
ns
ns
ns
ns
5
SN54ABT16601, SN74ABT16601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS210C – JUNE 1992 – REVISED JANUARY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74ABT16601
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
6
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
LEAB or LEBA
B or A
CLKAB or CLKBA
B or A
OEAB or OEBA
B or A
OEAB or OEBA
B or A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 5 V,
TA = 25°C
MIN
MAX
MIN
TYP
150
200
1.5
2.5
3.6
1.5
4
1.5
3.4
4.7
1.5
4.9
2
3.4
4.7
2
5
2
3.7
5
2
5.2
1.5
3.2
4.5
1.5
4.7
1.5
3.2
4.4
1.5
4.6
UNIT
MAX
150
MHz
2
4
5
2
5.5
2
4.2
5.6
2
5.8
2
4.5
5.4
2
6.2
1.5
3.4
4.7
1.5
5.4
ns
ns
ns
ns
ns
SN54ABT16601, SN74ABT16601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS210C – JUNE 1992 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
1.5 V
Input
1.5 V
Data Input
0V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
3V
1.5 V
Input
Output
Control
1.5 V
0V
1.5 V
1.5 V
VOL
tPLH
tPHL
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
VOH
Output
1.5 V
tPZL
tPHL
tPLH
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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• DALLAS, TEXAS 75265
7
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