82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Product Features ■ ■ ■ ■ ■ ■ ■ ■ ■ IEEE 802.3ab compliant — Robust operation over the installed base of Category-5 (Cat-5) twisted pair cabling Robust end to end connections over various cable lengths Full duplex at 10, 100, or 1000 Mbps and half duplex at 10 or 100 Mbps. IEEE 802.3ab Auto-negotiation with Next Page support — Automatic link configuration including speed, duplex, and flow control 10/100 downshift — Automatic link speed adjustment with poor quality cable Automatic MDI crossover — Helps to correct for infrastructure issues Advanced Cable Diagnostics — Improved end-user troubleshooting Footprint compatible with 82562V devices for a single-board dual design (Gigabit and 10/100) LCI interface for a very low power 10/100 link ■ ■ ■ ■ ■ ■ ■ ■ Gigabit LAN Connect Interface — Low pin count, high speed interface with special low power idle modes — Allows PHY placement proximity to I/O back panel. 3 LED outputs — Link and Activity indications (10, 100, and 1000 Mbps) Clock supplied to MAC — Cost optimized design Full chip power down — Support for lowest power state 81-pin, 1.0 mm pitch, 10 mm x 10 mm FCMMAP (BGA) Package — Smaller footprint and lower power dissipation compared to multi-chip MAC and PHY solutions. Footprint compatible with the Intel® 82562V Platform LAN Connect device Integrated voltage regulator and power supply control, which can be powered from a single 3.3V DC rail Operating temperatures: 0° C to 70° C and 0° C to 55° C (with internal regulator) – heat sink or forced airflow not required — Simple Thermal Design Power Consumption less than 1.16 Watts (silicon power) 317436-003 Revision 2.4 Revision History Date December 2007 August 2007 May 2007 August 2006 June 2006 Revision 2.4 2.3 2.2 2.1 2.0 Comments • Removed 802.3 SerDes reference in section 1.0. • Updated Section 1.2. Added reference document “Implementing the Intel® Auto Connect Battery Saver (ACBS) With the Intel® 82566”. • Added ICH9 information. • Added new power consumption table for the 82566 DC/DM. • Change ballout row “I” to “J”. Changed all “I” pinout designations to “J”. • Updated crystal specifications. • Replaced Figure 4. • Removed Vcase parameter from Table 9. • Removed section 3.4 “Thermal Diode (TD)”. This information can now be found in the 82566 Gigabit Platform LAN Connect Thermal Design Considerations Application Note. • Revised section 4.2 title. • Revised Table 10 (removed operating temperature range parameter and related notes). • Changed all “J” pinout designations to “I” to match Figure 10 “Visual Pin Assignments”. Initial public release. • March 2006 1.5 Added note to Table 16. Initial Intel Confidential release. Legal Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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Copyright © 2007, Intel Corporation. * Third-party brands and names are the property of their respective owners. ii 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Contents 1.0 Introduction......................................................................................................................... 1 1.1 1.2 1.3 2.0 Signal Descriptions............................................................................................................. 3 2.1 2.2 2.3 2.4 2.5 2.6 3.0 Signal Type Definitions.......................................................................................... 3 Gigabit LAN Connect Interface (GLCI) Pins.......................................................... 3 LAN Connect Interface (LCI) Pins ......................................................................... 4 Miscellaneous Pins................................................................................................ 4 PHY Pins ............................................................................................................... 5 2.5.1 LEDs......................................................................................................... 5 2.5.2 Analog Pins .............................................................................................. 5 2.5.3 Testability Pins ......................................................................................... 6 Power Supply Pins ................................................................................................ 6 Voltage, Temperature, and Timing Specifications.............................................................. 9 3.1 3.2 3.3 3.4 3.5 3.6 4.0 Document Scope................................................................................................... 2 Reference Documents...........................................................................................2 Product Codes....................................................................................................... 2 Absolute Maximum Ratings................................................................................... 9 Recommended Operating Conditions ................................................................... 9 DC and AC Characteristics .................................................................................10 LED/TEST/JTAG I/F DC Specifications ..............................................................10 Power Supply Connections .................................................................................11 3.5.1 External Voltage Regulator (EVR) Power Delivery ................................11 3.5.2 Internal Voltage Regulator (IVR) Power Delivery ...................................13 3.5.3 Crystal ....................................................................................................17 Power Consumption ............................................................................................19 Package and Pinout Information ......................................................................................21 4.1 4.2 4.3 4.4 4.5 Package Information ...........................................................................................21 Thermal ...............................................................................................................24 Internal Pull-Up Resistors....................................................................................24 Pull-Up and Pull-Down Current ...........................................................................25 Visual Pin Assignments.......................................................................................26 1 2 3 4 5 6 7 8 9 10 82566 Block Diagram ............................................................................................ 1 External LVR Power-up Sequence......................................................................13 Internal LVR Power-up Sequence.......................................................................14 Crystal Connectivity to the 82566........................................................................18 Mechanical Drawing (1 of 4)................................................................................21 Mechanical Drawing (2 of 4)................................................................................22 Mechanical Drawing (3 of 4)................................................................................23 Mechanical Drawing (4 of 4)................................................................................24 Vpad versus Ipad ................................................................................................25 82566 Pinout (Top View - Balls Down)................................................................26 Figures iii 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 iv Product Ordering Codes ....................................................................................... 2 GLCI Pins.............................................................................................................. 3 LCI Pins................................................................................................................. 4 Miscellaneous Pins ............................................................................................... 4 LED Pins ............................................................................................................... 5 Analog Pins ........................................................................................................... 5 Testability Pins ...................................................................................................... 6 Power Supply Pins ................................................................................................ 6 Absolute Maximum Ratings ................................................................................. 9 Recommended Operating Conditions ................................................................... 9 Preliminary DC and AC Characteristics .............................................................. 10 Preliminary LED/TEST/JTAG I/F DC Specifications ........................................... 10 3.3V DC External Power Supply Parameters...................................................... 11 1.8V DC External Power Supply Parameters...................................................... 11 1.0V DC External Power Supply Parameters...................................................... 12 3.3V DC External Power Supply Parameters..................................................... 13 1.8V DC Internal LVR Specification .................................................................... 15 1.0V DC Internal LVR Specification .................................................................... 15 PNP Specification for 1.8V DC LVR.................................................................... 16 PNP Specification for 1.0V DC LVR.................................................................... 17 Crystal Specifications.......................................................................................... 17 Power Consumption (82566MC/MM) .................................................................. 19 Power Consumption (82566DC/DM)................................................................... 20 Internal Pull-Up Resistors ................................................................................... 24 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 1.0 Introduction The 82566 is a single port Gigabit Ethernet Physical Layer Transceiver (PHY) that connects to its MAC through a dedicated interconnect. The 82566 is based on Intel's Gigabit PHY technology, and supports operation at data rates of 10/100/1000 Mbps. The physical layer circuitry provides a standard IEEE 802.3 Ethernet interface for 10BASE-T, 100BASE-TX, and 1000BASE-T applications (802.3, 802.3u, and 802.3ab). This device operates with the ICH8/ICH9 chipset that incorporates and integrates the media access controller (MAC), which is referred to as the ICH8/ICH9 LAN. The 82566 is packaged in a small footprint flip chip molded matrix array package (FCMMAP) with 81 balls in a 9 x 9 array. The package size is 10 mm x 10 mm with a pitch of 1.0 mm, making it attractive for small form-factor platforms. The device interfaces with its MAC through two interfaces: Gigabit LAN Connect Interface (GLCI) and LAN Connect Interface (LCI). The GLCI is a high speed proprietary serial interface. The LCI is a low speed proprietary parallel bus. The 82566 operates using both interfaces; the GLCI for 1000 Mbps traffic and LCI for all other traffic types. Figure 1 identifies the major components of the 82566 architecture. Figure 1. 82566 Block Diagram Crystal LCI GLCI LCI GLCI PLL Multiplexer LEDs Testability MDIO Status & Control Power Power Supply PHY 82566 MDI 1 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 1.1 Document Scope This document contains datasheet specifications for the 82566 Gigabit Platform LAN Connect (PLC), including signal descriptions, DC and AC parameters, packaging data, and pinout information. 1.2 Reference Documents This document assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide application information: • IEEE Standard 802.3, 2002 Edition. Incorporates various IEEE Standards previously published separately. Institute of Electrical and Electronic Engineers (IEEE). • IEEE Standard 1149.1, 2001 Edition (JTAG). Institute of Electrical and Electronics Engineers (IEEE). • • • • • • I/O Control Hub 8 NVM Map and Programming Information. Intel Corporation. I/O Control Hub 9 NVM Map and Programming Information. Intel Corporation. Intel® I/O Controller Hub 8 (ICH8) Family Datasheet, Intel Corporation. Intel® I/O Controller Hub 9 (ICH9) Family Datasheet, Intel Corporation. Intel 965 Express Chipset Family Platform Design Guide, Intel Corporation. Intel® Centrino® Pro Processor Technology and Intel® Centrino® Duo Processor Technology Design Guide. For Intel® Core™2 Duo Processor, Mobile Intel® 965 Express Chipset Family and Intel® 82801HBM ICH8M & Intel® 82801HEM ICH8M-E I/O Controller Hub Based Systems, Intel Corporation. • ICH8/ICH9 (MAC) GbE LAN Controller and 82566/82562V (PHY) Software Developer’s Manual. Intel Corporation. • Implementing the Intel® Auto Connect Battery Saver (ACBS) With the Intel® 82566. Intel Corporation. 1.3 Product Codes Table 1 lists the product ordering codes for the 82566 device. Table 1. Product Ordering Codesa Part Number Product Name Description RU82566DM Intel® 82566 Gigabit Platform LAN Connect Device Business Desktop GbE LAN connection RU82566DC Intel® 82566 Gigabit Platform LAN Connect Device Consumer Desktop GbE LAN connection RU82566MM Intel® 82566 Gigabit Platform LAN Connect Device Business Mobile GbE LAN connection. RU82566MC Intel® 82566 Gigabit Platform LAN Connect Device Consumer Mobile GbE LAN connection a. For more information regarding the differences, please contact your Intel field representative. 2 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 2.0 Signal Descriptions 2.1 Signal Type Definitions The signals are defined as follows in the table below: Type 2.2 Table 2. Description In (I) Standard input-only signal. Out (O) Standard output-only signal. T/S Bi-directional, tri-state input/output signal. S/T/S Sustained tri-state signal. O/D Open drain signal. A-in Analog input signal. A-out Analog output signal. P Power signal. B Input bias. PU Pull-up. PD Pull-down. Gigabit LAN Connect Interface (GLCI) Pins GLCI Pins Signal Name Ball GLAN_RXP J4 GLAN_RXN H4 GLAN_TXN J2 GLAN_TXP H2 KBIAS_P G7 KBIAS_N H7 Type A-in Description GLCI Serial Data Input. This is the differential input for GLCI (MAC to PHY). A-out GLCI Serial Data Output. This is the differential output for GLCI (MAC to PHY). B Impedance Compensation. External 1.4 KΩ 1% resistors should be used. 3 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 2.3 Table 3. LAN Connect Interface (LCI) Pins LCI Pins Signal Name Ball Type Description LCI/GLCI Clock. The clock is driven by the 82566 according to the operation mode: • JKCLK E2 O In 1000 Mbps mode, JKCLK frequency is 62.5 MHz. • In 100 Mbps mode, JKCLK frequency is 50 MHz. • In 10 Mbps mode, JKCLK frequency is 5 MHz. • In power down mode, JKCLK frequency is 0 MHz. Reset/SYNC. This pin is driven by the MAC and has two functions: JRSTSYNC E3 JTXD2 2.4 Table 4. F3 JTXD0 D1 JRXD2 C1 JRXD1 D2 JRXD0 D3 Reset. When this pin is asserted beyond one LCI clock, the 82566 refers to this signal as a reset signal. However, to ensure that the 82566 resets, the reset should remain active for at least 500 µs. This functionality is also used to bring the 82566 out of a power-down state. • SYNC. When this pin is activated synchronously for one LCI clock only, it is used for synchronization between the MAC and the 82566 on LCI word boundaries. I I LCI Transmit Data. These pins are used for receiving real time control and management data transmitted by the ICH8/ICH9 LAN. These pins are also used to move out of band control from the MAC to the 82566. The pins should be fully synchronous to JKCLK. O LCI Receive Data. These pins are used for transmitting real time control and management data received by the ICH8/ICH9 LAN. These pins are also used to move out of band control from the 82566 to the MAC. F1 JTXD1 • Miscellaneous Pins Miscellaneous Pins Signal Name Ball THERM_D_P A2 THERM_D_N A3 Type Description A-out Thermal Diode Reference. This pin can be used to measure the silicon temperature within the device. N/A No Connect. These pins must not be connected to any external circuitry. Pull-up or pull-down resistors should not be connected to these pins. J6 J7 RESERVED A6 B5 C5 4 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 2.5 PHY Pins 2.5.1 LEDs Table 5. LED Pinsa Signal Name Ball Type Description LED0 A4 O LED0. This signal is used for the programmable LED. It is programmed through the Intel® ICH8/ICH9 NVM word 18h. LED1 B4 O LED1. This signal is used for the programmable LED. It is programmed through the Intel® ICH8/ICH9 NVM word 17h. LED2 A5 O LED2. This signal is used for the programmable LED. It is programmed through the Intel® ICH8/ICH9 NVM word 18h. a. The I/O Control Hub 8 /ICH9 NVM Map and Programming Information Application Notes can be referenced for details regarding the programming of the LEDs and the various modes. 2.5.2 Table 6. Analog Pins Analog Pins Signal Name Ball Type Description A Media Dependent Interface [0]. In MDI configuration, MDI_PLUS[0]+/- is used for the transmit pair and in MDI-X configuration MDI_MINUS[0]+/- is used for the receive pair. A Media Dependent Interface [1]. In MDI configuration, MDI_PLUS[1]+/- is used for the receive pair and in MDI-X configuration MDI_MINUS[1]+/- is used for the transmit pair. A Media Dependent Interface [2:3]. For 1000BASE-T MDI configuration, MDI_PLUS[2:3]+/- is used for the receive pair and in MDI-X configuration MDI_MINUS[2:3]+/- is used for the transmit pair. These pins are not used for 100BASE-TX and 10BASE-T. A-out Analog Test Pins Output. These are used for measurement of the transmitter 125 MHz clock jitter. MDI_PLUS[0] B8 MDI_MINUS[0] B9 MDI_PLUS[1] D9 MDI_MINUS[1] D8 MDI_PLUS[2] F9 MDI_MINUS[2] F8 MDI_PLUS[3] H8 MDI_MINUS[3] H9 IEEE_TEST_P A7 IEEE_TEST_N B7 RBIAS_P E7 RBIAS_N E6 XTAL1 H6 A-in XTAL2 H5 A-out B Compensation Reference Resistor. A 1.4 KΩ, 1% tolerance resistor should be used. RBIAS_N should also be connected to ground (VSS). Crystal In. These pins can be driven by an external 25 MHz crystal or by an external MOS level 25 MHz oscillator. It is also used as the clock reference for the PHY. 5 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 2.5.3 Table 7. Testability Pins Testability Pins Signal Name 2.6 Table 8. Type Description JTAG_TCK G1 I JTAG_TDI H1 I/PU JTAG TDI Input JTAG_TDO G3 T/S JTAG TDO Output JTAG_TMS G2 I/PU JTAG TMS Input TEST_EN B6 I JTAG Clock Input Test Mode Enable. This signal enables test mode capabilities. It should be strapped to GND for normal operation. Power Supply Pins Power Supply Pins (Sheet 1 of 2) Signal Name Ball VCC3P3 F2 VCC3P3 B3 VCC1P8 C2 VCC1P8 G5 VCC1P8 F5 VCC1P8 D5 CTRL_18 B2 VCC VCC1P0 VDD1P0 VDD1P0 6 Ball D4 E4 G4 Type Description P 3.3V DC Supply. This is connected to the 82566. P 1.8V DC Supply. This is connected to the 82566. Out 1.8V Control. This is the voltage control signal for the external PNP transistor that generates the 1.8V supply. P 1.0V DC Supply. This is connected to the 82566 core. P 1.0V DC Supply. This is connected to the GLCI circuits. P 1.0V DC Supply. This is connected to the PHY. P 1.0V DC Normal Operation. F7 D7 E8 E5 VCCF1P0, VCCFC1P0 H3 CTRL_10 C3 Out 1.0V Control. This is the voltage control signal for the external PNP transistor that generates the 1.0V supply. 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Table 8. Power Supply Pins (Sheet 2 of 2) Signal Name V1P0_OUT Ball Type Description B1 P 1.0V DC Output. This output is from the on-die internal regulator. This signal should be connected to VCC1P8 when external voltage regulators are used or in IVRd mode. V1P0_OUT should be connected to VCC1P0 for IVRi mode. P Ground P Analog Ground A1 VSS C4 E1 F4 A8 A9 C6 C7 C8 C9 D6 E9 VSSA F6 G6 G8 G9 J1 J3 J5 J8 J9 7 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Note: 8 This page intentionally left blank. 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 3.0 Voltage, Temperature, and Timing Specifications 3.1 Absolute Maximum Ratings Table 9. Absolute Maximum Ratingsa Symbol Tstorage Parameterb Minc Max Unit °C Storage Temperature Range -65 140 3.3V DC Digital Compatible I/O Voltage -0.5 4.6 Analog 1.0V DC I/O Voltage -0.2 1.68 Analog 1.8V DC I/O Voltage -0.3 2.52 VCCP 3.3V Periphery Voltage Range -0.5 4.6 V VCC1p8 1.8V Analog Voltage Range -0.3 2.52 V VCC1p0 1.0V DC Core/Analog DC Supply Voltage -0.2 1.68 V Vi Vo V a. Ratings in this table are those beyond which permanent device damage is likely to occur. These values should not be used as the limits for normal device operation. Exposure to these absolute maximum rating conditions for extended periods may affect device reliability. b. Recommended operating conditions require the accuracy of a power supply of +/- 5% relative to the nominal voltage. c. Maximum ratings are referenced to ground (VSS). 3.2 Recommended Operating Conditions Table 10. Recommended Operating Conditions Symbol Parameter Min Max Unit VCCP Periphery Voltage Range 3.0 3.6 V VCC1p8 Core Digital Voltage Range 1.71 1.89 V VCC1p0 Core/Analog Voltage Range 0.95 1.05 V 9 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 3.3 DC and AC Characteristics Table 11. Preliminary DC and AC Characteristics Symbol Parameter Condition Min Max Unit Notes VIL Voltage input LOW - - 0.8 V - VIH Voltage input HIGH V - V - - V - 160 - mV a - 15 µA - 2.0 - IOL= -12 mA; VCC=Min - 0.4 IOL=-100 µA; VCC=Min - 0.2 VOL Voltage output LOW VOH Voltage output HIGH Vhys Hysteresis Iil Input Current IOFF Current at IDDQ Mode - 50 µA b PU Internal Pull-Up 2.7 8.6 KΩ c Cin Input capacitance - 2.5 pF d Cout Load capacitance - 16 pF d IOH= -16 mA; VCC=Min 2.4 IOH=-100 µA; VCC=Min VCC-0.2 VCC-Max; VI=3.6V DC/GND @ 160 MHz a. The input buffer has a hysteresis greater than 160 mV. b. IDDQ mode maximum current consumption: CORE_VCCP: 15 µA; VCCP: 35 µA c. The internal pull-up maximum was characterized at slow corner (110C, VCC=min, process slow); and the internal pull-up minimum, at fast corner (0C, VCC=max, process fast). d. Pad Cin = 2.5 pF (maximum input capacitance), and Cout = 16 pF (characterized maximum output load capacitance per 160 MHz). 3.4 LED/TEST/JTAG I/F DC Specifications Table 12. Preliminary LED/TEST/JTAG I/F DC Specifications 10 Symbol Parameter Condition Min Max Unit Notes VCCP Periphery Supply - 3.0 3.6 V - Vih Input High Voltage - 2.0 VCC +0.3 V - Vil Input Low Voltage - -0.3 0.8 V - Vleak Input Leakage Current 0 < Vin< VCCP - ±20 µA - Voh Output High Voltage Iout = -16 mA 2.4 - V - Vol Output Low Voltage Iout = -0.1 mA - 0.2 Iout = -12 mA - 0.4 V - Cin Input Pin Capacitance - - 2.5 pF - 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 3.5 Power Supply Connections There are two options in providing power to the 82566: • Connecting the 82566 to three external power supplies with nominal voltages of 3.3V DC, 1.8V DC, and 1.0V DC, which is covered in Section 3.5.1. • Powering the 82566 with only an external 3.3V DC supply and using internal power regulators from the device itself combined with external PNP transistors to supply the 1.8V DC and 1.0V DC levels as described in Section 3.5.2. 3.5.1 External Voltage Regulator (EVR) Power Delivery The following power supply requirements apply to designs where the 82566 is supplied by external voltage regulators (EVRs). These systems do not use the internal regulator logic built into the device as described in Section 3.5.2. Table 13. 3.3V DC External Power Supply Parameters Title Description Min Max Units Rise Time Time from 10% to 90% mark 0.1 100 ms Monotonicity Voltage dip allowed in ramp - 0 mV 24 28800 V/s Ramp rate at any given time between 10% and 90% Slope Min: 0.8*V(min)/Rise time (max) Max: 0.8*V(max)/Rise time (min) Operational Range Voltage range for normal operating conditions 3.0 3.6 V Ripple Maximum voltage ripple (peak to peak)a - 100 mV Overshoot Maximum overshoot allowed - 100 mV a. This is dependent on capacitance. Table 14. 1.8V DC External Power Supply Parameters Title Description Min Max Units Rise Time Time from 10% to 90% mark 0.1 100 ms Monotonicity Voltage dip allowed in ramp - 0 mV Ramp rate at any given time between 10% and 90% Slope Min: 0.8*V(min)/Rise time (max) 14 V/s Max: 0.8*V(max)/Rise time (min) Operational Range Voltage range for normal operating conditions 1.71 1.89 V Ripple Maximum voltage ripple (peak to peak)a - 40 mV 11 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Table 14. 1.8V DC External Power Supply Parameters Title Description Min Max Units Overshoot Maximum overshoot allowed - 100 mV Decoupling Capacitance Capacitance range 15 25 µF Capacitance ESR Equivalent series resistance of output capacitance - 50 mΩ Units a. This is dependent on capacitance. Table 15. 1.0V DC External Power Supply Parameters Title Description Min Max Rise Time Time from 10% to 90% mark 0.1 100 ms Monotonicity Voltage dip allowed in ramp - 0 mV 7.6 17 V/s Ramp rate at any given time between 10% and 90% Slope Min: 0.8*V(min)/Rise time (max) Max: 0.8*V(max)/Rise time (min) Operational Range Voltage range for normal operating conditions 0.95 1.05a V Ripple Maximum voltage ripple (peak to peak)b - 40 mV Overshoot Maximum overshoot allowed - 100 mV Decoupling Capacitance Capacitance range 15 25 µF Capacitance ESR Equivalent series resistance of output capacitance - 50 mΩ a. To reduce BOM costs, the ICH8/ICH9 1.05V +/-5% supply can be used. b. This is dependent on capacitance. 3.5.1.1 In-Rush Current To meet 375 mA in-rush current requirements (not including external capacitors), the ramp time should be 5 ms to 100 ms on all power rails. For faster ramps (100 µs to 5 ms), higher in-rush current is expected due to the high charging current of the decoupling capacitors on the 3.3V DC, 1.8V DC, and 1.0V DC power rails. 3.5.1.2 82566 Power Up Sequence (External LVR) Designs must comply with power sequencing requirements to avoid latch-up and forward-biased internal diodes. The board designer controls the power up sequence with the following stipulations: • 1.8V must not exceed 3.3V by more than 0.3 V. • 1.0V must not exceed 3.3V by more than 0.3 V. For power down, there is no requirement (only charge that remains is stored in the decoupling capacitors). 12 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Figure 2. External LVR Power-up Sequence 3.5.2 Internal Voltage Regulator (IVR) Power Delivery The 82566 has two IVR controllers. One for the 1.8V supply and one for the 1.0V supply. There are two IVR modes of operation known as IVRd and IVRi. IVRd uses two external transistors to generate the 1.8V and 1.0V supplies. In this mode, these two voltages are stepped down from a 3.3V DC source. IVRi mode uses an external transistor to generate the 1.8V supply and an internal transistor to generate the 1.0V supply. In this mode, the 1.8V supply is stepped down from a 3.3V DC source, and the 1.0V supply is stepped down from the 1.8V DC supply. Table 16. 3.3V DC External Power Supply Parameters Title Description Min Max Units Rise Time Time from 10% to 90% mark 0.1 100 ms Voltage dip allowed in ramp - 0 mV 24 9.5 mV/ms Operational Range Voltage range for normal operating conditions 3.0 3.6 V Ripple Maximum voltage ripple (peak to peak) @ f < 20 MHz - 100 mV Overshoot Maximum overshoot allowed - 100 mV - 0.05 ms Monotonicity Ramp rate at any given time between 10% and 90% Slope Min: 0.8*V(min)/Rise time (max) Max: 0.8*V(max)/Rise time (min) Overshoot Settling Time Maximum overshoot allowed duration. (At that time delta voltage should be lower than 5 mV from steady state voltage) 13 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 3.5.2.1 In-Rush Current To meet 375 mA in-rush current requirements, the ramp time should be 5 ms to 100 ms on the 3.3V DC power rail. For faster ramps (100 µs to 5 ms), higher in-rush current is expected due to the high charging current of the decoupling capacitors on the 3.3V DC power rail. 3.5.2.2 82566 Power Up Sequence (Internal LVR) The 82566 controls the power up sequence internally and automatically with the following conditions: • 3.3V must be the source for the internal LVR. • 1.8V will never exceed the 3.3V. • 1.0V will never exceed 3.3V or 1.8V. The ramp is delayed internally, with Tdelay depending on the rising slope of the 3.3V ramp. For power down, there is no requirement (only charge that remains is stored in the decoupling capacitors). Figure 3. Internal LVR Power-up Sequence 14 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 3.5.2.3 1.8V DC Internal LVR Specification Table 17. 1.8V DC Internal LVR Specification Value Parameter Units Comments 3.6 V Typically 3.3V - - ms Typically 5 ms DC Output Voltage (Vdd1p8) 1.71 1.89 V Measured on the internal sense point. Output Current (I_vdd1p8) 5 950 mA Typically 300 mA Turn-On Time (T_on) 3 10 ms Both for 1.8V DC and 1.0V DC LVRs Minimum Maximum Input Voltage (V_in) 3.0 Input Voltage Slew Rate (V_in_rise) Peak-to-Peak Output Ripple (Vac) Power Supply Rejection Ratio (1p8_PSRR) 1p8 LVR Voltage @ Over/Under Shoot Event (1p8_event) 3.5.2.4 - 50 mV The peak to peak output ripple is measured at 20 MHz Bandwidth. - -20 dB Typically -40 dB - 50 mV - Units Comments 1.0V DC Internal LVR Specification Table 18. 1.0V DC Internal LVR Specification Value Parameter Minimum Maximum Input Voltage (V_in) 3.0 3.6 V Typically 3.3V Input Voltage Slew Rate (V_in_rise) - - ms Typically 5 ms DC Output Voltage (V1p0_out) 0.95 1.05 V Measured on the internal sense point. Output Current (I_v1p0) 5 400 mA Typically 200 mA 15 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Table 18. 1.0V DC Internal LVR Specification Value Parameter Minimum Maximum 3 10 Turn-On Time (T_on) Units Comments ms Both for 1.8V DC and 1.0V DC LVRs Both for 1.8V DC and 1.0V DC LVRs. 3.5.2.5 Peak-to-Peak Output Ripple (Vac) - 50 mV The peak to peak output ripple is measured at 20 MHz Bandwidth. Power Supply Rejection Ratio (1p0_PSRR) - -20 dB Typically -40 dB PNP Transistor Specification for 1.8V DC LVR Table 19. PNP Specification for 1.8V DC LVR PNP Connection PNP Transistor for 1.8V DC LVR, using internal Transistor for 1.0V DC LVR PNP Transistor for 1.8V DC LVR, using external Transistor for 1.0V DC LVR Description Symbol Min Typ Max Units DC Gaina β 60 - 400 Transition Frequency fT - 40 - MHz Thermal Resistance Junction to Ambientb Rt_ja - - 60 °C/W Maximum Operation Junction Temperature Tj_max - - 150 °C Maximum Collector Current Ic_max - - 1 A Maximum total power dissipationc Pmax - - 1.2 W DC Gaind β 60 - 400 V Transition Frequency fT - 40 - MHz Thermal Resistance Junction to Ambientb Rt_ja - - 60 °C/W Maximum Operation Junction Temperature Tj_max - - 150 °C Maximum Collector Current Ic_max - - 1 A Maximum Power Dissipatione Pmax - - 1.2 W a. Vce = 0.4 V DC; Ic = 1 A; T = 25 °C. b. The thermal resistance feature depends on the PNP package along with the board layout including: number of layers, layer thickness, copper area for collector pad, and component locations. c. Ta = 70 °C; Vin = 3.6 V DC; Vout = 1.71 V DC; I = 0.95 A; 1.4 Ω 5% Series Resistor. d. Vce = 1 V DC; Ic = 0.5 A; T = 25 °C. e. Ta = 70 °C; Vin = 3.6 V DC; Vout = 1.7 1 V DC; I = 0.55 A. 16 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 3.5.2.6 PNP Transistor Specification for 1.0V DC LVR Table 20. PNP Specification for 1.0V DC LVR PNP Connection PNP Transistor for 1.0V DC LVR Description Symbol Min Typ Max Units dc Gaina β 60 - 400 - Transition Frequency fT - 40 - MHz Thermal Resistance Junction to Ambientb Rt_ja - - 60 °C/W Maximum Operation Junction Temperature Tj_max - - 150 °C Maximum Collector Current Ic_max - - 1 A Maximum Power Dissipationc Pmax - - 1.1 W a. Vce = -1.0 V DC; Ic = 0.5 A; T = 25 °C. b. The thermal resistance feature depends on the PNP package along with the board layout including: number of layers, layer thickness, copper area for collector pad, and component locations. c. Ta = 70 °C; Vin = 3.6 V DC; Vout = 0.95 V DC; I = 0.4 A 3.5.3 Crystal Table 21 lists the recommended crystal specifications for operation with the 82566. Table 21. Crystal Specifications (Sheet 1 of 2) Parameter Name Symbol Recommended Value Max/Min Range Conditions Frequency fo 25.000 MHz - @25 °C Vibration mode - Fundamental - - Cut - AT - - Operating/Calibration Mode - Parallel - - Frequency Tolerance ∆f/fo @25°C ±30 ppm a @25 °C ±30 ppm a - Temperature Tolerance ∆f/fo Operating Temperature Topr -20 to +70 °C a Non Operating Temperature Topr -40 to +90 °C - - Equivalent Series Resistance (ESR) Rs 10 Ω 50 Ω @25 MHz Load Capacitance Cload 20 pF (max 24 pF) a - Shunt Capacitance Co 6 pF a - Pullability from Nominal Load Capacitance ∆f/Cload 15 ppm/pF max - - Max Drive Level DL 500 µW - - Insulation Resistance IR 500 MΩ min Aging ∆f/fo ±5 ppm per year @ 100V DC ±5 ppm per year - 17 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Table 21. Crystal Specifications (Sheet 2 of 2) Parameter Name Symbol Recommended Value Max/Min Range Conditions Differential Board Capacitance CD 2 pF b Board Capacitance Cs 4 pF c - External Capacitors C1, C2 27 pF a - Board Resistance Rs 0.1 Ω 1Ω - a. When not using values within 1% of the recommended values, the following procedures must be used: 1. On the board with the crystal and the 82566, measure the clock at the output of the receive and transmit lines. 2. Change C1 and C2 to meet with the 25 MHz requirement. 3. Ensure the demand on the 25 MHz clock has a deviation of less then 100 ppm (for example, 25 ± 0.0025 MHz). 4. If the measured frequency is higher then 25.0025 MHz, replace capacitors C1 and C2 with larger capacitors. 5. If the measured frequency is lower then 24.9975 MHz, replace capacitors C1 and C2 with smaller capacitors. b. Differential board capacitance is the capacitance between Ser_CLK_PLUS and Ser_CLK_MINUS. c. Board capacitance is the differential capacitance between the input and output. This parasitic capacitance must be less than or equal to the specification. This value can change up to 10%. The procedures listed in footnote “a” must be followed to comply with the ppm specification. Figure 4. Crystal Connectivity to the 82566 Crystal “B” 90 mils Capacitor 90 mils Crystal Pad “A” 27pF 0402 “B” Crystal Pad Capacitor 27pF 0402 Less than 660 mils “C” Resistor 30-ohm 0402 Xtal2 Xtal1 Ethernet Controller Note: 18 Refer to Technical Advisory (TA-181), the 82566 Board Layout Checklist, and the 82566 Design Checklist for details relating to Figure 4. 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 3.6 Power Consumption This section lists the estimated targets for the 82566 power. The numbers apply to the device current and power but do not include power losses on external components. Table 22. Power Consumption (82566MC/MM) System State So (Max) S0 (Typ) Sx (Typ) 3.3V Current (mA) 1.8V Current (mA) 1.0V Current (mA) 82566 Device Only Power (mW) External LVR Solution Powera (mW) 1000 Mbps Active 28 440 297 1180 2525 1000 Mbps Active 26 441 281 1161 2468 1000 Mbps Idle 25 442 263 1141 2409 100 Mbps Active 33 145 56 424 772 100 Mbps Idle 27 145 56 405 752 10 Mbps Active 17 148 19 343 607 10 Mbps Idle 15 46 18 150 261 Cable Disconnect (no SPD, LVR on) 15 46 18 150 261 Cable Disconnect (SPD, LVR on) 17 24 10 108 168 Cable Disconnect (no Intel® ACBSb, LVR off, no wake) 12 0 0 40 40 Cable Disconnect (Intel® ACBS, LVR off, wake)c 12 0 0 40 40 Cable Disconnect (Intel® ACBS, 3.3V power disabled, wake)c 0 0 0 0 0 100 Mbps Idle (wake) 29 144 56 411 756 10 Mbps Idle (wake) 19 46 18 159 271 No Link (no wake) PD, LVR off 12 0 0 40 40 LAN Disable 12 0 0 40 40 Link State a. Solution power is the total amount of power from the 3.3V supply required for the 82566 to operate. In its mathematical form: solution power = (82566 current) * 3.3V. The 3.3V is assumed since this is the normal voltage rail provided to the LAN solution. b. Intel® ACBS refers to the Intel® Auto-Connect Battery Saving feature. c. An additional 7 mW of power is consumed on the 3.3V rail by the external link detect circuitry while the device is in ACBS mode. 19 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Table 23. Power Consumption (82566DC/DM) System State So (Max) S0 (Typ) Sx (Typ) Link State 1000 Mbps Active 3.3V Current (mA) 1.8V Current (mA) 1.0V Current (mA) 82566 Device Only Power (mW) External LVR Solution Powera (mW) 28 440 297 1180 2525 1000 Mbps Active 26 441 281 1161 2468 1000 Mbps Idle 25 442 263 1141 2409 100 Mbps Active 33 145 56 424 772 100 Mbps Idle 27 145 56 405 752 10 Mbps Active 17 148 19 343 607 10 Mbps Idle 15 46 18 150 261 Cable Disconnect (no SPD, LVR on) 15 46 18 150 261 Cable Disconnect (SPD, LVR on) 17 24 10 108 168 100 Mbps Idle (wake) 29 144 56 411 756 10 Mbps Idle (wake) 19 46 18 159 271 No Link Idle (wake) 21 109 50 180 292 No Link (no wake) - PD 12 0 0 40 40 LAN Disable 12 0 0 40 40 a. Solution power is the total amount of power from the 3.3V supply required for the 82566 to operate. In its mathematical form: solution power = (82566 current) * 3.3V. The 3.3V is assumed since this is the normal voltage rail provided to the LAN solution. The current from the 82566 does not change regardless of generating the 1.0V using the on-die transistor or an external pass transistor. The total current demand remains constant, but the power dissipated by the 82566 package changes. The 1.0V power is either on-die or at the external pass transistor. 20 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 4.0 Package and Pinout Information The physical characteristics of the 82566 are described in this section. The pin number to signal mapping is indicated in Section 4.5. 4.1 Package Information The package used for the 82566 is an 81-pin, 10 mm x 10 mm, small footprint FCMMAP (BGA) with a ball pitch of 1.0 mm. Figure 5. Mechanical Drawing (1 of 4) &#--!08 MM0)4#(,!.$3 "/44/-,!.$3)$% ¼ ! 3%%$%4!), ¼ 3%%$%4!), " ¼ 8 ¼ 3/,$%2-!3+/0%.%$ ! &' ¼ ¼ -%4!,0!$ ¼ ¼ ! $%4!), 3#!,% 0,!#%3 ¼ " $%4!), 3#!,% "/44/-0).&)$5#)!, 21 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Figure 6. Mechanical Drawing (2 of 4) 4/0$)%3)$% 8 8 ¼ 8 $ 3%%$%4!), 8 8 3%%$%4!), 8 # -%4!,0!$ 8 3/,$%2-!3+/0%.%$ ¼ ¼ # $%4!), 3#!,% 0).&)$5#)!, 22 ¼ ¼ $ $%4!), 3#!,% 8 35"342!4%!,)'.-%.4 &)$5#)!,33!& ! $% 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Figure 7. Mechanical Drawing (3 of 4) NOTES: 1). DIMENSION APPLY AFTER SOLDER BALL REFLOW. 2). INTERPRET DIMENSIONS AND TOLERANCES IN ACCORDANCE WITH ASME Y14.5M-1994. 3). DIMENSION ENCLOSED IN PARENTHESES ARE FOR REFERENCE ONLY SEE DETAIL ITEM A B DIMENSION 1.745±0.07 0.515±0.035 INCOMING BALL SIZE(mm) N/A 0.610 A DETAIL 1.0 mm BALL PITCH 1.0 mm BALL PITCH 23 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet Figure 8. Mechanical Drawing (4 of 4) DETAIL A SCALE 50:1 4.2 Thermal The 82566 is specified for operation when the Ambient Temperature (TA) is within the range of 0 °C to 55 °C. For information about the thermal characteristics of the 82566, including operation outside this range, refer to the 82566 Gigabit Platform LAN Connect Thermal Design Considerations Application Note. 4.3 Internal Pull-Up Resistors Table 24 lists the internal pull-up resistors and their functionality in different device states. Each internal pull-up resistor has a nominal value of 5 KΩ, ranging from 2.7 KΩ to 8.6 KΩ. Table 24. Internal Pull-Up Resistors Default State Power-Down Statea LED0 (A4) Not connected Connected LED1 (B4) Not connected Connected LED2 (A5) Not connected Connected JTAG_TCK (G1) Not connected Connected JTAG_TDI (H1) Connected Connected JTAG_DO (G3) Not connected Connected Connected Connected JTXD[2:0] (F1, F3, D1) Not connected Connected JRXD[2:0] (C1, D2, D3) Not connected Connected Signal Name (Ball Location) JTAG_TMS (G2) a. This column describes the state of the internal pull-up resistors in device power-down mode when the internal voltage regulators are shut down. 24 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 4.4 Pull-Up and Pull-Down Current 1. External R pull-down recommended value: ≤ 400 Ω 2. External R pull-up recommended value: ≤ 3 KΩ 3. External buffer recommended strength: ≥ 2 mA 4. As the internal pull-up acts as a current source, the external pull-down resistor can be as low as required without raising the output current. Ipad[mA] Figure 9. Vpad versus Ipad OV 50%VCCP Vpad 5. The internal pull-up maximum was characterized at the fast corner (0C, VCCP=3.6V, process fast). 6. The internal pull-up minimum was characterized at the slow corner (115C, VCCP=2.9V, process slow). 25 82566 Gigabit Platform LAN Connect Networking Silicon Datasheet 4.5 Visual Pin Assignments Figure 10. 82566 Pinout (Top View - Balls Down) VSSA VSSA MDI_ MDI_ MINUS[3] PLUS[3] VSSA MDI_ PLUS[2] VSSA VSSA RSV KBIAS_N KBIAS_P MDI_ VDD1P0 MINUS[2] VDD1P0 RSV XTAL1 VSSA VSSA VSSA XTAL2 VCC1P8 VCC1P8 GLAN_ TXN VSSA GLAN_ TXP JTAG_TDI JTAG_ TDO JTAG_ TMS JTAG_ TCK JTXD1 VCC3P3 JTXD2 GLAN_ RXP VSSA GLAN_ RXN VCCFC1P0 VCC1P0 VSS J H G F RBIAS_P RBIAS_N VCCF1P0 VCC JRSTSYNC JKCLK VSS E MDI_ PLUS[1] VSSA MDI_ VDD1P0 MINUS[1] VSSA VSSA VSSA VCC1P8 VCC JRXD0 JRXD1 JTXD0 D VSSA RSV VSS CTRL_10 VCC1P8 JRXD2 C MDI_ MDI_ MINUS[0] PLUS[0] VSSA VSSA 9 8 IEEE_ TEST_N TEST_EN IEEE_ TEST_P RSV LED2 LED0 6 5 4 7 RSV LED1 VCC3P3 CTRL_18 THERM_ THERM_ D_N D_P 3 2 V1P0_ OU T VSS B A 1 NOTE: Some names in the pinout in Figure 10 may differ from the signal names in order for the pinout to be more easily read. 26