82562ET 10/100 Mbps Platform LAN Connect (PLC) Networking Silicon Datasheet Product Features ■ ■ ■ ■ ■ ■ ■ ■ IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface IEEE 802.3u Auto-Negotiation support Digital Adaptive Equalization control Link status interrupt capability XOR tree mode support 3-port LED support (speed, link and activity) 10BASE-T auto-polarity correction LAN Connect Interface ■ ■ ■ ■ ■ ■ ■ Diagnostic loopback mode 1:1 transmit transformer ratio support Low power (less than 300 mW in active transmit mode) Reduced power in “unplugged mode” (less than 50 mW) Automatic detection of “unplugged mode” 3.3 V device 48-pin Shrink Small Outline Package Revision 1.3 March 2003 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. 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The 82562ET PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © 2003, Intel Corporation * Other brands and names are the property of their respective owners. Datasheet Networking Silicon — 82562ET Revision History Revision Datasheet Revision Date Description 1.3 March 2003 1.2 October 2001 Removed confidential status. • Removed sections: “Physical Layer Interface Functionality” and “Platform LAN Connect”. • Changed “Electrical and Timing Specifications” section to “Voltage and Temperature Specifications” and removed timing specifications. Added product ordering code in Section 1.0. 1.1 June 2000 Advance Information Datasheet release (Intel Confidential). • On cover page, replaced Boundary Scan Support with XOR tree mode support. Added bullet for LAN Connect I/F. • Pg. 3, added a Solution Block Diagram as included in OR-2338 Pg. 4 but replaced EM with ET in diagram. • Pg. 11, removed Figure 4, “NRZ to MLT-3 Encoding Diagram”. • Pg. 35, changed the Rev. number on the 82562 Pinout symbol to 1.0. 1.0 May 2000 Advance Information Datasheet release (Intel Secret). • Modified Table 1 “82562ET Hardware Configuration” to add one row for XOR Tree and include column for comments. • Updated the descrition of the Activity LED signal in Section 3.6, “LED Pins”. • Revised Section 3.7, “Miscellaneous Control Pins” to reflect references to Table 1 “82562ET Hardware Configuration”. • Updated Section 4.0, “Voltage and Temperature Specifications”. • Replaced diagrams in Section 5.1, “Package Information”. 0.6 Nov. 1999 • Corrected Figure 4 “NRZ to MLT-3 Encoding Diagram on Pg. 11 to reflect correct signal transitions. • Removed “10BASE-T Error Detection and Reporting” section since the 82562 does not do 10BASE-T error reporting. 0.55 Sept. 1999 Initial release. iii 82562ET — Networking Silicon iv Datasheet Networking Silicon — 82562ET Contents 1.0 Introduction......................................................................................................................... 1 1.1 1.2 1.3 Overview ............................................................................................................... 1 Features ................................................................................................................ 1 References ............................................................................................................ 1 2.0 82562ET Architectural Overview........................................................................................ 3 3.0 82562ET Signal Descriptions ............................................................................................. 5 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 4.0 Voltage and Temperature Specifications ...........................................................................9 4.1 4.2 5.0 Absolute Maximum Ratings................................................................................... 9 DC Characteristics ............................................................................................... 9 4.2.1 X1 Clock DC Specifications ..................................................................... 9 4.2.2 LAN Connect Interface DC Specifications .............................................10 4.2.3 LED DC Specifications .......................................................................... 10 4.2.4 10BASE-T Voltage and Current DC Specifications ............................... 10 4.2.5 100BASE-TX Voltage and Current DC Specifications ..........................11 Package and Pinout Information ...................................................................................... 13 5.1 5.2 Datasheet Signal Type Definitions ......................................................................................... 5 Twisted Pair Ethernet (TPE) Pins .........................................................................5 External Bias Pins ................................................................................................ 5 Clock Pins ............................................................................................................ 6 Platform LAN Connect Interface Pins....................................................................6 LED Pins .............................................................................................................. 7 Miscellaneous Control Pins .................................................................................. 7 Power and Ground Connections .......................................................................... 8 Package Information ........................................................................................... 13 Pinout Information ............................................................................................... 14 5.2.1 82562ET Pin Assignments .................................................................... 14 5.2.2 82562ET Shrink Small Outlying Package Diagram ............................... 15 v 82562ET — Networking Silicon vi Datasheet Networking Silicon — 82562ET 1.0 Introduction 1.1 Overview The Intel® 82562ET is a highly-integrated Platform LAN Connect device designed for 10 or 100 Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards. The IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5 unshielded twisted pair cable or Type 1 shielded twisted pair cable. The 82562ET complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full Duplex Flow Control standard. The 82563ET also includes a PHY interface compliant to the current platform LAN connect interface. 1.2 Features • • • • • • • • • • • • • • • 1.3 IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface IEEE 802.3u Auto-Negotiation support Digital Adaptive Equalization control Link status interrupt capability XOR Tree mode support for board testing 3-port LED support (speed, link and activity) 10BASE-T auto-polarity correction Diagnostic loopback mode 1:1 transmit transformer ratio support Low power (less than 300 mW in active transmit mode) Reduced power in “unplugged mode” (less than 50 mW) Automatic detection of “unplugged mode” 3.3 V device 48-pin Shrink Small Outline Package Platform LAN connect interface support References • IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and Electronics Engineers • 82555 10/100 Mbps LAN Physical Layer Interface Datasheet, Intel Corporation • LAN Connect Interface Specification, Intel Corporation Datasheet 1 82562ET — Networking Silicon 1.4 Product Code The product ordering code for the 82562ET is: DA82562ET. 2 Datasheet Networking Silicon — 82562ET 2.0 82562ET Architectural Overview The 82562ET is a highly integrated Platform LAN Connect device that combines a 10BASE-T and 100BASE-TX physical layer interfaces. The 82562ET supports a single interface fully compliant with the IEEE 802.3 standard. Figure 1 provides a block diagram of the 82562ET architecture. Figure 1. 82562ET Block Diagram Digital Equalizer Adaptation LILED Port LED Drivers ACTLED SPEEDLED MDI/MDI-X RDN/RDP TDN/ TDP Equalizer & BLW correction Digital Clock Recovery (100) 100Base-TX PCS CRS/Link 10 Detection Digital Clock Recovery (10) 10Base-T PCS LAN_RSTSYNC 3 LAN Connect Interface Transmit DAC 10/100 3 LAN_TXD[2:0] LAN_RXD[2:0] LAN_CLK AutoNegotiation Bias & BandGap Voltage Circuit Clock Generator X1 Crystal 25 MHz Control Registers X2 The 8252ET is a 3.3 V device in a 48-pin Shrink Small Outline Package (SSOP). This document describes the architecture of the device in all modes of operation. Four pins, test Enable (TESTEN), Test Clock (ISOL_TCK), Test Input (ISOL_TI), and Test Execute (ISOL_EX), define the general operation of the device. Table 1 shows the pin settings for the different modes of operation. Table 1. 82562ET Hardware Configuration Mode of Operation Normal operating mode Isolate mode TESTEN ISOL_TCK ISOL_TI ISOL_EX 0 0 0 0 0 1 1 1 The device is in tri-state and power-down mode. 1 1 1 1 The device is in tri-state and the fully powered down. 1 0 0 0 The XOR Tree is used for board testing and tri-state mode. (Tri-state and full power-down mode) XOR Tree Comments The ISOL_TCK, ISOL_TI, and ISOL_EX pins can remain floating. NOTE: Combinations not shown in Table 1 are reserved and should not be used. Datasheet 3 82562ET — Networking Silicon Figure 2. 82562ET Solution Overview Clock DATA CTRL Procesor ADDR VRM DATA CTRL ADDR Termination 2 RIMM Modules MCH PCI Control Bus ICH2 USB Port 1 PCI Address/Data Bus USB PCI Connector 3 UltraDMA/33 PCI Connector 1 IDE Secondary PCI Connector 2 IDE Primary USB Port 2 AMC97 Audio/ Modem AC97 Link Control Address/Data 82550 LAN Controller LPC Bus SIO 82562ET PLC Keyboard Floppy Parallel Game Conn Mouse Serial 1 4 Datasheet Networking Silicon — 82562ET 3.0 82562ET Signal Descriptions 3.1 Signal Type Definitions Type 3.2 Name I Input Input pin to the 82562ET. O Output Output pin from the 82562ET. I/O Input/Output Multiplexed input and output pin to and from the 82562ET. MLT Multi-level analog I/O Multi-level analog pin used for input and output. B Bias Bias pin used for ground connection through a resistor or an external voltage reference. DPS Digital Power Supply Digital power or ground pin for the 82562ET. APS Analog Power Analog power or ground pin for the 82562ET. Supply Twisted Pair Ethernet (TPE) Pins Pin Name 3.3 Description Pin Number TDP 10 TDN 11 RDP 15 RDN 16 Type Description MLT Transmit Differential Pair. The transmit differential pair sends serial bit streams to the unshielded twisted pair (UTP) cable. The differential pair is a two-level signal in 10BASE-T (Manchester) mode and a three-level signal in 100BASE-TX mode (MLT-3). These signals directly interface with the isolation transformer. MLT Receive Differential Pair. The receive differential pair receive the serial bit stream from an unshielded twisted pair (UTP) cable. The differential pair is a two-level signal in 10BASE-T mode (Manchester) or a three-level signal in 100BASE-TX mode (MLT-3). These signals directly interface with an isolation transformer. External Bias Pins Pin Name Pin Number Type Description RBIAS10 4 B Bias Reference Resistor 10. This pin should be connected to a 549 Ω pull-down resistor.a RBIAS100 5 B Bias reference Resistor 100. This pin should be connected to a 619 Ω pull-down resistor.b a. 549 Ω for RBIAS10 is only a recommended value and should be fine tuned for various designs. b. 619 Ω for RBIAS100 is only a recommended value and should be fine tuned for various designs. Datasheet 5 82562ET — Networking Silicon 3.4 Clock Pins Pin Name 3.5 Pin Number Type X1 46 I Crystal Input Clock. X1 and X2 can be driven by an external 25 MHz crystal of 50 PPM or better. Otherwise, X1 is driven by an external metaloxide semiconductor (MOS) level 25 MHz oscillator when X2 is left floating. X2 47 O Crystal Output Clock. X1 and X2 can be driven by an external 25 MHz crystal of 50 PPM or better. Platform LAN Connect Interface Pins Pin Name Pin Number Type Description LAN_CLK 39 O LAN Connect Clock. The LAN Connect Clock is driven by the 82562ET on two frequencies depending on operation speed. When the 82562ET is in 100BASE-TX mode, LAN_CLK drives a 50 MHz clock. Otherwise, LAN_CLK drives a 5 MHz clock for 10BASE-T. The LAN_CLK does not stop during normal operation. LAN_ 42 I Reset/Synchronize. This is a multiplexed pin and is driven by the Media Access Control (MAC) layer device. Its functions are: RSTSYNC LAN_ TXD[2:0] LAN_ RXD[2:0] 6 Description • Reset. When this pin is asserted beyond one LAN Connect clock period, the 82562ET uses this signal Reset. To ensure reset of the 82562ET, the Reset signal should remain active for at least 500 µseconds. • Synchronize. When this pin is activated synchronously, for only one LAN Connect clock period, it is used to synchronize the MAC and PHY on LAN Connect word boundaries. 45, 44, 43 I LAN Connect Transmit Data. The LAN Connect transmit pins are used to transfer data from the MAC device to the 82562ET. These pins are used to move transmitted data and real time control and management data. They also transmit out of band control data from the MAC to the PHY. The pins should be fully synchronous to LAN_CLK. 37, 35, 34 O LAN Connect Receive Data. The LAN Connect receive pins are used to transfer data from the 82562ET to the MAC device. These pins are used to move received data and real time control and management data. They also move out of band control data from the PHY to the MAC. These pins are synchronous to LAN_CLK. Datasheet Networking Silicon — 82562ET 3.6 LED Pins Pin Name Pin Number Type Description LILED# 27 O Link Integrity LED. The LED is active low and the Link Integrity LED pin indicates link status in either 10BASE-T or 100BASE-TX mode. If a link is present in either mode, the LILED is asserted. ACTLED# 32 O Activity LED. The LED is active low and the Activity LED signal indicates either receive or transmit activity. When no activity is present, the LED is off. The Activity LED will flicker when activity is present. The flicker rate depends on the activity load. The individual address LED control bit (Word A hexadecimal, bit 4) in the ICH2 EEPROM can select the ACTLED# behavior. It controls the Activity LED (ACTLED) functionality in Wake on LAN (WOL) mode. 0 = In WOL mode, the ACTLED is activated by the transmission and reception of broadcast and individual address match packets. 1 = In WOL mode, the ACTLED is activated by the transmission and reception of individual address match packets only. This bit is configured by the OEM and is activated by a transmission and reception of individual address match packets. SPDLED# 3.7 31 O Speed LED. The LED is active low and the Speed LED signal indicates the speed of operation, either 10 Mbps or 100 Mbps. The Speed LED is on during 100BASE-TX operation and off in 10BASE-T mode. Miscellaneous Control Pins Pin Name Pin Number Type ADV10 41 I ISOL_TCK 30 I Description Advertise 10 Mbps Only. The Advertise 10 Mbps Only signal is asserted high, and the 82562ET advertises only 10BASE-T technology during Auto-Negotiation processes in this state. Otherwise, the 82562ET advertises all of its technologies. Note: ADV10 has an internal pull-down resistor. Test Clock. The Test Clock signal sets the device into asynchronous test mode in conjunction with the Test Input, Test Execute and Test Enable pins (refer to Table 1). In the manufacturing test mode, it acts as the test clock. Note: ISOL_TCK has an internal pull-down resistor. ISOL_TI 28 I Test Input. The Test Input signal sets the device into asynchronous test mode in conjunction with the Test Clock, Test Execute and Test Enable pins (refer to Table 1). In the manufacturing test mode, it acts as the test data input pin. Note: ISOL_TI has an internal pull-down resistor. Datasheet 7 82562ET — Networking Silicon Pin Name ISOL_TEX Pin Number 29 Type I Description Test Execute. The Test Execute signal sets the device into asynchronous test mode in conjunction with the Test Clock, Test Input, and Test Enable pins (refer to Table 1). In the manufacturing test mode, it places the command that was entered through the TI pin in the instruction register. Note: ISOL_TEX has an internal pull-down resistor. 3.8 TOUT 26 O Test Output. The Test Output pin is used for Boundary XOR scan output. In the manufacturing test mode, it acts as the test output port. TESTEN 21 I Test Enable. The Test Enable pin is used to enable test mode and should be pulled down to VSS to allow XOR Tree test mode. Power and Ground Connections Pin Name Pin Number VCC 1, 25 VCCP 36, 40 VCCA 2, VCCA2 7, VCCT 9, 12, Type DPS Description Digital 3.3 V Power. These pins should be connected to the main digital power supply. 14, 17 VSS 8, 13, 18 DPS 24, 48 8 VSSP 33, 38 VSSA 3 Digital Ground. These pins should be connected to the main digital ground. VSSA2 6 VCCR 19, 23 APS Analog Power. VSSR 20, 22 APS Analog Ground. These pins should not be isolated from the main digital. Datasheet Networking Silicon — 82562ET 4.0 Voltage and Temperature Specifications 4.1 Absolute Maximum Ratings Maximum ratings are listed below: Case Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 135 C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to 150 C Supply Voltage with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.45 V Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 V to 3.45 V Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 3.45 V Stresses above the listed absolute maximum ratings may cause permanent damage to the 82562ET device. This is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4.2 Table 2. DC Characteristics General DC Specifications Symbol VCC Supply Voltage T Temperature Power Consumption P 4.2.1 Table 3. Parameter Condition Minimum/Maximum Case Temperature Min Typical Max Units 3.0 3.3 3.45 V 85 C 0 10/100Mbps (transmitter on) 300 mW Reduced Power 50 mW Auto-Negotiation 200 mW Notes X1 Clock DC Specifications X1 Clock DC Specifications Symbol Parameter VIL Input Low Voltage VIH Input High Voltage IILIH Input Leakage Currents CI Input Capacitance Condition Min Typical Max Units 0.8 V 2.0 0 < V IN < VCC Notes V ±10 µA 8 pF 1 NOTES: 1. This characteristic is only characterized, not tested. It is valid for digital pins only. Datasheet 9 82562ET — Networking Silicon 4.2.2 Table 4. LAN Connect Interface DC Specifications LAN Connect Interface DC Specifications Symbol Parameter Condition Min Typical Max Units VCCJ Input/Output Supply Voltage 3.0 3.45 V VIL Input Low Voltage -0.5 0.3VCCJ V V IH Input High Voltage 0.6VCCJ VCCJ + 0.5 V IIL Input Leakage Current 0 < VIN < VCCJ ±10 µA VOL Output Low Voltage IOUT = 1500 µA 0.1VCCJ V VOH Output High Voltage IOUT = -500 µA CIN Input Pin Capacitance 0.9VCCJ Notes V 8 pF 1 Max Units Notes 0.7 V NOTES: 1. This characteristic is only characterized, not tested. It is valid for digital pins only. 4.2.3 Table 5. LED DC Specifications LED DC Specifications Symbol 4.2.4 Table 6. Parameter Condition VOLLED Output Low Voltage IOUT = 10 mA VOHLED Output High Voltage IOUT = -10 mA Min Typical 2.4 V 10BASE-T Voltage and Current DC Specifications 10BASE-T Transmitter Symbol VOD10 Parameter Condition Output Differential RL = 100 Ω Peak Voltage Min 2.2 Typical Max Units Notes 2.8 V 1 NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3.3 V. 1. RL is the resistive load measured across the transmit differential pins, TDP and TDN. 10 Datasheet Networking Silicon — 82562ET Table 7. 10BASE-T Receiver Symbol Parameter Condition Min RID10 Input Differential Resistance DC 10 VIDA10 Input Differential Accept Peak Voltage 5 MHz ≤ f ≤ 10 MHz 585 VIDR10 Input Differential Reject Peak Voltage 5 MHz ≤ f ≤ 10 MHz VICM10 Input Common Mode Voltage Typical Max Units Notes KΩ 1 3100 mV 300 mV VCC/2 V NOTES: 1. The input differential resistance is measured across the receive differential pins, RDP and RDN. 4.2.5 Table 8. 100BASE-TX Voltage and Current DC Specifications 100BASE-TX Transmitter Symbol VOD100 Parameter Condition Output Differential RL = 100 Ω Peak Voltage Min Typical Max Units Notes 0.95 1.0 1.05 V 1 Units Notes KΩ 1 NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3.3 V. 1. RL is the resistive load measured across the transmit differential pins, TDP and TDN. Table 9. 100BASE-TX Receiver Symbol Parameter RID100 Input Differential Resistance VIDA100 Input Differential Accept Peak Voltage VIDR100 Input Differential Reject Peak Voltage VICM100 Input Common Mode Voltage Condition DC Min Typical Max 10 500 VCC/2 1200 mV 100 mV V NOTES: 1. The input differential resistance is measured across the receive differential pins, RDP and RDN. Datasheet 11 82562ET — Networking Silicon 12 Datasheet Networking Silicon — 82562ET 5.0 Package and Pinout Information 5.1 Package Information The 82562ET is a 48-pin Shrink Small Outlying Package (SSOP). The Package dimensions are shown in Figure 3. More information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Literature Center or your local sales office. Figure 3. Dimension Diagram for the 82562ET 48-pin SSOP Datasheet 13 82562ET — Networking Silicon 5.2 Pinout Information 5.2.1 82562ET Pin Assignments Table 10. 82562ET Pin Assignments 14 Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name 1 VCC 13 VSS 25 VCC 37 LAN_RXD2 2 VCCA 14 VCCT 26 TOUT 38 VSSP 3 VSSA 15 RDP 27 LILED 39 LAN_CLK 4 RBIAS10 16 RDN 28 ISOL_TI 40 VCCP 5 RBIAS100 17 VCCT 29 ISOL_TEX 41 ADV10 6 VSSA2 18 VSS 30 ISOL_TCK 42 LAN_RSTSYNC 7 VCCA2 19 VCCR 31 SPDLED 43 LAN_TXD0 8 VSS 20 VSSR 32 ACTLED 44 LAN_TXD1 9 VCCT 21 TESTEN 33 VSSP 45 LAN_TXD2 10 TDP 22 VSSR 34 LAN_RXD0 46 X1 11 TDN 23 VCCR 35 LAN_RXD1 47 X2 12 VCCT 24 VSS 36 VCCP 48 VSS Datasheet Networking Silicon — 82562ET 5.2.2 82562ET Shrink Small Outlying Package Diagram Figure 4. 82562ET Pin Out Diagram Datasheet VCC (DPS) 1 48 VSS (DPS) VCCA (APS) 2 47 X2 (O) VSSA (APS) 3 46 X1(I) RBIAS10 (B) 4 45 LAN_TXD2 (I) RBIAS100 (B) 5 44 LAN_TXD1 (I) VSSA2 (APS) 6 43 LAN_TXD0 (I) VCCA2 (APS) 7 42 LAN_RSTSYNC VSS (DPS) 8 41 ADV10 (I) VCCT (APS) 9 40 VCCP (DPS) TDP (MLT) 10 39 LAN_CLK (O) TDN (MLT) 11 38 VSSP (DPS) VCCT (APS) 12 37 LAN_RXD2 (O) VSS (DPS) 13 36 VCCP (DPS) VCCT (APS) 14 35 LAN_RXD1 (O) RDP (MLT) 15 34 LAN_RXD0 (O) RDN (MLT) 16 33 VSSP (DPS) VCCT (APS) 17 32 ACTLED# (O) 82562ET PIN DIAGRAM SSOP48 Rev 1.0 Top View VSS (DPS) 18 31 SPDLED# (O) VCCR (APS) 19 30 ISOL_TCK (I) VSSR (APS) 20 29 ISOL_TEX (I) TESTEN (I) 21 28 ISOL_TI (I) VSSR (APS) 22 27 LILED# (O) VCCR (APS) 23 26 TOUT (O) VSS (DPS) 24 25 VCC (DPS) 15