PRELIMINARY Integrated Circuit Systems, Inc. ICS844008I-15 FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS844008I-15 is an 8 output LVDS Synthesizer optimized to generate PCI Express HiPerClockS™ reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 25MHz parallel resonant crystal, the following frequencies can be generated based on F_SEL pin: 100MHz or 125MHz. The ICS844008I-15 uses ICS’ 3rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting PCI Express jitter requirements. The ICS844008I-15 is packaged in a 32-pin LQFP package. • Eight LVDS outputs ICS • Crystal oscillator interface • Supports the following output frequencies: 100MHz or 125MHz • VCO: 500MHz • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.42ps (typical) • Full 3.3V supply modes • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages PIN ASSIGNMENT V DDA nPLL_SEL VDD M/N Divider Value 5 Output Frequency (MHz) 12 5 Q0 1 24 Q7 1 20 5 4 100 nQ0 2 23 nQ7 VDD 3 22 VDD Q1 4 21 Q6 nQ1 5 20 nQ6 GND 6 19 GND Q2 7 18 Q5 nQ2 8 17 nQ5 Q0 Pulldown nQ0 MR nQ4 Q4 GND 0 ÷4 ÷5 VDD (w/25MHz Reference) 9 10 11 12 13 14 15 16 nQ3 Q2 VCO 500MHz 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Q3 OSC Phase Detector ICS844008I-15 F_SEL 25MHz 32 31 30 29 28 27 26 25 nQ1 1 XTAL_OUT OE2 N Divider Value 4 Q1 XTAL_IN GND F_SEL 0 M Divider Value 20 BLOCK DIAGRAM nPLL_SEL XTAL_IN 25MHz OE1 Input Input Frequency (MHz) 25MHz XTAL_OUT FREQUENCY SELECT FUNCTION TABLE nQ2 Q3 nQ3 Q4 M = ÷20 (fixed) OE1 nQ4 Pullup Q5 nQ5 Q6 nQ6 Q7 nQ7 MR Pulldown F_SEL OE2 Pullup Pullup The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 844008AYI-15 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 2, 2006 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS844008I-15 FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 3, 12, 22, 27 4, 5 6, 13, 19, 29 7, 8 Q0, nQ0 Output Type Differential output pair. LVDS interface levels. Description VDD Power Core supply pin. Q1, nQ1 Ouput Differential output pair. LVDS interface levels. GND Power Power supply ground. Q2, nQ2 Output 9 F_SEL Input 10, 11 Q3, nQ3 Output Differential output pair. LVDS interface levels. 14, 15 Q4, nQ4 Output 16 MR Input 17, 18 nQ5, Q5 Output Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. 20, 21 nQ6, Q6 Output Differential output pair. LVDS interface levels. 23, 24 nQ7, Q7 Output Differential output pair. LVDS interface levels. 25 VDDA Power Differential output pair. LVDS interface levels. Pullup Pulldown Frequency select pin LVCMOS/LVTTL interface levels. Analog supply pin. Selects between the PLL and REF_CLK as input to the dividers. When LOW, Pulldselects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL 26 nPLL_SEL Input own Bypass). LVCMOS/LVTTL interface levels. Output enable for Q5/nQ5:Q7/nQ7 outputs. 28 OE2 Input Pullup LVCMOS/LVTTL interface levels. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_OUT, 30, 31 Input XTAL_IN is the input. XTAL_IN Output enable for Q0/nQ0:Q4/nQ4 outputs. 32 OE1 Input Pullup LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input PullUP Resistor 51 kΩ TABLE 3A. OE1 FUNCTION TABLE Input OE1 TABLE 3B. OE2 FUNCTION TABLE Outputs Input Q0:Q4, nQ0:nQ4 OE2 Outputs Q5:Q7, nQ5:nQ7 0 Places outputs in Hi-Z state 0 Places outputs in Hi-Z state 1 Normal operation 1 Normal operation 844008AYI-15 www.icst.com/products/hiperclocks.html 2 REV. A FEBRUARY 2, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844008I-15 FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 122 mA IDDA Analog Supply Current 11 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol VIH Parameter Input High Voltage Test Conditions VDD = 3.3V VIL Input Low Voltage VDD = 3.3V IIH Input High Current MR, nPLL_SEL Input Low Current MR, nPLL_SEL VDD = 3.465V, VIN = 0V -5 µA OE1, OE2, F_SEL VDD = 3.465V, VIN = 0V -150 µA IIL Minimum Typical 2 -0.3 VDD = VIN = 3.465 OE1, OE2, F_SEL VDD = VIN = 3.465 Maximum VDD + 0.3 Units V 0.8 V 150 µA 5 µA TABLE 4C. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage 350 mV Δ VOD VOD Magnitude Change 40 mV VOS Offset Voltage Δ VOS VOS Magnitude Change 844008AYI-15 Test Conditions Minimum www.icst.com/products/hiperclocks.html 3 Typical Maximum Units 1.25 V 50 mV REV. A FEBRUARY 2, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844008I-15 FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Maximum Units 27.2 MH z Par ts per Million (ppm); NOTE 1 100 ppm Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Mode of Oscillation Typical Fundamental Frequency 22.4 25 Drive Level 100 NOTE: Characterized using an18pF parallel resonant crystal. NOTE 1: When used with recommended 50ppm crystal and external trim caps adjusted for user PC board. µW TABLE 6. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol fOUT Parameter Output Frequency t sk(o) Output Skew; NOTE 1, 2 t jit(cc) Cycle-to-Cycle Jitter t jit(Ø) RMS Phase Jitter (Random); NOTE 3 t R / tF Output Rise/Fall Time Test Conditions Minimum Typical Units 125 MHz FSEL = 1 100 MHz 125MHz, (1.875MHz - 20MHz) 100MHz, (1.875MHz - 20MHz) 20% to 80% 200 TBD 50 25 50 ps 0.42 1 ps 0.46 1 ps 330 650 ps 52 % odc Output Duty Cycle 48 50 Minimum and Maximum values are design target specs. NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDD/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. 844008AYI-15 Maximum FSEL = 0 www.icst.com/products/hiperclocks.html 4 ps REV. A FEBRUARY 2, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844008I-15 FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 125MHZ AT 3.3V ➤ 0 -10 -20 PCI Express Jitter Filter -30 125MHz RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.42ps (typical) -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ NOISE POWER dBc Hz -40 -50 -60 -120 -130 -140 -150 ➤ -160 -170 -180 Phase Noise Result by adding PCI Express Filter to raw data -190 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 844008AYI-15 www.icst.com/products/hiperclocks.html 5 REV. A FEBRUARY 2, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844008I-15 FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION Phase Noise Plot SCOPE Noise Power Qx 3.3V±5% POWER SUPPLY + Float GND - LVDS Phase Noise Mask nQx f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER nQx nQ0:nQ7 Qx Q0:nQ7 ➤ nQy Qy tcycle n ➤ 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT ➤ tcycle ➤ n+1 t jit(cc) = tcycle n –tcycle n+1 tsk(o) 1000 Cycles OUTPUT SKEW CYCLE-TO-CYCLE JITTER nQ0:nQ7 80% 80% Q0:Q7 VSW I N G t PW t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME VDD out ➤ DC Input LVDS 100 VOD/Δ VOD ➤ out out VOS/Δ VOS ➤ LVDS ➤ DC Input out ➤ VDD ➤ DIFFERENTIAL OUTPUT VOLTAGE SETUP OFFSET VOLTAGE SETUP 844008AYI-15 www.icst.com/products/hiperclocks.html 6 REV. A FEBRUARY 2, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844008I-15 FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844008I-15 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VDDA. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE Figure 2 below were determined using a 25MHz parallel resonant crystal and were chosen to minimize the ppm error. The ICS844008I-15 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p Figure 2. CRYSTAL INPUt INTERFACE 844008AYI-15 www.icst.com/products/hiperclocks.html 7 REV. A FEBRUARY 2, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844008I-15 FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVDS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. 3.3V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V LVDS + R1 100 - 100 Ohm Differential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION 844008AYI-15 www.icst.com/products/hiperclocks.html 8 REV. A FEBRUARY 2, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844008I-15 FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS844008I-15. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844008I-15 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (122mA + 11mA) = 460.85mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.461W * 42.1°C/W = 104.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 32-LEAD LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 844008AYI-15 www.icst.com/products/hiperclocks.html 9 REV. A FEBRUARY 2, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844008I-15 FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS844008I-15 is: TBD 844008AYI-15 www.icst.com/products/hiperclocks.html 10 REV. A FEBRUARY 2, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844008I-15 FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 9. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC 0.60 0.75 L 0.45 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 844008AYI-15 www.icst.com/products/hiperclocks.html 11 REV. A FEBRUARY 2, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS844008I-15 FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS844008AYI-15 ICS44008AI15 32 Lead LQFP tube -40°C to 85°C ICS844008AYI-15T ICS44008AI15 32 Lead LQFP 1000 tape & reel -40°C to 85°C ICS844008AYI-15LF TBD 32 Lead "Lead-Free" LQFP tube -40°C to 85°C ICS844008AYI-15LFT TBD 32 Lead "Lead-Free" LQFP 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844008AYI-15 www.icst.com/products/hiperclocks.html 12 REV. A FEBRUARY 2, 2006