ICS ICS8422004AGI

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8422004I is a 4 output LVHSTL Synthesizer
optimized to generate Fibre Channel reference
HiPerClockS™ clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 26.5625MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 156.25, 106.25MHz and
53.125MHz. The ICS8422004I uses ICS’ 3rd generation low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS8422004I is packaged in a small
24-pin TSSOP package.
• Four LVHSTL outputs (VOHmax = 1.2V)
ICS
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25, 106.25MHz, 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.59ps (typical)
• Power supply modes:
Core/Output
3.3V/1.8V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
FREQUENCY SELECT FUNCTION TABLE
Input
Frequency
(MHz)
Inputs
M Divider N Divider
Value
Value
24
3
F_SEL1 F_SEL0
M/N
Divider Value
8
Output
Frequency
(MHz)
26.5625
0
0
26.5625
0
1
24
4
6
159.375
26.5625
1
0
24
6
4
106.25
212.5
26.5625
1
1
24
12
2
53.125
26.04166
0
1
24
4
6
156.25
23.4375
0
0
24
3
8
187.5
nQ1
Q1
VDDO
Q0
nQ0
MR
nPLL_SEL
nc
VDDA
F_SEL0
VDD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
VDDO
Q3
nQ3
GND
nc
nXTAL_SEL
TEST_CLK
GND
XTAL_IN
XTAL_OUT
ICS8422004I
BLOCK DIAGRAM
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
Q0
2
F_SEL[1:0] Pulldown
nPLL_SEL Pulldown
TEST_CLK Pulldown
F_SEL[1:0]
0 0 ÷3
1
1
26.5625MHz
XTAL_IN
OSC
0
Phase
Detector
VCO
0
01
10
11
÷4
÷6
÷12
nQ0
Q1
nQ1
XTAL_OUT
nXTAL_SEL
Q2
Pulldown
nQ2
M = 24 (fixed)
MR
Q3
nQ3
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8422004AGI
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REV. B NOVEMBER 14, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2
nQ1, Q1
Output
Differential output pair. LVHSTL interface levels.
3, 22
VDDO
Power
Output supply pins.
4, 5
Q0, nQ0
Ouput
6
MR
Input
7
nPLL_SEL
Input
8, 18
nc
Unused
9
Power
15, 19
VDDA
F_SEL0,
F_SEL1
VDD
XTAL_OUT,
XTAL_IN
GND
Power
16
TEST_CLK
Input
17
nXTAL_SEL
Input
20, 21
nQ3, Q3
Output
23, 24
Q2, nQ2
Output
10, 12
11
13, 14
Type
Input
Power
Input
Description
Differential output pair. LVHSTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Power supply ground.
Pulldown LVCMOS/LVTTL clock input.
Selects between cr ystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
8422004AGI
Test Conditions
Minimum
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2
Typical
Maximum
Units
REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
70°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
VDD
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
1.6
1.8
2.0
V
IDD
Power Supply Current
90
mA
IDDA
Analog Supply Current
10
mA
IDDO
Output Supply Current
0
mA
No Load
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
VDD
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
2.375
2.5
2.625
V
Analog Supply Voltage
2.375
2.5
2.625
V
1.6
1.8
2.0
VDDO
Output Supply Voltage
IDD
Power Supply Current
80
mA
IDDA
Analog Supply Current
10
mA
IDDO
Output Supply Current
0
mA
No Load
V
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5% OR 2.5V±5%, VDDO = 1.8V±0.2V,
TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input
Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
8422004AGI
Test Conditions
VDD = 3.3V
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Minimum Typical
2
Maximum
VDD + 0.3
Units
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
150
µA
VDD = VIN = 3.465V
or 2.5V
VDD = 3.465V or 2.5V,
VIN = 0V
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3
-150
µA
REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
TABLE 3D. LVHSTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
1.0
1.2
V
VOL
Output Low Voltage; NOTE 1
0
0.4
V
VOX
Output Crossover Voltage; NOTE 2
40
60
%
0.6
1.1
V
Maximum
Units
1.2
V
60
%
Peak-to-Peak Output Voltage Swing
VSWING
NOTE 1: Outputs terminated with 50Ω to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Typical
TABLE 3E. LVHSTL DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
Typical
1.0
VOL
Output Low Voltage; NOTE 1
VOX
Output Crossover Voltage; NOTE 2
0.235
40
Peak-to-Peak Output Voltage Swing
VSWING
NOTE 1: Outputs terminated with 50Ω to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
V
0.9
V
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
28.33
MHz
Fundamental
Frequency
23.33
26.5625
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
8422004AGI
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4
REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 3
tjit(Ø)
t R / tF
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
Units
F_SEL[1:0] = 00
186.67
226.66
MHz
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.66
MHz
TBD
ps
212.5MHz, (637kHz - 10MHz)
0.59
ps
187.5MHz, (637kHz - 10MHz)
0.53
ps
159.375MHz, (637kHz - 10MHz)
0.56
ps
156.25MHz, (1.875MHz - 20MHz)
0.50
ps
106.25MHz, (1.875MHz - 20MHz)
0.56
ps
53.125MHz, (637kHz - 10MHz)
0.66
ps
20% to 80%
410
ps
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
%
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 3
tjit(Ø)
t R / tF
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
Typical
Units
226.66
MHz
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.66
MHz
TBD
ps
212.5MHz, (637kHz - 10MHz)
0.60
ps
187.5MHz, (637kHz - 10MHz)
0.72
ps
159.375MHz, (637kHz - 10MHz)
0.64
ps
156.25MHz, (1.875MHz - 20MHz)
0.50
ps
106.25MHz, (1.875MHz - 20MHz)
0.55
ps
53.125MHz, (637kHz - 10MHz)
0.68
ps
20% to 80%
380
ps
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8422004AGI
Maximum
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5
%
REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 212.5MHZ
0
➤
-10
-20
Fibre Channel Jitter Filter
-30
-40
-50
212.5MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.59ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-60
-120
-130
-140
➤
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
8422004AGI
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6
REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2.5V±5%
1.8V±0.2V
3.3V±5%
1.8V±0.2V
VDD,
VDDA VDDO
SCOPE
Qx
VDD,
VDDA VDDO
Qx
SCOPE
LVHSTL
LVHSTL
GND
GND
nQx
nQx
0V
0V
LVHSTL 3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
LVHSTL 2.5V/1.8V OUTPUT LOAD AC TEST CIRCUIT
nQx
80%
80%
Qx
VSW I N G
Clock
Outputs
nQy
20%
20%
Qy
tF
tR
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
Phase Noise Plot
nQ0, nQ1
Noise Power
Q0, Q1
t PW
t
Phase Noise Mask
odc =
f1
Offset Frequency
PERIOD
t PW
x 100%
t PERIOD
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
8422004AGI
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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7
REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8422004I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA.
3.3V or 2.5V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The ICS8422004I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
ICS8422004I
Figure 2. CRYSTAL INPUt INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resistor can be used.
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
OUTPUTS:
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the TEST_CLK to
ground.
8422004AGI
LVHSTL OUTPUT
All unused LVHSTL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
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8
REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8422004I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8422004I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 100mA = 346.5mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 32.8mW = 131.2mW
Total Power_MAX (3.465V, with all outputs switching) = 346.5mW + 131.2mW = 477.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.478W * 65°C/W = 99.85°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
24-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
8422004AGI
0
1
2.5
70°C/W
65°C/W
62°C/W
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9
REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 3.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 3. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
/R ) * (V
OH_MIN
Pd_L = (V
L
-V
DD_MAX
/R ) * (V
OL_MAX
L
DD_MAX
)
OH_MIN
-V
)
OL_MAX
Pd_H = (1V/50Ω) * (2V - 1V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
8422004AGI
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10
REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS8422004I is: 2951
8422004AGI
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REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
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Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
FOR
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
A
Maximum
24
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
8422004AGI
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REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I
FEMTOCLOCKS™LVCMOS/CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS8422004AGI
ICS8422004AGI
20 Lead TSSOP
tube
-40°C to 85°C
ICS8422004AGIT
ICS8422004AGI
20 Lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS8422004AGILF
TBD
20 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS8422004AGILFT
TBD
20 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
8422004AGI
www.icst.com/products/hiperclocks.html
13
REV. B NOVEMBER 14, 2005