TI SN10KHT5578

SN10KHT5578
OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE
SDZS014A – APRIL 1990 – REVISED JANUARY 1999
D
D
D
D
D
D
D
DW OR NT PACKAGE
(TOP VIEW)
10KH Compatible
TTL Clock and ECL Control Inputs
Noninverting Outputs
Flow-Through Architecture Optimizes PCB
Layout
Center Pin VCC, VEE, and GND Configurations
Minimize High-Speed Switching Noise
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
Package Options Include Plastic Small-Outline
(DW) Package and Standard Plastic (NT) DIPs
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
description
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
1D
2D
3D
4D
OE(ECL)
VCC
VEE
CLK(TTL)
5D
6D
7D
8D
This octal TTL-to-ECL translator is designed to
provide efficient translation between a TTL signal
environment and a 10KH ECL signal environment. This device is designed specifically to
improve the performance and density of
TTL-to-ECL CPU/bus-oriented functions such as
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The eight flip-flops of the ’5578 are edge-triggered D-type flip-flops. On the positive transition of the clock, the
Q outputs are set to the logic levels that were set up at the D inputs.
The output-control input OE does not affect the internal operations of the flip-flops. Old data can be retained
or new data can be entered while the outputs are off.
The SN10KHT5578 is characterized for operation from 0°C to 75°C.
FUNCTION TABLE
INPUTS
D
OUTPUT
(ECL)
Q
OE
CLK
L
↑
L
L
L
↑
H
H
L
L
X
Q0
H
X
X
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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• DALLAS, TEXAS 75265
1
SN10KHT5578
OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE
SDZS014A – APRIL 1990 – REVISED JANUARY 1999
logic symbol†
CLK
OE
1D
17
20
24
C1
TTL/ECL
EN
1D
TTL/ECL
1
1Q
23
2
22
3
21
4
16
9
15
10
7D
14
11
7Q
8D
13
12
8Q
2D
3D
4D
5D
6D
2Q
3Q
4Q
5Q
6Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
CLK
20
17
TTL/ECL
C1
1D
24
TTL/ECL
2D
3D
22
4D
1D
C1
1D
3
TTL/ECL
C1
4
TTL/ECL
TTL/ECL
6D
7D
8D
2
14
13
TTL/ECL
1D
TTL/ECL
1D
TTL/ECL
1D
C1
C1
POST OFFICE BOX 655303
3Q
4Q
9
5Q
1D
C1
15
2Q
1D
C1
16
5D
2
TTL/ECL
21
1Q
1D
C1
23
1
• DALLAS, TEXAS 75265
10
11
12
6Q
7Q
8Q
SN10KHT5578
OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE
SDZS014A – APRIL 1990 – REVISED JANUARY 1999
absolute maximum ratings over operating ambient temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Supply voltage range, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 8 V to 0 V
Input voltage range (TTL) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V
Input voltage range (ECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE to 0 V
Input current range (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA
Current out of any output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The TTL input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
MIN
NOM
MAX
VCC
VEE
TTL supply voltage
4.5
5
5.5
V
ECL supply voltage
– 4.94
– 5.2
– 5.46
V
VIH
TTL high-level input voltage
VIH
ECL high-level input voltage‡
VIL
TTL low-level input voltage
VIL
2
V
0°C
– 1170
– 840
mV
25°C
– 1130
– 810
mV
75°C
– 1070
– 735
mV
0.8
ECL low-level input voltage‡
UNIT
V
0°C
– 1950
– 1480
mV
25°C
– 1950
– 1480
mV
75°C
– 1950
– 1450
mV
IIK
TTL input clamp current
– 18
mA
TA
Operating ambient temperature (see Note 3)
0
75
°C
‡ The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only.
NOTE 3: Each 10KH-series circuit has been designed to meet the dc specifications shown in the electrical characteristics table after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board, and transverse airflow greater than
500 linear ft/min is maintained.
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• DALLAS, TEXAS 75265
3
SN10KHT5578
OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE
SDZS014A – APRIL 1990 – REVISED JANUARY 1999
electrical characteristics over recommended operating ambient temperature range (unless
otherwise noted)
PARAMETER
VIK
II
IIH
IIL
CLK and D inputs
TEST CONDITIONS
MIN
VCC = 4.5 V,
VCC = 5.5 V,
VEE = – 4.94 V,
VEE = – 5.46 V,
II = – 18 mA
VI = 7 V
CLK and D inputs
VCC = 5.5 V,
VCC = 5.5 V,
VEE = – 5.46 V,
VEE = – 5.46 V,
VI = 2.7 V
VI = – 840 mV
OE input
VCC = 5.5 V,
VCC = 5.5 V,
VEE = – 5.46 V,
VEE = – 5.46 V,
VI = – 810 mV
VI = – 735 mV
CLK and D inputs
VCC = 5.5 V,
VEE = – 5.46 V,
VI = 0.5 V
CLK and D inputs
OE input
VOH‡
VCC = 5.5 V,
VCC = 4.5 V,
VOL‡
VCC = 4.5 V,
ICCH
ICCL
VCC = 5.5 V,
VCC = 5.5 V,
VEE = – 5.46 V,
VEE = – 5.2 V ± 5%,
MAX
– 1.2
0.1
See Note 4
See Note 4
UNIT
V
mA
20
0°C
350
25°C
350
75°C
µA
350
– 0.5
VI = – 1950 mV
VEE = – 5.2 V ± 5%,
TYP†
0°C
0.5
25°C
0.5
75°C
0.5
µA
0°C
– 1020
– 840
25°C
– 980
– 810
75°C
– 920
– 735
0°C
– 1950
– 1630
25°C
– 1950
– 1630
75°C
– 1950
– 1600
VEE = – 5.46 V
VEE = – 5.46 V
mA
mV
mV
17.5
25
mA
15
22
mA
IEE
VCC = 5.5 V,
VEE = – 5.46 V
– 104
– 149
mA
Ci
VCC = 5 V,
VEE = – 5.2 V,
f = 10 MHz
4
pF
† All typical values are at VCC = 5 V, VEE = – 5.2 V, TA = 25°C.
‡ The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only.
NOTE 4: Outputs are terminated through a 50-Ω resistor to – 2 V.
timing requirements over recommended operating conditions
MIN
fclock
Clock frequency
tw
duration CLK
Pulse duration,
tsu
Setup time,
time data before CLK↑
th
Hold time
time, data after CLK↑
High
4
Low
4
High
1.5
Low
2.5
High
1
Low
1
MAX
UNIT
180
MHz
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating ambient
temperature (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tr
FROM
(INPUT)
MIN
TYP†
MAX
180
CLK
Q
OE
Q
tf
† All typical values are at VCC = 5 V, VEE = – 5.2 V, TA = 25°C.
4
TO
(OUTPUT)
POST OFFICE BOX 655303
UNIT
MHz
0.8
2.2
4
0.8
2.1
3.8
0.5
1.4
3.2
0.5
1.7
3.3
ns
ns
Y
1.5
ns
Y
1.5
ns
• DALLAS, TEXAS 75265
SN10KHT5578
OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE
SDZS014A – APRIL 1990 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
From Output Under Test
50 Ω
–2 V
OUTPUT LOAD CIRCUIT
3V
Timing
Input
3V
High-Level
Pulse
1.5 V
1.5 V
0V
0V
Data
Input
tw
th
tsu
3V
1.5 V
3V
1.5 V
Low-Level
Pulse
0V
SETUP AND HOLD TIMES
0V
tPLH
VOH
0V
tf
tr
80%
Output Enable 50%
(see Note B)
80%
50%
20%
20%
50%
VOL
VOH
50%
– 890 mV
– 1690 mV
tPHL
tPLH
tPHL
Out-of-Phase
Output
1.5 V
1.5 V
1.5 V
In–Phase
Output
1.5 V
PULSE DURATION
3V
Input
(see Note A)
1.5 V
VOH
ECL Output Waveform 1
(see Notes C and D)
50%
50%
VOL
TTL-INPUT PROPAGATION DELAY TIMES
VOL
ECL-OUTPUT PROPAGATION DELAY TIMES
NOTES: A. For TTL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr = 2.5 ns, tf = 2.5 ns.
B. For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr = 1.5 ns, tf = 1.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is high except when disabled by OE.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright  1998, Texas Instruments Incorporated