LINEAR LTC3112

LTC3115-1
40V, 2A Synchronous
Buck-Boost DC/DC
Converter
FEATURES
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DESCRIPTION
Wide VIN Range: 2.7V to 40V
Wide VOUT Range: 2.7V to 40V
1A Output Current for VIN ≥ 3.6V, VOUT = 5V
2A Output Current in Step-Down Operation
for VIN ≥ 6V
Programmable Frequency: 100kHz to 2MHz
Synchronizable Up to 2MHz with an External Clock
Up to 95% Efficiency
30µA No-Load Quiescent Current in Burst Mode®
Operation
Ultralow Noise Buck-Boost PWM
Internal Soft-Start
3µA Supply Current in Shutdown
Programmable Input Undervoltage Lockout
Small 4mm × 5mm × 0.75mm DFN Package
Thermally Enhanced 20-Lead TSSOP Package
The LTC®3115-1 is a high voltage monolithic synchronous
buck-boost DC/DC converter. Its wide 2.7V to 40V input and
output voltage ranges make it well suited to a wide variety
of automotive and industrial applications. A proprietary
low noise switching algorithm optimizes efficiency with
input voltages that are above, below or even equal to the
output voltage and ensures seamless transitions between
operational modes.
Programmable frequency PWM mode operation provides
low noise, high efficiency operation and the ability to synchronize switching to an external clock. Switching frequencies up to 2MHz are supported to allow use of small valued
inductors for miniaturization of the application circuit. Pin
selectable Burst Mode operation reduces standby current
and improves light load efficiency which combined with a
3µA shutdown current make the LTC3115-1 ideally suited for
battery-powered applications. Additional features include
output disconnect in shutdown, short-circuit protection
and internal soft-start. The LTC3115-1 is available in thermally enhanced 16-lead 4mm × 5mm × 0.75mm DFN and
20‑lead TSSOP packages.
APPLICATIONS
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24V/28V Industrial Applications
Automotive Power Systems
Telecom, Servers and Networking Equipment
FireWire Regulator
Multiple Power Source Supplies
L, LT, LTC, LTM, Burst Mode, LTspice, Linear Technology and the Linear logo are registered
trademarks and No RSENSE is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
6404251, 6166527 and others pending.
TYPICAL APPLICATION
Efficiency vs VIN
10µH
95
2.7V TO
40V
BST1 SW1
4.7µF
BURST PWM
OFF ON
PVIN
VIN
SW2 BST2
PVOUT
PWM/SYNC
VC
RUN
FB
60.4k
3300pF
PGND
1M
33pF
15k
PVCC
VCC
GND
5V
1A VIN > 3.6V
2A VIN ≥ 6V
47µF
LTC3115-1
RT
47.5k
ILOAD = 0.5A
0.1µF
249k
4.7µF
90
EFFICIENCY (%)
0.1µF
ILOAD = 1A
85
80
75
(OPTIONAL)
70
3115 TA01a
2
10
INPUT VOLTAGE (V)
40
31151 TA01b
31151f
1
LTC3115-1
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, PVIN, PVOUT......................................... –0.3V to 45V
VSW1
DC............................................ –0.3V to (PVIN + 0.3V)
Pulsed (<100ns).......................–1.5V to (PVIN + 1.5V)
VSW2
DC..........................................–0.3V to (PVOUT + 0.3V)
Pulsed (<100ns)..................... –1.5V to (PVOUT + 1.5V)
VRUN.............................................. –0.3V to (VIN + 0.3V)
VBST1......................................VSW1 – 0.3V to VSW1 + 6V
VBST2......................................VSW2 – 0.3V to VSW2 + 6V
Voltage, All Other Pins.................................. –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 4)
LTC3115E-1/LTC3115I-1...................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
FE...................................................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
RUN
1
16 PWM/SYNC
SW2
2
15 SW1
PVOUT
3
14 PVIN
GND
4
GND
5
VC
6
11 PVCC
FB
7
10 VIN
RT
8
9
PGND
17
13 BST1
12 BST2
VCC
PGND
1
20 PGND
RUN
2
19 PWM/SYNC
SW2
3
18 SW1
PVOUT
4
17 PVIN
GND
5
GND
6
VC
7
14 PVCC
FB
8
13 VIN
RT
9
12 VCC
21
PGND
PGND 10
DHD PACKAGE
16-LEAD (5mm × 4mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W, θJC = 4.3°C/W
EXPOSED PAD (PIN 17) IS PGND, MUST BE SOLDERED TO PCB
16 BST1
15 BST2
11 PGND
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED
TO PCB FOR RATED THERMAL PERFORMANCE
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3115EDHD-1#PBF
LTC3115EDHD-1#TRPBF
31151
16-Lead (5mm × 4mm) Plastic DFN
–40°C to 125°C
LTC3115IDHD-1#PBF
LTC3115IDHD-1#TRPBF
31151
16-Lead (5mm × 4mm) Plastic DFN
–40°C to 125°C
LTC3115EFE-1#PBF
LTC3115EFE-1#TRPBF
LTC3115FE-1
20-Lead Plastic TSSOP
–40°C to 125°C
LTC3115IFE-1#PBF
LTC3115IFE-1#TRPBF
LTC3115FE-1
20-Lead Plastic TSSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
31151f
2
LTC3115-1
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are for TA = 25°C (Note 2). VIN = 24V, VOUT = 5V, unless otherwise noted.
PARAMETER
Input Operating Voltage
Output Operating Voltage
Input Undervoltage Lockout Threshold
Input Undervoltage Lockout Hysteresis
VCC Undervoltage Lockout Threshold
VCC Undervoltage Lockout Hysteresis
Input Current in Shutdown
Input Quiescent Current in Burst Mode Operation
Oscillator Frequency
Oscillator Operating Frequency
PWM/SYNC Clock Input Frequency
PWM/SYNC Input Logic Threshold
Soft-Start Duration
Feedback Voltage
Feedback Voltage Line Regulation
Feedback Pin Input Current
RUN Pin Input Logic Threshold
RUN Pin Comparator Threshold
RUN Pin Hysteresis Current
RUN Pin Hysteresis Voltage
Inductor Current Limit
Reverse Inductor Current Limit
Burst Mode Inductor Current Limit
Maximum Duty Cycle
Minimum Duty Cycle
SW1, SW2 Minimum Low Time
N-Channel Switch Resistance
N-Channel Switch Leakage
PVCC/VCC External Forcing Voltage
VCC Regulation Voltage
VCC Load Regulation
VCC Line Regulation
VCC Current Limit
VCC Dropout Voltage
VCC Reverse Current
CONDITIONS
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l
VIN Falling
VIN Rising
VIN Rising (0°C to 125°C)
MIN
2.7
2.7
2.4
2.6
l
l
VCC Falling
l
VRUN = 0V
VFB = 1.1V (Not Switching)
RT = 35.7k
l
900
100
100
0.5
l
977
l
l
l
l
VIN = 2.7V to 40V
VRUN Rising
l
0.3
1.16
(Note 3)
Current into PVOUT (Note 3)
(Note 3)
Percentage of Period SW2 is Low in Boost Mode,
RT = 35.7k (Note 5)
Percentage of Period SW1 is High in Buck Mode,
RT = 35.7k (Note 5)
RT = 35.7k (Note 5)
Switch A (From PVIN to SW1)
Switch B (From SW1 to PGND)
Switch C (From SW2 to PGND)
Switch D (From PVOUT to SW2)
PVIN = PVOUT = 40V
l
2.4
l
0.65
90
IVCC = 1mA
IVCC = 1mA to 20mA
IVCC = 1mA, VIN = 5V to 40V
VCC = 2.5V
IVCC = 5mA, VIN = 2.7V
VCC = 5V, VIN = 3.6V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3115-1 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3115E-1 is guaranteed to meet specifications from 0°C to
85°C junction temperature. Specifications over the –40°C to 125°C operating
TYP
100
2.4
200
3
50
1000
1.0
9
1000
0.1
1
0.8
1.21
500
100
3.0
1.5
1.0
95
MAX
40
40
2.7
2.8
2.725
2.6
10
1100
2000
2000
1.5
1017
50
1.1
1.26
3.7
1.35
0
l
100
150
150
150
150
0.1
4.58
4.33
50
4.45
1.2
0.5
110
50
10
10
5.5
4.58
UNITS
V
V
V
V
V
mV
V
mV
µA
µA
kHz
kHz
kHz
V
ms
mV
%
nA
V
V
nA
mV
A
A
A
%
%
ns
mΩ
mΩ
mΩ
mΩ
µA
V
V
%
%
mA
mV
µA
junction temperature range are ensured by design, characterization and
correlation with statistical process controls. The LTC3115I-1 specifications
are guaranteed over the –40°C to 125°C operating junction temperature
range. The maximum ambient temperature is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal resistance and other environmental factors.
31151f
3
LTC3115-1
ELECTRICAL CHARACTERISTICS
The junction temperature (TJ in °C) is calculated from the ambient
temperature (TA in °C) and power dissipation (PD in Watts) according to
the following formula:
TJ = TA + (PD • θJA)
where θJA is the thermal impedance of the package.
Note 3: Current measurements are performed when the LTC3115-1 is
not switching. The current limit values measured in operation will be
somewhat higher due to the propagation delay of the comparators.
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 5: Switch timing measurements are made in an open-loop test
configuration. Timing in the application may vary somewhat from these
values due to differences in the switch pin voltage during the non-overlap
durations when switch pin voltage is influenced by the magnitude and
direction of the inductor current.
TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C unless otherwise specified)
PWM Mode Efficiency, VOUT = 5V,
fSW = 500kHz, Non-Bootstrapped
PWM Mode Efficiency,
VOUT = 12V, fSW = 500kHz
PWM Mode Efficiency,
VOUT = 24V, fSW = 500kHz
100
100
90
90
90
80
80
70
60
50
VIN = 3.6V
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
40
30
20
0.01
0.10
LOAD CURRENT (A)
EFFICIENCY (%)
EFFICIENCY (%)
80
EFFICIENCY (%)
100
70
60
50
30
0.01
1
0.1
LOAD CURRENT (A)
31151 G01
60
50
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
40
70
30
0.01
1
PWM Mode Efficiency,
VOUT = 12V, fSW = 1MHz
PWM Mode Efficiency,
VOUT = 24V, fSW = 1MHz
100
90
90
90
80
80
VIN = 3.6V
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
40
30
20
0.01
0.1
LOAD CURRENT (A)
1
31151 G04
EFFICIENCY (%)
EFFICIENCY (%)
50
EFFICIENCY (%)
100
80
70
60
50
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
40
30
0.01
0.1
LOAD CURRENT (A)
1
31151 G03
100
60
0.1
LOAD CURRENT (A)
31151 G02
PWM Mode Efficiency, VOUT = 5V,
fSW = 1MHz, Non-Bootstrapped
70
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 36V
40
1
31151 G05
70
60
50
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 36V
40
30
0.01
0.1
LOAD CURRENT (A)
1
31151 G06
31151f
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LTC3115-1
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Efficiency,
VOUT = 12V, L = 15µH
Burst Mode Efficiency,
VOUT = 24V, L = 15µH
90
95
90
85
90
85
80
85
75
70
65
60
VIN = 3.6V
VIN = 12V
VIN = 24V
VIN = 36V
55
50
0.1
1
10
LOAD CURRENT (mA)
80
80
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
Burst Mode Efficiency, VOUT = 5V,
L = 15µH, Non-Bootstrapped
75
70
65
55
50
0.1
100
1
10
LOAD CURRENT (mA)
INPUT CURRENT (µA)
250
200
150
100
50
fSW = 1MHz
45
1
10
LOAD CURRENT (mA)
31151 G09
2.5
L = 22µH
fSW = 500kHz
2.0
30
25
20
15
10
1.5
1.0
0.5
VOUT = 24V
VOUT = 12V
VOUT = 5V
5
10
INPUT VOLTAGE (V)
2
0
40
10
INPUT VOLTAGE (V)
2
0
40
2
40
10
INPUT VOLTAGE (V)
31151 G11
Maximum Load Current
vs VIN, PWM Mode
2.5
100
Maximum Load Current
vs VIN, PWM Mode
35
31151 G10
2.5
L = 15µH
fSW = 1MHz
Maximum Load Current
vs VIN, PWM Mode
31151 G12
Maximum Load Current
vs VIN, Burst Mode Operation
1000
L = 5.2µH
fSW = 2MHz
L = 22µH
LOAD CURRENT (A)
1.5
1.0
0.5
10
INPUT VOLTAGE (V)
1.5
1.0
100
0.5
VOUT = 24V
VOUT = 12V
VOUT = 5V
2
LOAD CURRENT (mA)
2.0
2.0
0
50
0.1
100
VOUT = 24V
VOUT = 12V
VOUT = 5V
40
50
0
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 36V
55
LOAD CURRENT (A)
VOUT = 24V
VOUT = 15V
VOUT = 5V
VOUT = 5V, BOOTSTRAPPED
300
65
PWM Mode No-Load Input
Current vs VIN
Burst Mode No-Load Input
Current vs VIN
350
70
31151 G08
INPUT CURRENT (mA)
400
75
60
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
60
31151 G07
LOAD CURRENT (A)
(TA = 25°C unless otherwise specified)
40
31151 G47
0
VOUT = 12V
VOUT = 5V
2
10
INPUT VOLTAGE (V)
40
31151 G48
10
VOUT = 32V
VOUT = 12V
VOUT = 5V
2
10
INPUT VOLTAGE (V)
40
31151 G13
31151f
5
LTC3115-1
TYPICAL PERFORMANCE CHARACTERISTICS
NON-BOOTSTRAPPED
75
70
16
30
14
25
VIN = 36V
VOUT = 24V
20
VIN = 12V
VOUT = 5V
15
10
0
1000
500
1500
SWITCHING FREQUENCY (kHz)
0
2000
8
4
2
0
500
1000
11.7
11.6
11.5
11.4
11.3
11.2
11.1
11.0
–50
0
50
100
TEMPERATURE (°C)
CHANGE IN VOLTAGE FROM ZERO LOAD (%)
VCC/PVCC CURRENT (mA)
11.8
150
0.5
0.4
0.3
0.2
0.1
0
–0.2
–0.4
–0.6
–0.8
–1.0
–50
0
50
100
TEMPERATURE (°C)
150
31151 G20
31151 G16
Output Voltage Line Regulation
0.5
0.4
0.3
0.2
0.1
0
0
2
1
0.5
1.5
LOAD CURRENT (A)
–0.5
0
10
40
20
30
INPUT VOLTAGE (V)
31151 G19
VCC Regulator Load Regulation
1.0
VCC Regulator Line Regulation
0.8
–0.5
CHANGE FROM VIN = 24V (%)
CHANGE IN VOLTAGE FROM ICC = 0mA (%)
0
5.5
–0.4
–0.4
–0.5
5
–0.3
–0.3
0
0.4
4.5
4
VCC (V)
–0.2
–0.2
VCC Voltage vs Temperature
0.2
3.5
31151 G18
1.0
0.6
3
–0.1
–0.1
31151 G17
0.8
0
2.5
2000
1500
SWITCHING FREQUENCY (kHz)
Output Voltage Load Regulation
VIN = 6V
VOUT = 5V
fSW = 1MHz
11.9
fSW = 500kHz
6
31151 G15
Combined VCC/PVCC Supply
Current vs Temperature
12.0
fSW = 1MHz
10
5
31151 G14
CHANGE FROM 25°C (%)
12
VCC/PVCC CURRENT (mA)
80
35
CHANGE IN OUTPUT VOLTAGE FROM VIN = 20V (%)
EFFICIENCY (%)
85
VCC/PVCC CURRENT (mA)
BOOTSTRAPPED
90
PWM MODE
L = 47µH
VIN = 24V
VOUT = 5V
ILOAD = 0.5A
Combined VCC/PVCC Supply
Current vs VCC
Combined VCC/PVCC Supply
Current vs Switching Frequency
Efficiency vs Switching Frequency
95
(TA = 25°C unless otherwise specified)
–1.0
0.6
0.4
0.2
0
–0.2
–1.5
–0.4
–0.6
–2.0
–0.8
–2.5
0
10
30
20
ICC (mA)
40
50
31151 G21
–1.0
0
10
20
30
INPUT VOLTAGE (V)
40
31151 G22
31151f
6
LTC3115-1
TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C unless otherwise specified)
VCC Regulator Dropout Voltage
vs Temperature
0.25
1.0
VIN = 4V
IVCC = 20mA
2.0
0.8
1.5
CHANGE FROM 25°C (%)
0.15
0.10
0.05
1.0
CHANGE FROM 25°C (%)
0.6
0.20
DROPOUT VOLTAGE (V)
RUN Pin Hysteresis Current
vs Temperature
RUN Pin Threshold
vs Temperature
0.4
0.2
0
–0.2
–0.4
0.5
0
–0.5
–1.0
–0.6
–1.5
–0.8
0
–50
0
50
100
TEMPERATURE (°C)
–1.0
–50
150
0
–2.0
–50
150
50
100
TEMPERATURE (°C)
2.0
10000
Oscillator Frequency vs VIN
2.0
fSW = 1MHz
1.0
0.5
0
–0.5
–1.0
0
50
5
4
3
2
1
0
40
31151 G29
10
VIN (V)
300
VRUN = 0V
2.5
2.0
1.5
1.0
0.5
0
0
10
40
Power Switch Resistance
vs Temperature
POWER SWITCH (A-D) RESISTANCE (mΩ)
COMBINED VIN/PVIN CURRENT (µA)
CURRENT INTO RUN PIN (µA)
6
2
31151 G28
Shutdown Current on VIN/PVIN
vs Input Voltage
3.0
20
10
30
RUN PIN VOLTAGE (V)
–2.0
150
100
TEMPERATURE (°C)
31151 G27
VIN = 40V
0
0
–1.5
–2.0
–50
RUN Pin Current
vs RUN Pin Voltage
–1
0.5
–1.0
31151 G26
7
1.0
–0.5
–1.5
1000
fSW = 1MHz
1.5
CHANGE FROM VIN = 24V (%)
CHANGE FROM 25°C (%)
SWITCHING FREQUENCY (kHz)
1.5
100
RT (kΩ)
150
31151 G25
Oscillator Frequency
vs Temperature
Oscillator Frequency vs RT
100
10
50
100
TEMPERATURE (°C)
31151 G24
31151 G23
1000
0
20
30
INPUT VOLTAGE (V)
40
31151 G30
250
200
150
100
50
0
–50
0
50
100
TEMPERATURE (°C)
150
31151 G31
31151f
7
LTC3115-1
TYPICAL PERFORMANCE CHARACTERISTICS
Power Switch Resistance
vs VCC
165
1.0
5
0.8
4
3
160
155
150
0.4
0.2
0
–0.2
–0.4
–0.6
145
2.5
3.5
3
4
VCC (V)
4.5
5
5.5
CHANGE FROM 25°C (%)
0.6
CHANGE FROM 25°C (%)
POWER SWITCH (A-D) RESISTANCE (mΩ)
Inductor Current Limit Thresholds
vs Temperature
FB Voltage vs Temperature
170
140
(TA = 25°C unless otherwise specified)
0
150
50
100
TEMPERATURE (°C)
98
96
94
SW1, SW2 Minimum Low Time
vs Switching Frequency
SW1, SW2 Minimum Low Time
vs VCC
200
180
fSW = 300kHz
140
120
fSW = 1MHz
100
fSW = 2MHz
80
50
100
TEMPERATURE (°C)
60
150
2.5
3.5
3
4
VCC (V)
4.5
MAXIMUM DUTY CYCLE (%)
95
94
93
92
91
1000
500
1500
SWITCHING FREQUENCY (kHz)
2000
31151 G38
VCC = 2.7V
120
100
VCC = 4.4V
60
5.5
0
500
1000
1500
SWITCHING FREQUENCY (kHz)
60
Die Temperature Rise vs Load
Current, VOUT = 5V, fSW = 1.5MHz
VIN = 36V
VIN = 24V
VIN = 12V
VIN = 6V
VIN = 3.6V
50
40
30
20
10
0
STANDARD DEMO PCB
L = 15µH MSS1048
0
0.5
1
1.5
LOAD CURRENT (A)
2000
31151 G37
Die Temperature Rise vs Load
Current, VOUT = 5V, fSW = 750kHz
DIE TEMPERATURE CHANGE FROM AMBIENT (°C)
SW2 Maximum Duty Cycle
vs Switching Frequency
0
140
31151 G36
31151 G35
90
5
2
31151 G49
DIE TEMPERATURE CHANGE FROM AMBIENT (°C)
0
160
80
92
90
–50
150
50
100
TEMPERATURE (°C)
31151 G34
MINIMUM LOW TIME (ns)
MINIMUM LOW TIME (ns)
MINIMUM LOW TIME (ns)
100
0
31151 G33
160
104
SWB
CURRENT
LIMIT
–3
–4
180
102
–2
–5
–50
fSW = 1MHz
NO LOAD
106
0
–1
–0.8
SW1, SW2 Minimum Low Time
vs Temperature
108
1
–1.0
–50
31151 G32
110
SWA
CURRENT
LIMIT
2
100
VIN = 36V
VIN = 24V
VIN = 12V
VIN = 6V
VIN = 3.6V
90
80
70
60
50
40
30
20
STANDARD DEMO PCB
L = 15µH MSS1048
10
0
0
0.5
1
1.5
LOAD CURRENT (A)
2
31151 G50
31151f
8
LTC3115-1
TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C unless otherwise specified)
DIE TEMPERATURE CHANGE FROM AMBIENT (°C)
Die Temperature Rise vs Load
Current, VOUT = 12V, fSW = 750kHz
80
VIN = 36V
VIN = 24V
VIN = 12V
VIN = 6V
70
60
Load Transient (0A to 1A),
VIN = 24V, VOUT = 5V
VOUT
(200mV/DIV)
VOUT
(200mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
INDUCTOR
CURRENT
(2A/DIV)
40
30
FRONT PAGE
APPLICATION
20
0
LOAD
CURRENT
(1A/DIV)
LOAD
CURRENT
(1A/DIV)
50
10
Load Transient (0A to 1A),
VIN = 3.6V, VOUT = 5V
200µs/DIV
31151 G39
FRONT PAGE
APPLICATION
200µs/DIV
31151 G40
STANDARD DEMO PCB
L = 15µH MSS1048
0
0.5
1
1.5
LOAD CURRENT (A)
2
31151 G51
Output Voltage Ripple in
Burst Mode Operation,
VIN = 24V, VOUT = 5V
Output Voltage Ripple in PWM
Mode, VIN = 24V, VOUT = 5V
Soft-Start Waveforms
VRUN
(5V/DIV)
VOUT
(50mV/DIV)
INDUCTOR
CURRENT
(100mA/DIV)
VCC
(2V/DIV)
INDUCTOR
CURRENT
(0.5A/DIV)
L = 15µH
COUT = 22µF
ILOAD = 25mA
20µs/DIV
31151 G41
VOUT
(2V/DIV)
INDUCTOR
CURRENT
(1A/DIV)
VOUT
(5mV/DIV)
FRONT PAGE
APPLICATION
Burst Mode Operation to PWM
Mode Output Voltage Transient
VPWM/SYNC
(5V/DIV)
VOUT
(200mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
FRONT PAGE
APPLICATION
500µs/DIV
31151 G44
2ms/DIV
31151 G42
L = 22µH
COUT = 22µF
ILOAD = 2A
fSW = 750kHz
VPWM/SYNC
(5V/DIV)
VPWM/SYNC
(5V/DIV)
VOUT
(200mV/DIV)
VOUT
(200mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
INDUCTOR
CURRENT
(1A/DIV)
50µs/DIV
31151 G45
31151 G43
Phase-Locked Loop Release,
VIN = 24V, 1.2MHz Clock
Phase-Locked Loop Acquisition,
VIN = 24V 1.2MHz Clock
FRONT PAGE
APPLICATION
1µs/DIV
FRONT PAGE
APPLICATION
50µs/DIV
31151 G46
31151f
9
LTC3115-1
PIN FUNCTIONS
(DHD/FE)
RUN (Pin 1/Pin 2): Input to Enable and Disable the IC and
Set Custom Input UVLO Thresholds. The RUN pin can be
driven by an external logic signal to enable and disable
the IC. In addition, the voltage on this pin can be set by
a resistor divider connected to the input voltage in order
to provide an accurate undervoltage lockout threshold.
The IC is enabled if RUN exceeds 1.21V nominally. Once
enabled, a 0.5µA current is sourced by the RUN pin to
provide hysteresis. To continuously enable the IC, this pin
can be tied directly to the input voltage. The RUN pin cannot
be forced more than 0.3V above VIN under any condition.
SW2 (Pin 2/Pin 3): Buck-Boost Converter Power Switch
Pin. This pin should be connected to one side of the buckboost inductor.
PVOUT (Pin 3/Pin 4): Buck-Boost Converter Power Output.
This pin should be connected to a low ESR capacitor with
a value of at least 10µF. The capacitor should be placed as
close to the IC as possible and should have a short return
path to ground. In applications with VOUT > 20V that are
subject to output overload or short-circuit conditions, it
is recommended that a Schottky diode be installed from
SW2 (anode) to PVOUT (cathode). In applications subject
to output short circuits through an inductive load, it is recommended that a Schottky diode be installed from ground
(anode) to PVOUT (cathode) to limit the extent that PVOUT
is driven below ground during the short-circuit transient.
GND (Pins 4, 5/Pins 5, 6): Signal Ground. These pins are
the ground connections for the control circuitry of the IC
and must be tied to ground in the application.
VC (Pin 6/Pin 7): Error Amplifier Output. A frequency
compensation network must be connected between this
pin and FB to stabilize the voltage control loop.
FB (Pin 7/Pin 8): Feedback Voltage Input. A resistor divider
connected to this pin sets the output voltage for the buckboost converter. The nominal FB voltage is 1000mV. Care
should be taken in the routing of connections to this pin in
order to minimize stray coupling to the switch pin traces.
RT (Pin 8/Pin 9): Oscillator Frequency Programming Pin.
A resistor placed between this pin and ground sets the
switching frequency of the buck-boost converter.
VCC (Pin 9/Pin 12): Low Voltage Supply Input for IC Control Circuitry. This pin powers internal IC control circuitry
and must be connected to the PVCC pin in the application.
A 4.7µF or larger bypass capacitor should be connected
between this pin and ground. The VCC and PVCC pins must
be connected together in the application.
VIN (Pin 10/Pin 13): Power Supply Connection for Internal
Circuitry and the VCC Regulator. This pin provides power
to the internal VCC regulator and is the input voltage sense
connection for the VIN divider. A 0.1µF bypass capacitor
should be connected between this pin and ground. The
bypass capacitor should be located as close to the IC as
possible and should have a short return path to ground.
PVCC (Pin 11/Pin 14): Internal VCC Regulator Output. This
pin is the output pin of the internal linear regulator that
generates the VCC rail from VIN. The PVCC pin is also the
supply connection for the power switch gate drivers. If
the trace connecting PVCC to VCC cannot be made short in
length, an additional bypass capacitor should be connected
between this pin and ground. The VCC and PVCC pins must
be connected together in the application.
BST2 (Pin 12/Pin 15): Flying Capacitor Pin for SW2. This pin
must be connected to SW2 through a 0.1µF capacitor. This
pin is used to generate the gate drive rail for power switch D.
BST1 (Pin 13/Pin 16): Flying Capacitor Pin for SW1. This pin
must be connected to SW1 through a 0.1µF capacitor. This
pin is used to generate the gate drive rail for power switch A.
PVIN (Pin 14/Pin 17): Power Input for the Buck-Boost
Converter. A 4.7µF or larger bypass capacitor should
be connected between this pin and ground. The bypass
capacitor should be located as close to the IC as possible
and should via directly down to the ground plane. When
powered through long leads or from a high ESR power
source, a larger bulk input capacitor (typically 47µF to
100µF) may be required.
SW1 (Pin 15/Pin 18): Buck-Boost Converter Power Switch
Pin. This pin should be connected to one side of the buckboost inductor.
31151f
10
LTC3115-1
PIN FUNCTIONS
(DHD/FE)
PWM/SYNC (Pin 16/Pin 19): Burst Mode/PWM Mode
Control Pin and Synchronization Input. Forcing this pin
high causes the IC to operate in fixed frequency PWM mode
at all loads using the internal oscillator at the frequency
set by the RT Pin. Forcing this pin low places the IC into
Burst Mode operation for improved efficiency at light load
and reduced standby current. If an external clock signal
is connected to this pin, the buck-boost converter will
synchronize its switching with the external clock using
fixed frequency PWM mode operation. The pulse width
(negative or positive) of the applied clock should be at
least 100ns.
BLOCK DIAGRAM
PGND (Exposed Pad Pin 17/Pins 1, 10, 11, 20, Exposed Pad Pin 21): Power Ground Connections. These
pins should be connected to the power ground in the
application. The exposed pad in the DHD package is the
power ground connection. It must be soldered to the
PCB and electrically connected to ground through the
shortest and lowest impedance connection possible. For
optimal thermal performance, the exposed pad should
be connected to the PCB ground plane in both the DHD
and FE packages.
Pin numbers are shown for the DHD package only.
14
15
2
3
SW2
SW1
PVIN
A
10
PVOUT
D
B
3A
–1.5A
+
–
0A
+
–
C
PGND
PGND
VIN
CURRENT
LIMIT
+
–
REVERSE
CURRENT
LIMIT
REVERSE
BLOCKING
LDO
PVCC*
ZERO
CURRENT
GATE
DRIVES
BST2
BST1
1.21V
1000mV
6
7
VC
VIN
FB
1000mV
SOFT-START
RAMP
–
+
+
÷
11
VCC
BANDGAP
REFERENCE
PWM
13
VCC*
+
–
INPUT UVLO
12
9
VIN
2.4V
VIN
0.5µA
8
16
RT
OSCILLATOR
PWM/SYNC
MODE
SELECTION
BURST/PWM
(PWM MODE IF PWM/SYNC
IS HIGH OR SWITCHING)
+
–
CHIP
ENABLE
UVLO
GND
GND
5
4
EXPOSED
PAD
*PVCC AND VCC MUST BE CONNECTED TOGETHER IN THE APPLICATION
THE EXPOSED PAD IS AN ELECTRICAL CONNECTION AND MUST BE SOLDERED
TO THE BOARD AND ELECTRICALLY CONNECTED TO GROUND
17
+
–
RUN
1
1.21V
VCC
2.4V
OVERTEMPERATURE
PGND
3115 BD
31151f
11
LTC3115-1
OPERATION
INTRODUCTION
The LTC3115-1 is a monolithic buck-boost converter that
can operate with input and output voltages from as low
as 2.7V to as high as 40V. Four internal low resistance Nchannel DMOS switches minimize the size of the application
circuit and reduce power losses to maximize efficiency.
Internal high side gate drivers, which require only the
addition of two small external capacitors, further simplify
the design process. A proprietary switch control algorithm
allows the buck-boost converter to maintain output voltage regulation with input voltages that are above, below
or equal to the output voltage. Transitions between these
operating modes are seamless and free of transients and
subharmonic switching. The LTC3115-1 can be configured
to operate over a wide range of switching frequencies, from
100kHz to 2MHz, allowing applications to be optimized for
board area and efficiency. With its configurability and wide
operating voltage range, the LTC3115-1 is ideally suited to
a wide range of power systems especially those requiring
compatibility with a variety of input power sources such
as lead-acid batteries, USB ports, and industrial supply
rails as well as from power sources which have wide or
poorly controlled voltage ranges such as FireWire and
unregulated wall adapters.
The LTC3115-1 has an internal fixed-frequency oscillator
with a switching frequency that is easily set by a single
external resistor. In noise sensitive applications, the converter can also be synchronized to an external clock via
the PWM/SYNC pin. The LTC3115-1 has been optimized
to reduce input current in shutdown and standby for applications which are sensitive to quiescent current draw,
such as battery-powered devices. In Burst Mode operation, the no-load standby current is only 50µA (typical)
and in shutdown the total supply current is reduced to
3µA (typical).
switching spectrum. A proprietary switching algorithm
provides seamless transitions between operating modes
and eliminates discontinuities in the average inductor current, inductor current ripple, and loop transfer function
throughout all regions of operation. These advantages
result in increased efficiency, improved loop stability, and
lower output voltage ripple in comparison to the traditional
4-switch buck-boost converter.
Figure 1 shows the topology of the LTC3115-1 power stage
which is comprised of four N-channel DMOS switches and
their associated gate drivers. In PWM mode operation both
switch pins transition on every cycle independent of the
input and output voltage. In response to the error amplifier output, an internal pulse width modulator generates
the appropriate switch duty cycles to maintain regulation
of the output voltage.
When stepping down from a high input voltage to a lower
output voltage, the converter operates in buck mode and
switch D remains on for the entire switching cycle except
for the minimum switch low duration (typically 100ns).
During the switch low duration switch C is turned on which
forces SW2 low and charges the flying capacitor, CBST2, to
ensure that the voltage of the switch D gate driver supply
rail is maintained. The duty cycle of switches A and B are
adjusted to provide the appropriate buck mode duty cycle.
If the input voltage is lower than the output voltage, the
converter operates in boost mode. Switch A remains on
for the entire switching cycle except for the minimum
switch low duration (typically 100ns) while switches C
and D are modulated to maintain the required boost mode
CBST1
BST1
PVIN
SW1
SW2 PVOUT
BST2
PVCC
PVCC
PWM MODE OPERATION
With the PWM/SYNC pin forced high or driven by an external clock, the LTC3115-1 operates in a fixed-frequency
pulse width modulation (PWM) mode using a voltage mode
control loop. This mode of operation maximizes the output
current that can be delivered by the converter, reduces
output voltage ripple, and yields a low noise fixed-frequency
CBST2
L
A
D
LTC3115-1
PVCC
B
PGND
PVCC
C
PGND
31151 F01
Figure 1. Power Stage Schematic
31151f
12
LTC3115-1
OPERATION
duty cycle. The minimum switch low duration ensures that
flying capacitor CBST1 is charged sufficiently to maintain
the voltage on the BST1 rail.
Oscillator and Phase-Locked Loop
The LTC3115-1 operates from an internal oscillator with a
switching frequency that is configured by a single external
resistor between the RT pin and ground. For noise sensitive applications, an internal phase-locked loop allows
the LTC3115-1 to be synchronized to an external clock
signal applied to the PWM/SYNC pin. The phase-locked
loop is only able to increase the frequency of the internal
oscillator to obtain synchronization. Therefore, the RT
resistor must be chosen to program the internal oscillator to a lower frequency than the frequency of the clock
applied to the PWM/SYNC pin. Sufficient margin must
be included to account for the frequency variation of the
external synchronization clock as well as the worst-case
variation in frequency of the internal oscillator. Whether
operating from its internal oscillator or synchronized to an
external clock signal, the LTC3115-1 is able to operate with
a switching frequency from 100kHz to 2MHz, providing
the ability to minimize the size of the external components
and optimize the power conversion efficiency.
Error Amplifier and VIN Divider
The LTC3115-1 has an internal high gain operational
amplifier which provides frequency compensation of the
control loop that maintains output voltage regulation. To
ensure stability of this control loop, an external compensation network must be installed in the application circuit.
A Type III compensation network as shown in Figure 2 is
recommended for most applications since it provides the
flexibility to optimize the converter’s transient response
while simultaneously minimizing any DC error in the
output voltage.
As shown in Figure 2, the error amplifier is followed by
an internal analog divider which adjusts the loop gain by
the reciprocal of the input voltage in order to minimize
loop-gain variation over changes in the input voltage.
This simplifies design of the compensation network and
optimizes the transient response over the entire range of
input voltages. Details on designing the compensation
VOUT
LTC3115-1
RFF
RTOP
CFF 1000mV
FB
VIN
+
–
÷
RBOT
PWM
VC
CFB
RFB
31151 F02
CPOLE
Figure 2. Error Amplifier and Compensation Network
network in LTC3115-1 applications can be found in the
Applications Information section of this data sheet.
Inductor Current Limits
The LTC3115-1 has two current limit circuits that are
designed to limit the peak inductor current to ensure that
the switch currents remain within the capabilities of the
IC during output short-circuit or overload conditions.
The primary inductor current limit operates by injecting
a current into the feedback pin which is proportional to
the extent that the inductor current exceeds the current
limit threshold (typically 3A). Due to the high gain of
the feedback loop, this injected current forces the error
amplifier output to decrease until the average current
through the inductor is approximately reduced to the
current limit threshold. This current limit circuit maintains
the error amplifier in an active state to ensure a smooth
recovery and minimal overshoot once the current limit
fault condition is removed. However, the reaction speed
of this current limit circuit is limited by the dynamics of
the error amplifier. On a hard output short, it is possible
for the inductor current to increase substantially beyond
the current limit threshold before the average current limit
has time to react and reduce the inductor current. For this
reason, there is a second current limit circuit which turns
off power switch A if the current through switch A exceeds
approximately 160% of the primary inductor current limit
threshold. This provides additional protection in the case of
an instantaneous hard output short and provides time for
the primary current limit to react. In addition, if VOUT falls
below 1.85V, the inductor current limit is folded back to half
its nominal value in order to minimize power dissipation.
31151f
13
LTC3115-1
OPERATION
Reverse Current Limit
Burst Mode OPERATION
In PWM mode operation, the LTC3115-1 synchronously
switches all four power devices. As a result, in addition to
being able to supply current to the output, the converter
has the ability to actively conduct current away from the
output if that is necessary to maintain regulation. If the
output is held above regulation, this could result in large
reverse currents. This situation can occur if the output of
the LTC3115-1 is held up momentarily by another supply
as may occur during a power-up or power-down sequence.
To prevent damage to the part under such conditions, the
LTC3115-1 has a reverse current comparator that monitors
the current entering power switch D from the load. If this
current exceeds 1.5A (typical) switch D is turned off for
the remainder of the switching cycle in order to prevent the
reverse inductor current from reaching unsafe levels.
When the PWM/SYNC pin is held low, the buck-boost
converter employs Burst Mode operation using a variable frequency switching algorithm that minimizes the
no-load input quiescent current and improves efficiency
at light load by reducing the amount of switching to the
minimum level required to support the load. The output
current capability in Burst Mode operation is substantially
lower than in PWM mode and is intended to support light
standby loads (typically under 50mA). Curves showing
the maximum Burst Mode load current as a function of
the input and output voltage can be found in the Typical
Characteristics section of this data sheet. If the converter
load in Burst Mode operation exceeds the maximum Burst
Mode current capability, the output will lose regulation.
Output Current Capability
The maximum output current that can be delivered by the
LTC3115-1 is dependent upon many factors, the most
significant being the input and output voltages. For VOUT
= 5V and VIN ≥ 3.6V, the LTC3115-1 is able to support up
to a 1A load continuously. For VOUT = 12V and VIN ≥ 12V,
the LTC3115-1 is able to support up to a 2A load continuously. Typically, the output current capability is greatest
when the input voltage is approximately equal to the output
voltage. At larger step-up voltage ratios, the output current capability is reduced because the lower duty cycle of
switch D results in a larger inductor current being needed
to support a given load. Additionally, the output current
capability generally decreases at large step-down voltage
ratios due to higher inductor current ripple which reduces
the maximum attainable inductor current.
The output current capability can also be affected by
inductor characteristics. An inductor with large DC resistance will degrade output current capability, particularly
in boost mode operation. Larger value inductors generally
maximize output current capability by reducing inductor
current ripple. In addition, higher switching frequencies
(especially above 750kHz) will reduce the maximum output
current that can be supplied (see the Typical Performance
Characteristics for details).
Each Burst Mode cycle is initiated when switches A and
C turn on producing a linearly increasing current through
the inductor. When the inductor current reaches the Burst
Mode current limit (1A typically) switches B and D are
turned on, discharging the energy stored in the inductor
into the output capacitor and load. Once the inductor
current reaches zero, all switches are turned off and the
cycle is complete. Current pulses generated in this manner
are repeated as often as necessary to maintain regulation
of the output voltage. In Burst Mode operation, the error
amplifier is not used but is instead placed in a low current
standby mode to reduce supply current and improve light
load efficiency.
SOFT-START
To minimize input current transients on power-up, the
LTC3115-1 incorporates an internal soft-start circuit with
a nominal duration of 9ms. The soft-start is implemented
by a linearly increasing ramp of the error amplifier reference voltage during the soft-start duration. As a result,
the duration of the soft-start period is largely unaffected
by the size of the output capacitor or the output regulation voltage. Given the closed-loop nature of the soft-start
implementation, the converter is able to respond to load
transients that occur during the soft-start interval. The
soft-start period is reset by thermal shutdown and UVLO
events on both VIN and VCC.
31151f
14
LTC3115-1
OPERATION
VCC REGULATOR
An internal low dropout regulator generates the 4.45V
(nominal) VCC rail from VIN. The VCC rail powers the internal control circuitry and power device gate drivers of
the LTC3115-1. The VCC regulator is disabled in shutdown
to reduce quiescent current and is enabled by forcing the
RUN pin above its logic threshold. The VCC regulator includes current limit protection to safeguard against short
circuiting of the VCC rail. For applications where the output
voltage is set to 5V, the VCC rail can be driven from the
output rail through a Schottky diode. Bootstrapping in this
manner can provide a significant efficiency improvement,
particularly at large voltage step down ratios, and may
also allow operation down to a lower input voltage. The
maximum operating voltage for the VCC pin is 5.5V. When
forcing VCC externally, care must be taken to ensure that
this limit is not exceeded.
UNDERVOLTAGE LOCKOUT
To eliminate erratic behavior when the input voltage is
too low to ensure proper operation, the LTC3115-1 incorporates internal undervoltage lockout (UVLO) circuitry.
There are two UVLO comparators, one that monitors VIN
and another that monitors VCC. The buck-boost converter
is disabled if either VIN or VCC falls below its respective
UVLO threshold. The input voltage UVLO comparator has
a falling threshold of 2.4V (typical). If the input voltage
falls below this level all switching is disabled until the input
voltage rises above 2.6V (nominal). The VCC UVLO has a
falling threshold of 2.4V. If VCC falls below this threshold
the buck-boost converter is prevented from switching until
VCC rises above 2.6V.
Depending on the particular application circuit it is possible that either of these UVLO thresholds could be the
factor limiting the minimum input operating voltage of the
LTC3115-1. The dominant factor depends on the voltage
drop between VIN and VCC which is determined by the
dropout voltage of the VCC regulator and is proportional
to the total load current drawn from VCC. The load current on the VCC regulator is principally generated by the
gate driver supply currents which are proportional to
operating frequency and generally increase with larger
input and output voltages. As a result, at higher switching
frequencies and higher input and output voltages the
VCC regulator dropout voltage will increase, making it
more likely that the VCC UVLO threshold could become
the limiting factor. Curves provided in the Typical Performance Characteristics section of this data sheet show the
typical VCC current and can be used to estimate the VCC
regulator dropout voltage in a particular application. In
applications where VCC is bootstrapped (powered by VOUT
or by an auxiliary supply rail through a Schottky diode)
the minimum input operating voltage will be limited only
by the input voltage UVLO threshold.
RUN PIN COMPARATOR
In addition to serving as a logic-level input to enable the
IC, the RUN pin features an accurate internal comparator allowing it to be used to set custom rising and falling
input undervoltage lockout thresholds with the addition
of an external resistor divider. When the RUN pin is driven
above its logic threshold (typically 0.8V) the VCC regulator
is enabled which provides power to the internal control
circuitry of the IC and the accurate RUN pin comparator is
enabled. If the RUN pin voltage is increased further so that
it exceeds the RUN comparator threshold (1.21V nominal),
the buck-boost converter will be enabled.
If the RUN pin is brought below the RUN comparator
threshold, the buck-boost converter will inhibit switching,
but the VCC regulator and control circuitry will remain
powered unless the RUN pin is brought below its logic
threshold. Therefore, in order to place the part in shutdown and reduce the input current to its minimum level
(3µA typical) it is necessary to ensure that the RUN pin
is brought below the worst-case logic threshold (0.3V).
The RUN pin is a high voltage input and can be connected
directly to VIN to continuously enable the part when the
input supply is present. If the RUN pin is forced above
approximately 5V it will sink a small current as given by
the following equation:
IRUN ≅
VRUN – 5V
5MΩ
With the addition of an external resistor divider as shown
in Figure 3, the RUN pin can be used to establish a custom
31151f
15
LTC3115-1
OPERATION
VCC
THERMAL CONSIDERATIONS
LTC3115-1
0.5µA
VIN
R1
RUN
R2
0.8V
1.21V
–
+
+
–
ENA
ENABLE
SWITCHING
ENABLE
VCC REGULATOR AND
CONTROL CIRCUITS
INPUT LOGIC
THRESHOLD
31151 F03
Figure 3. Accurate RUN Pin Comparator
input undervoltage lockout threshold. The buck-boost converter is enabled when the RUN pin reaches 1.21V which
allows the rising UVLO threshold to be set via the resistor divider ratio. Once the RUN pin reaches the threshold
voltage, the comparator switches and the buck-boost
converter is enabled. In addition, an internal 0.5µA (typical) current source is enabled which sources current out
of the RUN pin raising the RUN pin voltage away from
the threshold. In order to disable the part, VIN must be
reduced sufficiently to overcome the hysteresis generated
by this current as well as the 100mV hysteresis of the RUN
comparator. As a result, the amount of hysteresis can be
independently programmed without affecting the rising
UVLO threshold by scaling the values of both resistors.
The power switches in the LTC3115-1 are designed to operate continuously with currents up to the internal current
limit thresholds. However, when operating at high current
levels there may be significant heat generated within the
IC. In addition, in many applications the VCC regulator is
operated with large input-to-output voltage differentials
resulting in significant levels of power dissipation in its
pass element which can add significantly to the total power
dissipated within the IC. As a result, careful consideration
must be given to the thermal environment of the IC in order
to optimize efficiency and ensure that the LTC3115-1 is
able to provide its full-rated output current. Specifically,
the exposed die attach pad of both the DHD and FE packages should be soldered to the PC board and the PC board
should be designed to maximize the conduction of heat out
of the IC package. This can be accomplished by utilizing
multiple vias from the die attach pad connection to other
PCB layers containing a large area of exposed copper.
If the die temperature exceeds approximately 165°C, the
IC will enter overtemperature shutdown and all switching
will be inhibited. The part will remain disabled until the
die cools by approximately 10°C. The soft-start circuit is
re-initialized in overtemperature shutdown to provide a
smooth recovery when the fault condition is removed.
31151f
16
LTC3115-1
APPLICATIONS INFORMATION
The standard LTC3115-1 application circuit is shown as the
typical application on the front page of this data sheet. The
appropriate selection of external components is dependent
upon the required performance of the IC in each particular
application given considerations and trade-offs such as
PCB area, cost, output and input voltage, allowable ripple
voltage, efficiency and thermal considerations. This section
of the data sheet provides some basic guidelines and considerations to aid in the selection of external components
and the design of the application circuit.
VCC Capacitor Selection
The VCC output on the LTC3115-1 is generated from the
input voltage by an internal low dropout regulator. The VCC
regulator has been designed for stable operation with a
wide range of output capacitors. For most applications,
a low ESR ceramic capacitor of at least 4.7µF should be
utilized. The capacitor should be placed as close to the
pin as possible and should connect to the PVCC pin and
ground through the shortest traces possible. The PVCC
pin is the regulator output and is also the internal supply
pin for the gate drivers and boost rail charging diodes.
The VCC pin is the supply connection for the remainder
of the control circuitry. The PVCC and VCC pins must be
connected together on the application PCB. If the trace
connecting VCC to PVCC cannot be made via a short connection, an additional 0.1µF bypass capacitor should be
placed between the VCC pin and ground using the shortest
connections possible.
Inductor Selection
The choice of inductor used in LTC3115-1 application
circuits influences the maximum deliverable output current, the magnitude of the inductor current ripple, and
the power conversion efficiency. The inductor must have
low DC series resistance or output current capability and
efficiency will be compromised. Larger inductance values
reduce inductor current ripple and will therefore generally yield greater output current capability. For a fixed DC
resistance, a larger value of inductance will yield higher
efficiency by reducing the peak current to be closer to the
average output current and therefore minimize resistive
losses due to high RMS currents. However, a larger inductor value within any given inductor family will generally
have a greater series resistance, thereby counteracting
this efficiency advantage. In general, inductors with larger
inductance values and lower DC resistance will increase
the deliverable output current and improve the efficiency
of LTC3115-1 applications.
An inductor used in LTC3115-1 applications should have a
saturation current rating that is greater than the worst-case
average inductor current plus half the ripple current. The
peak-to-peak inductor current ripple for each operational
mode can be calculated from the following formula, where
f is the switching frequency, L is the inductance, and
tLOW is the switch pin minimum low time. The switch pin
minimum low time can be determined from curves given
in the Typical Performance Characteristics section of this
data sheet.
∆IL(P-P)(BUCK) =
VOUT  VIN – VOUT   1

 – tLOW 


L 
VIN
 f
∆IL(P-P)(BOOST ) =
VIN  VOUT – VIN   1

 – tLOW 


L  VOUT  f
In addition to its influence on power conversion efficiency,
the inductor DC resistance can also impact the maximum
output current capability of the buck-boost converter particularly at low input voltages. In buck mode, the output
current of the buck-boost converter is generally limited
only by the inductor current reaching the current limit
threshold. However, in boost mode, especially at large
step-up ratios, the output current capability can also be
limited by the total resistive losses in the power stage.
These include switch resistances, inductor resistance,
and PCB trace resistance. Use of an inductor with high DC
resistance can degrade the output current capability from
that shown in the Typical Performance Characteristics section of this data sheet. As a guideline, in most applications
the inductor DC resistance should be significantly smaller
than the typical power switch resistance of 150mΩ.
Different inductor core materials and styles have an impact
on the size and price of an inductor at any given current
rating. Shielded construction is generally preferred as it
minimizes the chances of interference with other circuitry.
The choice of inductor style depends upon the price, sizing,
and EMI requirements of a particular application. Table 1
31151f
17
LTC3115-1
APPLICATIONS INFORMATION
provides a small sampling of inductors that are well suited
to many LTC3115-1 applications.
In applications with VOUT ≥ 20V, it is recommended that
a minimum inductance value, LMIN, be utilized where f is
the switching frequency:
LMIN =
capacitance, tLOW is the switch pin minimum low time, and
ILOAD is the output current. Curves for the value of tLOW
as a function of switching frequency and temperature can
be found in Typical Performance Characteristics section
of this data sheet.
12H
( f / Hz )
∆VP-P(BUCK) =
Table 1. Representative Surface Mount Inductors
PART NUMBER
VALUE DCR
MAX DC
(µH) (mΩ) CURRENT (A)
SIZE (mm)
W×L×H
Coilcraft
LPS6225
LPS6235
MSS1038
D03316P
4.7
6.8
22
15
65
75
70
50
3.2
2.8
3.3
3.0
6.2 × 6.2 × 2.5
6.2 × 6.2 × 3.5
10.2 × 10.5 × 3.8
12.9 × 9.4 × 5.2
Cooper-Bussmann
CD1-150-R
DR1030-100-R
FP3-8R2-R
DR1040-220-R
15
10
8.2
22
50
40
74
54
3.6
3.18
3.4
2.9
10.5 × 10.4 × 4.0
10.3 × 10.5 × 3.0
7.3 × 6.7 × 3.0
10.3 × 10.5 × 4.0
Panasonic
ELLCTV180M
ELLATV100M
18
10
30
23
3.0
3.3
12 × 12 × 4.2
10 × 10 × 4.2
Sumida
CDRH8D28/HP
CDR10D48MNNP
CDRH8D28NP
10
39
4.7
78
105
24.7
3.0
3.0
3.4
8.3 × 8.3 × 3
10.3 × 10.3 × 5
8.3 × 8.3 × 3
Taiyo-Yuden
NR10050T150M
15
46
3.6
9.8 × 9.8 × 5
TOKO
B1047AS-6R8N
B1179BS-150M
892NAS-180M
6.8
15
18
36
56
42
2.9
3.3
3.0
7.6 × 7.6 × 5
10.3 × 10.3 × 4
12.3 × 12.3 × 4.5
Würth
7447789004
744771133
744066150
4.7
33
15
33
49
40
2.9
2.7
3.2
7.3 × 7.3 × 3.2
12 × 12 × 6
10 × 10 × 3.8
ILOAD tLOW
COUT
∆VP-P(BOOST) =
ILOAD  VOUT – VIN + tLOW fVIN 

fCOUT 
VOUT
The output voltage ripple increases with load current and is
generally higher in boost mode than in buck mode. These
expressions only take into account the output voltage ripple
that results from the output current being discontinuous.
They provide a good approximation to the ripple at any
significant load current but underestimate the output voltage ripple at very light loads where output voltage ripple
is dominated by the inductor current ripple.
In addition to output voltage ripple generated across the
output capacitance, there is also output voltage ripple
produced across the internal resistance of the output
capacitor. The ESR-generated output voltage ripple is
proportional to the series resistance of the output capacitor
and is given by the following expressions where RESR is
the series resistance of the output capacitor and all other
terms are as previously defined.
∆VP-P(BUCK) =
ILOADRESR
≅I
R
1– tLOW f LOAD ESR
∆VP-P(BOOST) =
V 
ILOADRESR VOUT
≅ILOAD RESR  OUT 
VIN (1– tLOW f )
 VIN 
Output Capacitor Selection
Input Capacitor Selection
A low ESR output capacitor should be utilized at the buckboost converter output in order to minimize output voltage
ripple. Multilayer ceramic capacitors are an excellent option
as they have low ESR and are available in small footprints.
The capacitor value should be chosen large enough to
reduce the output voltage ripple to acceptable levels.
Neglecting the capacitor ESR and ESL, the peak-to-peak
output voltage ripple can be calculated by the following
formulas, where f is the switching frequency, COUT is the
The PVIN pin carries the full inductor current and provides
power to internal control circuits in the IC. To minimize
input voltage ripple and ensure proper operation of the IC,
a low ESR bypass capacitor with a value of at least 4.7µF
should be located as close to this pin as possible. The
traces connecting this capacitor to PVIN and the ground
plane should be made as short as possible. The VIN pin
provides power to the VCC regulator and other internal
circuitry. If the PCB trace connecting VIN to PVIN is long, it
31151f
18
LTC3115-1
APPLICATIONS INFORMATION
may be necessary to add an additional small value bypass
capacitor near the VIN pin.
When powered through long leads or from a high ESR
power source, a larger value bulk input capacitor may be
required. In such applications, a 47µF to 100µF electrolytic
capacitor in parallel with a 1µF ceramic capacitor generally
yields a high performance, low cost solution.
Recommended Input and Output Capacitors
The capacitors used to filter the input and output of the
LTC3115-1 must have low ESR and must be rated to
handle the large AC currents generated by switching converters. This is important to maintain proper functioning
of the IC and to reduce output voltage ripple. There are
many capacitor types that are well suited to such applications including multilayer ceramic, low ESR tantalum,
OS-CON and POSCAP technologies. In addition, there
are certain types of electrolytic capacitors such as solid
aluminum organic polymer capacitors that are designed
for low ESR and high AC currents and these are also well
suited to LTC3115-1 applications (Table 2). The choice of
capacitor technology is primarily dictated by a trade-off
between cost, size and leakage current. Notice that some
capacitors such as the OS-CON and POSCAP technologies
can exhibit significant DC leakage currents which may limit
their applicability in devices which require low no-load
quiescent current in Burst Mode operation.
Ceramic capacitors are often utilized in switching converter applications due to their small size, low ESR, and
low leakage currents. However, many ceramic capacitors
designed for power applications experience significant
loss in capacitance from their rated value with increased
DC bias voltages. For example, it is not uncommon for
a small surface mount ceramic capacitor to lose more
than 50% of its rated capacitance when operated near its
rated voltage. As a result, it is sometimes necessary to
use a larger value capacitance or a capacitor with a higher
voltage rating than required in order to actually realize the
intended capacitance at the full operating voltage. To ensure
that the intended capacitance is realized in the application
circuit, be sure to consult the capacitor vendor’s curve of
capacitance versus DC bias voltage.
Table 2. Representative Bypass and Output Capacitors
MANUFACTURER,
PART NUMBER
VALUE
(µF)
VOLTAGE
(V)
SIZE L × W × H (mm),
TYPE, ESR
AVX
12103D226MAT2A
22
25
3.2 × 2.5 × 2.79
X5R Ceramic
TPME226K050R0075
22
50
7.3 × 4.3 × 4.1
Tantalum, 75mΩ
Kemet
C2220X226K3RACTU
22
25
5.7 × 5.0 × 2.4
X7R Ceramic
A700D226M016ATE030
22
16
7.3 × 4.3 × 2.8
Alum. Polymer, 30mΩ
Murata
GRM32ER71E226KE15L
22
25
3.2 × 2.5 × 2.5
X7R Ceramic
Nichicon
PLV1E121MDL1
82
25
8 × 8 × 12
Alum. Polymer, 25mΩ
Panasonic
ECJ-4YB1E226M
22
25
3.2 × 2.5 × 2.5
X5R Ceramic
Sanyo
25TQC22MV
22
25
7.3 × 4.3 × 3.1
POSCAP, 50mΩ
16TQC100M
100
16
7.3 × 4.3 × 1.9
POSCAP, 45mΩ
25SVPF47M
47
25
6.6 × 6.6 × 5.9
OS-CON, 30mΩ
Taiyo Yuden
UMK325BJ106MM-T
10
50
3.2 × 2.5 × 2.5
X5R Ceramic
TMK325BJ226MM-T
22
25
3.2 × 2.5 × 2.5
X5R Ceramic
TDK
KTJ500B226M55BFT00
22
50
6.0 × 5.3 × 5.5
X7R Ceramic
C5750X7R1H106M
10
50
5.7 × 5.0 × 2.0
X7R Ceramic
CKG57NX5R1E476M
47
25
6.5 × 5.5 × 5.5
X5R Ceramic
Vishay
94SVPD476X0035F12
47
35
10.3 × 10.3 × 12.6
OS-CON, 30mΩ
31151f
19
LTC3115-1
APPLICATIONS INFORMATION
Programming Custom Input UVLO Thresholds
With the addition of an external resistor divider connected
to the input voltage as shown in Figure 4, the RUN pin
can be used to program the input voltage at which the
LTC3115-1 is enabled and disabled.
For a rising input voltage, the LTC3115-1 is enabled when
VIN reaches the threshold given by the following equation,
where R1 and R2 are the values of the resistor divider
resistors:
 R1+R2 
VTH(RISING) = 1.21V 
 R2 
To ensure robust operation in the presence of noise, the
RUN pin has two forms of hysteresis. A fixed 100mV of
hysteresis within the RUN pin comparator provides a
minimum RUN pin hysteresis equal to 8.3% of the input
turn-on voltage independent of the resistor divider values.
In addition, an internal hysteresis current that is sourced
from the RUN pin during operation generates an additive
level of hysteresis which can be programmed by the value
of R1 to increase the overall hysteresis to suit the requirements of specific applications.
Once the IC is enabled, it will remain enabled until the
input voltage drops below the comparator threshold by the
hysteresis voltage, VHYST , as given by the following equation where R1 and R2 are values of the divider resistors:
 R1+R2 
VHYST = R1• 0.5µA + 
0.1V
 R2 
Therefore, the rising UVLO threshold and amount of
hysteresis can be independently programmed via appropriate selection of resistors R1 and R2. For high levels
of hysteresis, the value of R1 can become larger than is
desirable in a practical implementation (greater than 1MΩ
VIN
R1
LTC3115-1
RUN
R2
GND
31151 F04
Figure 4. Setting the Input UVLO Threshold and Hysteresis
to 2MΩ). In such cases, the amount of hysteresis can be
increased further through the addition of an additional
resistor, RH, as shown in Figure 5.
When using the additional RH resistor, the rising RUN pin
threshold remains as given by the original equation and
the hysteresis is given by the following expression:
R R2+RH R1+R1R2
 R1+R2 
VHYST = 
0.1V + H
(0.5µA )

 R2 
R2
VIN
R1
R2
RH
LTC3115-1
RUN
GND
3115 F05
Figure 5. Increasing Input UVLO hysteresis
To improve the noise robustness and accuracy of the UVLO
thresholds, the RUN pin input can be filtered by adding a
1000pF capacitor from RUN to GND. Larger valued capacitors should not be utilized because they could interfere
with operation of the hysteresis.
Bootstrapping the VCC Regulator
The high and low side gate drivers are powered through the
PVCC rail which is generated from the input voltage through
an internal linear regulator. In some applications, especially
at higher operating frequencies and high input and output
voltages, the power dissipation in the linear VCC regulator
can become a key factor in the conversion efficiency of
the converter and can even become a significant source
of thermal heating. For example, at a 1.2MHz switching
frequency, an input voltage of 36V, and an output voltage of
24V, the total PVCC/VCC current is approximately 18mA as
shown in the Typical Performance Characteristics section
of this data sheet. As a result, this will generate 568mW of
power dissipation in the VCC regulator which will result in
an increase in die temperature of approximately 24° above
ambient in the DFN package. This significant power loss
will have a substantial impact on the conversion efficiency
and the additional heating may limit the maximum ambient
operating temperature for the application.
31151f
20
LTC3115-1
APPLICATIONS INFORMATION
A significant performance advantage can be attained in
applications which have the converter output voltage programmed to 5V if the output voltage is utilized to power
the PVCC and VCC rails. This can be done by connecting a
Schottky diode from VOUT to PVCC/VCC as shown in Figure  6.
With this bootstrap diode installed, the gate driver currents
are generated directly by the buck-boost converter at high
efficiency rather than through the internal linear regulator.
To minimize current drawn from the output, the internal
VCC regulator contains reverse blocking circuitry which
minimizes the current into the PVCC/VCC pins when they
are driven above the input voltage.
The gain term, GBUCK, is comprised of three different
components: the gain of the analog divider, the gain of the
pulse width modulator, and the gain of the power stage as
given by the following expressions where VIN is the input
voltage to the converter, f is the switching frequency, R is
the load resistance, and tLOW is the switch pin minimum
low time. Curves showing the switch pin minimum low time
can be found in the Typical Performance Characteristics
section of this data sheet. The parameter RS represents
the average series resistance of the power stage and can
be approximated as twice the average power switch resistance plus the DC resistance of the inductor.
GBUCK = GDIVIDER GPWM GPOWER
PVOUT
VOUT
GDIVIDER =
LTC3115-1
VCC
GPWM = 1.5 (1– tLOW f )
PVCC
4.7µF
31151 F06
Figure 6. Bootstrapping PVCC and VCC
Buck Mode Small-Signal Model
The LTC3115-1 uses a voltage mode control loop to
maintain regulation of the output voltage. An externally
compensated error amplifier drives the VC pin to generate
the appropriate duty cycle of the power switches. Use of
an external compensation network provides the flexibility
for optimization of closed loop performance over the wide
variety of output voltages, switching frequencies, and external component values supported by the LTC3115-1.
The small-signal transfer function of the buck-boost
converter is different in the buck and boost modes of operation and care must be taken to ensure stability in both
operating regions. When stepping down from a higher
input voltage to a lower output voltage, the converter
will operate in buck mode and the small-signal transfer
function from the error amplifier output, VC, to the converter
output voltage is given by the following equation:
VO
VC
= GBUCK
BUCK MODE

s 
 1+ 2πf 
Z
 s 
s
+
1+
2πfOQ  2πfO 
19.8
VIN
2
GPOWER =
VIN R
(1– tLOW f )(R+RS )
Notice that the gain of the analog divider cancels the input
voltage dependence of the power stage. As a result, the
buck mode gain is well approximated by a constant as
given by the following equation:
GBUCK = 29.7
R
≅ 29.7 = 29.5dB
R+RS
The buck mode transfer function has a single zero which
is generated by the ESR of the output capacitor. The zero
frequency, fZ, is given by the following expression where
RC and CO are the ESR and value of the output filter capacitor respectively.
fZ =
1
2πRC CO
In most applications, an output capacitor with a very low
ESR is utilized in order to reduce the output voltage ripple
to acceptable levels. Such low values of capacitor ESR
result in a very high frequency zero and as a result the
zero is commonly too high in frequency to significantly
impact compensation of the feedback loop.
31151f
21
LTC3115-1
APPLICATIONS INFORMATION
The denominator of the buck mode transfer function exhibits a pair of resonant poles generated by the LC filtering
of the power stage. The resonant frequency of the power
stage, fO, is given by the following expression where L is
the value of the inductor:
1
2π
fO =
R +RS
1
≅
LCO (R +RC ) 2π
1
LCO
The quality factor, Q, has a significant impact on compensation of the voltage loop since a higher Q factor produces
a sharper loss of phase near the resonant frequency. The
quality factor is inversely related to the amount of damping
in the power stage and is substantially influenced by the
average series resistance of the power stage, RS. Lower
values of RS will increase the Q and result in a sharper
loss of phase near the resonant frequency and will require
more phase boost or lower bandwidth to maintain an
adequate phase margin.
Q=
LCO (R +RC ) (R +RS )
RRCCO +L + CORS (R +RC )
≅
LCO
L
+C R
R O S
The boost mode gain, GBOOST , is comprised of three
components: the analog divider, the pulse width modulator
and the power stage. The gain of the analog divider and
PWM remain the same as in buck mode operation, but
the gain of the power stage in boost mode is given by the
following equation:
GPOWER ≅
VOUT 2
(1– tLOW f ) VIN
By combining the individual terms, the total gain in boost
mode can be reduced to the following expression. Notice
that unlike in buck mode, the gain in boost mode is a
function of both the input and output voltage.
GBOOST ≅
29.7VOUT 2
VIN 2
In boost mode operation, the frequency of the right half
plane zero, fRHPZ, is given by the following expression.
The frequency of the right half plane zero decreases at
higher loads and with larger inductors.
R (1– tLOW f ) VIN2
2
fRHPZ =
2πL VOUT 2
Boost Mode Small-Signal Model
When stepping up from a lower input voltage to a higher
output voltage, the buck-boost converter will operate in
boost mode where the small-signal transfer function from
control voltage, VC, to the output voltage is given by the
following expression.
In boost mode, the resonant frequency of the power stage
has a dependence on the input and output voltage as shown
by the following equation.
VO
VC
= GBOOST
BOOST MODE

s 
s 
 1+ 2πf   1– 2πf

Z
RHPZ 
 s 
s
1+
+
2πfO Q  2πfO 
2
In boost mode operation, the transfer function is characterized by a pair of resonant poles and a zero generated by
the ESR of the output capacitor as in buck mode. However,
in addition there is a right half plane zero which generates
increasing gain and decreasing phase at higher frequencies. As a result, the crossover frequency in boost mode
operation generally must be set lower than in buck mode
in order to maintain sufficient phase margin.
fO =
1
2π
RVIN2
VOUT 2
1 VIN
≅
•
LCO (R +RC ) 2π VOUT
RS +
1
LC
Finally, the magnitude of the quality factor of the power
stage in boost mode operation is given by the following
expression.
Q=

RV 2 
LCOR  RS + IN 
VOUT 2 

L + CO RS R
31151f
22
LTC3115-1
APPLICATIONS INFORMATION
Compensation of the Voltage Loop
VOUT
The small-signal models of the LTC3115-1 reveal that the
transfer function from the error amplifier output, VC, to
the output voltage is characterized by a set of resonant
poles and a possible zero generated by the ESR of the
output capacitor as shown in the Bode plot of Figure 7.
In boost mode operation, there is an additional right half
plane zero that produces phase lag and increasing gain at
higher frequencies. Typically, the compensation network
is designed to ensure that the loop crossover frequency
is low enough that the phase loss from the right half
plane zero is minimized. The low frequency gain in buck
mode is a constant, but varies with both VIN and VOUT in
boost mode.
GAIN
RTOP
RBOT
C1
+
–
VC
GND
31151 F08
Figure 8. Error Amplifier with Type I Compensation
In most applications, the low bandwidth of the Type I compensated loop will not provide sufficient transient response
performance. To obtain a wider bandwidth feedback loop,
optimize the transient response, and minimize the size of
the output capacitor, a Type III compensation network as
shown in Figure 9 is required.
VOUT
RFF
–40dB/DEC
RTOP
–20dB/DEC
0°
LTC3115-1
1000mV
FB
RBOT
LTC3115-1
1000mV
FB
CFF
CFB
RFB
CPOLE
PHASE
+
–
VC
GND
31151 F09
–90°
BUCK MODE
–180°
–270°
Figure 9. Error Amplifier with Type III Compensation
BOOST MODE
fO
fRHPZ
f
31151 F07
Figure 7. Buck-Boost Converter Bode Plot
For charging or other applications that do not require an
optimized output voltage transient response, a simple Type
I compensation network as shown in Figure 8 can be used
to stabilize the voltage loop. To ensure sufficient phase
margin, the gain of the error amplifier must be low enough
that the resultant crossover frequency of the control loop
is well below the resonant frequency.
A Bode plot of the typical Type III compensation network
is shown in Figure 10. The Type III compensation network
provides a pole near the origin which produces a very high
loop gain at DC to minimize any steady-state error in the
regulation voltage. Two zeros located at fZERO1 and fZERO2
provide sufficient phase boost to allow the loop crossover
frequency to be set above the resonant frequency, fO, of
the power stage. The Type III compensation network also
introduces a second and third pole. The second pole, at
frequency fPOLE2, reduces the error amplifier gain to a
zero slope to prevent the loop crossover from extending
too high in frequency. The third pole at frequency fPOLE3
provides attenuation of high frequency switching noise.
31151f
23
LTC3115-1
APPLICATIONS INFORMATION
In most applications the compensation network is designed
so that the loop crossover frequency is above the resonant
frequency of the power stage, but sufficiently below the
boost mode right half plane zero to minimize the additional
phase loss. Once the crossover frequency is decided upon,
the phase boost provided by the compensation network
is centered at that point in order to maximize the phase
margin. A larger separation in frequency between the
zeros and higher order poles will provide a higher peak
phase boost but may also increase the gain of the error
amplifier which can push out the loop crossover to a
higher frequency.
GAIN
–20dB/DEC
–20dB/DEC
90°
0°
–90°
PHASE
fZERO1
fPOLE2 fPOLE3
f
31151 F10
fZERO2
Figure 10. Type III Compensation Bode Plot
The transfer function of the compensated Type III error
amplifier from the input of the resistor divider to the output
of the error amplifier, VC, is:

s
 1+ 2πf

s
  1+ 2πf


VC (s)
ZERO1
ZERO2
= GEA



VOUT (s)
s
s
1+
s  1+


 2πfPOLE1  2πfPOLE2 
The error amplifier gain is given by the following equation.
The simpler approximate value is sufficiently accurate in
most cases since CFB is typically much larger in value
than CPOLE.
GEA =
1
1
≅
R TOP (CFB + CPOLE ) R TOP CFB
The pole and zero frequencies of the Type III compensation
network can be calculated from the following equations
where all frequencies are in Hz, resistances are in ohms,
and capacitances are in farads.
fZERO1 =
1
2πRFB CFB
1
1
fZERO2 =
≅
2π (R TOP +RFF ) CFF 2πR TOP CFF
CFB + CPOLE
1
fPOLE2 =
≅
2πCFBCPOLE RFB 2πCPOLE RFB
fPOLE3 =
24
1
2πCFF RFF
The Q of the power stage can have a significant influence
on the design of the compensation network because it
determines how rapidly the 180° of phase loss in the power
stage occurs. For very low values of series resistance, RS,
the Q will be higher and the phase loss will occur sharply.
In such cases, the phase of the power stage will fall rapidly
to –180° above the resonant frequency and the total phase
margin must be provided by the compensation network.
However, with higher losses in the power stage (larger RS)
the Q factor will be lower and the phase loss will occur
more gradually. As a result, the power stage phase will not
be as close to –180° at the crossover frequency and less
phase boost is required of the compensation network.
The LTC3115-1 error amplifier is designed to have a
fixed maximum bandwidth in order to provide rejection
of switching noise to prevent it from interfering with the
control loop. From a frequency domain perspective, this
can be viewed as an additional single pole as illustrated in
Figure 11. The nominal frequency of this pole is 300kHz.
For typical loop crossover frequencies below about 50kHz
the phase contributed by this additional pole is negligible.
However, for loops with higher crossover frequencies this
additional phase loss should be taken into account when
designing the compensation network.
LTC3115-1
1000mV
FB
VC
+
–
RFILT
CFILT
INTERNAL
VC
31151 F11
Figure 11. Internal Loop Filter
31151f
LTC3115-1
APPLICATIONS INFORMATION
Loop Compensation Example
This section provides an example illustrating the design of
a compensation network for a typical LTC3115-1 application circuit. In this example a 5V regulated output voltage
is generated with the ability to supply a 500mA load from
an input power source ranging from 3.5V to 30V. To reduce
switching losses a 750kHz switching frequency has been
chosen for this example. In this application the maximum
inductor current ripple will occur at the highest input voltage. An inductor value of 8.2µH has been chosen to limit
the worst-case inductor current ripple to approximately
600mA. A low ESR output capacitor with a value of 20µF
is specified to yield a worst-case output voltage ripple
(occurring at the worst-case step-up ratio and maximum
load current) of approximately 12mV. In summary, the key
power stage specifications for this LTC3115-1 example
application are given below.
f = 0.75MHz, tLOW = 0.1µs
VIN = 3.5V to 30V
VOUT = 5V at 500mA
COUT = 20µF, RC = 10mΩ
L = 8.2µH, RL = 45mΩ
With the power stage parameters specified, the compensation network can be designed. In most applications, the
most challenging compensation corner is boost mode
operation at the greatest step-up ratio and highest load
current since this generates the lowest frequency right half
plane zero and results in the greatest phase loss. Therefore,
a reasonable approach is to design the compensation
network at this worst-case corner and then verify that
sufficient phase margin exists across all other operating
conditions. In this example application, at VIN = 3.5V and
the full 500mA load current, the right half plane zero will
be located at 70kHz and this will be a dominant factor in
determining the bandwidth of the control loop.
The first step in designing the compensation network is
to determine the target crossover frequency for the com-
pensated loop. A reasonable starting point is to assume
that the compensation network will generate a peak phase
boost of approximately 60°. Therefore, in order to obtain
a phase margin of 60°, the loop crossover frequency, fC,
should be selected as the frequency at which the phase
of the buck-boost converter reaches –180°. As a result,
at the loop crossover frequency the total phase will be
simply the 60° of phase provided by the error amplifier
as shown:
Phase Margin = φBUCK-BOOST + φERRORAMPLIFIER + 180°
= –180° + 60° + 180° = 60°
Similarly, if a phase margin of 45° is required, the target
crossover frequency should be picked as the frequency
at which the buck-boost converter phase reaches –195°
so that the combined phase at the crossover frequency
yields the desired 45° of phase margin.
This example will be designed for a 60° phase margin to
ensure adequate performance over parametric variations
and varying operating conditions. As a result, the target
crossover frequency, fC, will be the point at which the
phase of the buck-boost converter reaches –180°. It is
generally difficult to determine this frequency analytically
given that it is significantly impacted by the Q factor of
the resonance in the power stage. As a result, it is best
determined from a Bode plot of the buck-boost converter
as shown in Figure 12. This Bode plot is for the LTC3115-1
buck-boost converter using the previously specified power
stage parameters and was generated from the small-signal
model equations using LTspice® software. In this case, the
phase reaches –180° at 24kHz making fC = 24kHz the target
crossover frequency for the compensated loop.
From the Bode plot of Figure 12 the gain of the power
stage at the target crossover frequency is 19dB. Therefore,
in order to make this frequency the crossover frequency
in the compensated loop, the total loop gain at fC must
be adjusted to 0dB. To achieve this, the gain of the compensation network must be designed to be –19dB at the
crossover frequency.
31151f
25
LTC3115-1
APPLICATIONS INFORMATION
50
40
–80
PHASE
20
–120
10
–160
0
–200
–10
–240
–20
10
–280
fC
100
1k
10k
FREQUENCY (Hz)
PHASE (DEG)
GAIN (dB)
–40
GAIN
30
–30
the compensated error amplifier is determined simply by
the amount of separation between the poles and zeros as
shown by the following equation:
0
100k
–320
1M
31151 F12
Figure 12. Converter Bode Plot, VIN = 3.5V, ILOAD = 500mA
At this point in the design process, there are three constraints that have been established for the compensation
network. It must have –19dB gain at fC = 24kHz, a peak
phase boost of 60° and the phase boost must be centered
at fC = 24kHz. One way to design a compensation network
to meet these targets is to simulate the compensated error
amplifier Bode plot in LTspice for the typical compensation
network shown on the front page of this data sheet. Then,
the gain, pole frequencies and zero frequencies can be
iteratively adjusted until the required constraints are met.
Alternatively, an analytical approach can be used to design
a compensation network with the desired phase boost,
center frequency and gain. In general, this procedure can
be cumbersome due to the large number of degrees of
freedom in a Type III compensation network. However the
design process can be simplified by assuming that both
compensation zeros occur at the same frequency, fZ, and
both higher order poles (fPOLE2 and fPOLE3) occur at the
common frequency, fP . In most cases this is a reasonable
assumption since the zeros are typically located between
1kHz and 10kHz and the poles are typically located near
each other at much higher frequencies. Given this assumption, the maximum phase boost, fMAX, provided by

φ MAX = 4 tan –1 

fP 
 – 270°
fZ 
A reasonable choice is to pick the frequency of the poles,
fP , to be about 50 times higher than the frequency of the
zeros, fZ, which provides a peak phase boost of approximately φMAX = 60° as was assumed previously. Next, the
phase boost must be centered so that the peak phase
occurs at the target crossover frequency. The frequency
of the maximum phase boost, fCENTER, is the geometric
mean of the pole and zero frequencies as:
fCENTER = fP • fZ = 50 • fZ ≅ 7 • fZ
Therefore, in order to center the phase boost given a factor
of 50 separation between the pole and zero frequencies,
the zeros should be located at one seventh of the crossover frequency and the poles should be located at seven
times the crossover frequency as given by the following
equations:
1
1
fZ = • fC = ( 24kHz ) = 3.43kHz
7
7
fP = 7 • fC = 7 ( 24kHz ) = 168kHz
This placement of the poles and zeros will yield a peak phase
boost of 60° that is centered at the crossover frequency,
fC. Next, in order to produce the desired target crossover
frequency, the gain of the compensation network at the
point of maximum phase boost, GCENTER, must be set to
–19dB. The gain of the compensated error amplifier at the
point of maximum phase gain is given by:


2πfP

 dB
GCENTER = 10log
 ( 2πf )3 (R C )2 
Z
TOP FB 

31151f
26
LTC3115-1
APPLICATIONS INFORMATION


50
GCENTER = 20log 
 dB
2πfC R TOP CFB 

This equation completes the set of constraints needed to
determine the compensation component values. Specifically, the two zeros, fZERO1 and fZERO2, should be located
near 3.43kHz. The two poles, fPOLE2 and fPOLE3, should be
located near 168kHz and the gain should be set to provide
a gain at the crossover frequency of GCENTER = –19dB.
The first step in defining the compensation component
values is to pick a value for RTOP that provides an acceptably
low quiescent current through the resistor divider. A value
of RTOP = 1MΩ is a reasonable choice. Next, the value of
CFB can be found in order to set the error amplifier gain
at the crossover frequency to –19dB as follows:
G CENTER = –19.1dB
The compensation poles can be set at 168kHz and the
zeros at 3.43kHz by using the expressions for the pole
and zero frequencies given in the previous section. Setting
the frequency of the first zero, fZERO1, to 3.43kHz results
in the following value for RFB:
RFB =
1
≅ 15.4kΩ
2π ( 3nF ) ( 3.43kHz)
CFF =
1
2π (1MΩ) ( 3.43kHz)
≅ 47pF
Finally, the resistor value RFF can be chosen to place the
second pole at 168kHz.
RFF =
1
≅ 20.0kΩ
2π ( 47pF ) (168Hz)
Now that the pole frequencies, zero frequencies and gain
of the compensation network have been established, the
next step is to generate a Bode plot for the compensated
error amplifier to confirm its gain and phase properties.
A Bode plot of the error amplifier with the designed compensation component values is shown in Figure 13. The
Bode plot confirms that the peak phase occurs at 24kHz
and the phase boost at that point is 57.7°. In addition,
the gain at the peak phase frequency is –19.3dB which is
close to the design target.
90
15
10
5
60
PHASE
0
30
–5
GAIN
–10
0
–15
–20
–30
–25
–30
–60
–35
–40
PHASE (DEG)


50
= 20 log 

 2π ( 24kHz ) (1M Ω) CFB 
50
≅ 3.0nF
CFB =
 –19.1
2π ( 24kHz ) (1M Ω ) a log 
 20 
Next, CFF can be chosen to set the second zero, fZERO2, to
the common zero frequency of 3.43kHz.
GAIN (dB)
Assuming a multiple of 50 separation between the pole
frequencies and zero frequencies this can be simplified
to the following expression:
fC
10
100
1k
10k
FREQUENCY (Hz)
100k
–90
1M
3115 F13
Figure 13. Compensated Error Amplifier Bode Plot
This leaves the free parameter, CPOLE, to set the frequency
fPOLE1 to the common pole frequency of 168kHz as
given:
CPOLE =
1
≅ 62pF
2π (15.4kΩ ) (168kHz)
31151f
27
LTC3115-1
APPLICATIONS INFORMATION
The final step in the design process is to compute the Bode
plot for the entire loop using the designed compensation
network and confirm its phase margin and crossover
frequency. The complete loop Bode plot for this example
is shown in Figure 14. The loop crossover frequency is
22kHz which is close to the design target and the phase
margin is approximately 60°.
The Bode plot for the complete loop should be checked over
all operating conditions and for variations in component
values to ensure that sufficient phase margin exists in all
cases. The stability of the loop should also be confirmed
via time domain simulation and by evaluating the transient
response of the converter in the actual circuit.
Output Voltage Programming
The output voltage is set via the external resistor divider
comprised of resistors RTOP and RBOT as show in Figures  8
and 9. The resistor divider values determine the output
regulation voltage according to:
 R

VOUT = 1.000V  1+ TOP 
 RBOT 
60
180
PHASE
40
120
GAIN (dB)
60
GAIN
0
0
PHASE (DEG)
20
–20
–60
–40
–120
–60
fC
10
100
1k
10k
FREQUENCY (Hz)
100k
In addition to setting the output voltage, the value of
RTOP is instrumental in controlling the dynamics of the
compensation network. When changing the value of this
resistor, care must be taken to understand the impact this
will have on the compensation network.
In addition, the Thevenin equivalent resistance of the
resistor divider controls the gain of the current limit. To
maintain sufficient gain in this loop, it is recommended
that the value of RTOP be chosen to be 1MΩ or larger.
Switching Frequency Selection
The switching frequency is set by the value of a resistor
connected between the RT pin and ground. The switching
frequency, f, is related to the resistor value by the following
equation where RT is the resistance:
f=
35.7MHz
( RT / kΩ )
Higher switching frequencies facilitate the use of smaller
inductors as well as smaller input and output filter capacitors which results in a smaller solution size and reduced
component height. However, higher switching frequencies
also generally reduce conversion efficiency due to the
increased switching losses.
In addition, higher switching frequencies (above 750kHz)
will reduce the maximum output current that can be supplied (see Typical Performance Characteristics for details).
For applications with VOUT ≥ 20V, a maximum switching
frequency of 1MHz is recommended.
–180
1M
31151 F14
Figure 14. Complete Loop Bode Plot
31151f
28
LTC3115-1
APPLICATIONS INFORMATION
PCB Layout Considerations
The LTC3115-1 buck-boost converter switches large
currents at high frequencies. Special attention should be
paid to the PC board layout to ensure a stable, noise-free
and efficient application circuit. Figures 15 and 16 show
a representative PCB layout for each package option to
outline some of the primary considerations. A few key
guidelines are provided below:
1. The parasitic inductance and resistance of all circulating high current paths should be minimized. This can
be accomplished by keeping the routes to all bold
components in Figures 15 and 16 as short and as wide
as possible. Capacitor ground connections should via
down to the ground plane by way of the shortest route
possible. The bypass capacitors on PVIN, PVOUT and
PVCC/VCC should be placed as close to the IC as possible and should have the shortest possible paths to
ground.
2. The exposed pad is the electrical power ground connection for the LTC3115-1 in the DHD package. Multiple vias
should connect the backpad directly to the ground plane.
In addition, maximization of the metallization connected
to the backpad will improve the thermal environment
and improve the power handling capabilities of the IC
in both the FE and DHD packages.
4. Connections to all of the components shown in bold
should be made as wide as possible to reduce the series
resistance. This will improve efficiency and maximize the
output current capability of the buck-boost converter.
5. To prevent large circulating currents in the ground
plane from disrupting operation of the LTC3115-1, all
small-signal grounds should return directly to GND
by way of a dedicated Kelvin route. This includes the
ground connection for the RT pin resistor, and the
ground connection for the feedback network as shown
in Figures 15 and 16.
6. Keep the routes connecting to the high impedance,
noise sensitive inputs FB and RT as short as possible
to reduce noise pick-up.
7. The BST1 and BST2 pins transition at the switching
frequency to the full input and output voltage respectively. To minimize radiated noise and coupling, keep
the BST1 and BST2 routes as short as possible and
away from all sensitive circuitry and pins (VC, FB, RT).
In many applications the length of traces connecting to
the boost capacitors can be minimized by placing the
boost capacitors on the back side of the PC board and
routing to them via traces on an internal copper layer.
3. The components shown in bold and their connections
should all be placed over a complete ground plane to
minimize loop cross-sectional areas. This minimizes
EMI and reduces inductive drops.
31151f
29
LTC3115-1
APPLICATIONS INFORMATION
VIA TO GROUND PLANE
(AND TO INNER LAYER
WHERE SHOWN)
[16]
PWM/
SYNC
[1]
RUN
[2]
SW2
VOUT
KELVIN
BACK TO
GND PIN
RBOT
RT
[17]
PGND
[15]
SW1
VIN
[3]
PVOUT
[14]
PVIN
[4]
GND
[13]
BST1
CBST1
CBST2
[5]
GND
[12]
BST2
[6]
VC
[11]
PVCC
[7]
FB
[10]
VIN
[8]
RT
[9]
VCC
INNER PCB
LAYER ROUTES
RTOP
KELVIN
TO VOUT
31151 F15
UNINTERRUPTED GROUND PLANE SHOULD EXIST UNDER ALL COMPONENTS SHOWN IN
BOLD AND UNDER TRACES CONNECTING TO THOSE COMPONENTS
Figure 15. PCB Layout Recommended for the DHD Package
31151f
30
LTC3115-1
APPLICATIONS INFORMATION
VIA TO GROUND PLANE
(AND TO INNER LAYER
WHERE SHOWN)
[1]
PGND
[20]
PGND
[2]
RUN
[19]
PWM/
SYNC
[3]
SW2
VOUT
KELVIN
BACK TO
GND PIN
RBOT
RT
[21]
PGND
[18]
SW1
VIN
[4]
PVOUT
[17]
PVIN
[5]
GND
[16]
BST1
CBST1
CBST2
[6]
GND
[15]
BST2
[7]
VC
[14]
PVCC
[8]
FB
[13]
VIN
[9]
RT
[12]
VCC
[10]
PGND
[11]
PGND
INNER PCB
LAYER ROUTES
RTOP
KELVIN
TO VOUT
31151 F16
UNINTERRUPTED GROUND PLANE SHOULD EXIST UNDER ALL COMPONENTS SHOWN IN
BOLD AND UNDER TRACES CONNECTING TO THOSE COMPONENTS
Figure 16. PCB Layout Recommended for the FE Package
31151f
31
LTC3115-1
TYPICAL APPLICATIONS
Wide Input Voltage Range (2.7V to 40V), High Efficiency 300kHz, Low Noise 5V Regulator
L1
33µH
CBST1
0.1µF
CBST2
0.1µF
BST1 SW1
2.7V TO
40V
SW2 BST2
PVIN
VIN
CIN
10µF
PVOUT
RUN
LTC3115-1
VC
FB
PWM/SYNC
PVCC
VCC
RT
RT
121k
GND
PGND
+
CO
RTOP
330µF
1M
CFB
RFB 3300pF
93.1k
CFF
82pF
5V
1A VIN > 3.6V
2A VIN ≥ 6V
RFF
249k
27pF
RBOT
249k
D1
31151 TA02a
C1
4.7µF
CIN: MURATA GRM55DR61H106K
CO: POSCAP 6TPB330M (7.3mm × 4.3mm × 2.8mm)
D1: PANASONIC MA785
L1: COILCRAFT MSS1260
PWM Mode Efficiency
vs Load Current
100
100
95
95
90
90
85
85
EFFICIENCY (%)
EFFICIENCY (%)
PWM Mode Efficiency
vs Load Current
80
75
70
65
60
VIN = 5V
VIN = 3.6V
VIN = 2.7V
55
50
0.01
0.1
LOAD CURRENT (A)
1
80
75
70
65
60
VIN = 12V
VIN = 24V
VIN = 36V
55
50
0.01
0.1
LOAD CURRENT (A)
31151 TA02b
VOUT Transient for a 0A to 1A Load Step
31151 TA02c
VOUT Transient for a 0A to 2A Load Step, VIN = 24V
VOUT
(200mV/DIV)
VIN = 36V
VOUT
(200mV/DIV)
VIN = 12V
VOUT
(200mV/DIV)
VOUT
(200mV/DIV)
VIN = 5V
INDUCTOR CURRENT
(2A/DIV)
VOUT
(200mV/DIV)
VIN = 3.6V
2ms/DIV
31151 TA02d
1
LOAD CURRENT
(2A/DIV)
2ms/DIV
31151 TA02e
31151f
32
LTC3115-1
TYPICAL APPLICATIONS
Wide Input Voltage Range (10V to 40V) 1MHz 24V Supply at 500mA
L1
15µH
CBST1
0.1µF
CBST2
0.1µF
BST1 SW1
10V TO 40V
UVLO
PROGRAMMED
TO 10V (1.3V
HYSTERESIS)
R1
953k
SW2 BST2
PVIN
VIN
CIN
10µF
RUN
PVOUT
RTOP
1M
CFB
RFB 3300pF
10k
LTC3115-1
R2
130k
24V
500mA
CO
10µF
VC
RFF
10k
FB
RT
35.7k
RBOT
43.2k
PWM/SYNC
PVCC
VCC
RT
GND
CFF
22pF
C1
4.7µF
PGND
31151 TA03a
L1: WÜRTH 744 066 150
Maximum Load Current vs VIN
Efficiency vs VIN
92
2.5
90
EFFICIENCY (%)
LOAD CURRENT (A)
2.0
1.5
1.0
0.5
0
ILOAD = 1A
88
86
84
82
80
10
ILOAD = 0.5A
30
20
INPUT VOLTAGE (V)
40
10
20
30
INPUT VOLTAGE (V)
40
31151 TA03c
31151 TA03b
Power-Up/Down Waveforms,
ILOAD = 0.5A
VIN
(5V/DIV)
VOUT
(10V/DIV)
INDUCTOR
CURRENT
(2A/DIV)
50ms/DIV
31151 TA03d
31151f
33
LTC3115-1
TYPICAL APPLICATIONS
Industrial 12V 1MHz Regulator with Custom Input Undervoltage Lockout Thresholds
L1
10µH
CBST2
0.1µF
CBST1
0.1µF
BST1 SW1
10V TO
40V
ENABLED WHEN VIN
REACHES 10.6V
DISABLED WHEN VIN
FALLS BELOW 8.7V
CIN
10µF
R1
2M
SW2 BST2
PVIN
VIN
PVOUT
LTC3115-1
VC
RUN
R2
255k
RT
35.7k
FB
PWM/SYNC
PVCC
VCC
RT
GND
PGND
CO
22µF
CFB
RFB 820pF
40.2k
12V
1.4A
RTOP
1M
CFF
33pF
RFF
10k
RBOT
90.9k
C1
4.7µF
31151 TA04a
CIN: MURATA GRM55DR61H106K
CO: TDK CKG57NX5R1H226M
L1: WÜRTH 744065100
PWM Mode Efficiency
vs Load Current
0A to 1.5A Load Step, VIN = 24V
100
VOUT
(500mV/DIV)
EFFICIENCY (%)
90
80
INDUCTOR
CURRENT
(1A/DIV)
70
60
VIN = 10.6V
VIN = 12V
VIN = 24V
VIN = 36V
50
40
0.01
0.1
LOAD CURRENT (A)
500µs/DIV
31151 TA04c
1
31151 TA04b
0A to 1.5A Load Step, VIN = 10.6V
0A to 1.5A Load Step, VIN = 40V
VOUT
(500mV/DIV)
VOUT
(500mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
INDUCTOR
CURRENT
(1A/DIV)
500µs/DIV
31151 TA04d
500µs/DIV
31151 TA04e
31151f
34
LTC3115-1
TYPICAL APPLICATIONS
24V 750kHz Industrial Rail Restorer
L1
22µH
*
CBST1
0.1µF
BST1 SW1
20V TO 40V
OPEN
DRAIN
OUTPUT
R1
500k
SW2 BST2
PVIN
VIN
CIN
10µF
*OPTIONAL: INSTALL IN
APPLICATIONS SUBJECT TO
OUTPUT OVERLOAD OR
SHORT-CIRCUIT CONDITIONS
CBST2
0.1µF
RUN
PVOUT
1µF
RFB
25k
LTC3115-1
ON OFF
+
VC
CO
82µF
CFB
3300pF
CFF
47pF
RTOP
1M
RFF
51k
100pF
FB
RT
PWM/SYNC
PVCC
VCC
GND
24V
1.5A
RT
47.5k
RBOT
43.2k
C1
4.7µF
PGND
31151 TA05a
CO: OS-CON 35SVPF82M
L1: TOKO 892NBS-220M
Regulated Output Voltage from a
Time Varying Input Rail
40V
VIN
(5V/DIV)
0A to 1.5A Load Step, VIN = 20V
LOAD
CURRENT
(1A/DIV)
VOUT
(1V/DIV)
VOUT
(5V/DIV)
INDUCTOR
CURRENT
(2A/DIV)
20V
31151 TA05b
10ms/DIV
500µs/DIV
31151 TA05c
Efficiency vs Load Current
100
90
EFFICIENCY (%)
80
70
60
50
40
VIN = 20V
VIN = 24V
VIN = 36V
30
20
0.01
0.10
LOAD CURRENT (A)
1
31151 TA05d
31151f
35
LTC3115-1
TYPICAL APPLICATIONS
USB, FireWire, Automotive and Unregulated Wall Adapter to Regulated 5V (750kHz)
USB
4.1V TO 5.5V
FireWire
8V TO 36V
AUTOMOTIVE
3.6V TO 40V
WALL ADAPTER
4V TO 40V
D1
D2
L1
10µH
CBST2
0.1µF
CBST1
0.1µF
D3
D4
BST1 SW1
10µF
SW2 BST2
PVIN
VIN
PVOUT
LTC3115-1
PWM/SYNC
BURST PWM
VC
RUN
OFF ON
CO
47µF
×2
CFB
RFB 4700pF
100k
FB
RT
47.5k
PVCC
VCC
RT
GND
PGND
5V
750mA
RTOP
1M
CFF
47pF
RFF
51k
RBOT
249k
C1
4.7µF
31151 TA06a
CIN: MURATA GRM55DR61H106K
CO: GRM43ER60J476
D1-D4: B360A-13-F
L1: COILCRAFT LPS6225
Soft-Start Waveform, VIN = 24V, ILOAD = 0.5A
VRUN
(5V/DIV)
VCC
(5V/DIV)
Efficiency vs Load Current,
from Automotive Input
VOUT
(2V/DIV)
100
INDUCTOR
CURRENT
(500mA/DIV)
90
2ms/DIV
EFFICIENCY (%)
80
31151 TA06c
70
Output Voltage Transient Response,
750mA Load Step, Powered from Automotive Input
60
50
VIN = 3.6V
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
40
30
20
0.01
0.1
LOAD CURRENT (A)
1
31151 TA06b
VOUT
(200mV/DIV)
VIN = 36V
VOUT
(200mV/DIV)
VIN = 12V
VOUT
(200mV/DIV)
VIN = 3.6V
1ms/DIV
31151 TA06d
31151f
36
LTC3115-1
TYPICAL APPLICATIONS
Miniature Size 1.5MHz 12V Supply
L1
4.7µH
CBST2
0.1µF
CBST1
0.1µF
BST1 SW1
6V TO 40V
CI
4.7µF
SW2 BST2
PVIN
VIN
PVOUT
RUN
LTC3115-1
BURST PWM
RT
23.7k
PWM/SYNC
VC
RT
FB
CO
10µF
CFB
RFB 1000pF
15k
RTOP
1M
CFF
33pF
RFF
15k
RBOT
90.9k
PVCC
VCC
GND
12V AT 500mA
1A VIN > 10V
C1
4.7µF
PGND
31151 TA07a
CO: MURATA GRM55DR61H106K
L1: WÜRTH 7447789004
Load Step Transient Response, 0mA to 500mA,
VIN = 6V
LOAD CURRENT
(500mA/DIV)
Load Step Transient Response, 0mA to 500mA,
VIN = 24V
LOAD CURRENT
(500mA/DIV)
VOUT
(500mV/DIV)
VOUT
(500mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
INDUCTOR
CURRENT
(1A/DIV)
31151 TA07b
200µs/DIV
Efficiency vs Load Current, PWM Mode
200µs/DIV
Efficiency vs Load Current, Burst Mode Operation
100
90
90
80
70
EFFICIENCY (%)
EFFICIENCY (%)
80
70
60
50
40
VIN = 6V
VIN = 10V
VIN = 24V
VIN = 36V
30
20
0.01
31151 TA07c
0.1
LOAD CURRENT (A)
1
31151 TA07d
60
50
40
VIN = 6V
VIN = 10V
VIN = 24V
VIN = 36V
30
20
0.1
1
10
LOAD CURRENT (mA)
100
31151 TA07e
31151f
37
LTC3115-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DHD Package
16-Lead Plastic DFN (5mm × 4mm)
(Reference LTC DWG # 05-08-1707)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.44 ±0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
4.34 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
5.00 ±0.10
(2 SIDES)
R = 0.20
TYP
4.00 ±0.10
(2 SIDES)
9
R = 0.115
TYP
0.40 ± 0.10
16
2.44 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
8
0.200 REF
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.00 – 0.05
(DHD16) DFN 0504
4.34 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
31151f
38
LTC3115-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation CA
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
4.95
(.195)
20 1918 17 16 15 14 13 12 11
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
6.40
2.74
(.252)
(.108)
BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP REV I 0211
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
31151f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
39
LTC3115-1
TYPICAL APPLICATION
750kHz Automotive 5V Regulator with Cold Crank Capability
L1
6.8µH
CBST2
0.1µF
CBST1
0.1µF
BST1 SW1
AUTOMOTIVE
3.6V TO 40V
CIN
10µF
SW2 BST2
PVIN
VIN
PVOUT
LTC3115-1
PWM/SYNC
BURST PWM
VC
RUN
OFF ON
CO
47µF
CFB
RFB 1000pF
54.9k
FB
CIN: MURATA GRM55DR61H106K
CO: MURATA GRM43ER60J476K
D1: PANASONIC MA785
L1: SUMIDA CDRH8D43HPNP
RT
47.5k
PVCC
VCC
RT
GND
PGND
5V
1A
CFF
33pF
RTOP
1M
RFF
42.2k
RBOT
249k
D1*
C1
4.7µF
31151 TA08a
*OPTIONAL-INSTALL D1 FOR IMPROVED EFFICIENCY AND LOWER INPUT OPERATING VOLTAGE
Cold Crank Line Transient with 1A Load
VIN
(10V/DIV)
15ms FALL TIME
EFFICIENCY (%)
80
VOUT
(200mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
VOUT
(200mV/DIV)
200ms/DIV
90
13.8V
6V
4.5V
INDUCTOR
CURRENT
(1A/DIV)
100
40V
12V
VIN
(2V/DIV)
Efficiency vs Load Current
VIN = 12V
Load Dump Line Transient with 1A Load
31151 TA08b
2ms/DIV
31151 TA08c
70
60
50
40
30
20
0.01
WITH BOOTSTRAP DIODE
WITHOUT BOOTSTRAP DIODE
0.1
1
LOAD CURRENT (A)
31151 TA08d
RELATED PARTS
PART NUMBER
LTC3112
DESCRIPTION
2.5A (IOUT), 15V Synchronous Buck-Boost DC/DC Converter
LTC3113
3A (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter
LTC3127
1A (IOUT), 1.2MHz Buck-Boost DC/DC Converter with
Programmable Input Current Limit
High Efficiency, Synchronous, 4-Switch Buck-Boost Controller
LTC3789
LTC3785
LTC3534
≤10A (IOUT), High Efficiency, 1MHz Synchronous, No RSENSE™
Buck-Boost Controller
7V, 500mA (IOUT), 1MHz Synchronous Buck-Boost DC/DC
Converter
COMMENTS
VIN: 2.7V to 15V, VOUT : 2.5V to 14V, IQ = 40µA, ISD < 1µA, DFN and
TSSOP Packages
VIN: 1.8V to 5.5V, VOUT : 1.8V to 5.25V, IQ = 30µA, ISD < 1µA, DFN
and TSSOP Packages
96% Efficiency VIN: 1.8V to 5.5V, VOUT : 1.8V to 5.25V, IQ = 35µA,
ISD < 4µA, MSOP and DFN Packages
VIN: 4V to 38V, VOUT : 0.8V to 38V, IQ = 3mA, ISD < 60µA,
SSOP-28, QFN-28 Packages
VIN: 2.7V to 10V, VOUT : 2.7V to 10V, IQ = 86µA, ISD < 15µA,
QFN Package
94% Efficiency, VIN: 2.4V to 7V, VOUT : 1.8V to 7V, IQ = 25µA,
ISD < 1µA, DFN and GN Packages
31151f
40 Linear Technology Corporation
LT 0312 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2012