LTM4616 Dual 8A per Channel Low VIN DC/DC µModule Regulator Description Features Complete Dual DC/DC Regulator System Input Voltage Range: 2.7V to 5.5V n Dual 8A Outputs, or Single 16A Output with a 0.6V to 5V Range n Output Voltage Tracking and Margining n ±1.75% Total DC Output Error (–55°C to 125°C) n Current Mode Control/Fast Transient Response n Power Good Tracking and Margining n Overcurrent/Thermal Shutdown Protection n Onboard Frequency Synchronization n Spread Spectrum Frequency Modulation n Multiphase Operation n Selectable Burst Mode® Operation n Output Overvoltage Protection n RoHS Compliant with Pb-Free Finish, Gold Finish LGA (e4) or SAC 305 BGA (e1) n Small Surface Mount Footprint, Low Profile (15mm × 15mm × 2.82mm) LGA and (15mm × 15mm × 3.42mm) BGA Packages n n Applications Telecom, Networking and Industrial Equipment Storage and ATCA, PCI Express Cards n Battery Operated Equipment The LTM®4616 is a complete dual 2-phase 8A per channel switch mode DC/DC power regulator system in a 15mm × 15mm surface mount LGA or BGA package. Included in the package are the switching controller, power FETs, inductor and all support components. Operating from an input voltage range of 2.7V to 5.5V, the LTM4616 supports two outputs within a voltage range of 0.6V to 5V, each set by a single external resistor. This high efficiency design delivers up to 8A continuous current (10A peak) for each output. Only bulk input and output capacitors are needed, depending on ripple requirement. The part can also be configured for a 2-phase single output at up to 16A. The low profile package enables utilization of unused space on the back side of PC boards for high density point-ofload regulation. Fault protection features include overvoltage protection, overcurrent protection and thermal shutdown. The power module is offered in space saving and thermally enhanced 15mm × 15mm × 2.82mm LGA and 15mm × 15mm × 3.42mm BGA packages. The LTM4616 is RoHS compliant with Pb-free finish. n n L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, µModule and PolyPhase are registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174. Different Combinations of Input and Output Number of Inputs Number of Outputs IOUT (MAX) 2 2 8A, 8A 2 1 16A 1 2 8A, 8A 1 1 16A Typical Application Efficiency vs Load Current Dual Output DC/DC µModule Regulator ® VIN1 VOUT1 FB1 10µF VIN2 3.3V TO 5V VOUT1 3.3V/8A LTM4616 2.21k 100µF ITHM1 VIN2 VOUT2 2.5V/8A VOUT2 FB2 10µF 3.09k 100µF 5VIN 3.3VOUT 90 EFFICIENCY (%) VIN1 5V 95 5VIN 2.5VOUT 85 80 75 ITHM2 GND1 GND2 70 4616 TA01a 0 2 4 6 LOAD CURRENT (A) 8 4616 TA01b 4616fd 1 LTM4616 Absolute Maximum Ratings (Note 1) VIN1, SVIN1, VIN2, SVIN2................................. –0.3V to 6V CLKOUT1, CLKOUT2..................................... –0.3V to 2V PGOOD1, PLLLPF1, CLKIN1, PHMODE1, MODE1, PGOOD2, PLLLPF2, CLKIN2, PHMODE2, MODE2...................................... –0.3V to VIN ITH1, ITHM1, RUN1, FB1, TRACK1, MGN1, BSEL1, ITH2 , ITHM2 , RUN2, FB2, TRACK2, MGN2, BSEL2.............................................. –0.3V to VIN VOUT1, VOUT2 , SW1, SW2............................. –0.3V to VIN Internal Operating Temperature Range (Note 2) E- and I-Grades................................... –40°C to 125°C MP-Grade........................................... –55°C to 125°C Junction Temperature............................................ 125°C Storage Temperature Range................... –55°C to 125°C Pin Configuration VIN2 TOP VIEW TOP VIEW SGND2 CLKOUT2 ITH2 RUN2 SGND2 CLKOUT2 ITH2 RUN2 VIN2 VOUT2 SVIN2 PLLLPF2 BSEL2 RUN1 SVIN1 PLLLPF1 VIN1 SW1 TRACK2 L ITHM2 K FB2 FB2 J SW2 GND2 H MODE2 G PGOOD2 F ITH1 SGND1 TRACK1 E VOUT1 D C A MGN2 CLKOUT1 ITHM1 2 3 4 5 6 CLKIN1 7 8 9 10 11 BSEL2 RUN1 SVIN1 PLLLPF1 VIN1 SW1 BSEL1 GND2 H MODE2 G PGOOD2 F ITH1 SGND1 TRACK1 E VOUT1 D C MGN2 CLKOUT1 ITHM1 MGN1 1 12 PHMODE2 FB1 GND1 PGOOD1 B A MGN1 1 CLKIN2 PHMODE2 FB1 GND1 PGOOD1 B BSEL1 PLLLPF2 ITHM2 J SW2 SVIN2 TRACK2 L K CLKIN2 VOUT2 M M 2 3 4 5 6 CLKIN1 MODE1 PHMODE1 7 8 9 10 11 12 MODE1 PHMODE1 BGA PACKAGE 144-LEAD (15mm × 15mm × 3.42mm) LGA PACKAGE 144-LEAD (15mm × 15mm × 2.82mm) TJMAX = 125°C, θJA = 10.5°C/W, θJCbottom = 2°C/W, θJCtop = 16°C/W, WEIGHT = 1.8g θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS TJMAX = 125°C, θJA = 10.5°C/W, θJCbottom = 2°C/W, θJCtop = 16°C/W, WEIGHT = 2.0g θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS Order Information LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE (NOTE 2) LTM4616EV#PBF LTM4616EV#PBF LTM4616V 144-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 125°C LTM4616IV#PBF LTM4616IV#PBF LTM4616V 144-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 125°C LTM4616MPV#PBF LTM4616MPV#PBF LTM4616V 144-Lead (15mm × 15mm × 2.82mm) LGA –55°C to 125°C LTM4616EY#PBF LTM4616EY#PBF LTM4616Y 144-Lead (15mm × 15mm × 3.42mm) BGA –40°C to 125°C LTM4616IY#PBF LTM4616IY#PBF LTM4616Y 144-Lead (15mm × 15mm × 3.42mm) BGA –40°C to 125°C LTM4616MPY#PBF LTM4616MPY#PBF LTM4616Y 144-Lead (15mm × 15mm × 3.42mm) BGA –55°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ 4616fd 2 LTM4616 Electrical Characteristics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). TA = 25°C, VIN = 5V unless otherwise noted. Per the typical application in Figure 18. Specified as each channel (Note 3). SYMBOL PARAMETER VIN1(DC), VIN2(DC) Input DC Voltage VOUT1(DC), VOUT2(DC) Output Voltage, Total Variation with Line and Load CONDITIONS MIN l CIN = 10µF × 1, COUT = 100µF Ceramic, 100µF POSCAP, RFB = 6.65k, MODE = 0V VIN = 2.7V to 5.5V, IOUT = IOUT(DC)MIN to IOUT(DC)MAX (Note 4) l TYP 2.7 MAX UNITS 5.5 V 1.472 1.49 1.508 V 1.464 1.49 1.516 V 2.05 1.85 2.2 2.0 2.35 2.15 V V Input Specifications VIN1(UVLO), VIN2(UVLO) Undervoltage Lockout Threshold SVIN Rising SVIN Falling IQ(VIN1, VIN2) Input Supply Bias Current VIN = 3.3V, VOUT = 1.5V, No Switching, MODE = VIN VIN = 3.3V, VOUT = 1.5V, No Switching, MODE = 0V VIN = 3.3V, VOUT = 1.5V, Switching Continuous 400 1.15 55 µA mA mA VIN = 5V, VOUT = 1.5V, No Switching, MODE = VIN VIN = 5V, VOUT = 1.5V, No Switching, MODE = 0V VIN = 5V, VOUT = 1.5V, Switching Continuous 450 1.3 75 µA mA mA 1 µA 4.5 2.93 A A Shutdown, RUN = 0, VIN = 5V IS(VIN1, VIN2) Input Supply Current VIN = 3.3V, VOUT = 1.5V, IOUT = 8A VIN = 5V, VOUT = 1.5V, IOUT = 8A Output Specifications IOUT1(DC), IOUT2(DC) Output Continuous Current Range VOUT = 1.5V VIN = 3.3V, 5.5V (Note 4) VIN = 2.7V ΔVOUT1(LINE)/VOUT1 ΔVOUT2(LINE)/VOUT2 Line Regulation Accuracy VOUT = 1.5V, VIN from 2.7V to 5.5V, IOUT = 0A l 0.1 0.25 %/V ΔVOUT1(LOAD)/VOUT1 ΔVOUT2(LOAD)/VOUT2 Load Regulation Accuracy VOUT = 1.5V (Note 4) VIN = 3.3V, 5.5V, ILOAD = 0A to 8A VIN = 2.7V, ILOAD = 0A to 5A l l 0.3 0.3 0.5 0.5 % % 0 0 8 5 A A VOUT1(AC), VOUT2(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF X5R Ceramic, VIN = 5V, VOUT = 1.5V fS1, fS2 Switching Frequency IOUT = 8A, VIN = 5V, VOUT = 1.5V fSYNC1, fSYNC2 SYNC Capture Range ΔVOUT1(START), ΔVOUT2(START) Turn-On Overshoot COUT = 100µF, VOUT = 1.5V, IOUT = 0A VIN = 3.3V VIN = 5V 10 10 tSTART1, tSTART2 Turn-On Time COUT = 100µF, VOUT = 1.5V, VIN = 5V, IOUT = 1A Resistive Load, Track = VIN 100 µs ΔVOUT1(LS), ΔVOUT2(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, COUT = 100µF Ceramic x2, 470µF POSCAP, VIN = 5V, VOUT = 1.5V 20 mV tSETTLE1, tSETTLE2 Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, VIN = 5V, VOUT = 1.5V, COUT = 100µF 10 µs IOUT1(PK), IOUT2(PK) Output Current Limit COUT = 100µF VIN = 2.7V, VOUT = 1.5V VIN = 3.3V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V 8 11 13 A A A 10 1.25 1.5 0.75 mVP-P 1.75 MHz 2.25 MHz mV mV 4616fd 3 LTM4616 Electrical Characteristics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). TA = 25°C, VIN = 5V unless otherwise noted. Per the typical application in Figure 18. Specified as each channel (Note 3). SYMBOL PARAMETER CONDITIONS Voltage at FB Pin IOUT = 0A, VOUT = 1.5V, VIN = 2.7V to 5.5V MIN TYP MAX UNITS 0.590 0.587 0.596 0.596 0.602 0.606 V V Control Section FB1, FB2 l SS Delay Internal Soft-Start Delay IFB1, IFB2 VRUN1, VRUN2 RUN Pin On/Off Threshold RUN Rising RUN Falling TRACK1, TRACK2 Tracking Threshold (Rising) Tracking Threshold (Falling) Tracking Disable Threshold RUN = VIN RUN = 0V RFBHI1, RFBHI2 Resistor Between VOUT and FB Pins 1.4 1.3 9.95 10 Efficiency vs Load Current CONTINUOUS MODE 90 90 85 5VIN 1.2VOUT 5VIN 1.5VOUT 5VIN 1.8VOUT 5VIN 2.5VOUT 5VIN 3.3VOUT 4 LOAD CURRENT EFFICIENCY (%) 90 EFFICIENCY (%) EFFICIENCY (%) 100 95 2 V V V 10.05 kΩ 85 80 3.3VIN 1.2VOUT 3.3VIN 1.5VOUT 3.3VIN 1.8VOUT 3.3VIN 2.5VOUT 75 6 8 4616 G01 70 0 2 % % % % % % % 6 11 16 –6 –11 –16 Efficiency vs Load Current 100 95 0 V V Specified as Each Channel 95 70 1.7 1.5 controls. The LTM4616I is guaranteed to meet specifications over the –40°C to 125°C internal operating temperature range. The LTM4616MP is guaranteed and tested over the –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: Two channels are tested separately and the same testing conditions are applied to each channel. Note 4: See Output Current Derating curves for different VIN, VOUT and TA. Efficiency vs Load Current CONTINUOUS MODE 5 10 15 –5 –10 –15 4 9 14 –4 –9 –14 MGN = VIN , BSEL = 0V MGN = VIN , BSEL = VIN MGN = VIN , BSEL = Float MGN = 0V, BSEL = 0V MGN = 0V, BSEL = VIN MGN = 0V, BSEL = Float Typical Performance Characteristics 75 µA ±10 Output Voltage Margining Percentage 80 0.2 0.57 0.18 VIN – 0.5 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4616 is tested under pulsed load conditions, such that TJ ≈ TA. The LTM4616E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process 100 µs 1.55 1.4 ΔVPGOOD1, ΔVPGOOD2 PGOOD Range %Margining 90 4 LOAD CURRENT CONTINUOUS MODE 85 80 2.7VIN 1.0VOUT 2.7VIN 1.5VOUT 2.7VIN 1.8VOUT 75 6 8 4616 G02 70 0 1 4 3 2 5 LOAD CURRENT (A) 6 7 4616 G03 4616fd 4 LTM4616 Typical Performance Characteristics Burst Mode Efficiency with 5V Input VIN to VOUT Step-Down Ratio 80 VOUT (V) EFFICIENCY (%) 90 70 60 VOUT = 1.5V VOUT = 2.5V VOUT = 3.3V 40 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 LOAD CURRENT (A) 4.0 3.5 3.5 3.0 3.0 2.5 2.5 2.0 1.5 1.0 0.5 0 2 3 4 VIN (V) SUPPLY CURRENT (mA) 1.4 VO = 1.2V PULSE-SKIPPING MODE 1 0.8 0.6 6 0 VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V IOUT = 6A VOUT = 1.2V VOUT = 1.5V 2 3 4 5 VIN (V) 4616 G05 6 4616 G06 Load Transient Response ILOAD 1A/DIV ILOAD 1A/DIV 0A 0A VOUT 50mV/DIV VOUT 50mV/DIV VO = 1.2V Burst Mode OPERATION 0.4 4616 G09 VIN = 5V 20µs/DIV VOUT = 2.5V 2A/µs STEP COUT = 2 × 100µF X5R, 470µF 4V POSCAP 4616 G08 VIN = 5V 20µs/DIV VOUT = 3.3V 2A/µs STEP COUT = 2 × 100µF X5R, 470µF 4V POSCAP 0.2 0 1.5 0.5 Load Transient Response Supply Current vs VIN 1.2 5 2.0 1.0 VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V IOUT = 8A VOUT = 1.2V VOUT = 1.5V 4616 G04 1.6 VIN to VOUT Step-Down Ratio 4.0 VOUT (V) 100 50 Specified as Each Channel 2.5 3 3.5 4 4.5 INPUT VOLTAGE (V) 5 5.5 4616 G07 Load Transient Response Load Transient Response Load Transient Response ILOAD 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV 0A 0A 0A VOUT 50mV/DIV VOUT 50mV/DIV VOUT 50mV/DIV 4616 G10 VIN = 5V 20µs/DIV VOUT = 1.8V 2.5A/µs STEP COUT = 2 × 100µF X5R, 470µF 4V POSCAP 4616 G11 VIN = 5V 20µs/DIV VOUT = 1.5V 2.5A/µs STEP COUT = 2 × 100µF X5R, 470µF 4V POSCAP VIN = 5V 20µs/DIV VOUT = 1.2V 2.5A/µs STEP COUT = 2 × 100µF X5R, 470µF POSCAP 4616 G12 4616fd 5 LTM4616 Typical Performance Characteristics Start-Up Specified as Each Channel VFB vs Temperature Load Regulation vs Current 0 602 –0.1 600 VOUT 0.5V/DIV VFB (mV) 598 VIN 2V/DIV LOAD REGULATION (%) VIN = 5.5V VIN = 3.3V 596 VIN = 2.7V 594 VIN = 5V 50µs/DIV VOUT = 1.5V COUT = 100µF NO LOAD AND 8A LOAD (DEFAULT 100µs SOFT-START) –0.2 –0.3 –0.4 4616 G13 FC MODE VIN = 3.3V VOUT = 1.5V –0.5 592 590 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 –0.6 2 0 4616 G14 4 6 LOAD CURRENT (A) 8 4616 G15 Short-Circuit Protection (2.5V Short, No Load) 2.5V Output Current Short-Circuit Protection (2.5V Short, 4A Load) 3.0 2V/DIV OUTPUT VOLTAGE (V) 2.5 2V/DIV 2.0 5A/DIV 1.5 VIN 5V/DIV 5V/DIV VOUT VIN VOUT IOUT LOAD 5A/DIV IOUT 1.0 VIN = 5V VOUT = 2.5V 0.5 0 0 5 10 15 OUTPUT CURRENT (A) 50µs/DIV 4616 G17 VIN = 5V VOUT = 2.5V 50µs/DIV 4616 G18 20 4616 G16 4616fd 6 LTM4616 Pin Functions VIN1, VIN2, (BANK1 and BANK2); (F1-F4, E1-E4, C1-C2, D1-D2) and (J1-J2, K1-K2, L1-L4, M1-M4): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. VOUT1, VOUT2 (BANK3 and BANK6); (D9-D12, E9-E12, F9-F12) and (K9-K12, L9-L12, M9-M12): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. See Table 1. GND1 and GND2 (BANK2 and BANK5); (A1-A5, A12, B1B5, B7-B12, C3-C12, D3-D7) and (G1-G5, G12, H1-H5, H7-H12, J3-J12, K3-K7): Power Ground Pins for Both Input and Output Returns. SVIN1 and SVIN2 (E5 and L5): Signal Input Voltage for Each Channel. This pin is internally connected to VIN through a lowpass filter. SGND1 and SGND2 (F5 and M5): Signal Ground Pin for Each Channel. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See layout guidelines in Figure 17. MODE1 and MODE2 (A8 and G8): Mode Select Input for Each Channel. Tying this pin high enables Burst Mode operation. Tying this pin low enables forced continuous operation. Floating this pin or tying it to VIN/2 enables pulse-skipping operation. CLKIN1 and CLKIN2 (A7 and G7): External Synchronization Input to Phase Detector for Each Channel. This pin is internally terminated to SGND with a 50k resistor. The phase-locked loop will force the internal top power PMOS turn on to be synchronized with the rising edge of the CLKIN signal. Connect this pin to SVIN to enable spread spectrum modulation. During external synchronization, make sure the PLLLPF pin is not tied to VIN or GND. PLLLPF1 and PLLLPF2 (E6 and L6): Phase-Locked Loop Lowpass Filter for Each Channel. An internal lowpass filter is tied to this pin. In spread spectrum mode, placing a capacitor here to SGND controls the slew rate from one frequency to the next. Alternatively, floating this pin allows normal running frequency at 1.5MHz, tying this pin to SVIN forces the part to run at 1.33 times its normal frequency (2MHz), tying it to ground forces the frequency to run at 0.67 times its normal frequency (1MHz). PHMODE1 and PHMODE2 (A9 and G9): Phase Selector Input for Each Channel. This pin determines the phase relationship between the internal oscillator and CLKOUT. Tie it high for 2-phase operation, tie it low for 3-phase operation, and float or tie it to VIN/2 for 4-phase operation. MGN1 and MGN2 (A10 and G10): Voltage Margining Pin for Each Channel. Increases or decreases the output voltage by the amount specified by the BSEL pin. To disable margining, tie the MGN pin to a voltage divider with 50k resistors from VIN to ground (see Figure 5). For margining, connect a voltage divider from VIN to GND with the center point connected to the MGN pin for the specific channel. Each resistor should be close to 50k. Margin High is within 0.3V of VIN , and Margin Low is within 0.3V of GND. See the Applications Information section and Figure 18 for margining control. The specified tri-state drivers are capable of the high and low requirements for margining. BSEL1 and BSEL2 (A6 and G6): Margining Bit Select Pin for Each Channel. Tying BSEL low selects ±5% margin value, tying it high selects 10% margin value. Floating it or tying it to VIN/2 selects 15% margin value. TRACK1 and TRACK2 (E8 and L8): Output Voltage Tracking Pin for Each Channel. Voltage tracking is enabled when the TRACK voltage is below 0.57V. If tracking is not desired, then connect the TRACK pin to SVIN. If TRACK is not tied to SVIN , then the TRACK pin’s voltage needs to be below 0.18V before the chip shuts down even though RUN is 4616fd 7 LTM4616 Pin Functions already low. Do not float this pin. A resistor and capacitor can be applied to the TRACK pin to increase the soft-start time of the regulator. TRACK1 and TRACK2 can be tied together for parallel operation and tracking. See the Applications Information section. FB1 and FB2 (D8 and K8): The Negative Input of the Error Amplifier for Each Channel. Internally, this pin is connected to VOUT with a 10k precision resistor. Different output voltages can be programmed with an additional resistor between FB and GND pins. In PolyPhase® operation, tying the FB pins together allows for parallel operation. See the Applications Information section for details. ITH1 and ITH2 (F8 and M8): Current Control Threshold and Error Amplifier Compensation Point for Each Channel. The current comparator threshold increases with this control voltage. Tie together in parallel operation. ITHM1 and ITHM2 (E7 and L7): Negative Input to the Internal ITH Differential Amplifier for Each Channel. Tie this pin to SGND for single phase operation on each channel. For PolyPhase operation, tie the master’s ITHM to SGND while connecting all of the ITHM pins together at the master. PGOOD1 and PGOOD2 (A11 and G11): Output Voltage Power Good Indicator for Each Channel. Open-drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. Power good is disabled during margining. RUN1 and RUN2 (F6 and M6): Run Control Pin. A voltage above 1.7V will turn on the module. SW1 and SW2 (B6 and H6): Switching Node of Each Channel That is Used for Testing Purposes. This can be connected to an electronically open circuit copper pad on the board for improved thermal performance. CLKOUT1 and CLKOUT2 (F7 and M7): Output Clock Signal for PolyPhase Operation. The phase of CLKOUT is determined by the state of the PHMODE pin. 4616fd 8 LTM4616 Simplified Block Diagram SVIN1 INTERNAL FILTER TRACK1 VOUT1 10µF 10µF 10µF + VIN1 3V TO 5.5V CIN1 PGND1 MGN1 BSEL1 M1 PGOOD1 MODE1 0.22µH POWER CONTROL RUN1 SW1 VOUT1 1.5V 8A CLKIN1 CLKOUT1 PHMODE1 + 10µF M2 COUT1 ITH1 PGND1 50k PLLLPF1 INTERNAL COMP SGND1 SVIN2 INTERNAL FILTER TRACK2 VOUT2 FB1 RSET1 6.65k INTERNAL FILTER ITHM1 PGND1 10k 10µF 10µF 10µF VIN2 3V TO 5.5V CIN2 PGND2 MGN2 BSEL2 M3 PGOOD2 MODE2 SW2 0.22µH POWER CONTROL RUN2 VOUT2 1.2V 8A CLKIN2 CLKOUT2 M4 PHMODE2 + 10µF ITH2 PLLLPF2 ITHM2 COUT2 PGND2 50k PGND2 + INTERNAL COMP 10k FB2 RSET2 10k INTERNAL FILTER SGND2 4616 BD Figure 1. Simplified LTM4616 Block Diagram 4616fd 9 LTM4616 simplified block diagram Table 1. Decoupling Requirements. TA = 25°C, Block Diagram Configuration. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CIN1 CIN2 External Input Capacitor Requirement (VIN1 = 2.7V to 5.5V, VOUT1 = 1.5V) (VIN2 = 2.7V to 5.5V, VOUT2 = 2.5V) IOUT1 = 8A IOUT2 = 8A 22 22 µF µF COUT1 COUT2 External Output Capacitor Requirement (VIN1 = 2.7V to 5.5V, VOUT1 = 1.5V) (VIN2 = 2.7V to 5.5V, VOUT2 = 2.5V) IOUT1 = 8A IOUT2 = 8A 100 100 µF µF Operation The LTM4616 is a dual-output standalone nonisolated switching mode DC/DC power supply. It can provide two 8A outputs with few external input and output capacitors. This module provides precisely regulated output voltages programmable via external resistors from 0.6VDC to 5VDC over 2.7V to 5.5V input voltages. The typical application schematic is shown in Figure 18. The LTM4616 has integrated constant frequency current mode regulators and built-in power MOSFET devices with fast switching speed. The typical switching frequency is 1.5MHz. For switching noise sensitive applications, it can be externally synchronized from 0.75MHz to 2.25MHz. Even spread spectrum switching can be implemented in the design to reduce noise. With current mode control and internal feedback loop compensation, the LTM4616 module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit and thermal shutdown in an overcurrent condition. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. The power good pins are disabled during margining. Pulling the RUN pins below 1.3V forces the regulators into a shutdown state, by turning off both MOSFETs. The TRACK pin is used for programming the output voltage ramp and voltage tracking during start-up. See the Applications Information section. The LTM4616 is internally compensated to be stable over all operating conditions. Table 3 provides a guideline for input and output capacitances for several operating conditions. LTpowerCAD™ design tool is available for fine tuning transient and stability perfromance. The FB pin is used to program the output voltage with a single external resistor to ground. Multiphase operation can be easily employed with the synchronization and phase mode controls. The LTM4616 has clock in and clock out for poly phasing multiple devices or frequency synchronization. High efficiency at light loads can be accomplished with selectable Burst Mode operation using the MODE pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. Output voltage margining is supported, and can be programed from ±5% to ±15% using the MGN and BSEL pins. 4616fd 10 LTM4616 Applications Information The typical LTM4616 application circuit is shown in Figure 18. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 3 for specific external capacitor requirements for a particular application. VIN to VOUT Step-Down Ratios There are restrictions in the maximum VIN to VOUT stepdown ratio that can be achieved for a given input voltage. Each output of the LTM4616 is capable of 100% duty cycle, but the VIN to VOUT minimum drop out is still shown as a function of its load current. For a 5V input voltage, both outputs can deliver 8A for any output voltage. For a 3.3V input, all outputs can deliver 8A, except 2.5VOUT and above which is limited to 6A. All outputs derived from a 2.7V input voltage are limited to 5A. ceramic capacitors are included inside the module. Additional input capacitors are only needed if a large load step is required up to the 4A level. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this 47µF capacitor is not needed. For a buck converter, the switching duty-cycle can be estimated as: VOUT = 0.596V • 10k + RFB RFB Table 2. FB Resistor vs Various Output Voltages VOUT 0.596V 1.2V 1.5V 1.8V 2.5V 3.3V RFB Open 10k 6.65k 4.87k 3.09k 2.21k For parallel operation of N number of outputs, the below equation can be used to solve for RFB . Tie the FB pins together for each paralleled output with a single resistor to ground as determined by: R FB = 10k / N VOUT −1 0.596 Input Capacitors The LTM4616 module should be connected to a low AC impedance DC source. For each regulator, three 10µF VOUT VIN Without considering the inductor current ripple, the RMS current of the input capacitor can be estimated as: Output Voltage Programming Each PWM controller has an internal 0.596V reference voltage. As shown in the Block Diagram, a 10k internal feedback resistor connects VOUT and FB pins together. The output voltage will default to 0.596V with no feedback resistor. Adding a resistor RFB from FB pin to GND programs the output voltage: D= ICIN(RMS) = IOUT(MAX) η% • D • (1– D) In the above equation, η% is the estimated efficiency of the power module so the RMS input current at the worst case for 8A maximum current is about 4A. The input bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or polymer capacitor. Each internal 10µF ceramic input capacitor is typically rated for 2 amps of RMS ripple current. Output Capacitors The LTM4616 is designed for low output voltage ripple noise. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, low ESR polymer capacitor or ceramic capacitor. The typical output capacitance range is from 47µF to 220µF. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spikes is desired. Table 3 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 3A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 3 matrix. LTpowerCAD is available 4616fd 11 LTM4616 Applications Information Table 3. Output Voltage Response Versus Component Matrix (Refer to Figure 18) 0A to 3A Load Step TYPICAL MEASURED VALUES VALUE COUT1 VENDORS TDK 22µF, 6.3V Murata 22µF, 16V TDK 100µF, 6.3V Murata 100µF, 6.3V VOUT (V) 1.0 1.0 1.0 1.0 1.2 1.2 1.2 1.2 1.5 1.5 1.5 1.5 1.5 1.5 1.8 1.8 CIN (CERAMIC) 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF CIN (BULK)* 100µF 100µF 100µF 100µF 100µF 100µF 100µF 100µF 100µF 100µF 100µF 100µF 100µF 100µF 100µF 100µF PART NUMBER C3216X7S0J226M GRM31CR61C226K C4532X5R0J107MZ GRM32ER60J107M COUT1 (CERAMIC) 100µF × 2 100µF × 2 100µF × 2 22µF × 1 100µF × 2 22µF × 1 100µF × 2 22µF × 1 100µF × 2 22µF × 1 100µF × 1 22µF × 1 100µF × 2 22µF × 1 100µF × 1 22µF × 1 COUT2 (BULK) 470µF COUT2 VENDORS Sanyo POSCAP CIN (BULK) VENDORS SUNCON VALUE 470µF, 4V VALUE 100µF, 10V PART NUMBER 4TPE470M PART NUMBER 10CE100FH ITH None None None None None None None None None None None None None None None None C1 None None None None None None None None None None None None None None None None C3 None None None None None None None None None None None None None None None None VIN (V) 5 5 2.7 2.7 5 5 2.7 2.7 5 5 3.3 3.3 2.7 2.7 5 5 DROOP (mV) 20 30 30 25 20 20 30 30 32 25 22 25 30 25 42 25 PEAK-TO- PEAK DEVIATION (mV) 40 60 60 50 40 41 60 60 64 50 42 50 60 50 80 50 RECOVERY TIME (µs) 40 25 25 25 25 25 20 25 20 25 25 25 25 25 25 30 LOAD STEP (A/µs) 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 RFB (kΩ) 14.7 14.7 14.7 14.7 10 10 10 10 6.65 6.65 6.65 6.65 6.65 6.65 4.87 4.87 100µF 100µF × 2 None 1.8 10µF 1.8 10µF 100µF 22µF × 1 470µF None 1.8 10µF 100µF 100µF × 2 None 1.8 10µF 100µF 22µF × 1 470µF None 2.5 10µF 100µF 100µF × 1 None 2.5 10µF 100µF 22µF × 1 470µF None 2.5 10µF 100µF 100µF × 1 None 2.5 10µF 100µF 22µF × 1 470µF None 3.3 10µF 100µF 100µF × 1 None 3.3 10µF 100µF 22µF × 1 470µF None *Bulk capacitance is optional if VIN has very low input impedance. None None None None None None None None None None None None None None None None None None None None 3.3 3.3 2.7 2.7 5 5 3.3 3.3 5 5 35 25 35 35 35 32 50 32 65 40 70 50 70 20 40 65 100 65 135 87 30 30 30 30 30 40 30 40 30 40 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 4.87 4.87 4.87 4.87 3.09 3.09 3.09 3.09 2.21 2.21 470µF 470µF 470µF 470µF 470µF 470µF 470µF for those who wish to perform additional stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance will be more a function of stability and transient response. LTpowerCAD also calculates the output ripple reduction as the number of phases increases. Burst Mode Operation The LTM4616 is capable of Burst Mode operation on each regulator in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. To enable Burst Mode operation, simply tie the MODE pin to VIN. During this operation, the peak current of the inductor is set to approximately 20% of the maximum 4616fd 12 LTM4616 Applications Information peak current value in normal operation even though the voltage at the ITH pin indicates a lower value. The voltage at the ITH pin drops when the inductor’s average current is greater than the load requirement. As the ITH voltage drops below 0.2V, the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In Burst Mode operation, the internal circuitry is partially turned off, reducing the quiescent current to about 450µA for each output. The load current is now being supplied from the output capacitors. When the output voltage drops, causing ITH to rise above 0.25V, the internal sleep line goes low, and the LTM4616 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Each regulator can be configured for Burst Mode operation. Pulse-Skipping Mode Operation In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4616 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Floating the MODE pin or tying it to VIN /2 enables pulse-skipping operation. This allows discontinuous conduction mode (DCM) operation down to near the limit defined by the chip’s minimum on-time (about 100ns). Below this output current level, the converter will begin to skip cycles in order to maintain output regulation. Increasing the output load current slightly, above the minimum required for discontinuous conduction mode, allows constant frequency PWM. Each regulator can be configured for pulse-skipping mode. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE pin to GND. In this mode, inductor current is allowed to reverse during low output loads, the ITH voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4616’s output voltage is in regulation. Each regulator can be configured for forced continuous mode. Multiphase Operation For output loads that demand more than 8A of current, two outputs in LTM4616 or even multiple LTM4616s can be cascaded to run out-of-phase to provide more output current without increasing input and output voltage ripple. The CLKIN pin allows the LTC4616 to synchronize to an external clock (between 0.75MHz and 2.25MHz) and the internal phase-locked loop allows the LTM4616 to lock onto CLKIN’s phase as well. The CLKOUT signal can be connected to the CLKIN pin of the following LTM4616 stage to line up both the frequency and the phase of the entire system. Tying the PHMODE pin to SVIN , SGND or SVIN /2 (floating) generates a phase difference (between CLKIN and CLKOUT) of 180°, 120° or 90° respectively, which corresponds to a 2-phase, 3-phase or 4-phase operation. For a 6-phase example in Figure 2, the 2nd stage that is 120° out-of-phase from the 1st stage can generate a 240° (PHMODE = 0) CLKOUT signal for the 3rd stage, which then can generate a CLKOUT signal that’s 420°, or 60° (PHMODE = SVIN) for the 4th stage. With the 60° CLKIN input, the next two stages can shift 120° (PHMODE = 0) for each to generate a 300° signal for the 6th stage. Finally, the signal with a 60° phase shift on the 6th stage (PHMODE is floating) goes back to the 1st stage. Figure 3 shows the configuration for 12-phase operation. A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used. 4616fd 13 LTM4616 Applications Information 0 CLKIN CLKOUT 120 +120 PHMODE CLKIN CLKOUT PHMODE PHASE 1 (420) 60 240 +120 SVIN CLKIN CLKOUT +180 PHMODE PHMODE PHASE 5 PHASE 3 CLKIN CLKOUT 180 +120 CLKIN CLKOUT 300 +120 PHMODE PHMODE PHASE 4 PHASE 2 CLKIN CLKOUT 4616 F02 PHASE 6 Figure 2. 6-Phase Operation 0 CLKIN CLKOUT 120 +120 PHMODE CLKIN CLKOUT PHMODE PHASE 1 +120 SVIN PHASE 5 VIN (420) 60 240 CLKIN CLKOUT +180 PHMODE CLKIN CLKOUT 180 +120 PHMODE CLKIN CLKOUT 300 +120 PHMODE CLKIN CLKOUT PHMODE PHASE 9 PHASE 3 PHASE 7 PHASE 11 330 (510) 150 270 (390) 30 OUT1 LTC6908-2 OUT2 90 CLKIN CLKOUT PHMODE PHASE 4 210 +120 CLKIN CLKOUT PHMODE PHASE 8 +120 SVIN CLKIN CLKOUT PHMODE PHASE 12 +180 CLKIN CLKOUT PHMODE PHASE 6 +120 CLKIN CLKOUT +120 PHMODE PHASE 10 CLKIN CLKOUT PHMODE PHASE 2 4616 F03 Figure 3. 12-Phase Operation The LTM4616 device is an inherently current mode controlled device, so parallel modules will have very good current sharing. This will balance the thermals on the design. Tie the ITH pins of each LTM4616 together to share the current. Current sharing is inherently guaranteed by the current mode operation of the LTM4616’s DC/DC regulators. Moreover, the accuracy of current sharing between the two outputs is approximately ±15%. To reduce ground potential noise, tie the ITHM pins of all LTM4616s together and then connect to the SGND of the master at the point it connects to the output capacitor GND. See layout guideline in Figure 17. Figure 19 shows a schematic of the parallel design. The FB pins of the parallel module are tied together. Input RMS Ripple Current Cancellation Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases. Figure 4 shows this graph. 4616fd 14 LTM4616 Applications Information 0.60 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.55 0.50 RMS INPUT RIPPLE CURRENT DC LOAD CURRENT 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY FACTOR (VO/VIN) 4616 F04 Figure 4. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Channels (Phases) Spread Spectrum Operation Switching regulators can be particularly troublesome where electromagnetic interference (EMI) is concerned. Switching regulators operate on a cycle-by-cycle basis to transfer power to an output. In most cases, the frequency of operation is fixed based on the output load. This method of conversion creates large components of noise at the frequency of operation (fundamental) and multiples of the operating frequency (harmonics). To reduce this noise, the LTM4616 can run in spread spectrum operation by tying the CLKIN pin to SVIN . In spread spectrum operation, the LTM4616’s internal oscillator is designed to produce a clock pulse whose period is random on a cycle-by-cycle basis but fixed between 70% and 130% of the nominal frequency. This has the benefit of spreading the switching noise over a range of frequencies, thus significantly reducing the peak noise. Spread spectrum operation is disabled if CLKIN is tied to ground or if it’s driven by an external frequency synchronization signal. A capacitor value of 0.01µF to 0.1µF be placed from the PLLLPF pin to ground to control the slew rate of the spread spectrum frequency change. To ensure proper start-up, add a control ramp on the TRACK pin with a resistor, RSR, from TRACK to SVIN and a capacitor, CSR, from TRACK to ground: RSR ≥ 1 0.592 – In 1– • 500 • C SR VIN 4616fd 15 LTM4616 Applications Information CLKIN1 VIN 4V TO 5.5V VIN1 RUN 10µF RSR SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2 SVIN1 FB1 RUN1 ITH1 PLLLPF1 MASTER 3.3V RTA 6.65k 50k SLAVE 1.5V/8A VOUT2 SVIN2 FB2 RUN2 ITH2 PLLLPF2 RFB2 6.65k ITHM2 MODE2 PGOOD2 PHMODE2 BSEL2 TRACK2 MGN2 SW2 50k MGN1 LTM4616 VIN2 RTB 10k 100µF BSEL1 TRACK1 10µF VIN PGOOD1 PHMODE1 RUN RFB1 2.21k ITHM1 MODE1 CSR MASTER 3.3V/7A VOUT1 SGND1 GND1 SGND2 100µF 100µF PGOOD BSEL GND2 4616 F05 FOR TRACK1: 1. TIE TO VIN TO DISABLE TRACK WITH DEFAULT 100µs SOFT START 2. APPLY A CONTROL RAMP WITH RSR AND CSR TIED TO VIN WITH t = –(ln(1–0.596/VIN) • RSR • CSR)) 3. APPLY AN EXTERNAL TRACKING RAMP DIRECTLY Figure 5. Dual Outputs (3.3V and 1.5V) with Tracking Output Voltage Tracking Output voltage tracking can be programmed externally using the TRACK pin. The output can be tracked up and down with another regulator. The master regulator’s output is divided down with an external resistor divider that is the same as the slave regulator’s feedback divider to implement coincident tracking. The LTM4616 uses an accurate 10k resistor internally for the top feedback resistor. Figure 5 shows an example of coincident tracking: ⎛ 10k ⎞ • VTRACK Slave = ⎜1+ ⎝ R TA ⎟⎠ VTRACK is the track ramp applied to the slave’s track pin. VTRACK has a control range of 0V to 0.596V, or the internal reference voltage. When the master’s output is divided down with the same resistor values used to set the slave’s output, then the slave will coincident track with the master until it reaches its final value. The master will continue to its final value from the slave’s regulation point. Voltage tracking is disabled when VTRACK is more than 0.596V. RTA in Figure 5 will be equal to RFB for coincident tracking. The track pin of the master can be controlled by an external ramp or by RSR and CSR in Figure 5 referenced to VIN . The RC ramp time can be programmed using equation: ⎛ ⎛ 0.596V ⎞ ⎞ • RSR • CSR⎟ t = – ⎜ln ⎜1– ⎟ VIN ⎠ ⎝ ⎝ ⎠ Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master’s track pin. As mentioned above, the TRACK pin has 4616fd 16 LTM4616 Applications Information a control range from 0V to 0.596V. The master’s TRACK pin slew rate is directly equal to the master’s output slew rate in Volts/Time: MR • 10k = R TB SR where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus RTB is equal to 10k. RTA is derived from equation: R TA = 0.596V VFB VFB VTRACK + – 10k RFB R TB where VFB is the feedback voltage reference of the regulator and VTRACK is 0.596V. Since RTB is equal to the 10k top feedback resistor of the slave regulator in coincident tracking, then RTA is equal to RFB2 with VFB = VTRACK . Therefore RTB = 10k and RTA = 6.65k in Figure 5. Figure 6 shows the output voltage for coincident tracking. MASTER OUTPUT For applications that do not require tracking or sequencing, simply tie the TRACK pin to SVIN to let RUN control the turn on/off. Connecting TRACK to SVIN also enables the ~100µs of internal soft-start during start-up. Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point. As shown in Figure 20, the sequencing function can be realized in a dual output application by controlling the RUN pins and the PGOOD signals from each other. The 1.5V output begins its soft starting after the PGOOD signal of 3.3V output becomes high, and 3.3V output starts its shutdown after the PGOOD signal of 1.5V output becomes low. This can be applied to systems that require voltage sequencing between the core and sub-power supplies. Stability Compensation The module has already been internally compensated for all output voltages. Table 2 is provided for most application requirements. LTpowerCAD is available for fine adjustments to the control loop. OUTPUT VOLTAGE (V) Output Margining SLAVE OUTPUT TIME 4616 F06 Figure 6. Output Voltage Coincident Tracking In ratiometric tracking, a different slew rate maybe desired for the slave regulator. RTB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. For example: MR = 3.3V/ms and SR = 1.5V/ms. Then RTB = 22.1k. Solve for RTA to equal to 4.87k. For a convenient system stress test on the LTM4616’s output, the user can program each output to ±5%, ±10% or ±15% of its normal operational voltage. Margining can be disabled by connecting the MGN pin to a voltage divider as shown in Figure 5. When the MGN pin is <0.3V, it forces negative margining, in which the output voltage is below the regulation point. When MGN is >VIN – 0.3V, the output voltage is forced above the regulation point. The MGN pin with a voltage divider is driven with a small tri-state gate as shown in Figure 18 for three margin states, (High, Low, and No Margin). The amount of output voltage margining is determined by the BSEL pin. When BSEL is low, it’s 5%. When BSEL is high, it’s 10%. When BSEL is floating, it’s 15%. When margining is active, the internal output overvoltage and undervoltage comparators are disabled and PGOOD remains high. 4616fd 17 LTM4616 Applications Information Thermal Considerations and Output Current Derating Safety Considerations The LTM4616 modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The device does support thermal shutdown and overcurrent protection. 8 8 7 7 6 6 POWER LOSS (W) POWER LOSS (W) The power loss curves in Figures 7 and 8 can be used in coordination with the load current derating curves in Figures 9 to16 for calculating an approximate θJA thermal resistance for the LTM4616 with various heat sinking and airflow conditions. Both LTM4616 outputs are placed in parallel for a total output current of 16A, and the power loss curves are plotted for specific output voltages up to 16A. The derating curves are plotted with each output at 8A combined for a total of 16A. The output voltages are 1.2V, 2.5V and 3.3V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature increases with and without airflow. The junctions are maintained at ~115°C while lowering output current or power with increasing ambient temperature. The 115°C value is chosen to allow for 10°C of margin relative to the maximum temperature of 125°C. The decreased output current will decrease the internal module loss as ambient temperature is increased. The power loss curves in Figures 7 and 8 show this amount of power loss as a function of load current that is specified with both channels in parallel. The monitored junction temperature of 115°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example, in Figure 10 the load current is derated to 10A at ~ 80°C and the power loss for the 5V to 1.2V at 10A output is ~3.2W. If the 80°C ambient temperature is subtracted from the 115°C maximum junction temperature, then difference of 35°C divided by 3.2W equals a 10.9°C/W. Table 4 specifies a 10.5°C/W value which is very close. Table 4 and Table 5 provide equivalent thermal resistances for 1.2V and 3.3V outputs, with and without airflow and heat sinking. The printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. The PCB dimensions are 95mm × 76mm. The BGA heat sinks are listed below Table 5. At load currents on each channel from 3A to 8A (6A to16A in parallel on the derating curves), the thermal resistance values in Tables 4 and 5 are fairly accurate. As the load currents go below the 3A level on each channel the thermal resistance starts to increase due to the reduced power loss on the board. The approximate thermal resistance values for these lower currents is 15°C/W. 5 4 3 4 3 2 2 1 0 5 3.3VIN 1.2VOUT 3.3VIN 2.5VOUT 0 4 8 12 16 1 0 5VIN 1.2VOUT 5VIN 3.3VOUT 0 4 8 12 16 LOAD CURRENT (A) LOAD CURRENT (A) 4616 F07 Figure 7. 1.2V, 2.5V Power Loss 4616 F08 Figure 8. 1.2V, 3.3V Power Loss 4616fd 18 LTM4616 Applications Information 400 LFM 12 0 LFM LOAD CURRENT (A) 10 200 LFM 8 6 16 14 14 400 LFM 12 10 0 LFM 8 200 LFM 6 2 2 55 70 85 40 100 AMBIENT TEMPERATURE (°C) 0 115 40 50 60 70 80 90 100 AMBIENT TEMPERATURE (°C) 0 110 Figure 10. 5VIN to 1.2VOUT with No Heat Sink Figure 11. 5VIN to 3.3VOUT with BGA Heat Sink 16 16 14 14 14 LOAD CURRENT (A) 400 LFM 10 0 LFM 200 LFM 6 12 400 LFM 0 LFM 10 8 200 LFM 6 12 6 4 2 2 2 50 60 70 80 110 90 100 AMBIENT TEMPERATURE (°C) 0 40 60 80 100 AMBIENT TEMPERATURE (°C) 16 16 14 14 12 400 LFM 10 0 LFM 6 200 LFM 70 90 110 AMBIENT TEMPERATURE (°C) 4616 F14 Figure 14. 3.3VIN to 2.5VOUT with No Heat Sink 12 400 LFM 10 0 LFM 8 200 LFM 6 4 2 0 50 30 Figure 13. 3.3VIN to 1.2VOUT with No Heat Sink LOAD CURRENT (A) LOAD CURRENT (A) Figure 12. 5VIN to 1.2VOUT with BGA Heat Sink 4 200 LFM 4616 F13 4616 F12 8 0 120 0 LFM 8 4 40 400 LFM 10 4 0 115 4616 F11 16 8 55 70 85 40 100 AMBIENT TEMPERATURE (°C) 25 4616 F10 Figure 9. 5VIN to 3.3VOUT with No Heat Sink 12 200 LFM 6 2 25 0 LFM 8 4 4616 F09 LOAD CURRENT (A) 10 4 0 400 LFM 12 4 LOAD CURRENT (A) LOAD CURRENT (A) 14 16 LOAD CURRENT (A) 16 2 40 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (°C) 0 30 50 70 90 110 AMBIENT TEMPERATURE (°C) 4616 F15 Figure 15. 3.3VIN 1.2VOUT with BGA Heat Sink 4616 F16 Figure 16. 3.3VIN 2.5VOUT with BGA Heat Sink 4616fd 19 LTM4616 Applications Information Table 4. 1.2V Output DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK qJA (°C/W) Figures 10, 13 3.3, 5 Figures 7, 8 0 None 10.5 Figures 10, 13 3.3, 5 Figures 7, 8 200 None 8.0 Figures 10, 13 3.3, 5 Figures 7, 8 400 None 7.0 Figures 12, 15 3.3, 5 Figures 7, 8 0 BGA Heat Sink 9.5 Figures 12, 15 3.3, 5 Figures 7, 8 200 BGA Heat Sink 6.3 Figures 12, 15 3.3, 5 Figures 7, 8 400 BGA Heat Sink 5.2 DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK qJA (°C/W) Figure 9 5 Figure 8 0 None 10.5 Table 5. 3.3V Output Figure 9 5 Figure 8 200 None 8.0 Figure 9 5 Figure 8 400 None 7.0 Figure 11 5 Figure 8 0 BGA Heat Sink 9.8 Figure 11 5 Figure 8 200 BGA Heat Sink 7.0 Figure 11 5 Figure 8 400 BGA Heat Sink 5.5 HEAT SINK MANUFACTURER PART NUMBER WEBSITE AAVID Thermalloy 375424B00034G www.aavidthermalloy.com Cool Innovations 4-050503P to 4-050508P www.coolinnovations.com 4616fd 20 LTM4616 Applications Information Layout Checklist/Example • To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. The high integration of LTM4616 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. • Do not put vias directly on the pads, unless they are capped or plated over. • Use large PCB copper areas for high current paths, including VIN1, VIN2 , GND1 and GND2, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress. • Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to GND underneath the unit. • For parallel modules, tie the ITH, FB and ITHM pins together. Use an internal layer to closely connect these pins together. All of the ITHM pins connect to the SGND of the master regulator, then the master SGND connects to GND. • Place high frequency ceramic input and output capacitors next to the VIN, GND and VOUT pins to minimize high frequency noise. • Place a dedicated power ground layer underneath the unit. VIN1 Figure 17 gives a good example of the recommended layout. VOUT1 VIA TO GND EACH CHANNEL CONTROL1 M VIN1 CIN1 COUT2 VOUT1 L K J GND1 H GND1 G CONTROL1 & 2 F VIN2 CIN2 COUT2 VOUT2 E D C B GND2 GND2 A 1 2 GND2 3 4 5 6 7 8 9 CONTROL2 10 11 12 GND2 4616 F17 LTM4616 TOP VIEW Figure 17. Recommended PCB Layout (LGA and BGA PCB Layouts Are Identical with the Exception of Circle Pads for BGA. See Package Description.) 4616fd 21 LTM4616 Applications Information CLKIN1 10µF CLKIN1 CLKOUT1 CLKIN2 CLKOUT2 SVIN1 FB1 RUN1 ITH1 PLLLPF1 PGOOD1 PHMODE1 BSEL1 TRACK1 MGN1 LTM4616 VIN2 10µF 4.87k ITHM1 MODE1 VIN2 3V TO 5.5V VOUT1 1.8V/8A 100µF VOUT1 PGOOD BSEL VOUT2 SVIN2 FB2 RUN2 ITH2 PLLLPF2 R3 50k 6.65k ITHM2 MODE2 PGOOD2 PHMODE2 BSEL2 TRACK2 MGN2 SW2 SGND1 GND1 SGND2 VIN R4 50k PGOOD BSEL GND2 4616 F18 OUT VOUT2 1.5V/8A 100µF ×2 R1 50k IOE IIN GND 5 PIN SC70 PACKAGE VIN R2 50k A2 V+ OUT A1 V+ + – SW1 VIN1 + – VIN1 3V TO 5.5V IOE IIN GND 5 PIN SC70 PACKAGE BSEL: HIGH = 10% FLOAT = 15% LOW = 5% OE IN OUT H H L H L X H L Z A1, A2 PERICOM PI74ST1G126CEX TOSHIBA TC7SZ126AFE MGN MARGIN VALUE + Value of BSEL Selection H – Value of BSEL Selection L VIN/2 No Margin Figure 18. Typical 3V to 5.5VIN, to 1.8V, 1.5V Outputs 4616fd 22 LTM4616 Applications Information VIN 3V TO 5.5V SW1 VIN1 10µF RUN ENABLE CLKIN1 CLKOUT1 CLKIN2 CLKOUT2 SVIN1 FB1 RUN1 ITH1 PLLLPF1 100µF 3.32k ITHM1 MODE1 PGOOD1 PHMODE1 BSEL1 TRACK1 MGN1 LTM4616 VIN2 10µF VOUT 1.5V/16A VOUT1 VOUT2 SVIN2 FB2 RUN2 ITH2 PLLLPF2 100µF ITHM2 MODE2 VIN PGOOD2 PHMODE2 BSEL2 TRACK2 MGN2 SW2 SGND1 GND1 SGND2 100µF 50k GND2 50k 4616 F19 Figure 19. LTM4616 Two Outputs Parallel, 1.5V at 16A Design CLKIN VIN 5V VIN1 22µF SHDNB 100k SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2 SVIN1 FB1 RUN1 ITH1 PLLLPF1 BSEL1 TRACK1 MGN1 LTM4616 100µF 50k 100k SVIN1 SVIN2 FB2 RUN2 ITH2 PLLLPF2 VOUT2 1.5V/8A 6.65k 100µF 100µF ITHM2 PGOOD2 PHMODE2 BSEL2 TRACK2 MGN2 SW2 50k VOUT2 MODE2 PGOOD1 VIN PGOOD1 PHMODE1 VIN2 100k 2.21k ITHM1 MODE1 PGOOD2 VOUT1 3.3V/7A VOUT1 SGND1 GND1 SGND2 GND2 4616 F20 100k SVIN2 SHDNB 3.3V 1.5V Figure 20. LTM4616 Output Sequencing Application 4616fd 23 LTM4616 Applications Information SW1 VIN1 10µF 6.3V CLKIN1 CLKOUT1 CLKIN2 CLKOUT2 SVIN1 FB1 RUN1 ITH1 PLLLPF1 MGN1 LTM4616 VIN2 VOUT2 SVIN2 FB2 RUN2 ITH2 PLLLPF2 VIN1 SGND1 SW1 CLKIN1 GND1 SGND2 CLKOUT1 CLKIN2 GND2 CLKOUT2 SVIN1 VOUT1 FB1 ITH1 RUN1 ITHM1 MODE1 PGOOD1 PHMODE1 BSEL1 TRACK1 MGN1 LTM4616 VIN2 VOUT2 SVIN2 FB2 ITH2 RUN2 PLLLPF2 BSEL2 TRACK2 MGN2 SGND1 GND1 SGND2 GND2 4616 F21 OUT H L Z A1, A2 PERICOM PI74ST1G126CEX TOSHIBA TC7SZ126AFE MGN C5 22µF 6.3V + C4 22µF 6.3V PGOOD2 PHMODE2 SW2 H L X + ITHM2 MODE2 IN C3 470µF 6.3V MGN2 SW2 PLLLPF1 H H L + BSEL2 TRACK2 OE C2 470µF 6.3V PGOOD2 PHMODE2 BSEL: HIGH = 10% FLOAT = 15% LOW = 5% + ITHM2 MODE2 10µF 6.3V VOUT 1.2V AT 32A C1 470µF 6.3V SANYO POSCAP 10mΩ BSEL1 TRACK1 10µF 6.3V 2.47k PGOOD1 PHMODE1 10µF 6.3V + ITHM1 MODE1 TRACK INPUT OR VIN VOUT1 MARGIN VALUE + Value of BSEL Selection H – Value of BSEL Selection L VIN/2 No Margin R1 50k R2 50k A1 V+ OUT GND VIN 3V TO 5.5V + – VIN 3V TO 5.5V IOE IIN 6 PIN SC70 PACKAGE OPTIONAL MARGINING CIRCUIT, IF NOT USED TIE THE MGN PINS TO A VOLTAGE EQUAL TO HALF OF THE RESPECTIVE VIN Figure 21. Four Phase in Parallel, 1.2V at 32A 4616fd 24 LTM4616 Applications Information VIN 4V TO 5.5V VIN1 10µF SVIN1 RUN ENABLE RUN1 SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2 FB1 ITH1 PLLLPF1 BSEL1 TRACK1 FB2 RUN2 ITH2 PLLLPF2 BSEL2 TRACK2 MGN2 SW2 SGND1 SW1 CLKIN1 GND1 SGND2 CLKOUT1 CLKIN2 GND2 CLKOUT2 FB1 RUN1 ITH1 BSEL1 TRACK1 MGN1 LTM4616 VIN2 10µF SVIN2 FB2 ITH2 PLLLPF2 10k 6.65k 100µF ITHM2 MODE2 PGOOD2 PHMODE2 BSEL2 TRACK2 6.65k VOUT4 1.5V/8A 100µF VOUT2 RUN2 3.3V 100µF PGOOD1 PHMODE1 4.99k 4.99k ITHM1 MODE1 10k VOUT3 1.8V/8A 100µF VOUT1 SVIN1 PLLLPF1 3.3V 3.16k PGOOD2 PHMODE2 10µF 50k ITHM2 MODE2 VIN1 VOUT2 2.5V/8A 100µF VOUT2 SVIN2 3.16k 50k MGN1 LTM4616 VIN2 10k VIN PGOOD1 PHMODE1 3.3V 2.21k ITHM1 MODE1 10µF VOUT1 3.3V/7A 100µF VOUT1 MGN2 SW2 SGND1 GND1 SGND2 GND2 4616 F22 Figure 22. 4-Phase, Four Outputs (3.3V, 2.5V, 1.8V and 1.5V) with Tracking 4616fd 25 LTM4616 Package Description Pin Assignment Table (Arranged by Pin Number) PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME A1 GND1 B1 GND1 C1 VIN1 D1 VIN1 E1 VIN1 F1 VIN1 A2 GND1 B2 GND1 C2 VIN1 D2 VIN1 E2 VIN1 F2 VIN1 A3 GND1 B3 GND1 C3 GND1 D3 GND1 E3 VIN1 F3 VIN1 A4 GND1 B4 GND1 C4 GND1 D4 GND1 E4 VIN1 F4 VIN1 A5 GND1 B5 GND1 C5 GND1 D5 GND1 E5 SVIN1 F5 SGND1 A6 BSEL1 B6 SW1 C6 GND1 D6 GND1 E6 PLLLPF1 F6 RUN1 A7 CLKIN1 B7 GND1 C7 GND1 D7 GND1 E7 ITHM1 F7 CLKOUT1 A8 MODE1 B8 GND1 C8 GND1 D8 FB1 E8 TRACK1 F8 ITH1 A9 PHMODE1 B9 GND1 C9 GND1 D9 VOUT1 E9 VOUT1 F9 VOUT1 A10 MGN1 B10 GND1 C10 GND1 D10 VOUT1 E10 VOUT1 F10 VOUT1 A11 PGOOD1 B11 GND1 C11 GND1 D11 VOUT1 E11 VOUT1 F11 VOUT1 A12 GND1 B12 GND1 C12 GND1 D12 VOUT1 E12 VOUT1 F12 VOUT1 PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME G1 GND2 H1 GND2 J1 VIN2 K1 VIN2 L1 VIN2 M1 VIN2 G2 GND2 H2 GND2 J2 VIN2 K2 VIN2 L2 VIN2 M2 VIN2 G3 GND2 H3 GND2 J3 GND2 K3 GND2 L3 VIN2 M3 VIN2 G4 GND2 H4 GND2 J4 GND2 K4 GND2 L4 VIN2 M4 VIN2 G5 GND2 H5 GND2 J5 GND2 K5 GND2 L5 SVIN2 M5 SGND2 G6 BSEL2 H6 SW2 J6 GND2 K6 GND2 L6 PLLLPF2 M6 RUN2 G7 CLKIN2 H7 GND2 J7 GND2 K7 GND2 L7 ITHM2 M7 CLKOUT2 G8 MODE2 H8 GND2 J8 GND2 K8 FB2 L8 TRACK2 M8 ITH2 G9 PHMODE2 H9 GND2 J9 GND2 K9 VOUT2 L9 VOUT2 M9 VOUT2 G10 MGN2 H10 GND2 J10 GND2 K10 VOUT2 L10 VOUT2 M10 VOUT2 G11 PGOOD2 H11 GND2 J11 GND2 K11 VOUT2 L11 VOUT2 M11 VOUT2 G12 GND2 H12 GND2 J12 GND2 K12 VOUT2 L12 VOUT2 M12 VOUT2 4616fd 26 4 3.1750 1.9050 3.1750 SUGGESTED PCB LAYOUT TOP VIEW 0.6350 0.0000 0.6350 PACKAGE TOP VIEW E 1.9050 PIN “A1” CORNER 6.9850 5.7150 4.4450 4.4450 5.7150 6.9850 aaa Z Y 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 X D aaa Z bbb Z 0.27 2.45 MIN 2.72 0.60 NOM 2.82 0.63 15.00 15.00 1.27 13.97 13.97 0.32 2.50 DIMENSIONS eee S X Y H1 SUBSTRATE 0.37 2.55 0.15 0.10 0.05 MAX 2.92 0.66 NOTES DETAIL B PACKAGE SIDE VIEW A TOTAL NUMBER OF LGA PADS: 144 SYMBOL A b D E e F G H1 H2 aaa bbb eee DETAIL A 0.630 ±0.025 SQ. 143x DETAIL B H2 MOLD CAP Z (Reference LTC DWG # 05-08-1816 Rev B) LGA Package 144-Lead (15mm × 15mm × 2.82mm) e b 11 10 9 3x, C (0.22 x45°) 7 G 6 e 5 PACKAGE BOTTOM VIEW 8 4 3 1 DETAIL A 2 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 4 TRAY PIN 1 BEVEL LGA 144 1111 REV B PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX µModule 5. PRIMARY DATUM -Z- IS SEATING PLANE BALL DESIGNATION PER JESD MS-028 AND JEP95 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 COMPONENT PIN “A1” 3 SEE NOTES F b 12 A B C D E F G H J K L M DIA 0.630 PAD 1 LTM4616 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4616fd 27 aaa Z 0.630 ±0.025 Ø 144x E PACKAGE TOP VIEW 3.1750 3.1750 SUGGESTED PCB LAYOUT TOP VIEW 1.9050 4 0.6350 0.0000 0.6350 PIN “A1” CORNER 1.9050 28 Y 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 X D 2.45 – 2.55 aaa Z SYMBOL A A1 A2 b b1 D E e F G aaa bbb ccc ddd eee NOM 3.42 0.60 2.82 0.75 0.63 15.0 15.0 1.27 13.97 13.97 DIMENSIONS 0.15 0.10 0.20 0.30 0.15 MAX 3.62 0.70 2.92 0.90 0.66 NOTES DETAIL B PACKAGE SIDE VIEW TOTAL NUMBER OF BALLS: 144 MIN 3.22 0.50 2.72 0.60 0.60 DETAIL A b1 0.27 – 0.37 SUBSTRATE ddd M Z X Y eee M Z DETAIL B MOLD CAP ccc Z A1 A2 A Z (Reference LTC DWG # 05-08-1902 Rev A) Øb (144 PLACES) // bbb Z BGA Package 144-Lead (15mm × 15mm × 3.42mm) e b 11 10 9 7 G 6 e 5 PACKAGE BOTTOM VIEW 8 4 3 2 1 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE BALL DESIGNATION PER JESD MS-028 AND JEP95 TRAY PIN 1 BEVEL BGA 144 1011 REV A PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX µModule 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu 5. PRIMARY DATUM -Z- IS SEATING PLANE 4 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 COMPONENT PIN “A1” 3 SEE NOTES F b 12 DETAIL A A B C D E F G H J K L M PIN 1 LTM4616 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4616fd 6.9850 5.7150 4.4450 4.4450 5.7150 6.9850 LTM4616 Revision History REV DATE DESCRIPTION C 2/11 Updated Features (Revision history begins at Rev C) PAGE NUMBER 1 Updated Pin Configuration Updated Electrical Characteristics Replaced graphs G05 and G06 5 Updated graph G18 6 Updated Pin Functions 7 Updated Simplified Block Diagram 8 Updated Operation section D 3/12 2 2, 3, 4 9 Text updated in Applications Information section 10 through 20 Updated figures 3, 5, 17, 18, 19, 20, 21, 22 13 through 24 Updated Package Description table 25 Added Package Photo and updated Related Parts 28 Added BGA package option and MP temperature grade 1 Added BGA package option, MP temperature grade, thermal resistance, and device weight 2 Updated Note 2 4 Clarified Load Transient Response conditions 5 Updated recommended heat sinks Table 20 Corrected MGN Pin usage 24 Added package photo 30 4616fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 29 LTM4616 Package Photo Related Parts PART NUMBER DESCRIPTION COMMENTS LTC6908-2 Resistor Set Oscillator with Spread Spectrum Modulation Two Outputs 0°/90°, TSOT-23 and 2mm × 3mm DFN Packages LTM4600 10A DC/DC µModule Regulator Basic 10A DC/DC µModule Regulator, LGA Package LTM4600HVMP Military Plastic 10A DC/DC µModule Regulator Guaranteed Operation from –55°C to 125°C Ambient, LGA Package LTM4601/ LTM4601A 12A DC/DC µModule Regulator with PLL, Output Tracking/Margining and Remote Sensing Synchronizable, PolyPhase Operation, LTM4601-1/LTM4601A-1 Version Has No Remote Sensing, LGA Package LTM4602 6A DC/DC µModule Regulator Pin Compatible with the LTM4600, LGA Package LTM4603 6A DC/DC µModule Regulator with PLL and Output Tracking/Margining and Remote Sensing Synchronizable, PolyPhase Operation, LTM4603-1 Version Has No Remote Sensing, Pin Compatible with the LTM4601, LGA Package LTM4604A Low VIN 4A DC/DC µModule Regulator 2.375V ≤ VIN ≤ 5.5V, 0.8V ≤ VOUT ≤ 5V, 9mm × 15mm × 2.32mm LGA Package LTM4608A Low VIN 8A DC/DC µModule Regulator 2.7V ≤ VIN ≤ 5.5V; 0.6V ≤ VOUT ≤ 5V; 9mm × 15mm × 2.82mm LGA Package LTM8022/LTM8023 36VIN, 1A and 2A DC/DC µModule Regulator Pin Compatible; 4.5V ≤ VIN ≤ 36V; 9mm × 11.25mm × 2.82mm LGA Package 4616fd 30 Linear Technology Corporation LT 0312 REV D • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear.com LINEAR TECHNOLOGY CORPORATION 2008