DATASHEET Dual 15A/Single 30A Step-Down Power Module ISL8225M Features The ISL8225M is a fully-encapsulated step-down switching power supply that can deliver up to 100W output power from a small 17mm square PCB footprint. The two 15A outputs may be used independently or combined to deliver a single 30A output. Designing a high-performance board mounted power supply has never been simpler -- only a few external components are needed to create a very dense and reliable power solution. • Fully-encapsulated dual step-down switching power supply Automatic current sharing and phase interleaving allow up to six modules to be paralleled for 180A output capability. 1.5% output voltage accuracy, differential remote voltage sensing and fast transient response create a very high-performance power system. Built-in output overvoltage, overcurrent and over-temperature protection enhance system reliability. The ISL8225M is available in a thermally-enhanced QFN package. Excellent efficiency and low thermal resistance permit full power operation without heat sinks or fans. In addition, the QFN package with external leads permits easy probing and visual solder inspection. • AN1789 “ISL8225MEVAL2Z Evaluation Board User Guide” • AN1790 “ISL8225MEVAL3Z Evaluation Board User Guide” • AN1793, “ISL8225MEVAL4Z Evaluation Board User Guide” • ISL8225M 110A Thermal Performance Video 4.5V TO 20V 4x22µF VIN1 VIN2 OFF ON VSEN1+ EN/FF2 VSEN2- VSEN1ISL8225M PGND SGND MODE • Up to 95% conversion efficiency • 4.5V to 20V input voltage range • 0.6V to 7.5V output voltage range • 1.5% output voltage accuracy with differential remote sensing • Up to six modules may be paralleled to support 180A output current • Output overvoltage, overcurrent and over-temperature protection • Full power operation without heat sinks or fans • QFN package with exposed leads permits easy probing and visual solder inspection • Computing, networking and telecom infrastructure equipment • Industrial and medical equipment • General purpose point-of-load (POL) power 17m m 17 mm 1kΩ RSET 1kΩ 5x100µF 7.5mm VMON1 VMON2 VCC 4.7µF 1.2V AT 30A VOUT VOUT1 VOUT2 EN/FF1 • Dual 15A or single 30A output Applications Related Literature VIN • Up to 100W output from a 17mmx17mm square PCB footprint COMP1 COMP2 470pF NOTE: ALL PINS NOT SHOWN ARE FLOATING. FIGURE 1. COMPLETE 30A STEP-DOWN POWER SUPPLY December 8, 2014 FN7822.2 1 FIGURE 2. SMALL FOOTPRINT WITH HIGH POWER DENSITY CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012-2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL8225M Table of Contents Pinout Internal Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transient Response Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-up and Short Circuit Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 12 Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selection of Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selection of Output Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EN/FF Turn ON/OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 22 23 23 23 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable and Voltage Feed-forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Share . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over-Temperature Protection (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent Protection (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Synchronization and Phase Lock Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tracking Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two Phase Parallel Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 23 24 24 25 25 25 25 25 26 26 27 27 28 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB Layout Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 28 28 28 Derating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Submit Document Feedback 2 FN7822.2 December 8, 2014 ISL8225M Pinout Internal Circuit VCC 7 FILTER 2.2µF 14 VIN1 15 EN/FF1 12 PHASE1 23 VOUT1 13 PGND 22 VSEN1+ 21 VSEN1- 18 VMON1 20 COMP1 8 VIN2 16 EN/FF2 10 PHASE2 25 VOUT2 9 PGND + 26 VSEN2+ - 1 VSEN2- 4 VMON2 2 COMP2 LDO PGOOD SOFT-START AND FAULT LOGIC UGATE1 24 GATE DRIVER CLKOUT 17 ISHARE 19 Q1 L1 LGATE1 0.32µH Q2 CURRENT SENSING/ SHARING 10k ISEN1B ISEN1A + MODE DIFF AMP1 3 - ZCOMP1 - 5 INTERNAL REFERENCE ERROR AMP1 + SYNC ZCOMP2 SOFT-START AND FAULT LOGIC UGATE2 GATE DRIVER Q3 L2 0.32µH LGATE2 Q4 CURRENT ISEN2B SENSING/ SHARING ISEN2A SGND DIFF AMP2 6 ZCOMP3 ZCOMP4 - Submit Document Feedback 3 MODE + INTERNAL REFERENCE ERROR AMP2 7.5k FN7822.2 December 8, 2014 ISL8225M Ordering Information PART NUMBER (Notes 2, 3) PART MARKING TEMP RANGE (°C) (Note 4) PACKAGE (RoHS Compliant) PKG. DWG. # ISL8225MIRZ ISL8225M -40 to +125 26 Ld QFN L26.17x17 ISL8225MIRZ-T (Note 1) ISL8225M -40 to +125 26 Ld QFN L26.17x17 ISL8225MEVAL2Z 6 Phase 90A Evaluation Board ISL8225MEVAL3Z Dual Phase Single Output 30A Evaluation Board ISL8225MEVAL4Z Dual 15A/optional 30A Cascadable Evaluation Board NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil plastic packaged products are RoHS compliant by EU exemption 7C-I and employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3) termination finish which is compatible with both SnPb and Pb-free soldering operations. Intersil RoHS compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8225M. For more information on MSL, please see tech brief TB363 4. The ISL8225M is guaranteed over the full -40°C to +125°C internal junction temperature range. Note that the allowed ambient temperature consistent with these specifications is determined by specific operating conditions, including board layout, cooling scheme and other environmental factors. Submit Document Feedback 4 FN7822.2 December 8, 2014 ISL8225M Pin Configuration VIN2 VCC SGND SYNC VMON2 MODE COMP2 8 7 6 5 4 3 2 PIN 1 1 VSEN2- 26 VSEN2+ 25 VOUT2 24 PGOOD 23 VOUT1 22 VSEN1+ 21 VSEN1- 5 13 14 15 16 17 18 19 20 CLKOUT VMON1 ISHARE COMP1 12 EN/FF2 PHASE1 EN/FF1 11 VIN1 10 N/C Submit Document Feedback 9 PGND PHASE2 PGND ISL8225M (26 LD QFN) TOP VIEW FN7822.2 December 8, 2014 ISL8225M Pin Descriptions PIN# PIN NAME TYPE 21, 1 VSEN1-, VSEN2- I 20, 2 COMP1, COMP2 I/O Error amplifier outputs. Typically floating for dual-output use. For parallel use, a 470pF~1nF capacitor is recommended on the COMP pins of each SLAVE phase to eliminate the coupling noise. All COMP pins of SLAVE phases need to tie to MASTER phase COMP1 pin (first phase). Internal compensation networks are implemented for working in the full range of I/O conditions. 3 18, 4 MODE I DESCRIPTION Output voltage negative feedback. Negative input of the differential remote sense for the regulator. Connect to the negative rail or ground of the load/processor, as shown in Figure 19. The negative feedback pins can be used to program the module operation conditions. See Tables 3 and 5 for details. Mode setting. Typically floating for dual-output use; tie to SGND for parallel use. See Tables 3 and 5 for details. When VSEN2- is pulled within 700mV of VCC, the 2nd channel’s remote sensing amplifier is disabled. The MODE pin, as well as the VSEN2+ pin, determine relative phase-shift between the two channels and the CLKOUT signal output. VMON1, VMON2 I/O Remote sensing amplifier outputs. These pins are connected internally to OV/UV/PGOOD comparators, so they can’t be floated when the module works in multi-phase operation. When VSEN1-, VSEN2- are pulled within 700mV of VCC, the corresponding remote sensing amplifier is disabled; the output (VMON pin) is in high impedance. In this event, the VMON pins can be used as an additional monitor of the output voltage, with a resistor divider to protect the system against single point of failure. The default setting voltage is 0.6V. See Table 3 for details. 5 SYNC 6 SGND 7 VCC 14, 8 VIN1, VIN2 9, 13 PGND 12, 10 PHASE1, PHASE2 I Signal synchronization. An optional external resistor (RSYNC) connected from this pin to SGND increases oscillator switching frequency (Figure 33 and Table 1). The internal default frequency is 500kHz with this pin floating. Also, the internal oscillator can lock to an external frequency source or the CLKOUT signal from another ISL8225M. Input voltage range for external source: 3V to 5V square wave. No capacitor is recommended on this pin. PWR Control signal ground. Connect to PGND under the module in the quiet inner layer. Make sure to have the single location for the connection between SGND and PGND to avoid noise coupling. See “Layout Guide” on page 27. PWR 5V internal linear regulator output. Voltage range: 3V to 5.6V. The decoupling ceramic capacitor for the VCC pin is recommended to be 4.7µF. PWR Power inputs. Input voltage range: 4.5V to 20V. Tie directly to the input rail. VIN1 provides power to the internal linear drive circuitry. When the input is 4.5V to 5.5V, VIN should be tied directly to VCC. PWR Power ground. Power ground pins for both input and output returns. PWR Phase node. Use for monitoring switching frequency. Phase pins should be floating or used for snubber connections.To achieve better thermal performance, the phase planes can also be used for heat removal with thermal vias connected to large inner layers. See “Layout Guide” on page 27 11 N/C 15, 16 EN/FF1, EN/FF2 I/O Enable and feed-forward control. Tie a resistor divider to VIN or use the system enable signal for this pin. The voltage turn-on threshold is 0.8V. With a voltage lower than the threshold, the corresponding channel can be disabled independently. By connecting to VIN with a resistor divider, the input voltage can be monitored for UVLO (undervoltage lockout) function. The voltage on each EN/FF pin is also used to adjust the internal control loop gain independently to realize the feed-forward function. Please set the EN/FF between 1.25V to 5V. A 1nF capacitor is recommended on each EN/FF pin. Please see Table 1 to select resistor divider and application details in “EN/FF Turn ON/OFF” on page 23. 17 CLKOUT I/O Clock out. Provide the clock signal for the input synchronization signal of other ISL8225Ms. Typically tied to VCC for dual-output use with 180° phase-shift. See Tables 3 and 5 when using more than one ISL8225M. When the module is in dual-output mode, the clock-out signal is disabled. By programming the voltage level of this CLKOUT pin, the module can work for DDR/tracking or as two independent outputs with selectable phase-shift (see Table 6). 19 ISHARE O Current sharing control. Tie all ISHARE pins together when multiple modules are configured for current sharing and share a common current output. The ISHARE voltage represents the average current of all active and connected channels. A 470pF capacitor is recommended for each ISHARE pin for multiple phase applications. Typically, the ISHARE pin should be floating for dual-output or single module application. 22, 26 VSEN1+, VSEN2+ I Output voltage positive feedback. Positive inputs of differential remote sense for the regulator. A resistor divider can be connected to this pin to program the output voltage. It is recommended to put the resistor divider close to the module and connect the kelvin sensing traces of VOUT and VSEN- to the sensing points of the load/processor (see Figure 19). The VSEN2+ pin can be used to program the module operation conditions. See Tables 3 and 5 for details. 23, 25 24 - Non-connection pin. This pin is floating with no connection inside. VOUT1, VOUT2 PWR Power Output. Apply output load between these pins and PGND pins. Output voltage range: 0.6V to 7.5V. PGOOD Submit Document Feedback O Power good. Provide open-drain power-good signal when the output is within 9% of the nominal output regulation point with 4% hysteresis (13%/9%) and soft-start complete. PGOOD monitors the outputs (VMON) of the internal differential amplifiers. 6 FN7822.2 December 8, 2014 ISL8225M Absolute Maximum Ratings Thermal Information Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +25V Driver Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Phase Voltage, VPHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +30V Input, Output or I/O Control Voltage . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . 750V Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) JA (°C/W) JC (°C/W) QFN Package (Notes 5, 6) . . . . . . . . . . . . . . 10.0 0.9 Maximum Storage Temperature Range . . . . . . . . . . . . . .-55°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to Figure 48 Recommended Operating Conditions Input Voltage, VIN1 and VIN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 20.0V Output Voltage, VOUT1 and VOUT2 . . . . . . . . . . . . . . . . . . . . . . . 0.6V to 7.5V Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For JC, the “case temp” location is the center of the phase exposed metal pad on the package underside. Electrical Specifications TA = +25°C, VIN = 12V, unless otherwise noted. Boldface limits apply across the internal junction temperature range, -40°C to +125°C (Note 4). PARAMETER SYMBOL TEST CONDITIONS MIN TYP (Note 7) (Note 8) MAX (Note 7) UNITS VCC SUPPLY CURRENT Nominal Supply VIN Current IQ_VIN VIN = 20V; no load; EN1 = EN2 = high 131 mA VIN1 = 20V; no load; EN1 = high, EN2 = low 72 mA 71 mA VIN1 = 12V; no load; EN1 = high, EN2 = high VIN2 = 20V; no load; EN1 = 0, EN2 = high 134 mA VIN = 4.5V; no load; EN1 = EN2 = high 136 mA VIN1 = 4.5V; no load; EN1 = high, EN2 = low 73 mA VIN2 = 4.5V; no load; EN1 = 0, EN2 = high 70 mA 250 mA 1 Ω INTERNAL LINEAR REGULATOR (Note 9) Maximum Current IPVCC VCC = 4V to 5.6V Saturated Equivalent Impedance RLDO P-Channel MOSFET (VIN = 5V) VCC Voltage Level VCC IVCC = 0mA 5.1 5.4 5.6 V POWER-ON RESET (Note 9) Rising VCC Threshold 0°C to +75°C 2.85 2.97 V -40°C to +85°C 2.85 3.05 V 2.65 2.75 Falling VCC Threshold System Soft-start Delay tSS_DLY After PLL and VCC PORs, and EN above their thresholds 384 V Cycles ENABLE (Note 9) Turn-on Threshold Voltage Hysteresis Sink Current IEN_HYS Undervoltage Lockout Hysteresis VEN_HYS VEN_RTH = 10.6V; VEN_FTH = 9V, RUP = 53.6kΩ, RDOWN = 5.23kΩ Sink Current IEN_SINK VENFF = 1V Sink Impedance REN_SINK IEN_SINK = 5mA, VENFF = 1V Submit Document Feedback 7 0.75 0.8 0.86 V 23 30 35 µA 1.6 V 15.4 mA 64 Ω FN7822.2 December 8, 2014 ISL8225M Electrical Specifications TA = +25°C, VIN = 12V, unless otherwise noted. Boldface limits apply across the internal junction temperature range, -40°C to +125°C (Note 4). (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP (Note 7) (Note 8) MAX (Note 7) UNITS OSCILLATOR Oscillator Frequency fOSC SYNC pin is open VCC = 5V; -40°C < TA < +85°C Total Variation (Note 9) 510 -9 kHz +9 % 1500 kHz FREQUENCY SYNCHRONIZATION AND PHASE LOCK LOOP (Note 9) Synchronization Frequency VCC = 5V PLL Locking Time VCC = 5.4V, fSW = 500kHz Input Signal Duty Cycle Range 300 130 10 µs 90 % PWM (Note 9) Minimum PWM OFF Time 310 tMIN_OFF Current Sampling Blanking Time 345 410 175 tBLANKING ns ns OUTPUT CHARACTERISTICS Output Continuous Current Range IOUT(DC) VIN = 12V, VOUT1 = 1.5V 0 15 A VIN = 12V, VOUT2 = 1.5V 0 15 A VIN = 12V, VOUT = 1.5V, in Parallel mode 0 30 A VOUT/VIN VIN = 4.5V to 20V Line Regulation Accuracy VOUT1 = 1.5V, IOUT1 = 0A 0.0065 % VOUT2 = 1.5V, IOUT2 = 0A 0.0065 % VOUT1 = 1.5V, IOUT1 = 15A 0.01 % VOUT2 = 1.5V, IOUT2 = 15A 0.01 % VIN = 4.5V to 20V VOUT/VOUT VIN = 12V, 5x22µF, 2x4.7µF ceramic capacitor and 1x330µF POSCAP Load Regulation Accuracy VOUT Output Ripple Voltage IOUT1 = 0A to 15A, VOUT1 = 1.5V 0.3 1 % IOUT2 = 0A to 15A, VOUT2 = 1.5V 0.3 1 % VIN = 12V, 3x100µF ceramic capacitor and 1x330µF POSCAP IOUT1 = 0A, VOUT1 = 1.5V 11 mVP-P IOUT2 = 0A, VOUT2 = 1.5V 11 mVP-P IOUT1 = 15A, VOUT1 = 1.5V 14 mVP-P IOUT2 = 15A, VOUT2 = 1.5V 14 mVP-P IOUT1 = 0A to 7.5A 75 mVP-P IOUT2 = 0A to 7.5A 75 mVP-P IOUT1 = 7.5A to 0A 70 mVP-P IOUT2 = 7.5A to 0A 70 mVP-P DYNAMIC CHARACTERISTICS Voltage Change for Positive Load Step Voltage Change for Negative Load Step VOUT-DP VOUT-DN Current slew rate = 2.5A/µs VIN = 12V, VOUT = 1.5V, 2x47µF ceramic capacitor and 1x330µF POSCAP Current slew rate = 2.5A/µs VIN = 12V, VOUT = 1.5V, 2x47µF ceramic capacitor and 1x330µF POSCAP REFERENCE (Note 9) Reference Voltage (Include Error and Differential Amplifier Offsets) VREF1 Reference Voltage (Include Error and Differential Amplifier Offsets) VREF2 Submit Document Feedback 8 TA = -40°C to +85°C 0.5958 0.6 -0.7 TA = -40°C to +85°C 0.5955 -0.75 0.6 0.6042 V 0.7 % 0.6057 V 0.95 % FN7822.2 December 8, 2014 ISL8225M Electrical Specifications TA = +25°C, VIN = 12V, unless otherwise noted. Boldface limits apply across the internal junction temperature range, -40°C to +125°C (Note 4). (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP (Note 7) (Note 8) MAX (Note 7) UNITS DIFFERENTIAL AMPLIFIER (Note 9) DC Gain UG_DA Unity Gain Bandwidth Unity gain amplifier 0 UGBW_DA VSEN+ Pin Sourcing Current IVSEN+ Maximum Source Current for Current Sharing IVSEN1- Input Impedance RVSEN+_to _VSEN- 5 0.2 1 MHz 2.5 µA VSEN1- Source Current for Current Sharing when parallel multiple modules, each of which has its own voltage loop 350 µA VVSEN+/IVSEN+, VVSEN+ = 0.6V -600 kΩ Output Voltage Swing 0 Input Common Mode Range VCC - 1.8 VCC - 1.8 -0.2 Disable Threshold dB VVSEN- VMON1, 2 = tri-state Ilimit1 VIN = 12V, VOUT1 = 1.5V, RSYNC = Open Ilimit2 VIN = 12V, VOUT2 = 1.5V, RSYNC = Open V V VCC - 0.4 V 20 A OVERCURRENT PROTECTION (Note 9) Channel Overcurrent Limit Share Pin OC Threshold VOC_SET VCC = 5V (comparator offset included) I/IOUT VIN = 12V, VOUT = 1.5V IOUT = 30A, VSEN2- = high 20 1.16 1.20 A 1.22 V CURRENT SHARE Current Share Accuracy ±10 % POWER-GOOD MONITOR (Note 9) Undervoltage Falling Trip Point VUVF Undervoltage Rising Hysteresis VUVR_HYS Overvoltage Rising Trip Point VOVR Overvoltage Falling Hysteresis VOVF_HYS Percentage below reference point -15 -13 11 13 Percentage above UV trip point Percentage above reference point IPGOOD = 2mA Sinking Impedance IPGOOD = 2mA Maximum Sinking Current VPGOOD < 0.8V % 15 % 4 Percentage below OV trip point PGOOD Low Output Voltage -11 % 4 % 0.35 70 10 V Ω mA OVERVOLTAGE PROTECTION (Note 9) OV Latching-up Trip Point EN/FF = UGATE = LATCH Low, LGATE = High OV Non Latching-up Trip Point EN = Low, UGATE = Low, LGATE = High LGATE Release Trip Point EN = Low/HIGH, UGATE = Low, LGATE = Low 118 120 122 % 113 % 87 % Over-Temperature Trip (Controller Junction Temperature) 150 °C Over-Temperature Release Threshold (Controller Junction Temperature) 125 °C OVER-TEMPERATURE PROTECTION (Note 9) NOTES: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. Parameters with TYP limits are not production tested, unless otherwise specified. 9. Parameters are 100% tested for internal IC prior to module assembly. Submit Document Feedback 9 FN7822.2 December 8, 2014 ISL8225M Typical Performance Characteristics Efficiency Performance TA = +25°C, if not specified, as shown in Figure 18 with 2nd phase disabled. The efficiency equation is as follows: V OUT xI OUT P OUT Output Power Efficiency = ----------------------------------------- = ---------------- = -------------------------------------P IN V IN xI IN Input Power 100 3.3V 95 100 1.8V 2.5V 90 EFFICIENCY (%) EFFICIENCY (%) 90 85 1V 80 1.5V 1.2V 75 70 85 80 70 65 60 60 55 55 0 2 4 6 8 10 LOAD CURRENT (A) 12 14 50 16 2.5V AT 500kHz 75 65 50 1.8V AT 500kHz 2 95 EFFICIENCY (%) 80 75 70 1.2V AT 500kHz 1.8V AT 500kHz 2.5V AT 500kHz 1.5V AT 500kHz 1V AT 500kHz 60 55 12 14 16 2.5VOUT 1.8VOUT 95 85 65 6 8 10 LOAD CURRENT (A) FIGURE 4. EFFICIENCY vs LOAD CURRENT (12VIN) 5V AT 900kHz 90 EFFICIENCY (%) 4 6.5V AT 750kHz 7.5V AT 750kHz 1V AT 500kHz 7.5V AT 750kHz 0 100 100 1.2V AT 500kHz 1.5V AT 500kHz 6.5V AT 750kHz FIGURE 3. EFFICIENCY vs LOAD CURRENT (5VIN AT 500kHz) 50 5V AT 850kHz 3.3V AT 650kHz 95 90 1.2VOUT 85 1.5VOUT 1VOUT 80 75 3.3V AT 650kHz 0 2 4 6 8 10 12 14 70 0 16 5 10 15 20 25 30 LOAD CURRENT (A) LOAD CURRENT (A) FIGURE 5. EFFICIENCY vs LOAD CURRENT (20VIN) FIGURE 6. EFFICIENCY vs LOAD CURRENT (PARALLEL SINGLE OUTPUT, AS SHOWN IN Figure 19 AT 5VIN/500kHz) 95 1.8VOUT 2.5VOUT 90 EFFICIENCY (%) 85 1.5VOUT 1.2VOUT 80 1VOUT 75 70 65 60 0 5 10 15 20 25 30 LOAD CURRENT (A) FIGURE 7. EFFICIENCY vs LOAD CURRENT (PARALLEL SINGLE OUTPUT, AS SHOWN IN Figure 19 AT 12VIN/500kHz Submit Document Feedback 10 FN7822.2 December 8, 2014 ISL8225M Typical Performance Characteristics (Continued) Transient Response Performance VIN = 12V, COUT = 1x10µF and 3x100µF ceramic capacitors, IOUT = 0A to 7.5A, current slew rate = 2.5A/µs. TA = +25°C, if not specified, as shown in Figure 18 with 2nd phase disabled. 50mV/DIV 50mV/DIV 50mV/DIV 2A/DIV 2A/DIV 2A/DIV 200µs/DIV 200µs/DIV 200uS/DIV FIGURE 8. 1VOUT TRANSIENT RESPONSE FIGURE 9. 1.2VOUT TRANSIENT RESPONSE 50mV/DIV 50mV/DIV 50mV/DIV 50mV/DIV 2A/DIV 2A/DIV 2A/DIV 2A/DIV 200µs/DIV 200uS/DIV FIGURE 10. 1.5VOUT TRANSIENT RESPONSE 200µs/DIV 200uS/DIV FIGURE 11. 1.8VOUT TRANSIENT RESPONSE 50mV/DIV 50mV/DIV 100mV/DIV 100mV/DIV 2A/DIV 2A/DIV 2A/DIV 2A/DIV 200µs/DIV 200uS/DIV FIGURE 12. 2.5VOUT TRANSIENT RESPONSE Submit Document Feedback 11 200µs/DIV 200uS/DIV FIGURE 13. 3.3VOUT TRANSIENT RESPONSE FN7822.2 December 8, 2014 ISL8225M Typical Performance Characteristics (Continued) Start-up and Short Circuit Performance VIN = 12V, VOUT = 1.5V, CIN = 1x180µF, 2 x 10µF/Ceramic, COUT = 2x47µF and 1x330µF POSCAP. TA = +25°C, if not specified, as shown in Figure 18 with 2nd phase disabled. VOUT Vout VVout OUT 0.5V/DIV 0.5V/DIV 0.5V/DIV 0.5V/DIV IIin IN IIN Iin 0.1A/DIV 0.1A/DIV 0.1A/DIV 1A/DIV 1ms/DIV 1ms/DIV 1ms/DIV 1ms/DIV FIGURE 14. START-UP AT 0A FIGURE 15. START-UP AT 15A V Vout OUT VVout OUT 0.5V/DIV 0.5V/DIV 0.5V/DIV 0.5V/DIV IIin IN IIin IN 0.2A/DIV 0.2A/DIV 0.5A/DIV 0.5A/DIV 100us/DIV 100µs/DIV FIGURE 16. SHORT CIRCUIT AT 0A Submit Document Feedback 12 100µs/DIV 100us/DIV FIGURE 17. SHORT CIRCUIT AT 15A FN7822.2 December 8, 2014 ISL8225M Typical Application Circuits CIN1 330µF + CIN2 4x22µF 8 15 R5* 16 7 R6* 17 C1 4.7µF 3 19 *SEE Table 1 on page 19 FOR R5/R6 VALUES. 5 20 2 VIN1 VOUT1 VIN2 VSEN1+ EN/FF1 VSEN1- EN/FF2 VOUT2 VCC VSEN2+ CLKOUT ISL8225M VSEN2- MODE VMON1 ISHARE VMON2 SYNC PHASE1 COMP1 PHASE2 COMP2 6 PGND 14 SGND 4.5V TO 20V VIN PGOOD 23 22 21 CFF (OPTIONAL) R2* 1kΩ R1* 1kΩ COUT1 2x47µF R3* 1kΩ 1.5V AT 15A VOUT2 + COUT4 330µF COUT3 2x47µF 25 26 1 CFF (OPTIONAL) R4* 665Ω 1.2V AT 15A VOUT1 + COUT2 330µF 18 *SEE Table 4 on page 22, RESISTORS SET ON VSEN+ AND VSEN- PINS. 4 12 10 24 9 SEE “LAYOUT GUIDE” ON PAGE 27 FOR SHORTING SGND TO PGND FIGURE 18. DUAL OUTPUTS FOR 1.2V/15A AND 1.5V/15A CIN1 330µF + CIN2 4x22µF 8 15 R3* 16 7 17 R4* C1 4.7µF 3 19 *SEE Table 1 on page 19 FOR R3/R4 VALUES. 5 20 2 C2 470pF VIN1 VOUT1 VIN2 VSEN1+ EN/FF1 VSEN1- EN/FF2 VOUT2 VSEN2+ VCC CLKOUT ISL8225M VSEN2- MODE VMON1 ISHARE VMON2 21 26 1 9 COUT 5x100µF LOAD KELVIN REMOTE SENSING LINES VCC 18 4 12 PHASE2 10 6 R1 1kΩ R2 665Ω 25 COMP1 PGOOD VOUT 22 PHASE1 COMP2 1.5V AT 30A 23 SYNC PGND 14 SGND 4.5V TO 20V VIN 24 2Ω 2200pF SIZE:1210 2Ω SIZE:1210 2200pF OPTIONAL SNUBBER FOR NOISE ATTENUATION. SEE Figure 34 on page 28. SEE “LAYOUT GUIDE” ON PAGE 27 FOR SHORTING SGND TO PGND FIGURE 19. PARALLEL USE FOR SINGLE 1.5V/30A OUTPUT WITH 180° INTERLEAVING Submit Document Feedback 13 FN7822.2 December 8, 2014 ISL8225M Typical Application Circuits (Continued) + CIN1 330µF 14 8 CIN2 4x22µF R5* 15 16 *SEE Table 1 on page 19 FOR R5/R6 VALUES. 7 R6* C1 4.7µF 17 3 VDDQ 19 R7 1kΩ 5 20 R8 324Ω C2 1nF 2 VIN1 VOUT1 VIN2 VSEN1+ EN/FF1 VSEN1- EN/FF2 VOUT2 VCC VSEN2+ CLKOUT VSEN2- ISL8225M MODE VMON1 ISHARE VMON2 SYNC PHASE1 COMP1 PHASE2 COMP2 6 PGND 4.5V TO 20V SGND VIN PGOOD 2.5V 23 VDDQ R1 22 R2 1kΩ 316Ω 21 COUT1 3x100µF 1.25V VDDQ/2 VTT 25 R3 26 R4 1kΩ 931Ω 1 COUT2 3x100µF 18 4 12 10 24 9 *SET THE CLKOUT VOLTAGE CLOSE TO 0.612V. SEE DETAILS IN “Functional Description” on page 23 FIGURE 20. DDR/TRACKING USE CIN1 330µF + 8 CIN2 4x22µF R5 7.15kΩ 15 16 7 R6 2.05kΩ C1 4.7µF 17 3 19 5 20 R7 88.7kΩ 2 VIN1 VOUT1 VIN2 VSEN1+ EN/FF1 VSEN1- EN/FF2 VOUT2 VCC VSEN2+ CLKOUT VSEN2- ISL8225M MODE VMON1 ISHARE VMON2 SYNC PHASE1 COMP1 PHASE2 COMP2 6 PGND 14 SGND 8V TO 20V VIN 9 PGOOD 3.3V AT 10A VOUT1 23 R1 22 R2 1kΩ 221Ω 21 COUT1 3x100µF 5V AT 10A VOUT2 25 R3 26 R4 1kΩ 137Ω 1 COUT2 3x100µF 18 4 *SEE Figure 27 on page 22 FOR THE FREQUENCY SETTING FOR I/O CONDITIONS. 12 10 24 *SEE Figure 31, “RSYNC vs SWITCHING FREQUENCY,” ON page 24 TO SELECT R7 FOR THE DESIRED FREQUENCY OPERATION. FIGURE 21. 3.3V/5V VOLTAGE APPLICATION WITH THE FREQUENCY SET AT 900kHz Submit Document Feedback 14 FN7822.2 December 8, 2014 ISL8225M Typical Application Circuits (Continued) + CIN1 330µF 8 CIN2 8x22µF R5 16.5kΩ 15 16 7 R6 4.12kΩ 17 C1 4.7µF 3 19 5 20 R7 147kΩ 2 VIN1 VOUT1 VIN2 VSEN1+ EN/FF1 VSEN1- EN/FF2 VOUT2 VCC VSEN2+ CLKOUT VSEN2- ISL8225M MODE VMON1 ISHARE VMON2 SYNC PHASE1 COMP1 PHASE2 COMP2 PGND 14 SGND 11V TO 20V VIN 6 *SEE Figure 31, “RSYNC vs SWITCHING PGOOD 6.5V AT 10A VOUT1 23 R1 22 R2 1kΩ 102Ω 21 COUT1 6x47µF 7.5V AT 7A VOUT2 25 R3 26 R4 1kΩ 86.6Ω 1 COUT2 6x47µF 18 4 *SEE Figure 27 on page 22 FOR THE FREQUENCY SETTING FOR I/O CONDITIONS. 12 10 24 9 FREQUENCY,” ON page 24 TO SELECT R7 FOR THEDESIRED FREQUENCY OPERATION. FIGURE 22. HIGH OUTPUT VOLTAGE APPLICATION WITH THE FREQUENCY SET AT 750kHz CIN1 330µF + CIN2 8x22µF 8 15 R3 6.04kΩ 16 7 17 R4 2.05kΩ C1 4.7µF 3 19 5 20 R7 147kΩ 2 C2 470pF VIN1 VOUT1 VIN2 VSEN1+ EN/FF1 VSEN1- EN/FF2 VOUT2 VSEN2+ VCC CLKOUT ISL8225M VSEN2- MODE VMON1 ISHARE VMON2 9 SEE “LAYOUT GUIDE” ON PAGE 27 FOR SHORTING SGND TO PGND COUT1 5x47µF LOAD COUT2 330µF 25 26 1 KELVIN REMOTE SENSING LINES VCC 18 4 2Ω 12 COMP1 6 1kΩ R2 21 86.6Ω PHASE2 10 PGOOD VOUT R1 22 PHASE1 COMP2 7.5 AT 14A 23 SYNC PGND 14 SGND 15V TO 20V VIN 2200pF SIZE:1210 24 2Ω SIZE:1210 2200pF R8 953Ω C3 22nF OPTIONAL SNUBBER FOR NOISE ATTENUATION. SEE Figure 34 on page 28. FIGURE 23. PARALLEL USE FOR SINGLE OUTPUT WITH 240° INTERLEAVING Submit Document Feedback 15 FN7822.2 December 8, 2014 ISL8225M Typical Application Circuits (Continued) + VIN1 CIN2 4x22µF VOUT1 VIN2 VSEN1+ EN/FF1 VSEN1- EN/FF2 VOUT2 R4* VCC1 *SEE Table 1 on page 19 FOR R3/R4 VALUES. R3* VSEN2+ VCC C1 4.7µF CLKOUT ISL8225M 1.5V/60A MASTER PHASE VOUT1 R1 1kΩ R2 665Ω COUT1 4x100µF SLAVE VCC1 VSEN2- MODE VMON1 ISHARE VMON2 SYNC PHASE1 COMP1 PHASE2 COMP2 PGOOD PGND CIN1 2x470µF 4.5V TO 20V SGND VIN VCC C6 22nF R8 953Ω R5 3.3kΩ PGOOD C3 470pF CIN2 4x22µF VCC2 VIN1 VOUT1 VIN2 VSEN1+ EN/FF1 VSEN1- EN/FF2 VOUT2 CLKOUT ISL8225M VMON1 ISHARE VMON2 PHASE1 COMP1 PHASE2 COMP2 PGOOD PGND SYNC C5 470pF SLAVE VSEN2- MODE SGND C4 470pF COUT2 4x100µF VCC2 VSEN2+ VCC C2 4.7µF SLAVE R6 1kΩ C7 22nF R7 665Ω R9 953Ω FIGURE 24. 4-PHASE PARALLELED AT 1.5V/60A WITH 90° INTERLEAVING Submit Document Feedback 16 FN7822.2 December 8, 2014 ISL8225M Typical Application Circuits (Continued) 8 CIN1 4x22µF R4* *SEE Table 1 on page 19 FOR R3/R4 VALUES. 15 16 VCC1 R3* C1 4.7µF 7 17 VCC 3 19 5 20 R7 100kΩ 2 8 15 CIN2 4x22µF 16 VCC2 7 17 C3 4.7µF 3 19 5 20 C4 470pF 2 VSEN1+ VIN2 EN/FF1 VSEN1- EN/FF2 VOUT2 VCC VSEN2+ CLKOUT VSEN2- ISL8225M MODE VMON1 ISHARE VMON2 SYNC PHASE1 COMP1 PHASE2 COMP2 PGOOD C2 470pF 14 VOUT1 6 PGND + VIN1 VIN1 VOUT1 VIN2 VSEN1+ EN/FF1 VSEN1- EN/FF2 VOUT2 VCC VSEN2+ CLKOUT VSEN2- ISL8225M MODE VMON1 ISHARE VMON2 SYNC PHASE1 COMP1 PHASE2 COMP2 PGOOD 6 23 VOUT1 R1 22 21 1.5V/40A MASTER PHASE R2 1kΩ 316Ω 25 SLAVE 26 VCC1 COUT1 4x100µF 1 18 VCC1 4 12 10 R6 C5 22nF 953Ω R5 3.3kΩ 24 PGOOD 9 PGND 2x470µF 14 SGND 4.5V TO 20V SGND VIN 23 SLAVE COUT2 2x100µF 22 21 VCC2 5V/10A 25 26 1 18 4 12 VOUT2 R8 R9 1kΩ 137Ω COUT3 3x100µF R10 1kΩ R11 316Ω 10 24 9 FIGURE 25. 3-PHASE PARALLELED AT 1.5V/40A AND 1-PHASE AT 5V/10A OUTPUT WITH 90° INTERLEAVING Submit Document Feedback 17 FN7822.2 December 8, 2014 ISL8225M Typical Application Circuits (Continued) 8 15 16 VCC1 R3* 7 C1 4.7µF EN/FF1 VSEN1- 21 EN/FF2 VOUT2 VCC 17 CLKOUT 3 19 5 ISHARE VMON2 C8 470pF 8 15 16 7 17 C2 4.7µF 3 19 5 20 2 C3 470pF 14 8 15 16 7 VCC3 17 C5 4.7µF 3 19 5 20 2 C6 470pF C7 470pF PHASE2 6 9 PGOOD VIN1 VOUT1 VIN2 VSEN1+ EN/FF1 VSEN1- EN/FF2 VOUT2 VCC VSEN2+ CLKOUT ISL8225M VSEN2- MODE VMON1 ISHARE VMON2 SYNC PHASE1 COMP1 PHASE2 6 9 COMP2 C4 470pF CIN3 4x22µF PHASE1 COMP2 14 VSEN2VMON1 COMP1 2 VCC2 ISL8225M MODE SYNC 20 CIN2 4x22µF VSEN2+ PGND *SEE Table 1 on page 19 FOR R3/R4 VALUES. VSEN1+ PGND R4* VIN2 PGOOD VIN1 VOUT1 VIN2 VSEN1+ EN/FF1 VSEN1- EN/FF2 VOUT2 VCC VSEN2+ CLKOUT ISL8225M VSEN2- MODE VMON1 ISHARE VMON2 SYNC PHASE1 COMP1 PHASE2 COMP2 PGND CIN1 4x22µF VOUT1 SGND + 23 VIN1 SGND 2x470µF 14 SGND 4.5V TO 20V VIN 6 9 PGOOD 26 VOUT R1 22 25 1.2V/90A MASTER PHASE R2 1kΩ 1kΩ COUT1 4x100µF SLAVE VCC1 1 18 4 VCC1 12 R5 3.3kΩ 10 24 23 22 PGOOD SLAVE VCC2 COUT2 4x100µF 21 25 SLAVE 26 1 R6* 18 4 R7* 500Ω 12 10 24 23 22 *KEEP R6/R7 THE SAME RATIO AS R1/R2. EACH VMON PIN CAN HAVE SEPERATE RESISTOR DIVIDER TO MONITOR THE OUTPUT VOLTAGE. SLAVE VCC3 21 25 500Ω COUT3 4x100µF SLAVE 26 1 18 4 12 10 24 FIGURE 26. SIX-PHASE 90A 1.2V OUTPUT CIRCUIT Submit Document Feedback 18 FN7822.2 December 8, 2014 ISL8225M TABLE 1. ISL8225M DESIGN GUIDE MATRIX (REFER TO Figure 18) VIN VOUT R2 or R4 CASE (V) (V) (Ω) CIN1 (BULK) µF (Note 10) CIN2 (CERAMIC) (µF) COUT1 (CERAMIC) (µF) COUT2 (BULK) (µF) CFF (nF) EN/FF (kΩ) R5/R6 (Note 11) FREQ. (kHz) RSYNC (kΩ) LOAD (A) (Note 12) 1 5 1 1.5k 1x330 1x100 1x100 1x330 None 6.04/3.01 500 None 15 2 5 1 1.5k 1x330 1x100 3x100 None 3.3 6.04/3.01 500 None 15 3 12 1 1.5k 1x330 2x22 1x100 1x330 None 6.04/1.50 500 None 15 4 12 1 1.5k 1x330 2x22 3x100 None 3.3 6.04/1.50 500 None 15 5 5 1.2 1.0k 1x330 1x100 1x100 1x330 None 6.04/3.01 500 None 15 6 5 1.2 1.0k 1x330 1x100 3x100 None 3.3 6.04/3.01 500 None 15 7 12 1.2 1.0k 1x330 2x22 1x100 1x330 None 6.04/1.50 500 None 15 8 12 1.2 1.0k 1x330 2x22 3x100 None 3.3 6.04/1.50 500 None 15 9 20 1.2 1.0k 1x330 2x22 1x100 1x330 3.3 6.04/1.50 500 None 15 10 20 1.2 1.0k 1x330 2x22 3x100 None 4.7 6.04/1.50 500 None 15 11 5 1.5 665 1x330 1x100 1x100 1x330 None 6.04/3.01 500 None 15 12 5 1.5 665 1x330 1x100 3x100 None 3.3 6.04/3.01 500 None 15 13 12 1.5 665 1x330 2x22 1x100 1x330 None 6.04/1.50 500 None 15 14 12 1.5 665 1x330 2x22 3x100 None 3.3 6.04/1.50 500 None 15 15 20 1.5 665 1x330 2x22 1x100 1x330 None 6.04/1.50 500 None 15 16 20 1.5 665 1x330 2x22 3x100 None 3.3 6.04/1.50 500 None 15 17 5 2.5 316 1x330 1x100 1x100 1x330 None 6.04/3.01 500 None 15 18 5 2.5 316 1x330 1x100 3x100 None 3.3 6.04/3.01 500 None 15 19 12 2.5 316 1x330 2x22 1x100 1x330 None 6.04/1.50 650 249 15 20 12 2.5 316 1x330 2x22 3x100 None 3.3 6.04/1.50 650 249 15 21 20 2.5 316 1x330 2x22 1x100 1x330 None 6.04/1.50 750 147 14 22 20 2.5 316 1x330 2x22 3x100 None 3.3 6.04/1.50 750 147 14 23 5 3.3 221 1x330 1x100 1x100 1x330 None 6.04/3.01 500 None 15 24 5 3.3 221 1x330 1x100 3x100 None None 6.04/3.01 500 None 15 25 12 3.3 221 1x330 2x22 1x100 1x330 None 6.04/1.50 800 124 14 26 12 3.3 221 1x330 2x22 3x100 None None 6.04/1.50 800 124 14 27 20 3.3 221 1x330 2x22 1x100 1x330 None 6.04/1.50 850 107 13 28 20 3.3 221 1x330 2x22 3x100 None 3.3 6.04/1.50 850 107 13 29 12 5 137 1x330 2x22 1x100 1x330 None 6.04/1.50 950 82.5 12 30 12 5 137 1x330 2x22 3x100 None None 6.04/1.50 950 82.5 12 31 20 5 137 1x330 2x22 1x100 1x330 None 6.04/1.50 950 82.5 10 32 20 5 137 1x330 2x22 3x100 None 3.3 6.04/1.50 950 82.5 10 33 12 6.5 102 1x330 4x22 2x47 1x330 None 16.5/4.12 750 147 10 34 12 6.5 102 1x330 4x22 6x47 None 3.3 16.5/4.12 750 147 10 35 20 6.5 102 1x330 4x22 2x47 1x330 None 16.5/4.12 750 147 10 36 20 6.5 102 1x330 4x22 6x47 None 3.3 16.5/4.12 750 147 10 37 12 7.5 86.6 1x330 4x22 2x47 1x330 None 16.5/4.12 750 147 7 Submit Document Feedback 19 FN7822.2 December 8, 2014 ISL8225M TABLE 1. ISL8225M DESIGN GUIDE MATRIX (REFER TO Figure 18) (Continued) VIN VOUT R2 or R4 (Ω) CASE (V) (V) CIN1 (BULK) µF (Note 10) CIN2 (CERAMIC) (µF) COUT1 (CERAMIC) (µF) COUT2 (BULK) (µF) CFF (nF) EN/FF (kΩ) R5/R6 (Note 11) FREQ. (kHz) RSYNC (kΩ) LOAD (A) (Note 12) 38 12 7.5 86.6 1x330 4x22 6x47 None 3.3 16.5/4.12 750 147 7 39 20 7.5 86.6 1x330 4x22 2x47 1x330 None 16.5/4.12 750 147 7 40 20 7.5 86.6 1x330 4x22 6x47 None 3.3 16.5/4.12 750 147 7 NOTES: 10. CIN bulk capacitor is optional only for decoupling noise due to the long input cable. CIN2 and COUT1 ceramic capacitors are listed for one phase only. Please double the capacitor quantity for dual-phase operations. 11. EN/FF resistor divider is tied directly to VIN. The resistors listed here are for two channels' EN/FF pins tied together. If the separate resistor divider is used for each channel, the resistor value needs to be doubled. 12. MAX load current listed in the table is for conditions at +25°C and no air flow on a typical Intersil 4-layer evaluation board. TABLE 2. RECOMMENDED I/O CAPACITOR IN Table 1 VENDOR VALUE PART NUMBER TDK, Input and Output Ceramic 100µF, 6.3V, 1210 C3225X5R0J107M Murata, Input and Output Ceramic 100µF, 6.3V, 1210 GRM32ER60J107M AVX, Input and Output Ceramic 100µF, 6.3V, 1210 12106D107MAT2A Murata, Input Ceramic 22µF, 25V, 1210 GRM32ER61E226KE15L Taiyo Yuden, Input Ceramic 22µF, 25V, 1210 TMK325BJ226MM-T AVX, Input Ceramic 22µF, 25V, 1210 12103D226KAT2A Panasonic POSCAP, Output Bulk 330µF, 10V 10TPB330M Panasonic SMT, Input Bulk 330µF, 25V EEVHA1E331UP Murata, Input and Output Ceramic 47µF, 10V, 1210 GRM32ER71A476KE15L Submit Document Feedback 20 FN7822.2 December 8, 2014 ISL8225M TABLE 3. ISL8225M OPERATION MODES 1ST MODULE (I = INPUT; O = OUTPUT; I/O = INPUT AND OUTPUT, BI-DIRECTION) MODE EN1/FF1 EN2/FF (I) 2 (I) VSEN2(I) 1 0 0 - 2A 0 1 Active 2B 1 0 - 3A 1 1 3B 1 3C CLKOUT/RE MODE VSEN2+ FIN WRT 1ST VMON2 (I) (I) (I OR O) (Note 14) - - VMON1 OF 2ND MODULE (Note 14) MODES OF OPERATION 2ND CHANNEL WRT 1ST (O) (Note 13) OPERATION OPERATION MODE MODE OUTPUT (SEE OF 2ND OF 3RD DESCRIPTION MODULE MODULE FOR DETAILS) - - - - - - Disabled - Active - VMON1 = VMON2 to Keep PGOOD Valid - - Single Phase - - - VMON1 = VMON2 to Keep PGOOD Valid - - Single Phase <VCC -0.7V Active Active 29% to 45% of VCC (I) Active - 0° - - Dual Regulator 1 <VCC -0.7V Active Active 45% to 62% of VCC (I) Active - 90° - - Dual Regulator 1 1 <VCC -0.7V Active Active >62% of VCC (I) Active - 180° - - Dual Regulator 4 1 1 <VCC -0.7V Active Active <29% of VCC (I) Active - -60° - - DDR Mode 5A 1 1 VCC GND - 60° VMON1 or Divider - 180° - - 2-Phase 5B 1 1 VCC GND - 60° Divider Divider 180° 5B 5B 6-Phase 5C 1 1 VCC GND - 60° VMON1 or Divider Active 180° 5C 5C 3 Outputs 6 1 1 VCC VCC GND 120° 953Ω// 22nF Active 240° 2B - 3-Phase 7A 1 1 VCC VCC VCC 90° 953Ω// 22nF Divider 180° 7A - 4-Phase 7B 1 1 VCC VCC VCC 90° 953Ω// 22nF Active 180° 7B - 2 Outputs (1st module in Mode 7A) 7C 1 1 VCC VCC VCC 90° 953Ω// 22nF Active 180° 3, 4 - 3 Outputs (1st module in Mode 7A) Active Active - - 8 Cascaded Module Operation MODEs 5B+5B+7A+5B+5B+5B/7A, No External Clock Required 12-Phase 9 External Clock or External Logic Circuits Required for Equal Phase Interval 5, 7, 8, 9, 10, 11, or (PHASE >12) NOTE: 13. “2ND CHANNEL WRT 1ST” means “second channel with respect to first;” in other words, Channel 2 lags Channel 1 by the degrees specified in this column. For example, 90° means Channel 2 lags Channel 1 by 90°; -60° means Channel 2 leads Channel 1 by 60°. 14. “VMON1” means that the pin is tied to the VMON1 pin of the same module. “Divider” means that there is a resistor divider from VOUT to SGND; refer to Figure 26.“ 953Ω//22nF” means that there are 953Ω resistor and 22nF connecting the pin to SGND; refer to Figure 24. Submit Document Feedback 21 FN7822.2 December 8, 2014 ISL8225M Application Information Programming the Output Voltage The ISL8225M has an internal 0.6V ±0.7% reference voltage. Programming the output voltage requires a resistor divider (R1 and R2) between the VOUT, VSEN+, and VSEN- pins, as shown in Figure 18. Please note that the output voltage accuracy is also dependent on the resistor accuracy of R1 and R2. The user needs to select a high accuracy resistor (i.e. 0.5%) in order to achieve the overall output accuracy. The output voltage can be calculated as shown in Equation 1: (EQ. 1) R1 V OUT = 0.6 1 + -------- R2 NOTE: It is recommended to use a 1kΩ value for the top resistor, R1. The value of the bottom resistor for different output voltages is shown in Table 4. TABLE 4. VALUE OF BOTTOM RESISTOR FOR DIFFERENT OUTPUT VOLTAGES (VOUT vs R2) Selection of Input Capacitor Selection of the input filter capacitor is based on how much ripple the supply can tolerate on the DC input line. The larger the capacitor, the less ripple expected, however, consideration should be given to the higher surge current during power-up. The ISL8225M provides a soft-start function that controls and limits the current surge. The value of the input capacitor can be calculated as shown in Equation 2: IO D 1 – D C IN MIN = ----------------------------------V P-P f SW R1 (Ω) VOUT (V) R2 (Ω) 1k 0.6 Open 1k 0.8 3.01k 1k 1.0 1.50k • CIN(MIN) is the minimum required input capacitance (µF) 1k 1.2 1.00k • IO is the output current (A) 1k 1.5 665 • D is the duty cycle 1k 1.8 491 • VP-P is the allowable peak-to-peak voltage (V) 1k 2.0 422 • fSW is the switching frequency (Hz) 1k 2.5 316 1k 3.3 221 1k 5.0 137 1k 6.0 110 1k 6.5 102 1k 7.5 86.6 In addition to the bulk capacitance, some low Equivalent Series Resistance (ESR) ceramic capacitance is recommended to decouple between the VIN and PGND of each channel. Table 2 shows for some recommended capacitors. This capacitance reduces voltage ringing created by the switching current across parasitic circuit elements. All these ceramic capacitors should be placed as closely as possible to the module pins. The estimated RMS current should be considered in choosing ceramic capacitors. Io D 1 – D I IN RMS = -------------------------------- 1100 20VIN 1000 (EQ. 2) where: Due to the minimum off-time limit of 410ns, the module has a maximum output voltage, depending on input voltage. Refer to Figure 27 for the 5V input voltage limitation. FREQUENCY (kHz) At higher output voltage, the inductor ripple increases, which makes both output ripple and inductor power loss higher. Therefore, higher switching frequency can be used to reduce the inductor ripple. However, higher switching frequency results in higher switching loss and higher gate driving loss, so the overall efficiency may suffer. Because of thermal and efficiency concerns, the optimal switching frequency is 750KHz for 6.5V and 7.5V output. With 750kHz switching frequency, the minimum input voltage is 10V for 6.5V output and 11V for 7.5V. Please refer to Figure 27 for frequency selection at different operating conditions, then refer to Figure 31 to choose RSYNC. 15VIN 900 (EQ. 3) Each 10µF X5R or X7R ceramic capacitor is typically good for 2A to 3A of RMS ripple current. Refer to the capacitor vendor to check the RMS current ratings. In a typical 15A output application for one channel, if the duty cycle is 0.5, it needs at least three 10µF X5R or X7R ceramic input capacitors. 12VIN 10VIN 800 700 8VIN 600 500 5VIN 0 1 2 3 4 5 VOUT (V) FIGURE 27. RECOMMENDED FREQUENCY vs VIN AT VOUT Submit Document Feedback 22 FN7822.2 December 8, 2014 ISL8225M Selection of Output Capacitors where: The ISL8225M is designed for low output voltage ripple. The output voltage ripple and transient requirements can be met with bulk output capacitors (COUT) that have adequately low ESR. COUT can be a low ESR tantalum capacitor, a low ESR polymer capacitor, or a ceramic capacitor. The typical capacitance is 330µF, and decoupled ceramic output capacitors are used for each phase. See Tables 1 and 2 for more capacitor information. Internally optimized loop compensation provides sufficient stability margins for all ceramic capacitor applications, with a recommended total value of 300µF per phase. Additional output filtering may be needed if further reduction of output ripple or dynamic transient spike is required. • Tjunction is the module internal maximum temperature (°C) EN/FF Turn ON/OFF Each output of the ISL8225M can be turned on/off independently through the EN/FF pins. For parallel use, tie all EN/FF pins together. Since this pin has the feed-forward function, the voltage on this pin can actively adjust the loop gain to be constant for variable input voltage. Please refer to Table 1 to select the resistor divider for commonly used conditions. Otherwise, use the following procedures to finish the EN/FF design: 1. A resistor divider from VIN to GND is recommended to set the EN/FF voltage between 1.25V to 5.0V. The resistor divider ratio is recommended to be between 3/1 to 4/1 (as shown in Figure 21) with a resistor divider at 7.15kΩ/2.05kΩ. 2. Check EN turn-on hysteresis (Recommend VEN_HYS > 0.3V): • Tambient is the system ambient temperature (°C) • P is the total power loss of the module package (W) • JA is the thermal resistance of module junction to ambient If the calculated temperature, Tjunction, is over the required design target, the extra cooling scheme is required. Please refer to “Current Derating” on page 28 for adding air flow. Functional Description Initialization Initially, the Power-On Reset (POR) circuits continuously monitor bias voltages (VCC) and voltage at the EN/FF pin. The POR function initiates soft-start operation 384 clock cycles after: (1) the EN pin voltage is pulled above 0.8V, (2) all input supplies exceed their POR thresholds, and (3) the PLL locking time expires. The Enable pin can be used as a voltage monitor and to set the desired hysteresis, with an internal 30µA sinking current going through an external resistor divider. The sinking current is disengaged after the system is enabled. This feature is specially designed for applications that require higher input rail POR for better undervoltage protection. For example, in 12V applications, RUP = 53.6kΩ and RDOWN = 5.23kΩ sets the turn-on threshold (VEN_RTH) to 10.6V and the turn-off threshold (VEN_FTH) to 9V, with 1.6V hysteresis (VEN_HYS). where: During shutdown or fault conditions, soft-start is quickly reset, and the gate driver immediately changes state (<100ns) when input drops below POR. • RUP is the top resistor of the resistor divider Enable and Voltage Feed-forward • N is the total number of the EN/FF pins tied to the resistor divider Voltage applied to the EN/FF pin is fed to adjust the sawtooth amplitude of the channel. Sawtooth amplitude is set to 1.25 times the corresponding FF voltage when the module is enabled. This configuration helps maintain a constant gain. This configuration also helps maintain input voltage to achieve optimum loop response over a wide input voltage range. V EN – HYS = N R UP 3x10 – 5 (EQ. 4) 3. Set the maximum current flowing through the top pull-up resistor RUP to below 7mA (considering EN/FF is pulled to ground (VEN/FF = 0)). Refer to Figure 25; a 3.01kΩ/1kΩ resistor is used to allow for the input voltage from 5V to 20V operation. In addition, the maximum current flowing through R5 is 6.6mA (<7mA). 4. If the EN/FF is controlled by system EN signal instead of the input voltage, we recommend setting the fixed EN/FF voltage to about 1/3.5 of the input voltage. If the input voltage is 12V, a 3.3V system EN signal can be tied to EN/FF pin directly. 5. If the input voltage is below 5.5V, it is recommended to have EN/FF voltage >1.5V to have better stability. The input voltage can be directly tied to the VCC pin to disable the internal LDO. 6. A 1nF capacitor is recommended on the EN/FF pin to avoid the noise injecting into the feed-forward loop. Thermal Considerations The ISL8225M QFN package offers typical junction to ambient thermal resistance JA of approximately 10°C/W at natural convection (~5.8°C/W at 400LFM) with a typical 4-layer PCB. Therefore, use Equation 5 to estimate the module junction temperature: T junction = P jA + T ambient Submit Document Feedback 23 A 384-cycle delay is added after the system reaches its rising POR and prior to soft-start. The RC timing at the FF pin should be small enough to ensure that the input bus reaches its static state and that the internal ramp circuitry stabilizes before soft-start. A large RC could cause the internal ramp amplitude not to synchronize with the input bus voltage during output start-up or when recovering from faults. A 1nF capacitor is recommended as a starting value for typical applications. In a multi-module system, with the EN pins are wired together, all modules can immediately turn off, at one time, when a fault condition occurs in one or more modules. A fault pulls the EN pin low, disabling all modules, and does not create current bounce; thus, no single channel is overstressed when a fault occurs. Because the EN pins are pulled down under fault conditions, the pull-up resistor (RUP) should be scaled to sink no more than 7mA current from the EN pin. Essentially, the EN pins cannot be directly connected to VCC. (EQ. 5) FN7822.2 December 8, 2014 ISL8225M R UP V V EN_HYS = ----------------------------I EN_HYS EN_FTH = V VIN R ²V UP EN_REF R DOWN = --------------------------------------------------------------V –V EN_FTH EN_REF RUP EN_RTH –V EN_HYS ON/OFF EN 384 CLOCK CYCLES 0.8V SOFT-START IEN_HYS = 30µA RDOWN OV, OT, OC, AND PLL LOCKING FAULTS FIGURE 28. SIMPLIFIED ENABLE AND VOLTAGE FEED-FORWARD CIRCUIT Soft-Start The ISL8225M has an internal, digital, precharged soft-start circuitry (Figures 29 to 31). The circuitry has a rise time inversely proportional to the switching frequency. Rise time is determined by a digital counter that increments with every pulse of the phase clock. The full soft-start time from 0V to 0.6V can be estimated as shown in Equation 6. The typical soft-start time is ~2.5ms. 1280 t SS = ------------f SW (EQ. 6) The ISL8225M is able to work under a precharged output. The PWM outputs do not feed to the drivers until the first PWM pulse is seen. The low-side MOSFET is on for the first clock cycle, to provide charge for the bootstrap capacitor. If the precharged output voltage is greater than the final target level but less than the 113% set point, switching does not start until the output voltage is reduced to the target voltage and the first PWM pulse is generated. The maximum allowable precharged level is 113%. If the precharged level is above 113% but below 120%, the output hiccups between 113% (LGATE turns on) and 87% (LGATE turns off), while EN is pulled low. If the precharged load voltage is above 120% of the targeted output voltage, then the controller is latched off and cannot power up. OV = 113% FIRST PWM PULSE VOUT TARGET VOLTAGE FIGURE 31. SOFT-START WITH VOUT BELOW 113% BUT ABOVE FINAL TARGET VOLTAGE Power-Good Power-good comparators monitor voltage on the VMON pin. Trip points are shown in Figure 32. PGOOD is not asserted until the soft-start cycle is complete. PGOOD pulls low upon both ENs disabling it or when the VMON voltage is out of the threshold window. PGOOD does not pull low until the fault presents for three consecutive clock cycles. UV indication is not enabled until the end of soft-start. In a UV event, if the output drops below -13% of the target level due to a reason other than OV, OC, OT, or PLL faults (cases when EN is not pulled low), PGOOD is pulled low. CHANNEL 1 UV/OV SS SETTLING AT VREF + 100mV FIRST PWM PULSE CHANNEL 2 UV/OV VOUT TARGET VOLTAGE END OF SS1 END OF SS2 0.0V 1280 t SS = ------------f SW -100mV t SS_DLY SS1_PERIOD SS2_PERIOD 384 = -----------f SW FIGURE 29. SOFT-START WITH VOUT = 0V PGOOD AND OR AND +20% VMON1, 2 +13% +9% FIRST PWM PULSE VREF SS SETTLING AT VREF + 100mV -9% VOUT TARGET VOLTAGE INIT. VOUT -13% -100mV FIGURE 30. SOFT-START WITH VOUT < TARGET VOLTAGE PGOOD PGOOD LATCH OFF AFTER 120% OV FIGURE 32. POWER-GOOD THRESHOLD WINDOW Submit Document Feedback 24 FN7822.2 December 8, 2014 ISL8225M Current Share In parallel operations, the share bus voltages (ISHARE) of different modules must tie together. The ISHARE pin voltage is set by an internal resistor and represents the average current of all active modules. The average current signal is compared with the local module current, and the current share error signal is fed into the current correction block to adjust each module’s PWM pulse accordingly. The current share function provides at least 10% overall accuracy between modules. The current share bus works for up to 12 phases without requiring an external clock. A 470pF ~1nF capacitor is recommended for each ISHARE pin. In current sharing scheme, all slave channels have the feedback loops disabled with the VSEN- pin tied to VCC. The master channel can control all modules with COMP and ISHARE pins tied together. For phase-shift setting, all VMON pins of slave channels are needed to set 0.6V for monitoring use only. Typically, the slaved VMON pins can be tied together with a resistor divider to VOUT. However, if the MODE pin is tied to VCC for mode setting, the related VMON2 pin is needed to tie to SGND with a 953Ω resistor and 22nF capacitor, as shown in Figure 25 on page 17. If there are multiple modules paralleled with the MODE pins tied to VCC, each VMON2 pin of the slave module needs to have a 953Ω resistor to GND while all VMON1 pins of the slave modules can be tied together with a resistor divider from VOUT to GND, as shown in Figure 26 on page 18. Also see Table 3 for VMON settings. Because of the typical 5.4V VCC and 7.5kΩ resistor between MODE pin and VMON2 pin, the 953Ω resistor maintains VMON2 pin voltage close to 0.6V, so output OVP/UVP (caused by VMON2 voltage too high or too low) will not be triggered falsely by part to part tolerance at mass production. The 22nF capacitor is used to avoid output UVP/OVP triggered during input start-up. Overvoltage Protection (OVP) The overvoltage (OV) protection indication circuitry monitors voltage on the VMON pin. OV protection is active from the beginning of soft-start. An OV condition (>120%) would latch the IC off. In this condition, the high-side MOSFET (Q1 or Q3) latches off permanently. The low-side MOSFET (Q2 or Q4) turns on immediately at the time of OV trip and then turns off permanently after the output voltage drops below 87%. EN and PGOOD are also latched low in an OV event. The latch condition can be reset only by recycling VCC. There is another non-latch OV protection (113% of target level). When EN is low and output is over 113% OV, the low-side MOSFET turns on until output drops below 87%. This action protects the power trains when even a single channel of a multi-module system detects OV. The low-side MOSFET always turns on when EN = LOW and the output voltage rises above 113% (all EN pins are tied together) and turns off after the output drops below 87%. Thus, in a high phase count application (multi-module mode), all cascaded modules can latch off simultaneously via the EN pins (EN pins are tied together in multi-phase mode). Each channel shares the same sink current to reduce stress and eliminate bouncing among phases. other cascaded channels via their EN pins. All connected ENs stay low and then release after the module’s junction temperature drops below +125°C (typically), a +25°C hysteresis (typically). Overcurrent Protection (OCP) The OCP peak level is set to about 20A for each channel, but the OC trip point can vary, due mainly to MOSFET rDS(ON) variations (over process, current, and temperature). The OCP can be increased by increasing the switching frequency since the inductor ripple is reduced. However, the module efficiency drops accordingly with more switching loss. When OCP is triggered, the controller pulls EN low immediately to turn off all switches. The OCP function is enabled at start-up and has a 7-cycle delay before it triggers. In multi-module operation, ISHARE pins can be connected to create VISHARE, which represents the average current of all active channels. Total system currents are compared with a precision threshold to determine the overcurrent condition. Each channel also has an additional overcurrent set point with a 7-cycle delay. This scheme helps protect modules from damage in multi-module mode by having each module carry less current than the set point. For overload and hard short conditions, overcurrent protection reduces the regulator RMS output current to much less than full load by putting the controller into hiccup mode. A delay equal to three soft-start intervals is entered to allow time to clear the disturbance. After the delay time, the controller initiates a soft-start interval. If the output voltage comes up and returns to regulation, PGOOD transitions high. If the OC trip is exceeded during the soft-start interval, the controller pulls EN low again. The PGOOD signal remains low, and the soft-start interval is allowed to expire. Another soft-start interval is initiated after the delay interval. If an overcurrent trip occurs again, this same cycle repeats until the fault is removed. Since the output voltage may trigger the OVP if the output current changes too fast, the module can go into latch-off mode. In this case, the module needs to be restarted. Frequency Synchronization and Phase Lock Loop The SYNC pin has two primary capabilities: fixed frequency operation and synchronized frequency operation. The ISL8225M has an internally set fixed frequency of 500kHz. By tying a resistor (RSYNC) to SGND from the SYNC pin, the switching frequency can be set to be more than 500kHz. To increase the switching frequency, select an externally connected resistor, RSYNC, from SYNC to SGND according to the frequency setting curve shown in Figure 33. See Table 1 for RSYNC at commonly used frequency. Over-Temperature Protection (OTP) When the junction temperature of the internal controller is greater than +150°C (typically), the EN pin is pulled low to inform Submit Document Feedback 25 FN7822.2 December 8, 2014 ISL8225M (R1 and R2)together with the 0.612V target CLKOUT voltage as shown in Equation 7: 800 700 R1 k = 1 + -------- 1.02 – 1 R2 RSYNC (kΩ) 600 500 For Figure 20, R1 = 1kΩ, R2 = 316Ω. The resistor divider ratio of R7/R8 is calculated as 3.083, so R8 is 324Ω with 1kΩ used as R7. 400 300 200 Mode Programming 100 0 500 (EQ. 7) 600 700 800 900 1000 1100 1200 1300 1400 1500 FREQUENCY (kHz) FIGURE 33. RSYNC vs SWITCHING FREQUENCY Connecting the SYNC pin to an external square-pulse waveform (such as the CLKOUT signal, typically 50% duty cycle from another ISL8225M) synchronizes the ISL8225M switching frequency to the fundamental frequency of the input waveform. The synchronized frequency can be from 300kHz to 1500kHz. The applied square-pulse recommended high level voltage range is 3V to VCC+0.3V. The frequency synchronization feature synchronizes the leading edge of the CLKOUT signal with the falling edge of Channel 1’s PWM signal. CLKOUT is not available until PLL locks. No capacitor is recommended on the SYNC pin. Locking time is typically 130µs. EN is not released for a soft-start cycle until SYNC is stabilized and PLL is locking. Connecting all EN pins together in a multi-phase configuration is recommended. Loss of a synchronization signal for 13 clock cycles causes the module to be disabled until PLL returns locking, at which point, a soft-start cycle is initiated and normal operation resumes. Holding SYNC low disables the module. NOTE: That the quick change of the synchronization signal can cause module shutdown. Tracking Function If CLKOUT is less than 800mV, an external soft-start ramp (0.6V) can be in parallel with the Channel 2 internal soft-start ramp for tracking applications. Therefore, the Channel 2’s output voltage can track the output voltage of Channel 1. The tracking function can be applied to a typical Double Data Rate (DDR) memory application, as shown in Figure 20 on page 14. The output voltage (typical VTT output) of Channel 2 tracks with the input voltage [typical VDDQ/(1+k) from Channel 1] at the CLKOUT pin. As for the external input signal and the internal reference signal (ramp and 0.6V), the one with the lowest voltage is used as the reference for comparing with the FB signal. In DDR configuration, VTT channel should start up later, after its internal soft-start ramp, such that VTT tracks the voltage on the CLKOUT pin derived from VDDQ. This configuration can be achieved by adding more filtering at EN/FF1 than at EN/FF2. ISL8225M can be programmed for dual-output, paralleled single-output or mixed outputs (Channel 1 in parallel and Channel 2 in dual-output). With multiple ISL8225Ms, up to 6 modules using its internal cascaded clock signal control, the modules can supply large current up to 180A. For complete operation, please refer to Table 3 on page 21. Commonly used settings are listed in Table 5. TABLE 5. PHASE-SHIFT SETTING OPERATION PHASE-SHIFT BETWEEN PHASES VSEN2- VSEN2+ CLKOUT MODE Dual Output (Figure 18) 180° N/C N/C VCC N/C 30A (Figure 19) 180° VCC N/C N/C SGND 30A (Figure 23) 240° VCC SGND N/C VCC 60A (Figure 24) 90° VCC VCC N/C VCC 90A (Figure 26) 60° VCC N/C N/C SGND When the module is in the dual-output condition, depending upon the voltage level at CLKOUT (which is set by the VCC resistor divider output), ISL8225M operates with phase shifted as the CLKOUT voltage shown in Table 6. The phase shift is latched as VCC rises above POR; it cannot be changed on the fly. TABLE 6. CLKOUT TO PROGRAM PHASE SHIFT AT DUAL-OUTPUT CLKOUT VOLTAGE SETTING PHASE FOR CHANNEL 2 WRT CHANNEL 1 RECOMMENDED CLKOUT VOLTAGE <29% of VCC -60° 15% VCC 29% to 45% of VCC 0° 37% VCC 45% to 62% of VCC 90° 53% VCC 62% of VCC 180° VCC It is suggested to scale the target CLKOUT voltage to 0.612V (2% above 0.6V reference) with an external resistor divider. After start-up, the internal reference takes over to maintain the good regulation of VTT. The resistor divider ratio (k) of R7/R8 in Figure 20 is Based on the feedback divider of VDDQ Submit Document Feedback 26 FN7822.2 December 8, 2014 ISL8225M Two Phase Parallel Mode Operation TABLE 7. OPERATION MODE SETTING FOR 6.5V AND 7.5V OUTPUT APPLICATION VIN (V) VO (V) OPERATION MODE PHASE SHIFT BETWEEN PHASES VSEN2- VSEN2+ CLKOUT 11 to 13.9 6.5 5A 180° VCC N/C N/C VMON1 OR DIVIDER 13.9 to 15.6 6.5 6 240° VCC SGND N/C 953Ω//22nF 15.6 to 20 6.5 5A 180° VCC N/C N/C VMON1 OR DIVIDER SGND 11 to 15 7.5 5A 180° VCC N/C N/C VMON1 OR DIVIDER SGND 15 to 20 7.5 6 240° VCC SGND N/C 953Ω//22nF When ISL8225M operates in 2-phase mode, the current sensing and sharing circuit keeps each channel's current in balance. After a typical 175nS blanking period, with respect to the falling edge of the PWM pulse of each channel, the voltage developed across rDS(ON) of the low side MOSFETs is filtered and sampled as the sensed current. If the other phase's high-side MOSFET is turned on right at the moment when current is sensed, the switching noise can distort the sensed current signal, which may result in low frequency output ripple. For high output voltage of >5V, the low frequency ripple is worse due to higher switching noise at higher input voltage. Because of the 175ns current sensing blanking time, if the second channel has 180° phase lag with respect to the first channel, the low frequency ripple typically appears when the module operates at around 40% duty cycle depending upon switching frequency. To solve this problem, 240° phase shift (Mode 6 of Table 3) can be used instead of the 180° phase shift (Mode 5A of Table 3). Figure 23 shows a typical application with 240° phase shift. All other conditions equal, the module with 180° phase shift has lower input ripple and output ripple than the module with 240° phase shift, thus the selection of the optimum operation mode should be based on the input voltage. Table 7 shows the operation mode selection to avoid low frequency for 6.5V and 7.5V output applications with 750kHz switching frequency. Please refer to Table 3 on page 21 for more information about each operation mode. Layout Guide To achieve stable operation, low losses, and good thermal performance, some layout considerations are necessary (Figure 34). VMON2 MODE SGND VCC VCC connect the power planes in different layers under or around the module. • Place high-frequency ceramic capacitors between VIN, VOUT, and PGND, as closely to the module as possible in order to minimize high-frequency noise. • Use remote sensed traces to the regulation point to achieve tight output voltage regulation, and keep the sensing traces close to each other in parallel. • PHASE1 and PHASE2 pads are switching nodes that generate switching noise. Keep these pads under the module. For noise-sensitive applications, it is recommended to keep phase pads only on the top and inner layers of the PCB. Also, do not place phase pads exposed to the outside on the bottom layer of the PCB. • Avoid routing any noise-sensitive signal traces, such as the VSEN+, VSEN-, ISHARE, COMP and VMON sensing points, near the PHASE pins. • Use a separated SGND ground copper area for components connected to signal ground pins. Connect SGND to PGND with multiple vias underneath the unit in one location to avoid the noise coupling, as shown in Figure 34 Don't ground vias surrounded by the noisy planes of VIN, PHASE and VOUT. For dual output applications, the SGND to PGND vias are preferred to be as close as possible to SGND pin. • Optional snubbers can be put on the bottom side of the board layout, connecting the PHASE to PGND planes, as shown in Figure 34. • VOUT1, VOUT2, PHASE1, PHASE2, PGND, VIN1 and VIN2 should have large, solid planes. Place enough thermal vias to Submit Document Feedback 27 FN7822.2 December 8, 2014 ISL8225M COUT2 PCB Layout Pattern Design COUT1 PGND PGND VOUT2 VOUT1 R3 R1 + R4 KELVIN CONNECTIONS FOR THE VSENS LINES TO LOAD + TO LOAD - R2 KELVIN CONNECTIONS FOR THE VSENS LINES PIN 1 SGND VIN2 VIN1 CIN2 PHASE2 PHASE1 OPTIONAL SNUBBER CIN1 OPTIONAL SNUBBER PGND FIGURE 34. RECOMMENDED LAYOUT Current Derating Experimental power loss curves (Figures 35 and 36), along with JA from thermal modeling analysis, can be used to evaluate the thermal consideration for the module. Derating curves are derived from the maximum power allowed while maintaining temperature below the maximum junction temperature of +120°C (Figures 37 through 42). The maximum +120°C junction temperature is considered for the module to load the current consistently and it provides the 5°C margin of safety from the rated junction temperature of +125°C. If necessary, customers can adjust the margin of safety according to the real applications. All derating curves are obtained from the tests on the ISL8225MEVAL4Z evaluation board. In the actual application, other heat sources and design margins should be considered. Package Description The ISL8225M is integrated into a quad flatpack no lead package (QFN). This package has such advantages as good thermal and electrical conductivity, low weight, and small size. The QFN package is applicable for surface mounting technology and is becoming more common in the industry. The ISL8225M contains several types of devices, including resistors, capacitors, inductors, and control ICs. The ISL8225M is a copper lead-frame based package with exposed copper thermal pads, which have good electrical and thermal conductivity. The copper lead frame and multi-component assembly are over-molded with polymer mold compound to protect these devices. The bottom of ISL8225M is a lead-frame footprint, which is attached to the PCB by surface mounting. The PCB layout pattern is shown in the L26.17x17 package outline drawing on page 33. The PCB layout pattern is essentially 1:1 with the QFN exposed pad and the I/O termination dimensions, except that the PCB lands are slightly longer than the QFN terminations by about 0.2mm (0.4mm max). This extension allows for solder filleting around the package periphery and ensures a more complete and inspectable solder joint. The thermal lands on the PCB layout should match 1:1 with the package exposed die pads. Thermal Vias A grid of 1.0mm to 1.2mm pitched thermal vias, which drops down and connects to buried copper planes, should be placed under the thermal land. The vias should be about 0.3mm to 0.33mm in diameter, with the barrel plated to about 2.0 ounce copper. Although adding more vias (by decreasing pitch) improves thermal performance, it also diminishes results as more vias are added. Use only as many vias as are needed for the thermal land size and as your board design rules allow. Stencil Pattern Design Reflowed solder joints on the perimeter I/O lands should have about a 50µm to 75µm (2mil to 3mil) standoff height. The solder paste stencil design is the first step in developing optimized, reliable solder joins. The stencil aperture size to land size ratio should typically be 1:1. Aperture width may be reduced slightly to help prevent solder bridging between adjacent I/O lands. To reduce solder paste volume on the larger thermal lands, an array of smaller apertures instead of one large aperture is recommended. The stencil printing area should cover 50% to 80% of the PCB layout pattern. A typical solder stencil pattern is shown in the L26.17x17 package outline drawing on page 33. The gap width between pads is 0.6mm. Consider the symmetry of the whole stencil pattern when designing the pads. A laser-cut, stainless-steel stencil with electropolished trapezoidal walls is recommended. Electropolishing smooths the aperture walls, resulting in reduced surface friction and better paste release, which reduces voids. Using a trapezoidal section aperture (TSA) also promotes paste release and forms a brick-like paste deposit, which assists in firm component placement. A 0.1mm to 0.15mm stencil thickness is recommended for this large-pitch (1.0mm) QFN. The package outline, typical PCB layout pattern, and typical stencil pattern design are shown in the L26.17x17 package outline drawing on page 28. Figure 48 shows typical reflow profile parameters. These guidelines are general design rules. Users can modify parameters according to specific applications. Submit Document Feedback 28 FN7822.2 December 8, 2014 ISL8225M 7 8 6 7 6 POWER LOSS (W) POWER LOSS (W) 5 4 3 5VIN TO 2.5VOUT 2 5VIN TO 1VOUT 5 10 15 20 LOAD CURRENT (A) 3 12VIN TO 1VOUT 12VIN TO 1.5VOUT 1 5VIN TO 1.5VOUT 0 12VIN TO 2.5VOUT 4 2 1 0 5 25 0 30 0 20 400LFM 0LFM LOAD CURRENT (A) 200LFM 15 10 400LFM 0LFM 25 20 200LFM 15 10 5 5 25 45 65 85 TEMPERATURE (°C) 105 0 125 25 FIGURE 37. DERATING CURVE 5V TO 1V 45 65 85 TEMPERATURE (°C) 105 125 FIGURE 38. DERATING CURVE 12V TO 1V 30 30 400LFM 25 400LFM 25 0LFM 0LFM 200LFM LOAD CURRENT (A) LOAD CURRENT (A) 30 All of the following curves were plotted at TJ = +125°C. 20 20 15 10 5 0 25 30 25 LOAD CURRENT (A) 15 FIGURE 36. POWER LOSS CURVES OF 12VIN 30 0 10 LOAD CURRENT (A) FIGURE 35. POWER LOSS CURVES OF 5VIN Derating Curves 5 200LFM 20 15 10 5 25 45 65 85 TEMPERATURE (°C) 105 FIGURE 39. DERATING CURVE 5V TO 1.5V Submit Document Feedback 29 125 0 25 45 65 85 TEMPERATURE (°C) 105 125 FIGURE 40. DERATING CURVE 12V TO 1.5V FN7822.2 December 8, 2014 ISL8225M Derating Curves All of the following curves were plotted at TJ = +125°C. (Continued) 30 30 400LFM 200LFM 20 15 10 0LFM 20 200LFM 15 10 5 5 0 400LFM 25 0LFM LOAD CURRENT (A) LOAD CURRENT (A) 25 25 45 65 85 105 0 125 25 45 TEMPERATURE (°C) 65 85 FIGURE 41. DERATING CURVE 5V TO 2.5V 30 400LFM 400LFM 25 0LFM 200LFM LOAD CURRENT (A) LOAD CURRENT (A) 25 20 15 10 0LFM 20 200LFM 15 10 5 5 25 45 65 85 105 0 125 25 45 65 85 125 FIGURE 44. DERATING CURVE 12V/3.3V FIGURE 43. DERATING CURVE 5V/3.3V 20 30 400LFM 400LFM 25 16 0LFM LOAD CURRENT (A) LOAD CURRENT (A) 105 TEMPERATURE (°C) TEMPERATURE (°C) 20 200LFM 15 10 0LFM 200LFM 12 8 4 5 0 125 FIGURE 42. DERATING CURVE 12V TO 2.5V 30 0 105 TEMPERATURE (°C) 25 45 65 85 105 TEMPERATURE (°C) FIGURE 45. DERATING CURVE 12V/5V Submit Document Feedback 30 125 0 25 45 65 85 105 125 TEMPERATURE (°C) FIGURE 46. DERATING CURVE 12V/6.5V FN7822.2 December 8, 2014 ISL8225M Derating Curves All of the following curves were plotted at TJ = +125°C. (Continued) 14 200LFM 12 LOAD CURRENT (A) 0LFM 10 8 400LFM 6 4 2 0 25 45 65 85 105 125 TEMPERATURE (°C) FIGURE 47. DERATING CURVE 12V/7.5V Reflow Parameters 300 PEAK TEMPERATURE +230°C~+245°C; TYPICALLY 60s-70s ABOVE +220°C KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP. 250 TEMPERATURE (°C) Due to the low mount height of the QFN, "No Clean" Type 3 solder paste, per ANSI/J-STD-005, is recommended. Nitrogen purge is also recommended during reflow. A system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the QFN. The profile given in Figure 43 is provided as a guideline to customize for varying manufacturing practices and applications. 200 SLOW RAMP (3°C/s MAX) AND SOAK FROM +100°C TO +180°C FOR 90s~120s 150 100 RAMP RATE 1.5°C FROM +70°C TO +90°C 50 0 0 100 150 200 250 300 350 DURATION (s) FIGURE 48. TYPICAL REFLOW PROFILE For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 31 FN7822.2 December 8, 2014 ISL8225M Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE December 8, 2014 FN7822.2 -Features on page 1: changed the output voltage range: from: “0.6V to 6V to: “0.6V to 7.5V. -Features on page 1: Updated 17mm square PCB footprint to: 17mmx17mm square PCB footprint. -Ordering information table on page 4 added part numbers: ISL8225MEVAL2Z, ISL8225MEVAL3Z, ISL8225MEVAL4Z. -Pin description on page 6, updated the output voltage range for pin numbers 23, 25: from: 0.6V to 6V To: 0.6V to 7.5V. -Recommended Operation table on page 7, updated output voltage range: from 0.6V to 6V to: 0.6V to 7.5V. -Electrical spec table on page 7 under “VCC voltage level” section, updated Min from 5.15V to 5.1V and Max from 5.95V to 5.6V. -Electrical spec table on page 8 as follow: “Synchronization frequency s” section: Updated Min from 150kHz to 300kHz. Under Load Regulation Accuracy: Added a 0.3 typ value to IOUT1 and IOUT2 sections. Under REFERENCE section: Added Min 0.5958 and Max 0.6042 to VREF1. Under REFERENCE section: Added Min 0.5955 and Max 0.6057 to VREF2. -Typical performance characteristics on page 10: Update Figures 4 and 5 with 6.5V/7.5V data. -Updated the title for Figure 19 on page 13. -Updated the title for Figures 21 on page 14. -Added Figure 22 and 23 on page 15. -Updated Table 1 on page 19: Added rows 33, 34, 35, 36, 37, 38, 39, 40. -Table 2 on page 20: Added a row for 47µF 10V ceramic cap. -Table 3 on page 21 under Vmon2 section: Updated mode 6, 7A, 7B and 7C: from 1kΩ to 0.953Ω/ 22nF and updated note 14. Updated Table 4 on page 22: Added two rows for 6.5V and 7.5V values. -“Programming the Output Voltage” on page 22: Added a text with 6.5V and 7.5V information. -“Current Share” on page 25: changed the VMON2 value, From: 1.0k to 953Ω. -Section “Tracking Function” on page 26: Updated equation 7. -Table 5 on page 26: Added a row with 240°. -Table 6 on page 26 by Adding “CHANNEL 2” to checkout WRT and updated: “29% to 45% of VCC” section from 90° to 0° and “45% to 62% of VCC” section from 120° to 90°. On page 27: Added “Two Phase Parallel Mode” operation section. -Added Table 7 on page 27. -Updated Derating Curves on page 29. -On page 29 the title for “Derating Curves” updated: TJ = +120°C to TJ = +125°C. January 4, 2013 FN7822.1 “Thermal Information” on page 7: Changed “Maximum Storage Temperature Range” from “-40°C to +150°C” to “-55°C to +150°C” “Selection of Input Capacitor” on page 22: Added "fSW" to Equation 2. Added "fSW is the switching frequency (Hz)" December 3, 2012 FN7822.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support Submit Document Feedback 32 FN7822.2 December 8, 2014 ISL8225M Package Outline Drawing L26.17x17 26 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN) Rev 4, 10/12 17.8±0.2 17.0±0.2 9 8 9 7 6 5 4 3 2 8 7 6 5 4 3 2 1 26 1 26 10 10 25 25 17.0±0.2 17.8±0.2 11 11 24 23 12 24 23 12 22 21 22 21 14 13 15 1617 18 19 20 TOP VIEW 0.10 0.10 0.10 0.10 AAA AAAAA AA 3.50 3.50 0.70 B 0.38 8.95 4.93 10 4.93 8.95 0.38 0.80 AAA AAAAA AAAAA 52x 0.50 (ALL OF LEAD TIPS) 2.37 0.25 12x 1.07 0.10 2.77 5.33 0.25 0.10 5.33 3.66 3.50 16x 0.55 (FULL LEAD) 16X 0.70 (FULL LEAD) 12 15 1617 1819 20 0.2 S AB X4 4.00 3.50 14 PIN NO. DEFINITION (TOP VIEW) AAAA AAAAA AAA 13 12 10 1 1 3.35 3.35 A:1.0±0.1 2.97 AAA AAAAA AAAAA 14x 0.75 16x 1.75±0.05 (FULL LEAD) A 0.05 S AB PIN-TO-PIN DISTANCE (BOTTOM VIEW) BOTTOM VIEW .2 R0 All A ro 5 und of 1 0 °(MA X) 0.25 7.5±0.2 S 0.2 SIDE VIEW S S 0.03 Submit Document Feedback 33 FN7822.2 December 8, 2014 ISL8225M 0.25 0.40 0.65 0.75 9.30 7.98 6.35 5.65 5.35 5.24 4.65 4.35 3.65 3.35 2.65 2.35 1.65 1.35 0.65 0.25 0.00 0.55 3.10 3.25 3.75 3.90 7.15 7.25 7.70 7.96 9.30 9.30 7.83 6.53 6.50 6.13 5.73 5.33 0.75 0.65 0.40 0.25 9.30 7.15 6.35 5.65 5.35 4.65 4.35 1 10 0.75 0.35 0 0.35 0.75 12 4.35 4.65 5.35 5.65 6.35 7.15 9.30 5.33 5.73 6.13 6.50 6.53 7.83 9.30 9.30 7.98 7.15 6.35 5.93 5.65 5.35 5.24 4.65 4.35 3.65 3.35 2.65 2.35 1.65 1.35 1.35 0.65 0.25 0.05 0 0.55 3.10 3.25 3.75 3.90 7.15 7.25 7.70 7.83 7.96 9.30 TYPICAL RECOMMENDED LAND PATTERN (TOP VIEW) 9.20 7.83 7.25 6.25 5.75 5.25 4.75 4.25 3.75 3.25 2.75 2.25 1.75 1.25 0.75 0.15 0 0.25 0.75 1.25 1.75 2.25 2.75 3.15 3.85 4.25 4.75 5.25 5.75 6.25 6.75 7.15 7.83 7.93 9.20 7.38 6.60 4.05 2.70 2.40 1.05 0.00 1.05 2.40 2.70 4.05 3.36 5.03 5.43 6.43 6.83 7.38 6.60 7.38 34 * 7.38 6.03 5.54 Submit Document Feedback 7.38 7.38 6.83 6.43 5.43 5.03 3.36 2.76 0.95 0.70 0 0.70 0.95 0 0.05 1.13 1.73 2.80 4.20 5.28 5.88 6.95 9.20 7.83 7.25 6.25 5.75 5.25 4.75 4.25 3.75 3.25 2.75 2.25 1.75 1.25 0.75 0.15 0 0.25 0.75 1.25 1.75 2.25 2.75 3.15 3.85 4.25 4.75 5.25 5.75 6.25 6.75 7.15 7.83 9.20 SOLDER STENCIL PATTERN WITH SQUARE PADS 1 OF 2 (TOP VIEW) 5.54 0 0.05 0.60 1.13 1.73 1.80 2.40 2.80 3.60 4.20 5.28 5.41 5.88 6.01 6.95 7.23 7.25 6.25 5.75 5.25 4.75 4.25 3.75 3.25 2.75 2.25 1.75 1.25 0.95 0.25 0 0.25 0.95 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75 6.25 7.25 9.20 7.93 5.25 4.75 4.25 3.75 3.25 2.75 2.25 1.75 1.25 0.85 0.15 0 0.15 0.85 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 7.93 SOLDER STENCIL PATTERN WITH SQUARE PADS 2 OF 2 (TOP VIEW) FN7822.2 December 8, 2014