SGUS038 − AUGUST 2002 D Controlled Baseline D D D D D D D D D D D D D SMJ320C30 and SMJ320C31 Object Code − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† High-Performance Floating-Point Digital Signal Processor (DSP) SM320C32-50EP (5 V) − 40-ns Instruction Cycle Time − 275 MOPS − 50 MFLOPS − 25 MIPS SM320C32-60EP (5 V) − 33-ns Instruction Cycle Time − 330 MOPS − 60 MFLOPS − 30 MIPS 32-Bit High-Performance CPU 16- / 32-Bit Integer and 32- / 40-Bit Floating-Point Operations 32-Bit Instruction Word, 24-Bit Addresses Two 256 × 32-Bit Single-Cycle, Dual-Access On-Chip RAM Blocks Flexible Boot-Program Loader On-Chip Memory-Mapped Peripherals: − One Serial Port − Two 32-Bit Timers − Two-Channel Direct Memory Access (DMA) Coprocessor With Configurable Priorities Enhanced External Memory Interface That Supports 8- / 16- / 32-Bit-Wide External RAM for Data Access and Program Execution From 16- / 32-Bit-Wide External RAM D D D D D D D D D D D D D D D D Compatible Fabricated Using Enhanced Performance Implanted CMOS (EPIC) Technology by Texas Instruments 144-Pin Plastic Quad Flatpack ( PCM Suffix ) 5 V Eight Extended-Precision Registers Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Two Low-Power Modes Two- and Three-Operand Instructions Parallel Arithmetic Logic Unit (ALU) and Multiplier Execution in a Single Cycle Block-Repeat Capability Zero-Overhead Loops With Single-Cycle Branches Conditional Calls and Returns Interlocked Instructions for Multiprocessing Support One External Pin, PRGW, That Configures the External-Program-Memory Width to 16 or 32 Bits Two Sets of Memory Strobes (STRB0 and STRB1) and One I / O Strobe (IOSTRB) Allow Zero-Glue Logic Interface to Two Banks of Memory and One Bank of External Peripherals Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation, External Memory Width, and Data Type Size STRB0 and STRB1 Memory Strobes Handle 8-, 16-, or 32-Bit External Data Accesses (Reads and Writes) Multiprocessor Support Through the HOLD and HOLDA Signals Is Valid for All Strobes Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. EPIC is a trademark of Texas Instruments Incorporated. All trademarks are the property of their respective owners. Copyright 2002, Texas Instruments Incorporated !"# $% $ ! ! & ' $$ ()% $ !* $ #) #$ * ## !% POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 1 SGUS038 − AUGUST 2002 description The SM320C32-EP is a member of the 320C3x generation of digital signal processors from Texas Instruments. The SM320C32-EP is an enhanced 32-bit floating-point processor manufactured in 0.7-µm triple-level-metal CMOS technology. The enhancements to the 320C3x architecture include a variable-width external-memory interface, faster instruction cycle time, power-down modes, two-channel DMA coprocessor with configurable priorities, flexible bootloader, relocatable interrupt-vector table, and edge- or level-triggered interrupts. The internal busing and special digital signal processing instruction set of the SM320C32-EP have the speed and flexibility to execute up to 50 million floating-point operations per second (MFLOPS). The SM320C32-EP optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. For additional information when designing for cold temperature operation, please see Texas Instruments application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature number SGUA001. part order information DEVICE TECHNOLOGY POWER SUPPLY OPERATING FREQUENCY SM320C32PCMM50EP 0.65-µm CMOS 5 V ± 5% 50 MHz Plastic 144-lead quad flatpack EP SM320C32PCMM60EP 0.65-µm CMOS 5 V ± 5% 60 MHz Plastic 144-lead quad flatpack EP 2 POST OFFICE BOX 1443 PACKAGE TYPE • HOUSTON, TEXAS 77251−1443 PROCESSING LEVEL SGUS038 − AUGUST 2002 112 111 110 109 116 115 114 113 120 119 118 117 124 123 122 121 128 127 126 125 132 131 130 129 136 135 134 133 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC 70 71 72 66 67 68 69 62 63 64 65 58 59 60 61 54 55 56 57 50 51 52 53 46 47 48 49 H3 H1 D0 D1 D2 D3 DVDD D4 D5 D6 D7 D8 D9 VSSL VSSL DVSS CVSS D10 DVDD D11 IVSS D12 VDDL VDDL D13 D14 D15 D16 D17 DVDD D18 D19 D20 D21 DVSS CVSS A12 DVDD A11 A10 A9 A8 A7 A6 DV DD A5 A4 A3 VDDL VDDL A2 CVSS DV SS A1 V SSL V SSL A0 DV DD D31 D30 D29 D28 D27 D26 IVSS D25 DVDD D24 D23 D22 NC 41 42 43 44 45 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 DR0 DVDD FSR0 CLKR0 CLKX0 FSX0 DX0 IVSS SHZ TCLK0 TCLK1 DVDD EMU3 EMU0 VDDL VDDL EMU1 EMU2 VSSL MCBL / MP CVSS DVSS A23 A22 A21 A20 A19 A18 DVDD A17 A16 A15 A14 A13 CVSS DVSS 140 139 138 137 144 143 142 141 NC INT3 INT2 INT1 INT0 IACK XF1 XF0 DV SS CVSS RESET PRGW R/W STRB1_B0 STRB1_B1 DVDD STRB1_B2 / A −2 V SSL STRB1_B3 / A−1 V DDL V DDL STRB0_B0 STRB0_B1 STRB0_B2 / A −2 STRB0_B3 / A −1 IOSTRB IVSS RDY DV DD HOLD HOLDA CLKIN DV SS CVSS V SUBS NC PCM PACKAGE† ( TOP VIEW ) † NC=No internal connection POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 3 SGUS038 − AUGUST 2002 Pin Assignments PIN NO. 4 PIN NAME NO. PIN NAME NO. PIN NAME NO. 1 DR0 30 A17 59 DVDD 88 2 DVDD 31 A16 60 D31 3 FSR0 32 A15 61 D30 4 CLKR0 33 A14 62 5 CLKX0 34 A13 63 6 FSX0 35 7 DX0 36 CVSS DVSS 8 37 NC 9 IVSS SHZ 38 A12 10 TCLK0 39 11 TCLK1 40 DVDD A11 12 DVDD 41 13 EMU3 42 14 EMU0 15 16 VDDL VDDL 17 18 19 PIN NAME NO. NAME 117 RDY 89 IVSS D11 118 90 DVDD 119 IVSS IOSTRB D29 91 D10 120 STRB0_B3 / A−1 D28 92 CVSS 121 STRB0_B2 / A−2 64 D27 93 DVSS 122 STRB0_B1 65 D26 94 STRB0_B0 95 124 67 IVSS D25 VSSL VSSL 123 66 96 D9 125 VDDL VDDL 68 DVDD 97 D8 126 STRB1_B3/ A−1 69 D24 98 D7 127 A10 70 D23 99 D6 128 VSSL STRB1_B2/ A−2 A9 71 D22 100 D5 129 DVDD 43 A8 72 NC 101 D4 130 STRB1_B1 44 A7 73 CVSS 102 DVDD 131 STRB1_B0 45 A6 74 DVSS 103 D3 132 R/W EMU1 46 D21 104 D2 133 PRGW 47 DVDD A5 75 EMU2 76 D20 105 D1 134 RESET 48 A4 77 D19 106 D0 135 CVSS 20 VSSL MCBL / MP 49 A3 78 D18 107 H1 136 DVSS 21 CVSS 50 79 DVDD 108 H3 137 XF0 22 DVSS 51 VDDL VDDL 80 D17 109 NC 138 XF1 23 A23 52 A2 81 D16 110 139 IACK 24 A22 53 82 D15 111 140 INT0 25 A21 54 CVSS DVSS VSUBS CVSS 83 D14 112 DVSS 141 INT1 26 A20 55 A1 84 D13 113 CLKIN 142 INT2 27 A19 56 HOLDA 143 INT3 57 86 VDDL VDDL 114 A18 VSSL VSSL 85 28 115 HOLD 144 NC 29 DVDD 58 A0 87 D12 116 DVDD POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SGUS038 − AUGUST 2002 pin functions This section provides signal descriptions for the SM320C32-EP device. The following table lists each signal (grouped by function), the number of pins, operating modes, and a brief signal description. Pin Functions PIN NAME TYPE† DESCRIPTION NO. CONDITIONS WHEN SIGNAL IS IN HIGH Z‡ EXTERNAL BUS INTERFACE (70 PINS) D31 −D0 32 I/O/Z 32-bit data port of the external bus interface S H R A23 −A0 24 O/Z 24-bit address port of the external bus interface S H R H R R/W 1 O/Z Read / write for external memory interface. R / W is high when a read is performed S and low when a write is performed over the parallel interface. IOSTRB 1 O/Z External peripheral I / O strobe for the external memory interface S H S H STRB0_B3 / A −1 1 O/Z External memory-access strobe 0, byte enable 3 for 32-bit external memory interface and address pin for 8-bit and 16-bit external memory interface STRB0_B2 / A −2 1 O/Z External memory-access strobe 0, byte enable 2 for 32-bit external memory interface and address pin for 8-bit external memory interface S H STRB0_B1 1 O/Z External memory-access strobe 0, byte enable 1 for the external memory interface S H STRB0_B0 1 O/Z External memory-access strobe 0, byte enable 0 for the external memory interface S H STRB1_B3 / A −1 1 O/Z External memory-access strobe 1, byte enable 3 for 32-bit external memory interface and address pin for 8-bit and 16-bit external memory interface S H STRB1_B2 / A −2 1 O/Z External memory-access strobe 1, byte enable 2 for 32-bit external memory interface and address pin for 8-bit external memory interface S H STRB1_B1 1 O/Z External memory-access strobe 1, byte enable 1 for the external memory interface S H STRB1_B0 1 O/Z External memory-access strobe 1, byte enable 0 for the external memory interface S H RDY 1 I Ready. RDY indicates that the external device is prepared for an external memory interface transaction to complete. I Hold signal for external memory interface. When HOLD is a logic low, any ongoing transaction is completed. A23 −A0, D31 −D0, IOSTRB, STRB0_Bx, STRB1_Bx, and R / W are placed in the high-impedance state, and all transactions over the external memory interface are held until HOLD becomes a logic high or the NOHOLD bit of the STRB0 bus-control register is set. HOLD HOLDA PRGW 1 1 1 O/Z I Hold acknowledge for external memory interface. HOLDA is generated in response to a logic low on HOLD. HOLDA indicates that A23 −A0, D31 −D0, IOSTRB, STRB0_Bx, STRB1_Bx, and R / W are in the high-impedance state and S that all transactions over the memory are held. HOLDA is high in response to a logic high of HOLD or when the NOHOLD bit of the external bus-control register is set. Program memory width select. When PRGW is a logic low, program is fetched as a single 32-bit word. When PRGW is a logic high, two 16-bit program fetches are performed to fetch a single 32-bit instruction word. The status of PRGW at device reset affects the reset value of the STRB0 and STRB1 bus-control register. † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling capacitor is 0.1 µF. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 5 SGUS038 − AUGUST 2002 Pin Functions (Continued) PIN NAME TYPE† DESCRIPTION NO. CONDITIONS WHEN SIGNAL IS IN HIGH Z‡ CONTROL SIGNALS (9 PINS) RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vector. INT3 −INT0 4 I External interrupts CONTROL SIGNALS (9 PINS) (CONTINUED) Interrupt acknowledge. IACK is set to a logic high by the IACK instruction. This signal can be used to indicate the beginning or end of an interrupt-service routine. IACK 1 O/Z MCBL / MP 1 I XF1 −XF0 2 I/O/Z External flags. XF1 and XF0 are used as general-purpose I / Os or used to support interlocked-processor instructions. S Microcomputer bootloader / microprocessor mode S R S R SERIAL PORT SIGNALS (6 PINS) CLKX0 1 I/O/Z Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0 transmitter. DX0 1 I/O/Z Data transmit output. Serial port 0 transmits serial data on DX0. S R S R FSX0 1 I/O/Z Frame-synchronization pulse for transmit. The FSX0 pulse initiates the transmit-data process over DX0. CLKR0 1 I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver. S R DR0 1 I/O/Z Data receive. Serial port 0 receives serial data on DR0. S R FSR0 1 I/O/Z Frame-synchronization pulse for receive. The FSR0 pulse initiates the receive-data process over DR0. S R S R S R TIMER SIGNALS (2 PINS) TCLK0 1 I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an output, TCLK0 outputs pulses generated by timer 0. TCLK1 1 I/O/Z Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an output, TCLK1 outputs pulses generated by timer 1. CLOCK SIGNALS (3 PINS) CLKIN 1 I H1 1 O/Z Input to the internal oscillator from an external clock source External H1 clock. H1 has a period equal to twice CLKIN. S H3 1 O/Z External H3 clock. H3 has a period equal to twice CLKIN. S EMU0 −EMU2 3 I EMU3 1 O/Z RESERVED (5 PINS) SHZ 1 I Reserved for emulation. Use 18 kΩ −22 kΩ pullup resistors to 5 V. Reserved for emulation Shutdown high impedance. When active, SHZ shuts down the C32 and places all 3-state I/O pins in the high-impedance state. SHZ is used for board-level testing to ensure that no dual drive conditions occur. CAUTION: A low on SHZ corrupts C32 memory and register contents. Reset the device with SHZ high to restore it to a known operating condition. † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling capacitor is 0.1 µF. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 S SGUS038 − AUGUST 2002 Pin Functions (Continued) PIN NAME TYPE† DESCRIPTION NO. CONDITIONS WHEN SIGNAL IS IN HIGH Z‡ POWER / GROUND CVSS 7 I Ground DVSS 7 I Ground IVSS DVDD 4 I Ground 12 I 8 I 5 Vdc supply§ 5 Vdc supply§ 6 I Ground VDDL VSSL VSUBS 1 I Substrate, tie to ground † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling capacitor is 0.1 µF. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 7 SGUS038 − AUGUST 2002 functional block diagram Program Cache (64 × 32) 32 RAM Block 0 (256 × 32) 24 24 ÉÉÉ RAM Block 1 (256 × 32) 32 24 Boot ROM 32 24 32 A23 − A0 D31 − D0 R/W RDY HOLD HOLDA PRGW 32 PDATA Bus IR PC PADDR Bus External Memory Interface 24 DADDR1 Bus DADDR2 Bus Controller RESET INT(3-0) IACK XF(1,0) H1 H3 MCBL / MP CLKIN VDD VSS SHZ EMU0−3 Multiplexer DDATA Bus DMADATA Bus DMAADDR Bus Multiplexer STRB0 DMA Controller STRB0 Control Reg. DMA Channel 0 STRB1 Global-Contol Register Multiplexer Source-Address Register CPU2 Transfer-Counter Reg. DMA Channel 1 REG1 Global-Control Register REG2 REG1 CPU1 REG2 32 32 Source-Address Register 40 40 Destination-Address Reg. 32-Bit Barrel Shifter Multiplier Transfer-Counter Reg. 40 ExtendedPrecision Registers (R0−R7) 40 40 STRB1_B3/A−1 STRB1_B2/A−2 STRB1_B1 STRB1_B0 IOSTRB IOSTRB Control Reg. ÉÉÉ ÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉ ÉÉÉ Serial Port Serial PortControl Reg. Receive/Transmit (R/X)Timer Register Data-Transmit Register 40 32 IOSTRB ALU 40 40 STRB1 Control Reg. Peripheral Address Bus Destination-Address Reg. Peripheral Data Bus CPU1 STRB0_B3/A−1 STRB0_B2/A−2 STRB0_B1 STRB0_B0 FSX0 DX0 CLKX0 FSR0 DR0 CLKR0 Data-Receive Register Timer 0 DISP0, IR0, IR1 ARAU0 BK ARAU1 32 32 Auxiliary Registers (AR0 − AR7) 24 32 32 32 TCLK0 24 24 24 Global-Control Register Timer-Period Register Timer-Counter Register Other Registers (12) 32 Timer 1 Global-Control Register Timer-Period Register Timer-Counter Register TCLK1 operation Operation of the SM320C32-EP is identical to the 320C30 and 320C31 digital signal processors, with the exception of an enhanced external memory interface and the addition of two CPU power-management modes. external memory interface The SM320C32-EP has a configurable external memory interface with a 24-bit address bus, a 32-bit data bus, and three independent multi-function strobes. The flexibility of this unique interface enables product designers to minimize external memory-chip count. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SGUS038 − AUGUST 2002 external memory interface (continued) Up to three mutually exclusive memory areas—one program area and two data areas—can be implemented. Each memory area configuration is independent of the physical memory width and independent of the other memory areas configurations. See Figure 1. C32 STRB0 8-/16-/32-Bit Data in 8-/16-/32-Bit-Wide Memory 32-Bit Program in 16-/32-BitWide Memory 32-Bit CPU PRGW Pin STRB1 StrobeControl Registers 8-/16-/32-Bit Data in 8-/16-/32-Bit-Wide Memory 32-Bit Program in 16-/32-BitWide Memory Memory Interface IOSTRB 32-Bit Data in 32-Bit-Wide Memory 32-Bit Program in 32-BitWide Memory Figure 1. C32 External Memory Interface The SM320C32-EP external memory configuration is controlled by a combination of hardware configuration and memory-mapped control registers and can be reconfigured dynamically. The signals that control external memory configuration are the PRGW, STRB0, STRB1, and IOSTRB. The signals work as follows: D The SM320C32-EP is a 32-bit microprocessor, that is, the CPU operates on 32-bit program words. The external memory interface provides the capability of fetching instructions as either 32-bit words or two 16-bit half words from consecutive addresses. Program memory width is 16 bits if the PRGW signal is high, 32 bits if the PRGW signal is low. D STRB0 and STRB1 are sets of control signals, four signals each, that are mapped to specific ranges of external memory addresses. When an address within one of these ranges is accessed by a read or write instruction (CPU or DMA), the corresponding set of control signals is activated. Figure 8 illustrates the SM320C32-EP memory map, showing the address ranges for which the strobe signals become active. The behavior of the STRB0 and STRB1 control signals is determined by the contents of the STRB0 and STRB1 control registers. The STRB0 and STRB1 control registers each have a field that specifies the physical memory width (8, 16, or 32 bits) of the external memory address ranges they control. Another field specifies the data width (8, 16, or 32 bits) of the data contained in those addresses. The values in these fields are not required to match. For example, a 32-bit-wide physical memory space can be configured to segment each 32-bit word into four consecutive 8-bit locations, each having its own address. Each control signal set has two pins (STRBx_B2/A−2 and STRBx_B3/A−1) that can act as either byte-enable (chip-select) pins or address pins, and two dedicated byte-enable (chip-select) pins (STRBx_B0 and STRBx_B1). The pin functions are determined by the physical memory width specified in the corresponding control register: POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 9 SGUS038 − AUGUST 2002 external memory interface (continued) D For 8-bit-wide physical memory, the STRBx_B2/A−2 and STRBx_B3/A−1 pins function as address pins (least significant address bits) and the STRBx_B0 pin functions as a byte-enable (chip-select) pin. STRBx_B1 is unused. See Figure 2. 8-Bit Data Bus 8 8 Data A14 . . A3 A2 A1 A0 STRB0_B3/ A −1 STRB0_B2/ A −2 STRB0_B1 STRB0_B0 Data Memory TMS320C32 A14 A13 A12 . . A1 A0 CS NC Figure 2. C32 With 8-Bit-Wide External Memory D For 16-bit-wide physical memory, the STRBx_B3/A−1 pin functions as an address pin (least significant address bits). The STRBx_B0 and STRBx_B1 pins function as byte-enable (chip-select) pins. STRBx_B2/A−2 is unused. See Figure 3. 16-Bit Data Bus 16 8 8 STRB0_B3/ A −1 STRB0_B2 / A −2 A14 . . A3 A2 A1 A0 Data CS A14 . . A3 A2 A1 A0 NC STRB0_B1 STRB0_B0 Figure 3. C32 With 16-Bit-Wide External Memory 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Data Memory A14 A13 . . A2 A1 A0 Memory TMS320C32 Data CS SGUS038 − AUGUST 2002 external memory interface (continued) D For 32-bit-wide physical memory, all STRB0 and STRB1 pins function as byte-enable (chip-select) pins. See Figure 4. 32-Bit Data Bus 32 8 8 8 8 A2 A1 A0 CS A14 A13 . . A2 A1 A0 Data CS A14 A13 . . A2 A1 A0 Data CS A14 A13 . . A2 A1 A0 Data Memory A2 A1 A0 Data Memory A14 A13 . . Memory A14 A13 . . Memory TMS320C32 Data CS STRB0_B3/A −1 STRB0_B2/A −2 STRB0_B1 STRB0_B0 Figure 4. C32 With 32-Bit-Wide External Memory For more detailed information and examples, see TMS320C32 Addendum to the TMS320C3x User’s Guide (literature number SPRU132B) and Interfacing Memory to the SMQ320C32 DSP Application Report (literature number SPRA040). D The IOSTRB control signal, like STRB0 and STRB1, is also mapped to a specific range of addresses but it is a single signal that can access only 32-bit data from 32-bit-wide memory. Its range of addresses appears in Figure 8, the SM320C32-EP memory map. The IOSTRB bus timing is different from the STRB0 and STRB1 bus timings to accommodate slower I/O peripherals. examples Figure 5 and Figure 6 show examples of external memory configurations that can be implemented using the SM320C32-EP external memory interface. The first example has a 32-bit-wide external memory with 8- and 16-bit data areas and a 32-bit program area. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 11 SGUS038 − AUGUST 2002 examples (continued) 32-Bit-Wide Memory 8-Bit Data 8-Bit Data 320C32 8-Bit Data 8-Bit Data 32-Bit Program 16-Bit Data 32 16-Bit Data 8 8 8 8 32-Bit-Wide Data Bus Figure 5. C32 With 32-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas and 32-Bit Program Memory Figure 6 shows a configuration that can be implemented with a 16-bit external memory. Note that 32-bit data and program words can be stored and retrieved as half words. 16-Bit-Wide Memory 8-Bit Data 8-Bit Data 32-Bit Program 320C32 16-Bit Data 16 8 8 16-Bit-Wide Data Bus Figure 6. C32 With 16-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas and a 32-Bit Program Area 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SGUS038 − AUGUST 2002 examples (continued) Figure 7 shows one possible configuration that can be implemented with 8-bit external memory. Program words, which are 32-bit, cannot be executed from 8-bit-wide memory. 8-Bit-Wide Memory 8-Bit Data 320C32 16-Bit Data 8 8 8-Bit-Wide Data Bus Figure 7. C32 With 8-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 13 SGUS038 − AUGUST 2002 memory map Figure 8 depicts the memory map for the SM320C32-EP. See the TMS320C32 Addendum to the TMS320C3x User’s Guide (literature number SPRU132B) for a detailed description of this memory mapping. 0h 0h Reset-Vector Location Reserved for Boot-Loader Operations Boot 1 FFFh 1000h 1001h External Memory STRB0 Active (8.192M Words) External Memory STRB0 Active (8.188M Words) 7FFFFFh 800000h 7FFFFFh 800000h Reserved (32K Words) Reserved (32K Words) 807FFFh 808000h 8097FFh 809800h Peripheral-Bus Memory-Mapped Registers (6K-Word Internal) 807FFFh 808000h Peripheral-Bus Memory-Mapped Registers (6K-Word Internal) 8097FFh 809800h Reserved (26K Words) Reserved (26K Words) 80FFFFh 810000h 810001h 80FFFFh 810000h Boot 2 External Memory IOSTRB Active (128K) (128K Words) 82FFFFh 830000h 87FDFFh 87FE00h 87FEFFh 87FF00h 87FFFFh 880000h 8FFFFFh 900000h Reserved (314.5K Words) RAM Block 0 (256-Word Internal) RAM Block 1 (256-Word Internal) External Memory STRB0 Active (512K Words) External Memory STRB1 Active (7.168M Words) External Memory IOSTRB Active (128K) (128K Words) 82FFFFh 830000h 87FDFFh 87FE00h 87FEFFh 87FF00h 87FFFFh 880000h Reserved (319.5K Words) Internal Memory RAM Block 0 (256-Word Internal) Internal Memory RAM Block 1 (256-Word Internal) External Memory STRB0 Active (512K Words) 8FFFFFh 900000h 900001h Boot 3 External Memory STRB1 Active (7.168M Words) FFFFFFh FFFFFFh Microprocessor Mode Microcomputer/Boot-LoaderMode Figure 8. SM320C32-EP Memory Map 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SGUS038 − AUGUST 2002 power management The SM320C32-EP CPU has two power-management modes, IDLE2 and LOPOWER (low power). In IDLE2 mode, no instructions are executed and the CPU, peripherals, and memory retain their previous state while the external bus output pins are idle. During IDLE2 mode, the H1 clock signal is held high while the H3 clock signal is held low until one of the four external interrupts is asserted. In the LOPOWER mode, the CPU continues to execute instructions and the DMA continues to perform transfers, but at a reduced clock rate of the CLKIN frequency divided by 16 (that is, SM320C32-EP with a 32-MHz CLKIN frequency performs the same as a 2-MHz SM320C32-EP with an instruction cycle time of 1000 ns or 1 MHz. bootloader The SM320C32-EP flexible bootloader loads programs from the serial port, EPROM, or other standard non-volatile memory device. The boot-loader functionality of the SM320C32-EP is equivalent to that of the 320C31, and has added modes to handle the data-type sizes and memory widths supported by the external memory interface. The memory-bootload supports data transfers with and without handshaking. The handshake mode allows synchronous transfer of programs by using two pins as data-acknowledge and data-ready signals. peripherals The SM320C32-EP peripherals are comprised of one serial port, two timers, and two DMA channels. The serial port and timers are functionally identical to those in the 320C31 peripherals. The SM320C32-EP two-channel DMA coprocessor has user-configurable priorities: CPU, DMA, or rotating between CPU and DMA. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 15 SGUS038 − AUGUST 2002 peripherals (continued) Figure 9 shows the SM320C32-EP peripheral-bus control-register mapping. 808000h DMA 0 Global Control 808004h DMA 0 Source Address 808006h DMA 0 Destination Address 808008h 808009h DMA 0 Transfer Counter 808010h DMA 1 Global Control 808014h DMA 1 Source Address 808016h DMA 1 Destination Address 808018h DMA 1 Transfer Counter 808020h Timer 0 Global Control 808024h Timer 0 Counter 808028h Timer 0 Period 808030h Timer 1 Global Control 808034h Timer 1 Counter 808038h Timer 1 Period Register 808040h Serial Port Global Control 808042h FSX/DX/CLKX Port Control 808043h FSR/DR/CLKR Port Control 808044h R/X Timer Control 808045h R/X Timer Counter 808046h R/X Timer Period 808048h Data Transmit 80804Ch 808050h Data Receive Reserved 80805Fh 808060h IOSTRB-Bus Control 808064h STRB0-Bus Control 808068h 808069h STRB1-Bus Control Reserved 8097FFh Figure 9. Peripheral-Bus Memory-Mapped Registers 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SGUS038 − AUGUST 2002 interrupts To reduce external logic and simplify the interface, the external interrupts can be either edge- or level-triggered. Unlike the fixed interrupt-trap vector-table location of the 320C30 and 320C31 devices, the SM320C32-EP has a user-relocatable interrupt-trap vector table. The interrupt-trap vector table must start on a 256-word boundary. The interrupt and trap vector locations memory mapping is illustrated in Figure 10. The reset vector is fixed to address 0h as shown in Figure 8. EA (ITTP) + 00h Reserved EA (ITTP) + 01h INT0 EA (ITTP) + 02h INT1 EA (ITTP) + 03h INT2 EA (ITTP) + 04h INT3 EA (ITTP) + 05h XINT0 EA (ITTP) + 06h RINT0 EA (ITTP) + 07h Reserved EA (ITTP) + 08h Reserved EA (ITTP) + 09h TINT0 EA (ITTP) + 0Ah TINT1 EA (ITTP) + 0Bh DINT0 EA (ITTP) + 0Ch DINT1 EA (ITTP) + 0Dh Reserved EA (ITTP) + 1Fh EA (ITTP) + 20h TRAP0 . . . . EA (ITTP) + 3Bh TRAP27 EA (ITTP) + 3Ch TRAP28 EA (ITTP) + 3Dh TRAP29 EA (ITTP) + 3Eh TRAP30 EA (ITTP) + 3Fh TRAP31 Figure 10. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 17 SGUS038 − AUGUST 2002 absolute maximum ratings over specified temperature ranges (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 7 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 7 V Continuous power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.95 W Operating case temperature, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to VSS. 2. This value calculated for the C32-40. Actual operating power is less. This value was obtained under specially produced worst-case test conditions which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to the external bus at the maximum rate possible. See normal (IDD) current specification in the electrical characteristics table and see the Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020). recommended operating conditions (see Note 3) VDD VSS Supply voltage (DVDD, VDDL) MIN NOM‡ MAX UNIT 4.75 5 5.25 V Supply voltage (CVSS, VSSL, IVSS, DVSS, VSUBS) 0 CLKIN V 2.6 VDD + 0.3* VDD + 0.3* V 0.8 V VIH High-level input voltage VIL IOH Low-level input voltage High-level output current −300 µA IOL TC Low-level output current 2 mA 125 °C All other inputs 2 −0.3* Operating case temperature (see Note 4) −55 V * This parameter is not production tested. ‡ All nominal values are at VDD = 5 V, TA (ambient-air temperature)= 25°C. NOTE 3: All input and output voltage levels are TTL compatible. NOTE 4: TC MAX at maximum rated operating conditions at any point on case. TC MIN at initial (time zero) power-up. electrical characteristics over recommended ranges of supply voltage (unless otherwise noted) ‡ PARAMETER TEST CONDITIONS VOH VOL High-level output voltage IOZ II High-impedance state output current IDD VDD = MIN, VDD = MIN, Low-level output voltage VDD = MAX VI = VSS to VDD Input current Supply current (see Note 5) IOH = MAX IOL = MAX fx = 50 MHz‡ fx = 60 MHz‡ TA = 25 °C, C, fx = MAX‡ VDD = MAX, Standby IDLE2, CLKIN shut off CLKIN CI Input capacitance All other inputs POST OFFICE BOX 1443 2.4 NOM MAX 3 0.3 − 20 − 10 UNIT V 0.8 V 20 µA 10 µA 200 425 225 475 mA µA 50 25 15* Co Output capacitance * This parameter is not production tested. ‡ All nominal values are at VDD = 5 V, TA = 25°C. ‡ fx is the input clock frequency. NOTE 5: Actual operating current is less than this maximum value (see Note 2). 18 MIN • HOUSTON, TEXAS 77251−1443 20* pF pF SGUS038 − AUGUST 2002 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics VLoad CT Output Under Test IOH Where: IOL IOH VLoad CT = = = = 2 mA (all outputs) 300 µA (all outputs) Selected to emulate 50-Ω termination (typical value = 1.54 V) 80-pF typical load-circuit capacitance Figure 11. Test Load Circuit signal-transition levels TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V. Output transition times are specified in the following paragraph. For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be no longer high is 2 V and the level at which the output is said to be low is 1 V. For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at which the output is said to be high is 2 V (see Figure 12). 2.4 V 2V 1V 0.6 V Figure 12. TTL-Level Outputs Transition times for TTL-compatible inputs are specified as follows. For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 2 V and the level at which the input is said to be low is 0.8 V. For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 0.8 V and the level at which the input is said to be high is 2 V (see Figure 13). 2V 0.8 V Figure 13. TTL-Level Inputs POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 19 SGUS038 − AUGUST 2002 PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameter symbology Timing parameter symbols used in this document are in accordance with JEDEC Standard 100-A. Unless otherwise noted, in order to shorten the symbols, pin names and other related terminology have been abbreviated as follows: A A23−A0 when the physical-memory-width-bit field of the STRBx control register is set to 32 bits A23−A0 and STRBx_B3/A−1 when the physical-memory-width-bit field of the STRBx control register is set to 16 bits A23−A0, STRBx_B3/A−1, and STRBx_B2/A−2 when the physical-memory-width-bit field of the STRBx control register is set to 8 bits CI CLKIN RDY RDY D D(31 −0) H H1, H3 IOS IOSTRB P tc(H) Q tc(CI) RW R/ W S STRBx_B(3−0) when the physical-memory-width-bit field of the STRBx control register is set to 32 bits STRBx_B(1−0) when the physical-memory-width-bit field of the STRBx control register is set to 16 bits STRBx_B0 when the physical-memory-width-bit field of the STRBx control register is set to 8 bits XF XF0 or XF1 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SGUS038 − AUGUST 2002 timings for CLKIN [Q = tc(CI)] (see Figure 14) TEST CONDITIONS NO. 1 2 3 4 tf(CI)† tw(CIL)† Fall time, CLKIN Pulse duration, CLKIN low Q = min tw(CIH) tr(CI)† Pulse duration, CLKIN high Q = min 320C32-50 320C32-60 MIN MIN MAX 5* 7 8† Rise time, CLKIN 4* 6 6† 5* tc(CI)† Cycle time, CLKIN † Minimum CLKIN high-pulse duration at 3.3 MHz is 10 ns. * This parameter is not production tested. 5 20 MAX 303 16.67 UNIT ns ns ns 4* ns 303 ns 5 4 1 CLKIN 3 2 Figure 14. CLKIN Timing switching characteristics for H1 and H3 over recommended operating conditions (unless otherwise noted) (see Figure 15) NO. 6 7 8 9 9.1 10 PARAMETER TEST CONDITIONS 320C32-50 320C32-60 MIN MIN MAX tf(H) tw(HL) Fall time, H1 / H3 3 Pulse duration, H1 / H3 low Q −5 Q −4 tw(HH) tr(H) Pulse duration, H1 / H3 high Q −6 Q −5 td(HL-HH) tc(H) Delay time, H1 / H3 low to H1 / H3 high 0* 4 Cycle time, H1 / H3 40 606 Rise time, H1 / H3 MAX 3 3 UNIT ns ns ns 3 ns 0* 4 ns 33.33 606 ns * This parameter is not production tested. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 21 SGUS038 − AUGUST 2002 switching characteristics for H1 and H3 (see Figure 15) (continued) 10 6 9 H1 8 7 9.1 9.1 H3 8 9 7 10 Figure 15. H1 / H3 Timing 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 6 SGUS038 − AUGUST 2002 memory-read-cycle and memory-write-cycle timing (STRBx) (see Figure 16 and Figure 17) NO. 11 12 13 14 15 16 17 18 19 20 21 22 320C32-50 320C32-60 MIN MAX MIN MAX UNIT td(H1L - SL) td(H1L - SH) Delay time, H1 low to STRBx low 0* 9 0* 7 ns Delay time, H1 low to STRBx high 0* 9 0* 7 ns td(H1H - RWL) td(H1L - A) Delay time, H1 high to R / W low (read) 0* 9 0* 8 ns Delay time, H1 low to A valid 0* 9 0* 7 ns tsu(D)R th(D)R Setup time, D valid before H1 low (read) 10 Hold time, D after H1 low (read) tsu(RDY) th(RDY) Setup time, RDY before H1 low td(H1H - RWH) tv(D)W Delay time, H1 high to R / W high (write) th(D)W td(H1H - A) Hold time, D after H1 high (write) Hold time, RDY after H1 low 10 ns 0 0 ns 19 17 ns 0 0 Valid time, D after H1 low (write) ns 9 8 ns 14 12 ns 0* 0* Delay time, H1 high to A valid on back-to-back write cycles 9 ns 8 ns * This parameter is not production tested. H3 H1 11 12 STRBx† R/W 15 14 13 A 16 D 18 17 RDY NOTE A: STRBx remains operations. low during back-to-back Figure 16. Memory-Read-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 23 SGUS038 − AUGUST 2002 memory-read-cycle and memory-write-cycle timing (STRBx) (see Figure 16 and Figure 17) (continued) H3 H1 11 12 STRBx 13 19 R/W 22 14 A 20 21 D 18 RDY 17 Figure 17. Memory-Write-Cycle Timing 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SGUS038 − AUGUST 2002 memory-read-cycle timing using IOSTRB (see Figure 18) NO. 11.1 12.1 13.1 14.1 15.1 16.1 17.1 18.1 320C32-50 320C32-60 MIN MAX MIN MAX UNIT td(H3L-IOSL) td(H3L-IOSH) Delay time, H3 low to IOSTRB low 0* 9 0* 8 ns Delay time, H3 low to IOSTRB high 0* 9 0* 8 ns td(H1L-RWL) td(H1L-A) Delay time, H1 low to R / W high 0* 9 0* 8 ns Delay time, H1 low to A valid 0* 9 0* 8 ns tsu(D)R th(D)R Setup time, D before H1 high 10 9 ns Hold time, D after H1 high 0 0 ns tsu(RDY) th(RDY) Setup time, RDY before H1 high 8 7 ns Hold time, RDY after H1 high 0 0 ns * This parameter is not production tested. H3 H1 11.1 12.1 IOSTRB 23† 13.1 R/W 14.1 A 15.1 16.1 D 17.1 18.1 RDY NOTE A: See Figure 19 and accompanying table Figure 18. Memory-Read-Cycle Timing Using IOSTRB POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 25 SGUS038 − AUGUST 2002 memory-write-cycle timing using IOSTRB (see Figure 19) NO. 23 24 td(H1L-RWH) tv(D)W Delay time, H1 low to R / W low 320C32-50 320C32-60 MIN MAX MIN 9 0* 0* Valid time, D after H1 high 14 25 th(D)W Hold time, D after H1 low * This parameter is not production tested. 0 H3 H1 11.1† 12.1† IOSTRB 13.1† 23† R/W 14.1† A 24 25 D 17.1† 18.1† RDY NOTE A: See Figure 18 and accompanying table Figure 19. Memory-Write-Cycle Timing Using IOSTRB 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 0 MAX UNIT 8 ns 12 ns ns SGUS038 − AUGUST 2002 timing for XF0 and XF1 when executing LDFI or LDII (see Figure 20) NO. 38 320C32-50 320C32-60 MIN MIN MAX td(H3H-XF0L) tsu(XF1) Delay time, H3 high to XF0 low Setup time, XF1 before H1 low 9 8 ns 40 th(XF1) Hold time, XF1 after H1 low 0 0 ns Decode Read 11 UNIT 39 Fetch LDFI or LDII 12 MAX ns Execute H3 H1 STRBx R/W A D RDY 38 XF0 39 40 XF1 Figure 20. XF0 and XF1 When Executing LDFI or LDII POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 27 SGUS038 − AUGUST 2002 timing for XF0 when executing STFI or STII † (see Figure 21) NO. 320C32-50 320C32-60 MIN MIN MAX MAX UNIT 41 td(H3H-XF0H) Delay time, H3 high to XF0 high 12 11 ns † XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of the store is driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store from executing, the address of the store is not driven until the store can execute. Fetch STFI or STII Decode Read Execute H3 H1 STRBx R/W A D 41 RDY XF0 Figure 21. XF0 When Executing a STFI or STII 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SGUS038 − AUGUST 2002 timing for XF0 and XF1 when executing SIGI (see Figure 22) 320C32-50 320C32-60 MIN MIN NO. 41.1 42 43 44 MAX MAX UNIT td(H3H-XF0L) td(H3H-XF0H) Delay time, H3 high to XF0 low 12 11 ns Delay time, H3 high to XF0 high 12 11 ns tsu(XF1) th(XF1) Setup time, XF1 before H1 low 9 8 ns Hold time, XF1 after H1 low 0 0 ns Fetch SIGI Decode Read Execute H3 H1 41.1 43 42 XF0 44 XF1 Figure 22. XF0 and XF1 When Executing SIGI timing for loading XF register when configured as an output pin (see Figure 23) NO. 45 tv(H3H-XF) Valid time, H3 high to XF valid Fetch Load Instruction Decode 320C32-50 320C32-60 MIN MIN MAX 12 Read MAX 11 UNIT ns Execute H3 H1 OUTXF Bit† 1 or 0 45 XFx NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register. Figure 23. Loading XF Register When Configured as an Output Pin POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 29 SGUS038 − AUGUST 2002 timing of XF changing from output to input mode (see Figure 24) 320C32-50 NO. 46 47 MIN th(H3H-XF01) tsu(XF) Hold time, XF after H3 high 48 th(XF) Hold time, XF after H1 low * This parameter is not production tested. H3 MAX MIN MAX 12* Setup time, XF before H1 low Buffers Go from Ouput to Input Execute Load of IOF 320C32-60 11* 8 ns 0 0 ns Value on Pin Seen in IOF H1 47 48 46 XFx Output INXFx Bit† Data Sampled Data Seen NOTE A: I / OXFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register. Figure 24. Change of XF From Output to Input Mode 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ns 9 Synchronizer Delay I / OXFx Bit† UNIT SGUS038 − AUGUST 2002 timing of XF changing from input to output mode (see Figure 25) NO. 49 td(H3H-XFIO) 320C32-50 320C32-60 MIN MIN Delay time, H3 high to XF switching from input to output MAX 17 MAX 15 UNIT ns Execution of Load of IOF H3 H1 I / OXFx Bit† 49 XFx NOTE A: I / OXFx represents either bit 1 or bit 5 of the IOF register. Figure 25. Change of XF From Input to Output Mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 31 SGUS038 − AUGUST 2002 timing for RESET [Q = tc(CI)] (see Figure 26) NO. 50 320C32-50 320C32-60 MIN MAX MIN MAX UNIT tsu(RESET) td(CLKINH-H1H) Setup time, RESET before CLKIN low 10 Q* 17 Q* ns 51 Delay time, CLKIN high to H1 high 2 10 2 10 ns 52 td(CLKINH-H1L) Delay time, CLKIN high to H1 low 2 10 2 10 ns 53 tsu(RESETH-H1L) Setup time, RESET high before H1 low and after ten H1 clock cycles 7 54 td(CLKINH-H3L) td(CLKINH-H3H) Delay time, CLKIN high to H3 low 2 10 2 10 ns Delay time, CLKIN high to H3 high 2 10 2 10 ns tdis(H1H-D) tdis(H3HL-A) Disable time, H1 low to D in the high-impedance state 12* 11* ns Disable time, H3 low to A in the high-impedance state 9* 9* ns td(H3H-CONTROLH) td(H1H-RWH) Delay time, H3 high to control signals high 8* 7* ns Delay time, H1 low to R / W high 8* 7* ns 59 td(H1H-IACKH) Delay time, H1 high to IACK high 8* 7* ns 60 tdis(RESETL-ASYNCH) Disable time, RESET low to asynchronous reset signals in the high-impedance state 17* 14* ns 55 56 57 58.1 58.2 6 ns * This parameter is not production tested. CLKIN RESET†‡ 50 51 52 53 H1 54 H3 10 H1 Clock Cycles 56 55 D§ 57 A§ 58.1 Control Signals ¶ 58.2 R/W 59 IACK Asynchronous Reset Signals # 60 NOTES: A. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. B. The R / W output is placed in the high-impedance state during reset and can be provided with a resistive pullup, nominally 18 −22 kΩ, if undesirable spurious writes can occur when these outputs go low. C. In microprocessor mode (MCBL / MP = 0), reset vector is fetched twice with seven software wait states each. In microcomputer mode (MCBL / MP = 1), the reset vector is fetched two times, with no software wait states. D. Control signals include STRBx and IOSTRB. E. Asynchronous reset signals include XF0 / 1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLKx . Figure 26. RESET Timing 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SGUS038 − AUGUST 2002 timing for INT3 −INT0 interrupt response [P = tc(H)] (see Figure 27) NO. 61 62.1 tsu(INT) Setup time, INT3−INT0 before H1 low tw(INT) Pulse duration of interrupt to assure only one interrupt seen for level-triggered interrupts 320C32-50 320C32-60 MIN MIN MAX 10 62.2 tw(INT) Pulse duration of interrupt for edge-triggered interrupts * This parameter is not production tested. P P* Reset or Interrupt Vector Read MAX 8 2P* P P* UNIT ns 2P* ns ns Fetch First Instruction of Service Routine H3 H1 61 INT3 −INT0 Pin 62.1 INT3 −INT0 Flag 62.2 A Vector Address First Instruction Address D Figure 27. INT3−INT0 Interrupt-Response Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 33 SGUS038 − AUGUST 2002 timing for IACK (see Notes 6, 7, and Figure 28) NO. 63 64 td(H1H-IACKL) td(H1H-IACKH) 320C32-50 320C32-60 MIN MIN MAX MAX UNIT Delay time, H1 high to IACK low 7 6 ns Delay time, H1 high to IACK high 7 6 ns NOTES: 6. IACK is active for the entire duration of the bus cycle and is extended if the bus cycle utilizes wait states. 7. IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle (H1 rising) of the read phase of the IACK instruction. Because of pipeline conflicts, IACK remains low for one cycle even if the decode phase of the IACK instruction is extended. Fetch IACK Instruction Decode IACK Instruction IACK Data Read H3 H1 63 64 IACK A D Figure 28. IACK Timing 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SGUS038 − AUGUST 2002 serial-port timing serial-port timing [P = tc(H)] (see Figure 29 and Figure 30) 320C32-50 NO. MIN 65 td(H1-SCK) Delay time, H1 high to internal CLKX / R high/low 2.6P tc(SCK) Cycle time, CLKX / R CLKX / R ext 66 CLKX / R int 2P tw(SCK) Pulse duration, CLKX / R high / low CLKX / R ext 67 68 tr(SCK) tf(SCK) 69 CLKX / R int 320C32-60 MAX MIN MAX 10 Rise time, CLKX / R 8 ns (232)P ns 2.6P (232)P P + 10 [tc(SCK) / 2] −5 2P P + 10 [tc(SCK) / 2] + 5 6 Fall time, CLKX / R [tc(SCK) / 2] −5 [tc(SCK) / 2] + 5 5 6 5 24 20 CLKX int 16 15 70 td(DX) Delay time, CLKX to DX valid CLKX ext 9 8 tsu(DR) Setup time, DR before CLKR low CLKR ext 71 CLKR int 17 15 7 6 th(DR) Hold time, DR from CLKR low CLKR ext 72 CLKR int 0 0 22 20 td(FSX) Delay time, CLKX to internal FSX high / low CLKX ext 73 CLKX int 15 14 7 6 tsu(FSR) Setup time, FSR before CLKR low CLKR ext 74 CLKR int 7 6 7 6 th(FS) Hold time, FSX / R input from CLKX / R low CLKX / R ext 75 CLKX / R int 0 0 Setup time, external FSX before CLKX high CLKX ext 8 −P [tc(SCK) / 2]−10* 8 −P [tc(SCK) / 2]−10* tsu(FSX) CLKX int 21 −P tc(SCK) / 2* 21 −P tc(SCK) / 2* CLKX ext 24* 20* td(CH-DX)V Delay time, CLKX to first DX bit, FSX precedes CLKX high CLKX int 14* 12* 76 77 UNIT ns ns ns ns ns ns ns ns ns ns ns 78 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 24* 20* ns 79 td(DXZ) Delay time, CLKX high to DX in the high-impedance state following last data bit 14* 12* ns * This parameter is not production tested. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 35 SGUS038 − AUGUST 2002 serial-port timing 66 65 H1 65 67 67 CLKX / R 69 68 77 72 Bit n-1 DX 79 70 Bit 0 Bit n-2 71 DR Bit n-1 FSR Bit n-2 74 73 73 75 FSX(INT) FSX(EXT) 75 76 NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend upon the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. Figure 29. Fixed Data-Rate-Mode Timing CLKX / R 73 FSX(INT) 78 76 FSX(EXT) 70 79 77 Bit n-1 DX Bit n-2 Bit n-3 Bit 0 75 FSR 74 Bit n-1 DR 71 Bit n-2 Bit n-3 72 NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend upon the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed data-rate mode. Figure 30. Variable Data-Rate-Mode Timing 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SGUS038 − AUGUST 2002 timing for HOLD/HOLDA [P = tc(H)] (see Note 8 and Figure 31) 320C32-50 NO. 80 81 82 83 84 84.1 MIN 320C32-60 MAX MIN 7 0* MAX UNIT tsu(HOLD) tv(HOLDA) Setup time, HOLD before H1 low 10 Valid time, HOLDA after H1 low 0* tw(HOLD) tw(HOLDA) Pulse duration, HOLD low td(H1L-SH)H td(H1H-IOS)H Delay time, H1 low to STRBx high for a HOLD 0* 7* 0* 6* ns Delay time, H1 high to IOSTRB high for a HOLD 0* 7* 0* 6* ns Disable time, H1 low to STRBx or IOSTRB (in the high-impedance state) 0* 8* 0* 7* ns Pulse duration, HOLDA low 8 2P 2P P −5* P −5* ns 6 ns ns ns 85 tdis(H1L-S) 86 ten(H1L-S) tdis(H1L-RW) Enable time, H1 low to STRBx or IOSTRB active 0* 7* 0* 6* ns Disable time, H1 low to R/W in the high-impedance state 0* 8* 0* 7* ns ten(H1L-RW) tdis(H1L-A) Enable time, H1 low to R/W (active) 0* 7* 0* 6* ns Disable time, H1 low to A in the high-impedance state 0* 8* 0* 7* ns ten(H1L-A) tdis(H1H-D) Enable time, H1 low to A valid 0* 12* 0* 11* ns Disable time, H1 high to D disabled in the high-impedance state 0* 8* 0* 7* ns 87 88 89 90 91 * This parameter is not production tested. NOTE 8: HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. The NOHOLD bit of the primary-bit-control register overwrites the HOLD signal. H3 H1 80 80 82 HOLD 81 81 83 HOLDA (see Note A) 84 85 86 85 86 STRBx 84.1 IOSTRB 87 88 R/W 89 90 A 91 D Write Data NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle after HOLD goes back high. Figure 31. HOLD / HOLDA Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 37 SGUS038 − AUGUST 2002 timing of peripheral pin configured as general-purpose I/O (see Figure 32) 320C32-50 NO. 92 MIN MAX 320C32-60 MIN MAX UNIT tsu(GPIOH1L) th(GPIOH1L) Setup time, general-purpose input before H1 low 9 8 ns 93 Hold time, general-purpose input after H1 low 0 0 ns 94 td(GPIOH1H) Delay time, general-purpose output after H1 high 10 8 ns H3 H1 93 92 94 94 Peripheral Pin (see Note A) NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents of internal control registers associated with each peripheral. Figure 32. Peripheral-Pin General-Purpose I / O Timing timing of peripheral pin changing from general-purpose output to input mode (see Figure 33) NO. 95 96 th(H1H) tsu(GPI0H1L) 320C32-50 320C32-60 MIN MIN MAX Hold time, after H1 high 12* Setup time, peripheral pin before H1 low 97 th(GPIOH1L) Hold time, peripheral pin after H1 low * This parameter is not production tested. Execute Store of Peripheral Control Register Buffers Go From Output to Input MAX 11* UNIT ns 9 8 ns 0 0 ns Synchronizer Delay Value on Pin Seen in Peripheral Control Register H3 H1 I/O Control Bit 96 97 95 Peripheral Pin (see Note A) Output Data Bit Data Sampled Data Seen NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents of internal control registers associated with each peripheral. Figure 33. Timing of Peripheral Pin Changing From General-Purpose Output to Input Mode 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SGUS038 − AUGUST 2002 timing of peripheral pin changing from general-purpose input to output mode (see Figure 34) NO. 98 td(GPIOH1H) Delay time, H1 high to peripheral pin switching from input to output 320C32-50 320C32-60 MIN MIN MAX 10 MAX 8 UNIT ns Execution of Store of Peripheral Control Register H3 H1 I / O Control Bit 98 Peripheral Pin (see Note A) NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents of internal control registers associated with each peripheral. Figure 34. Timing of Peripheral Pin Changing From General-Purpose Input-to-Output Mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 39 SGUS038 − AUGUST 2002 timing for timer pin [P = tc(H)] (see Figure 35) 320C32-50 NO. MIN 320C32-60 MAX MIN MAX UNIT 99 tsu(TCLKH1L) Setup time, TCLK external before H1 low 8 6 ns 100 th(TCLKH1L) Hold time, TCLK external after H1 low 0 0 ns 101 td(TCLKH1H) Delay time, H1 high to TCLK internal valid 2.6P* tc(TCLK) Cycle time, TCLK cycle time TCLK external 102 TCLK internal 2P Pulse duration, TCLK high / low TCLK external P + 10* tw(TCLK) 103 9 8 ns 2.6P* (232)P* 2P (232)P* ns P + 10* ns TCLK internal [tc(TCLK) / 2] −5 [tc(TCLK) / 2]+5 [tc(TCLK) / 2] −5 [tc(TCLK) / 2]+5 * This parameter is not production tested. NOTE: Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous input clock. H3 H1 100 99 101 TCLKx 103 102 Figure 35. Timing for Timer Pin 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 101 SGUS038 − AUGUST 2002 timing for SHZ pin [Q = tc(CI)] (see Figure 36) NO. 104 tdis(SHZ) Disable time, SHZ low to all O, I/O pins in the high-impedance state * This parameter is not production tested. 320C32-50 320C32-60 MIN MAX MIN MAX 0* 2Q* 0* 2Q* UNIT ns H3 H1 SHZ (see Note A) 104 All I/O Pins NOTE A: Enabling SHZ destroys C32 register and memory contents. Assert SHZ = 1 and reset the C32 to restore it to a known condition. Figure 36. SHZ Pin Timing Table 1. Thermal Resistance Characteristics for PCM package PARAMETER RΘJA Junction-to-free-air RΘJC Junction-to-case POST OFFICE BOX 1443 MIN • HOUSTON, TEXAS 77251−1443 MAX UNIT 39 °C / W 10.0 °C / W 41 PACKAGE OPTION ADDENDUM www.ti.com 31-Mar-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp SM320C32PCMM50EP NRND QFP PCM 144 24 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR SM320C32PCMM60EP NRND QFP PCM 144 24 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR V62/03616-01XE NRND QFP PCM 144 24 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR V62/03616-02XE NRND QFP PCM 144 24 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MQFP022A – JANUARY 1995 – REVISED MAY 1999 PCM (S-PQFP-G***) PLASTIC QUAD FLATPACK 144 PINS SHOWN 108 73 109 NO. OF PINS*** A 144 22,75 TYP 160 25,35 TYP 72 0,38 0,22 0,13 M 0,65 144 37 0,16 NOM 1 36 A 28,20 SQ 27,80 31,45 SQ 30,95 3,60 3,20 Gage Plane 0,25 0,25 MIN 1,03 0,73 Seating Plane 4,10 MAX 0,10 4040024 / B 10/94 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-022 The 144 PCM is identical to the 160 PCM except that four leads per corner are removed. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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