ETC TMS320VC33-150

SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
D High-Performance Floating-Point Digital
D
D
D
D
D
D
D
D
D
D
Signal Processor (DSP):
– TMS320VC33-150
– 13-ns Instruction Cycle Time
– 150 Million Floating-Point Operations
Per Second (MFLOPS)
– 75 Million Instructions Per Second
(MIPS)
– TMS320VC33-120
– 17-ns Instruction Cycle Time
– 120 MFLOPS
– 60 MIPS
34K × 32-Bit (1.1-Mbit) On-Chip Words of
Dual-Access Static Random-Access
Memory (SRAM) Configured in 2 × 16K Plus
2 × 1K Blocks to Improve Internal
Performance
x5 Phase-Locked Loop (PLL) Clock
Generator
Very Low Power: < 200 mW @ 150 MFLOPS
32-Bit High-Performance CPU
16-/32-Bit Integer and 32-/40-Bit
Floating-Point Operations
Four Internally Decoded Page Strobes to
Simplify Interface to I/O and Memory
Devices
Boot-Program Loader
EDGEMODE Selectable External Interrupts
32-Bit Instruction Word, 24-Bit Addresses
Eight Extended-Precision Registers
D On-Chip Memory-Mapped Peripherals:
D
D
D
D
D
D
D
D
D
D
D
D
D
– One Serial Port
– Two 32-Bit Timers
– Direct Memory Access (DMA)
Coprocessor for Concurrent I/O and CPU
Operation
Fabricated Using the 0.18-µm (leff-Effective
Gate Length) TImeline Technology by
Texas Instruments (TI)
144-Pin Low-Profile Quad Flatpack (LQFP)
(PGE Suffix)
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Two Low-Power Modes
Two- and Three-Operand Instructions
Parallel Arithmetic/Logic Unit (ALU) and
Multiplier Execution in a Single Cycle
Block-Repeat Capability
Zero-Overhead Loops With Single-Cycle
Branches
Conditional Calls and Returns
Interlocked Instructions for
Multiprocessing Support
Bus-Control Registers Configure
Strobe-Control Wait-State Generation
1.8-V (Core) and 3.3-V (I/O) Supply Voltages
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1† (JTAG)
description
The TMS320VC33 DSP is a 32-bit, floating-point processor manufactured in 0.18-µm four-level-metal CMOS
(TImeline) technology. The TMS320VC33 is part of the TMS320C3x generation of DSPs from Texas
Instruments.
The TMS320C3x’s internal busing and special digital-signal-processing instruction set have the speed and
flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The TMS320VC33
optimizes speed by implementing functions in hardware that other processors implement through software or
microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.
The TMS320VC33 can perform parallel multiply and ALU operations on integer or floating-point data in a single
cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,
internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time.
High performance and ease of use are the results of these features.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TImeline is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port
Copyright  2002, Texas Instruments Incorporated
!"# $ %
$ ! ! & ' $$ ()% $ ! * $ #) #$
* ## ! %
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1
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
description (continued)
General-purpose applications are greatly enhanced by the large address space, multiprocessor interface,
internally and externally generated wait states, one external interface port, two timers, one serial port, and
multiple-interrupt structure. The TMS320C3x supports a wide variety of system applications from host
processor to dedicated coprocessor. High-level-language support is easily implemented through a
register-based architecture, large address space, powerful addressing modes, flexible instruction set, and
well-supported floating-point arithmetic.
The TMS320VC33 is a superset of the TMS320C31. Designers now have an additional 1M bits of on-chip
SRAM, a maximum throughput of 150 MFLOPS, and several I/O enhancements that allow easy upgrades to
current systems or creation of new baselines. This data sheet provides information required to fully utilize the
new features of the TMS320VC33 device. For general TMS320C3x architecture and programming information,
see the TMS320C3x User’s Guide (literature number SPRU031).
2
POST OFFICE BOX 1443
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
pinout
109
111
110
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
74
36
73
DV DD
DVDD
CLKR0
FSR0
VSS
DR0
TRST
TMS
CVDD
TDI
TDO
TCK
VSS
EMU0
EMU1
DVDD
D0
D1
D2
D3
VSS
D4
D5
DVDD
D6
D7
CVDD
D8
D9
VSS
D10
D11
DVDD
D12
D13
D14
D15
72
75
35
71
76
34
70
77
33
69
78
32
68
79
31
67
80
30
66
81
29
65
82
28
64
83
27
63
84
26
62
85
25
61
86
24
60
87
23
59
88
22
58
89
21
57
90
20
56
91
19
55
92
18
54
93
17
53
94
16
52
95
15
51
96
14
50
97
13
49
98
12
48
99
11
47
100
10
46
101
9
45
102
8
44
103
7
43
104
6
42
105
5
41
106
4
40
3
39
107
38
108
2
37
1
H1
H3
V SS
STRB
R/W
DV DD
IACK
RDY
CVDD
HOLD
HOLDA
V SS
D31
D30
D29
DVDD
D28
D27
V SS
D26
D25
D24
DV DD
D23
D22
V SS
D21
D20
CVDD
D19
D18
DV DD
D17
D16
V SS
A20
VSS
A19
A18
A17
DVDD
A16
A15
VSS
A14
A13
CVDD
A12
A11
DVDD
A10
A9
VSS
A8
A7
A6
A5
DVDD
A4
VSS
A3
A2
CVDD
A1
A0
DVDD
PAGE3
PAGE2
VSS
PAGE1
PAGE0
143
144
A21
DV DD
A22
A23
V SS
RSV0
RSV1
CVDD
CLKMD0
CLKMD1
PLLV SS
XIN
XOUT
PLLV DD
EXTCLK
DV DD
SHZ
RESET
V SS
MCBL/MP
EDGEMODE
CVDD
INT0
INT1
INT2
INT3
V SS
XF0
XF1
DV DD
TCLK0
TCLK1
V SS
DX0
FSX0
CLKX0
PGE PACKAGE†‡
(TOP VIEW)
† DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O
pins and the core CPU.
‡ PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively.
The TMS320VC33 device is packaged in 144-pin low-profile quad flatpack (PGE Suffix).
POST OFFICE BOX 1443
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3
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
Terminal Assignments† (Alphabetical)
SIGNAL
NAME
PIN
NUMBER
SIGNAL
NAME
PIN
NUMBER
A0
30
D0
93
A1
29
D1
92
A2
27
D2
A3
26
D3
A4
24
A5
A6
SIGNAL
NAME
PIN
NUMBER
31
R/W
42
37
RDY
45
91
43
RESET
127
90
53
RSV0
139
D4
88
60
RSV1
138
22
D5
87
69
SHZ
128
21
D6
85
77
STRB
41
A7
20
D7
84
86
TCK
98
A8
19
D8
82
94
TCLK0
114
A9
17
D9
81
108
TCLK1
113
A10
16
D10
79
115
TDI
100
A11
14
D11
78
129
TDO
99
A12
13
D12
76
143
TMS
102
A13
11
D13
75
DX0
111
TRST
103
A14
10
D14
74
EDGEMODE
124
2
A15
8
D15
73
EMU0
96
9
A16
7
D16
71
EMU1
95
18
A17
5
D17
70
EXTCLK
130
25
A18
4
D18
68
FSR0
106
34
A19
3
D19
67
FSX0
110
40
A20
1
D20
65
H1
38
49
A21
144
D21
64
H3
39
56
A22
142
D22
62
HOLD
47
A23
141
D23
61
HOLDA
48
CLKMD0
136
D24
59
IACK
44
80
CLKMD1
135
D25
58
INT0
122
89
CLKR0
107
D26
57
INT1
121
97
CLKX0
109
D27
55
INT2
120
105
12
D28
54
INT3
119
112
28
D29
52
MCBL/MP
125
118
46
D30
51
PAGE0
36
126
66
D31
50
PAGE1
35
140
83
DR0
CVDD
SIGNAL
NAME
PIN
NUMBER
DVDD
63
VSS
72
104
PAGE2
33
XIN
133
101
6
32
XOUT
132
123
15
PAGE3
PLLVDD‡
131
XF0
117
‡
137
23
PLLVSS
134
XF1
116
† DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core
CPU.
‡ PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively.
4
DVDD
POST OFFICE BOX 1443
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
Terminal Assignments† (Numerical)
PIN
NUMBER
SIGNAL
NAME
PIN
NUMBER
SIGNAL
NAME
PIN
NUMBER
SIGNAL
NAME
PIN
NUMBER
SIGNAL
NAME
1
A20
37
DVDD
73
D15
109
CLKX0
2
38
H1
74
D14
110
FSX0
3
VSS
A19
39
H3
75
D13
111
DX0
4
A18
40
76
D12
112
5
A17
41
VSS
STRB
77
DVDD
113
VSS
TCLK1
6
DVDD
A16
42
R/W
78
D11
114
TCLK0
43
DVDD
79
D10
115
DVDD
8
A15
44
IACK
80
XF1
VSS
A14
45
RDY
81
VSS
D9
116
9
117
XF0
46
CVDD
82
D8
118
11
A13
47
HOLD
83
CVDD
119
VSS
INT3
12
48
HOLDA
84
D7
120
INT2
13
CVDD
A12
49
D6
121
INT1
A11
50
VSS
D31
85
14
86
DVDD
122
INT0
15
51
D30
87
D5
123
CVDD
16
DVDD
A10
52
D29
88
D4
124
EDGEMODE
17
A9
53
DVDD
89
125
MCBL/MP
18
54
D28
90
126
19
VSS
A8
VSS
D3
55
D27
91
D2
127
VSS
RESET
20
A7
56
92
D1
128
SHZ
21
A6
57
VSS
D26
93
D0
129
22
A5
58
D25
94
DVDD
130
23
DVDD
A4
59
D24
95
EMU1
131
DVDD
EXTCLK
PLLVDD‡
60
DVDD
96
EMU0
132
XOUT
VSS
A3
61
D23
97
133
XIN
62
D22
98
VSS
TCK
134
27
A2
63
99
TDO
135
28
64
100
TDI
136
CLKMD0
29
CVDD
A1
VSS
D21
PLLVSS‡
CLKMD1
65
D20
101
CVDD
137
CVDD
30
A0
66
CVDD
102
TMS
138
RSV1
31
DVDD
PAGE3
67
D19
103
TRST
139
RSV0
32
68
D18
104
DR0
140
33
PAGE2
69
DVDD
105
141
VSS
A23
34
VSS
PAGE1
70
D17
106
VSS
FSR0
142
A22
71
D16
107
CLKR0
143
DVDD
7
10
24
25
26
35
36
PAGE0
72
VSS
108
DVDD
144
A21
† DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core
CPU.
‡ PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively.
POST OFFICE BOX 1443
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5
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
Terminal Functions
TERMINAL
NAME
TYPE†
DESCRIPTION
QTY
CONDITIONS
WHEN
SIGNAL IS Z TYPE‡
PRIMARY-BUS INTERFACE
32-bit data port
S
Data port bus keepers. (See Figure 9)
S
D31 D0
D31–D0
32
I/O/Z
A23–A0
24
O/Z
24-bit address port
H
R
S
H
R
S
H
R
R/W
1
O/Z
Read/write. R/W is high when a read is performed and low when a write is performed
over the parallel interface.
STRB
1
O/Z
Strobe. For all external-accesses
S
H
PAGE0 –
PAGE3
1
O/Z
Page strobes. Four decoded page strobes for external access
S
H
RDY
1
I
Ready. RDY indicates that the external device is prepared for a transaction
completion.
HOLD
1
I
Hold. When HOLD is a logic low, any ongoing transaction is completed. A23–A0,
D31–D0, STRB, and R/W are placed in the high-impedance state and all
transactions over the primary-bus interface are held until HOLD becomes a logic high
or until the NOHOLD bit of the primary-bus-control register is set.
O/Z
Hold acknowledge. HOLDA is generated in response to a logic-low on HOLD.
HOLDA indicates that A23–A0, D31–D0, STRB, and R/W are in the high-impedance
state and that all transactions over the bus are held. HOLDA is high in response to
a logic-high of HOLD or the NOHOLD bit of the primary-bus-control register is set.
HOLDA
1
R
S
CONTROL SIGNALS
RESET
1
I
Reset. When RESET is a logic low, the device is in the reset condition. When RESET
becomes a logic high, execution begins from the location specified by the reset
vector.
EDGEMODE
1
I
Edge mode. Enables interrupt edge mode detection.
INT3–INT0
4
I
External interrupts
IACK
1
O/Z
MCBL/MP
1
I
Microcomputer Bootloader/microprocessor mode-select
Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used
to indicate when a section of code is being executed.
SHZ
1
I
Shutdown high impedance. When active, SHZ places all pins in the high-impedance
state. SHZ can be used for board-level testing or to ensure that no dual-drive
conditions occur. CAUTION: A low on SHZ corrupts the device memory and register
contents. Reset the device with SHZ high to restore it to a known operating condition.
XF1, XF0
2
I/O/Z
External flags. XF1 and XF0 are used as general-purpose I/Os or to support
interlocked processor instruction.
CLKR0
1
I/O/Z
CLKX0
1
DR0
DX0
S
S
R
Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver.
S
R
I/O/Z
Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
transmitter.
S
R
1
I/O/Z
Data-receive. Serial port 0 receives serial data on DR0.
S
R
1
I/O/Z
Data-transmit output. Serial port 0 transmits serial data on DX0.
S
R
FSR0
1
I/O/Z
Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive
process using DR0.
S
R
FSX0
1
I/O/Z
Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit
process using DX0.
S
R
SERIAL PORT 0 SIGNALS
† I = input, O = output, Z = high-impedance state
‡ S = SHZ active, H = HOLD active, R = RESET active
§ Recommended decoupling. Four 0.1 µF for CVDD and eight 0.1 µF for DVDD.
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
Terminal Functions (Continued)
TERMINAL
NAME
CONDITIONS
WHEN
SIGNAL IS Z TYPE‡
TYPE†
DESCRIPTION
S
R
S
R
QTY
TIMER SIGNALS
TCLK0
1
I/O/Z
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As
an output, TCLK0 outputs pulses generated by timer 0.
TCLK1
1
I/O/Z
Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As
an output, TCLK1 outputs pulses generated by timer 1.
H1
1
O/Z
External H1 clock
S
H3
1
O/Z
External H3 clock
S
SUPPLY AND OSCILLATOR SIGNALS
CVDD
8
I
+VDD. Dedicated 1.8-V power supply for the core CPU. All must be connected to
a common supply plane.§
DVDD
16
I
+VDD. Dedicated 3.3-V power supply for the I/O pins. All must be connected to a
common supply plane.§
VSS
PLLVDD
18
I
Ground. All grounds must be connected to a common ground plane.
1
I
Internally isolated PLL supply. Connect to CVDD (1.8 V)
PLLVSS
1
I
Internally isolated PLL ground. Connect to VSS
EXTCLK
1
I
External clock. Logic level compatible clock input. If the XIN/XOUT oscillator is
used, tie this pin to ground.
XOUT
1
O
Clock out. Output from the internal-crystal oscillator. If a crystal is not used, XOUT
should be left unconnected.
XIN
1
I
Clock in. Internal-oscillator input from a crystal. If EXTCLK is used, tie this pin to
ground.
CLKMD0,
CLKMD1
2
I
Clock mode select pins
RSV0 – RSV1
2
I
Reserved. Use individual pullups to DVDD.
EMU1–EMU0
2
I/O
TDI
1
I
Test data input
TDO
1
O
Test data output
TCK
1
I
Test clock
TMS
1
I
Test mode select
JTAG EMULATION
Emulation pins 0 and 1, use individual pullups to DVDD
TRST
1
I
Test reset
† I = input, O = output, Z = high-impedance state
‡ S = SHZ active, H = HOLD active, R = RESET active
§ Recommended decoupling. Four 0.1 µF for CVDD and eight 0.1 µF for DVDD.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
functional block diagram
RAM
Block 0
(1K × 32)
Cache
(64 × 32)
32
24
PAGE0
PDATA Bus
PAGE1
PAGE2
PAGE3
RDY
HOLD
HOLDA
STRB
R/W
D31–D0
A23–A0
PADDR Bus
32
24
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
RAM
Block 1
(1K × 32)
24
RAM
Block 2
(16K × 32)
Boot
Loader
32
24
32
24
RAM
Block 3
(16K × 32)
32
24
32
MUX
MUX
DDATA Bus
DADDR1 Bus
DADDR2 Bus
DMADATA Bus
DMAADDR Bus
32
24
24
32
32
24
24
Peripheral Data Bus
DMA Controller
Global-Control
Register
Serial Port 0
MUX
DestinationAddress
Register
REG1
REG2
REG1
CPU1
32
32
40
TransferCounter
Register
40
Timer 0
40
32
Data-Transmit
Register
Global-Control
Register
ALU
40
Receive/Transmit
(R/X) Timer Register
Data-Receive
Register
32-Bit
Barrel
Shifter
Multiplier
40
CLKX0
FSR0
DR0
CLKR0
40
ExtendedPrecision
Registers
(R7–R0)
40
TCLK0
40
Timer-Period
Register
Timer-Counter
Register
Timer 1
DISP0, IR0, IR1
Global-Control
Register
ARAU0
BK
ARAU1
TCLK1
24
24
24
32
32
Auxiliary
Registers
(AR0–AR7)
Port Control
32
8
Other
Registers
(12)
POST OFFICE BOX 1443
Timer-Counter
Register
24
32
32
Timer-Period
Register
32
• HOUSTON, TEXAS 77251–1443
STRB-Control
Register
Peripheral Data Bus
CPU2
FSX0
DX0
Serial-Port-Control
Register
Peripheral Address Bus
Controller
JTAG Emulation
TCK
TMS
TRST
EXTCLK
XOUT
XIN
H1
H3
CLKMD(0,1)
Source-Address
Register
CPU1
REG2
PLL CLK
RSV(0,1)
SHZ
EDGEMODE
RESET
INT(3–0)
IACK
MCBL/MP
XF(1,0)
TDI
TDO
EMU0
EMU1
IR
PC
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
memory map
0h
Reset, Interrupt, Trap Vector, and
Reserved Locations (64)
(External STRB Active)
0h
03Fh
040h
Reserved for Bootloader
Operations
External
STRB Active
(8M Words – 64 Words)
FFFh
1000h
Boot 1
400000h
Boot 2
7FFFFFh
800000h
7FFFFFh
800000h
RAM Block 2
(16K Words Internal)
803FFFh
804000h
RAM Block 2
(16K Words Internal)
803FFFh
804000h
RAM Block 3
(16K Words Internal)
807FFFh
808000h
External
STRB
Active
(8M Words –
4K Words)
Peripheral Bus
Memory-Mapped Registers
(6K Words Internal)
8097FFh
809800h
RAM Block 3
(16K Words Internal)
807FFFh
808000h
Peripheral Bus
Memory-Mapped Registers
(6K Words Internal)
8097FFh
809800h
RAM Block 0
(1K Words Internal)
809BFFh
809C00h
RAM Block 0
(1K Words Internal)
809BFFh
809C00h
RAM Block 1
(1K Words Internal)
RAM Block 1
(1K Words Internal)
809FFFh
80A000h
FFFFFFh
External
STRB Active
(8M Words – 40K Words)
(a) Microprocessor Mode
User-Program Interrupt
and Trap Branch Table
809FC0h
809FC1h
809FFFh
80A000h
63 Words
FFF000h
Boot 3
FFFFFFh
External
STRB Active
(8M Words –
40K Words)
(b) Microcomputer/Bootloader Mode
NOTE A: STRB is active over all external memory ranges. PAGE0 to PAGE3 are configured as external bus strobes. These are simple
decoded strobes that have no configuration registers and are active only during external bus activity over the following ranges:
Name
PAGE0
PAGE1
PAGE2
PAGE3
STRB
Active range
0000000h – 03FFFFFh
0400000h – 07FFFFFh
0800000h – 0BFFFFFh
0C00000h – 0FFFFFFh
0000000h – 0FFFFFFh
Figure 1. TMS320VC33 Memory Maps
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memory map (continued)
00h
Reset
809FC1h
01h
INT0
809FC2h
02h
INT1
03h
INT2
04h
INT3
05h
XINT0
06h
RINT0
809FC6h
08h
Reserved
809FC8h
09h
TINT0
809FC9h
0Ah
TINT1
809FCAh
0Bh
DINT
809FCBh
0Ch
1Fh
Reserved
809FCCh
809FDFh
Reserved
20h
TRAP 0
809FE0h
TRAP 0
3Bh
TRAP 27
809FFBh
TRAP 27
3Ch
3Fh
Reserved
INT0
INT1
809FC3h
INT2
809FC4h
INT3
809FC5h
07h
XINT0
RINT0
809FC7h
Reserved
TINT0
TINT1
DINT
809FFCh
Reserved
809FFFh
(a) Microprocessor Mode
(b) Microcomputer/Bootloader Mode
Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations
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memory map (continued)
808000h
DMA Global Control
808004h
DMA Source Address
808006h
DMA Destination Address
808008h
DMA Transfer Counter
808020h
Timer 0 Global Control
808024h
Timer 0 Counter
808028h
Timer 0 Period Register
808030h
Timer 1 Global Control
808034h
Timer 1 Counter
808038h
Timer 1 Period Register
808040h
Serial Global Control
808042h
FSX/DX/CLKX Serial Port Control
808043h
FSR/DR/CLKR Serial Port Control
808044h
Serial R/X Timer Control
808045h
Serial R/X Timer Counter
808046h
Serial R/X Timer Period Register
808048h
Data-Transmit
80804Ch
Data-Receive
808064h
Primary-Bus Control
NOTE A: Shading denotes reserved address locations.
Figure 3. Peripheral Bus Memory-Mapped Registers
clock generator
The clock generator provides clocks to the VC33 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external clock source. The PLL circuit
generates the device clock by multiplying the reference clock frequency by a x5 scale factor, allowing use of
a clock source with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once
synchronized, locks onto and tracks an input clock signal.
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PLL and clock oscillator control
The clock mode control pins are decoded into four operational modes as shown in Figure 4. These modes
control clock divide ratios, oscillator, and PLL power (see Table 1).
When an external clock input or crystal is connected, the opposite unused input is simply grounded. An XOR
gate then passes one of the two signal sources to the PLL stage. This allows the direct injection of a clock
reference into EXTCLK, or 1–20 MHz crystals and ceramic resonators with the oscillator circuit. The two clock
sources include:
D A crystal oscillator circuit, where a crystal or ceramic resonator is connected across the XOUT and XIN pins
and EXTCLK is grounded.
D An external clock input, where an external clock source is directly connected to the EXTCLK pin, and XOUT
is left unconnected and XIN is grounded.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. The PLL
is a simple x5 reference multiplier with bypass and power control.
The clock divider, under CPU control, reduces the clock reference by 1 (MAXSPEED), 1/16 (LOPOWER), or
clock stop (IDLE2). Wake-up from the IDLE2 state is accomplished by a RESET or interrupt pin logic-low state.
A divide-by-two TMS320C31 equivalent mode of operation is also provided. In this case, the clock output
reference is further divided by two with clock synchronization being determined by the timing of RESET falling
relative to the present H1/H3 state.
Clock & Crystal OSC
PLL
Clock Divider
MAXSPEED/
LOWPOWER
EXTCLK
IDLE2
XOUT
M
U
X
XOR
S1
RF
X5 PLL
Á
XIN
Oscillator Enable
X1, 1/16, Off
1/2
M
U
X
CPU CLOCK
PLL PWR and Bypass
CLKMD0
SEL
C31 DIV2 Mode
CLKMD1
Figure 4. Clock Generation
Table 1. Clock Mode Select Pins
12
CLKMD0
CLKMD1
FEEDBACK
PLLPWR
0
0
0
Off
Off
1
1
On
Off
1/2
Oscillator enabled
1
0
On
Off
1
Oscillator enabled
1
1
On
On
5
2 mA @ 60 MHz, 1.8 V PLL power. Oscillator enabled
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PLL and clock oscillator control (continued)
Typical crystals in the 8–30 MHz range have a series resistance of 25 Ω, which increases below 8 MHz. To
maintain proper filtering and phase relationships, Rd and Zout of the oscillator circuit should be 10x–40x that of
the crystal. A series compensation resistor (Rd), shown in Figure 5, is recommended when using lower
frequency crystals. The XOUT output, the square wave inverse of XIN, is then filtered by the XOUT output
impedance, C1 load capacitor, and Rd (if present). The crystal and C2 input load capacitor then refilters this
signal, resulting in a XIN signal that is 75–85% of the oscillator supply voltage.
NOTE: Some ceramic resonators are available in a low-cost, three-terminal package that includes C1 and C2
internally. Typically, ceramic resonators do not provide the frequency accuracy of crystals.
NOTE: Better PLL stability can be achieved using the optional power supply isolation circuit shown in Figure 5.
A similar filter can be used to isolate the PLLVSS, as shown in Figure 6. PLLVDD can also be directly connected
to CVDD.
Table 2. Typical Crystal Circuit Loading
FREQUENCY (MHz)
Rd (Ω)
C1 (pF)
C2 (pF)
CL† (pF)
RL† (Ω)
2
4.7k
18
18
12
200
5
2.2k
18
18
12
60
10
470
15
15
12
30
15
0
15
12
12
25
20
0
9
9
10
25
† CL and RL are typical internal series load capacitance and resistance of the crystal.
XOUT
XIN
EXTCLK
PLLVSS
PLLVDD
CVDD
100 Ω
Rd
Crystal
C1
0.1 µF
C2
0.01 µF
Figure 5. Self-Oscillation Mode
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PLL isolation
The internal PLL supplies can be directly connected to CVDD and VSS (0 Ω case) or fully isolated as shown in
Figure 6. The RC network prevents the PLL supplies from turning high frequency noise in the CVDD and VSS
supplies into jitter.
CVDD
0 –100 Ω
PLLVDD
0.1 µF
0.01 µF
PLLVSS
0 –100 Ω
VSS
Figure 6. PLL Isolation Circuit Diagram
clock and PLL considerations on initialization
On power up, the CPU clock divide mode can be in MAXSPEED, LOPOWER or IDLE2, or the PLL could be
in an undefined mode. RESET falling in the presence of a valid CPU clock is used to clear this state, after which
the device will synchronously terminate any external activity.
The 5x Fclkin PLL of the TMS320VC33 contains an 8-bit PLL–LOCK counter which will cause the PLL to output
a frequency of Fclkin/2 during the initial ramp. This counter, however, does not increment while RESET is low
or in the absence of an input clock. A minimum of 256 input clocks are required before the first falling edge of
reset for the PLL to output to clear this counter. The setup and behavior that is seen is as follows.
Power is applied to the DSP with RESET low and the input clock high or low. A clock is applied (RESET is still
low) and the PLL appears to lock on to the input clock, producing the expected x5 output frequency. RESET
is driven high and the PLL output immediately drops to Fclkin/2 for up to 256 input cycles or 128 of the Fclkin/2
output cycles. The PLL/CPU clock then switches to x5 mode.
The switch over is synchronous and does not create a clock glitch, so the only effect is that the CPU will run
slow for up to the first 128 cycles after reset goes high. Once the PLL has stabilized, the counter will remain
cleared and subsequent resets will not exhibit this condition.
power sequencing considerations
Though an internal ESD and CMOS latchup protection diode exists between CVDD and DVDD, it should not be
considered a current-carrying device on power up. An external Schottky diode should be used to prevent CVDD
from exceeding DVDD by more than 0.7 V. The effect of this diode during power up is that if CVDD is powered
up first, DVDD will follow by one diode drop even when the DVDD supply is not active.
Typical systems using LDOs of the same family type for both DVDD and CVDD will track each other during power
up. In most cases, this is acceptable; but if a high-impedance pin state is required on power up, the SHZ pin
can be used to asynchronously disable all outputs. RESET should not be used in this case since some signals
require an active clock for RESET to have an effect and the clock may not yet be active. The internal core logic
becomes functional at approximately 0.8 V while the external pin IO becomes active at about 1.5 V.
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EDGEMODE
When EDGEMODE = 1, a sampled digital delay line is decoded to generate a pulse on the falling edge of the
interrupt pin. To ensure interrupt recognition, input signal logic-high and logic-low states must be held longer
than the synchronizer delay of one CPU clock cycle. Holding these inputs to no less than two cycles in both the
logic-low and logic-high states is sufficient.
When EDGEMODE = 0, a logic-low interrupt pin will continually set the corresponding interrupt flag. The CPU
or DMA can clear this flag within two cycles of it being set. This is the maximum interrupt width that can be applied
if only one interrupt is to be recognized. The CPU can manually clear IF bits within an interrupt service routine
(ISR), effectively lengthening the maximum ISR width.
After reset, EDGEMODE is temporarily disabled, allowing logic-low INT pins to be detected for bootload
operation.
Delay
RESET
EDGEMODE
INT
D Q
D Q
D Q
D Q
D Q
S
Q
IF Bit
R
CPU Reset
H1
CPU Set
H3
Figure 7. EDGEMODE and Interrupt Flag CIrcuit
reset operation
When RESET is applied, the CPU attempts to safely exit any pending read or write operations that may be in
progress. This can take as much as 10 CPU cycles, after which, the address, data, and control pins will be in
an inactive or high-impedance state.
When both RESET and SHZ are applied, the device will immediately enter the reset state with the pins held in
high-impedance mode. SHZ should then be disabled at least 10 CPU cycles before RESET is set high. SHZ
can be used during power-up sequencing to prevent undefined address, data, and control pins, avoiding system
conflicts.
PAGE0 – PAGE3 select lines
To facilitate simpler and higher speed connection to external devices, the TMS320VC33 includes four
predecoded select pins that have the same timings as STRB. These pins are decoded from A22, A23, and STRB
and are active only during external accesses over the ranges shown in Table 3. All external bus accesses are
controlled by a single bus control register.
Table 3. PAGE0 – PAGE3 Ranges
START
END
PAGE0
0x000000
0x3FFFFF
PAGE1
0x400000
0x7FFFFF
PAGE2
0x800000
0xBFFFFF
PAGE3
0xC00000
0xFFFFFF
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using external logic with the READY pin
The key to designing external wait-state logic is the internal bus control register and associated internal logic
that logically combines the external READY pin with the much faster on-chip bus control logic. This essentially
allows slow external logic to interact with the bus while easily meeting the READY input timings. It is also relevant
to mention that the combined ready signals are sampled on the rising edge of the internal H1 clock. Please refer
to Figure 8 for the following examples.
example 1
A simple 0 or WTCNT wait-state decoder can be created by simply tying an address line back to the READY
pin and selecting the AND option. When the tied back address is low, the bus will run with 0 wait states. When
the tied back address is high, the bus will be controlled by the internal wait-state counter.
By enabling the bank compare logic, proper operation is further ensured by inserting a null cycle before a read
on the next bank is performed (writes are not pre-extended). This extra time can also be used by external logic
to affect the feedback path.
example 2
An N–WTCNT minimum wait-state decoder can also be created by tying back an address line to READY and
logically ORing it with the internal bank compare and wait count signals. When the address pin is low, bus timing
is determined by the internal WTCNT and BNKCMP settings. When the address line is high, the bus can run
no faster than the WTCNT counter and will be extended as long as READY is held high.
A23
A22
PAGE_0
PAGE_1
PAGE_2
PAGE_3
Decode
Device
Enable
Pins
Bus_Enable_Strobe,
0 = Active
STRB Pin
0 = Bus Idle
To C31 Style
Decoder
(C31 Compatibility)
H3
External Bus Interface
Abus
D Q
N–Bit
Bank
Compare
Q
BUS_READY
Abus_old
H3
R
N_Wait
Counter
1
D
H1
2
3
0
R/W
R/W Pin
Figure 8. Internal Ready Logic, Simplified Diagram
16
READY Pin
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example 2 (continued)
Table 4. MUX Select (Bus Control Register Bits 4 and 3)
BIT 4
BIT 3
0
0
Ignore internal wait counter and use only external READY
RESULTS
0
1
Use only internal wait counter and ignore ready pin
1
0
Logically AND internal wait counter with ready pin
1
1
Logically OR internal wait counter with ready pin (reset default)
posted writes
External writes are effectively “posted” to the bus, which then acts like an output latch until the write completes.
Therefore, if the application code is executing internally, it can perform a very slow external write with no penalty
since the bus acts like it has a one-level-deep write FIFO.
data bus I/O buffer
The circuit shown in Figure 9 is incorporated into each data pin to lightly “hold” the last driven value on the data
bus pins when the DSP or an external device is not actively driving the bus. Each bus keeper is built from a
three-state driver with nominal 15 kΩ output resistance which is fed back to the input in a positive feedback
configuration. The resistance isolated driver then pulls the output in one direction or the other keeping the last
driven value. This circuit is enabled in all functional modes and is only disabled when SHZ is pulled low.
R/W
30 Ω
External Data
Bus Pin
Internal
Data Bus
15 kΩ
SHZ
Bus keeper
Figure 9. Bus Keeper Circuit
For an external device to change the state of these pins, it must be able to drive a small DC current until the
driver threshold is crossed. At the crossover point, the driver changes state, agreeing with the external driver
and assisting the change. The voltage threshold of the bus keeper is approximately at 50% of the DVDD supply
voltage. The typical output impedance of 30 Ω for all TMS320VC33 I/O pins is easily capable of meeting this
requirement.
bootloader operation
When MCBL/MP = 1, an internal ROM is decoded into the address range of 0x000000–0x000FFF. Therefore,
when reset occurs, execution begins within the internal ROM program and vector space. No external activity
will be evident until one of the boot options is enabled. These options are enabled by pulling an external interrupt
pin low, which the boot-load software then detects, causing a particular routine to be executed (see Table 5).
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bootloader operation (continued)
Table 5. INT0 – INT3 Sources
ACTIVE INTERRUPT
ADDRESS/SOURCE WHERE BOOT DATA IS
READ FROM
DATA FORMAT
INT0
0x001000
8, 16, or 32-bit width
INT1|
0x400000
8, 16, or 32-bit width
INT2
0xFFF000
8, 16, or 32-bit width
INT3
Serial Port
32-bit, external clock, and frame synch
When MCBL/MP = 1, the reset and interrupt vectors are hard-coded within the internal ROM. Since this is a
read-only device, these vectors cannot be modified. To enable user-defined interrupt routines, the internal
vectors contain fixed values that point to an internal section of SRAM beginning at 0x809FC1. Code execution
begins at these locations so it is important to place branch instructions (to the interrupt routine) at these locations
and not vectors.
The bootloader program requires a small stack space for calls and returns. Two SRAM locations at 0x809800
and 0x809801 are used for this stack. Data should not be boot loaded into these locations as this will corrupt
the bootloader program run-time stack. After the boot-load operation is complete, a program can reclaim these
locations. The simplest solution is to begin a program’s stack or uninitialized data section at 0x809800.
For additional detail on bootloader operation including the bootloader source code, see the TMS320C3x User’s
Guide (literature number SPRU031).
A bit I/O line or external logic can be used to safely disable the MCBL mode after bootloading is complete.
However, to ensure proper operation, the CPU should not be currently executing code or using external data
as the change takes place. In the following example, the XF0 pin is 3-state on reset, which allows the pullup
resistor to place the DSP in MCBL mode. The following code, placed at the beginning of an application then
causes the XF0 pin to become an active-logic-low output, changing the DSP mode to MP. The cache-enable
and RPTS instructions are used since they cause the LDI instruction to be executed multiple times even though
it has been fetched only once (before the mode change). In other words, the RPTS instruction acts as a
one-level-deep program cache for externally executed code. If the application code is to be executed from
internal RAM, no special provisions are needed.
LDI
8000h,ST
; Enable the cache
RPTS
4
; RPTS will fetch the following opcode 1 time
LDI
2h, IOF
; Drive MCBL/MP=0 for several cycles allowing
; the pipeline to clear
RESET
RESET
TMS320VC33
DVDD
RPU
XF0
MCBL/MP
Figure 10. Changing Bootload Select Pin
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JTAG emulation
Though the TMS320VC33 contains a JTAG debug port which allows multiple JTAG enabled chips to be
daisy-chained, boundary scan of the pins is not supported. If the pin scan path is selected, it will be routed
through a null register with a length of one. For additional information concerning the emulation interface, see
JTAG/MPSD Emulation Technical Reference (literature number SPDU079).
designing your target system’s emulator connector (14-pin header)
JTAG target devices support emulation through a dedicated emulation port. This port is a superset of the
IEEE 1149.1 standard and is accessed by the emulator. To communicate with the emulator, your target system
must have a 14-pin header (two rows of seven pins) with the connections that are shown in Figure 11. Table 6
describes the emulation signals.
TMS
1
2
TRST
TDI
3
4
GND
PD (VCC)
5
6
no pin (key)†
TDO
7
8
GND
TCK_RET
9
10
GND
TCK
11
12
GND
EMU0
13
14
EMU1
Header Dimensions:
Pin-to-pin spacing, 0.100 in. (X,Y)
Pin width, 0.025-in. square post
Pin length, 0.235-in. nominal
† While the corresponding female position on the cable connector is plugged to prevent improper
connection, the cable lead for pin 6 is present in the cable and is grounded, as shown in the
schematics and wiring diagrams in this document.
Figure 11. 14-Pin Header Signals and Header Dimensions
Table 6. 14-Pin Header Signal Descriptions
SIGNAL
DESCRIPTION
EMULATOR†
STATE
TARGET†
STATE
I
TMS‡
Test mode select
O
TDI
Test data input
O
I
TDO
Test data output
I
O
TCK
Test clock. TCK is a 10.368-MHz clock source from the emulation cable pod.
This signal can be used to drive the system test clock
O
I
TRST§
EMU0‡¶
Test reset
O
I
Emulation pin 0
I
I/O
EMU1‡¶
Emulation pin 1
I
I/O
PD(VCC)
Presence detect. Indicates that the emulation cable is connected and that the
target is powered up. PD should be tied to VCC in the target system.
I
O
TCK_RET
Test clock return. Test clock input to the emulator. May be a buffered or unbuffered version of TCK.
I
O
GND
Ground
† I = input; O = output
‡ Use 1–50K pullups for TMS, EMU0 and EMU1.
§ Use 1–50K pulldown for TRST. Do not use pullup resistors on TRST: it has an internal pulldown device. In a low-noise environment, TRST can
be left floating. In a high-noise environment, an additional pulldown resistor may be needed. (The size of this resistor should be based on electrical
current considerations.)
¶ EMU0 and EMU1 are I/O drivers configured as open-drain (open-collector) drivers. They are used as bidirectional signals for emulation global
start and stop.
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designing your target system’s emulator connector (14-pin header) (continued)
Although you can use other headers, recommended parts include:
straight header, unshrouded
DuPont Connector Systems
part numbers: 65610–114
65611–114
67996–114
67997–114
JTAG emulator cable pod logic
Figure 12 shows a portion of the emulator cable pod. The functional features of the pod are as follows:
D Signals TDO and TCK_RET can be parallel-terminated inside the pod if required by the application. By
default, these signals are not terminated.
D Signal TCK is driven with a 74LVT240 device. Because of the high-current drive (32 mA IOL/IOH), this signal
can be parallel-terminated. If TCK is tied to TCK_RET, the parallel terminator in the pod can be used.
D Signals TMS and TDI can be generated from the falling edge of TCK_RET, according to the IEEE 1149.1
bus slave device timing rules.
D Signals TMS and TDI are series-terminated to reduce signal reflections.
D A 10.368-MHz test clock source is provided. You may also provide your own test clock for greater flexibility.
+5 V
180 Ω
74F175
270 Ω
Q
JP1
Q
D
TDO (Pin 7)
74LVT240
10.368 MHz
Y
Y
GND (Pins 4,6,8,10,12)
A
33 Ω
33 Ω
TMS (Pin 1)
Y
TDI (Pin 3)
Y
EMU0 (Pin 13)
74AS1034
TCK (Pin 11){
EMU1 (Pin 14)
+5 V
180 Ω
270 Ω
JP2
TRST (Pin 2)
74AS1004
TCK_RET (Pin 9){
PD(VCC) (Pin 5)
100 Ω
RESIN
TL7705A
† The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided as an optional target system
test clock source.
Figure 12. JTAG Emulator Cable Pod Interface
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symbolization and speed ratings
The device revision can be determined by the lot trace code marked on the top of the package. The location
for the lot trace codes for the PGE package is shown in Figure 13.
TMS320VC33 devices are rated in peak MFLOPS, shown as a suffix to the orderable part number (see Table 8).
Figure 13 shows the device symbolization on the PGE package. A general “TMS320VC33” symbol defaults to
the lowest speed rating for that device (120 MFLOPS). 150-MFLOPS devices are denoted with a “150” mark
on the upper right-hand corner of the package. The VC33 CPU instruction rate is MFLOPS/2.
150
DSP
TMS320VC33PGE
Cx–YMLLLLW
Lot trace code
Figure 13. PGE Package (Top View)
Table 7. Example, Typical Lot Trace Code for TMS320VC33 DSP (PGE)
Lot Trace Code
Silicon Revision
Blank
(No letter in prefix)
Comments
1.0
TMX320VC33
A
(Letter in prefix is A)
1.1
TMS320VC33
B
(Letter in prefix is B)
1.2
TMS320VC33
Table 8. Device Orderable Part Numbers
DEVICE
SPEED (MFLOPS)
TEMPERATURE RATING
TMS320VC33PGE120
120
0°C to 90°C
TMS320VC33PGEA120
120
– 40°C to 100°C
TMS320VC33PGE150
150
0°C to 90°C
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device and development support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP family devices and support tools. Each TMS320 DSP member has one of three prefixes: TMX,
TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). This development flow
is defined below.
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
TMS
Fully-qualified production device
Support tool development evolutionary flow:
TMDX
Development support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development support product
TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development support tools have been characterized fully, and the quality and reliability
of the device has been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZ, PGE, PBK, or GGU) and temperature range (for example, L). Figure 14 provides a legend
for reading the complete device name for any TMS320 DSP family member.
TMS320 is a trademark of Texas Instruments.
22
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
device and development support tool nomenclature (continued)
TMS
PREFIX
TMX =
TMP =
TMS =
SMJ =
SM =
320
VC 33 PGE
120
SPEED
120 = 120 MFLOPS
150 = 150 MFLOPS
experimental device
prototype device
qualified device
MIL-PRF-38535
High Rel (non-38535)
PACKAGE TYPE†
N
= plastic DIP
J
= ceramic DIP
JD = ceramic DIP side-brazed
GB = ceramic PGA
FZ = ceramic CC
FN = plastic leaded CC
FD = ceramic leadless CC
PJ = 100-pin plastic EIAJ QFP
PZ = 100-pin plastic LQFP
PBK = 128-pin plastic LQFP
PQ = 132-pin plastic bumpered QFP
PGE = 144-pin plastic LQFP
GGU = 144-pin MicroStar BGA
PGF = 176-pin plastic LQFP
GGW= 176-pin MicroStar BGA
DEVICE FAMILY
320 = TMS320 Family
TECHNOLOGY
C = CMOS
E = CMOS EPROM
F = CMOS Flash EEPROM
LC = Low-Voltage CMOS (3.3 V)
VC = Low-Voltage CMOS [3 V (2.5 V
or 1.8 V core)]
UC= Ultra Low-Voltage CMOS [1.8 V
(1.5 V core)]
DEVICE
1x DSP
2x DSP
3x DSP
4x DSP
5x DSP
54x DSP
6x DSP
=
=
=
=
=
=
=
TMS320C1x DSP Generation
TMS320C2x DSP Generation
TMS320C3x DSP Generation
TMS320C4x DSP Generation
TMS320C5x DSP Generation
TMS320C54x DSP Generation
TMS320C6x DSP Generation
† DIP = Dual-In-Line Package
PGA = Pin Grid Array
CC = Chip Carrier
QFP = Quad Flat Package
LQFP = Low-Profile Quad Flat Package
BGA = Ball Grid Array
Figure 14. TMS320 DSP Device Nomenclature
MicroStar BGA is a trademark of Texas Instruments.
POST OFFICE BOX 1443
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23
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, DVDD‡
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Supply voltage range, CVDD‡
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.4 V
Input voltage range, VI§ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to 4.6 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V
Continuous power dissipation (worst case)¶ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
(for TMS320VC33-150)
Operating case temperature range, TC (PGE – commercial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 90°C
TC (PGEA – industrial) . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 100°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to VSS.
§ Absolute DC input level should not exceed the DVDD or VSS supply rails by more than 0.3 V. An instantaneous low current pulse of < 2 ns,
< 10 mA, and < 1 V amplitude is permissible.
¶ Actual operating power is much lower. This value was obtained under specially produced worst-case test conditions for the TMS320VC33, which
are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to the external
data and address buses at the maximum possible rate with a capacitive load of 30 pF. See normal (ICC) current specification in the electrical
characteristics table and also read TMS320C3x General-Purpose Applications User’s Guide (literature number SPRU194).
recommended operating conditions‡#||
MIN
CVDD
Supply voltage for the core CPUk
DVDD
Supply voltage for the I/O pinsh
VSS
VIH
Supply ground
VIL
IOH
Low-level input voltage
IOL
Low-level output current
MAX
High-level input voltage
1.89
V
3
3.3
3.6
V
0.7 * DVDD
– 0.3§
High-level output current
Operating case temperature (industrial)
UNIT
1.8
0
Operating case temperature (commercial)
TC
NOM
1.71
V
DVDD + 0.3§
0.3 * DVDD
V
V
4
mA
4
mA
0
90
–40
100
°C
CL
Capacitive load per output pin
30
pF
‡ All voltage values are with respect to VSS.
§ Absolute DC input level should not exceed the DVDD or VSS supply rails by more than 0.3 V. An instantaneous low current pulse of < 2 ns, < 10 mA,
and < 1 V amplitude is permissible.
# All inputs and I/O pins are configured as inputs.
|| All input and I/O pins use a Schmitt hysteresis inputs except SHZ and D0–D31. Hysteresis is approximately 10% of DVDD and is centered at
0.5 * DVDD.
k CVDD should not exceed DVDD by more than 0.7 V. (Use a Schottky clamp diode between these supplies.)
h DVDD should not exceed CVDD by more than 2.5 V.
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)†
TEST CONDITIONS‡
PARAMETER
MIN
TYP§
MAX
VOH
VOL
High-level output voltage
DVDD = MIN,IOH = MAX
Low-level output voltage
DVDD = MIN,IOL = MAX
IZ
II
High-impedance current
DVDD = MAX
Input current
IIPU
IIPD
Input current (with internal pullup)
VI = VSS to DVDD
Inputs with internal pullups¶
Input current (with internal pulldown)
Inputs with internal pulldowns¶
IBKU
IBKD
Input current (with bus keeper) pullup#
Bus keeper opposes until conditions match
S ppl current,
Supply
c rrent pins||k
TC = 25
25°C,
C,
DVDD = MAX
fx = 60 MHz
fx = 75 MHz
VC33-120
20
120
IDDD
VC33-150
25
150
S ppl current,
Supply
c rrent core CPU||k
TC = 25
25°C,
C,
CVDD = MAX
fx = 60 MHz
fx = 75 MHz
VC33-120
50
80
IDDC
VC33-150
60
100
IDD
Ci
2.4
Input current (with bus keeper) pulldown#
IDLE2, Supply
Su ly current, IDDD plus
lus IDDC
Inp t capacitance
Input
UNIT
V
0.4
V
–5
+5
µA
–5
+5
µA
– 600
10
µA
600
– 10
µA
– 600
10
µA
600
– 10
µA
PLL enabled, oscillator enabled
2
PLL disabled, oscillator enabled
500
PLL disabled, oscillator disabled, FCLK = 0
100
mA
mA
mA
µA
A
All inputs except XIN
10
XIN
10
pF
Co
Output capacitance
10
pF
† All voltage values are with respect to VSS.
‡ For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
§ For VC33, all typical values are at DVDD = 3.3, CVDD = 1.8 V, TC (case temperature) = 25°C.
¶ Pins with internal pullup devices: TDI, TCK, and TMS. Pin with internal pulldown device: TRST.
# Pins D0–D31 include internal bus keepers that maintain valid logic levels when the bus is not driven (see Figure 9).
|| Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which
are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern at the
maximum rate possible. See TMS320C3x General-Purpose Applications User’s Guide (literature number SPRU194).
k fx is the PLL output clock frequency.
PARAMETER MEASUREMENT INFORMATION
IOL
50 Ω
Tester Pin
Electronics
VLoad
CT
Output
Under
Test
IOH
Where:
IOL
= 4 mA (all outputs) for DC levels test.
IO and IOH are adjusted during AC timing analysis to achieve an AC termination of 50 Ω
VLOAD = DVDD/2
CT
= 40-pF typical load-circuit capacitance
Figure 15. Test Load Circuit
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100. In order to
shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows,
unless otherwise noted:
Lowercase subscripts and their meanings
Letters and symbols and their meanings
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
dis
disable time
Z
High Impedance
en
enable time
f
fall time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
x
unknown, changing, or don’t care level
Additional symbols and their meaning
26
A
Address lines (A23–A0)
H
H1 and H3
ASYNCH
Asynchronous reset signals (XF0, XF1, CLKX0, DX0,
FSX0, CLKR0, DR0, FSR0, TCLK0, and TCLK1)
HOLD
HOLD
CLKX
CLKX0
HOLDA
HOLDA
CLKR
CLKR0
IACK
IACK
CONTROL
Control signals
INT
INT3–INT0
D
Data lines (D31–D0)
PAGE
PAGE0–PAGE3
DR
DR
RDY
RDY
DX
DX
RW
R/W
R/W
EXTCLK
EXTCLK
RW
FS
FSX/R
RESET
RESET
FSX
FSX0
S
STRB
FSR
FSR0
SCK
CLKX/R
GPI
General-purpose input
SHZ
SHZ
GPIO
General-purpose input/output; peripheral pin (CLKX0,
CLKR0, DX0, DR0, FSX0, FSR0, TCLK0, and TCLK1)
TCLK
TCLK0, TCLK1, or TCLKx
GPO
General-purpose output
XF
XF0, XF1, or XFx
H1
H1
XF0
XF0
H3
H3
XF1
XF1
XIN
XIN
POST OFFICE BOX 1443
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
phase-locked loop (PLL) circuit timing
switching characteristics over recommended operating conditions for phase-locked loop using
EXTCLK or on-chip crystal oscillator†
MIN
MAX
UNIT
Fpllin
Fpllout
Frequency range, PLL input
PARAMETER
5
15
MHz
Frequency range, PLL output
25
75
MHz
Ipll
Ppll
PLL current, CVDD supply
2
mA
PLL power, CVDD supply
5
mW
PLLdc
PLLJ
PLL output duty cycle at H1
45
PLL output jitter, Fpllout = 25 MHz
PLLLOCK PLL lock time in input cycles
† Duty cycle is defined as 100*t1/(t1+t2)%
55
%
400
ps
1000
cycles
To ensure clean internal clock references, the minimal low and high pulse durations must be maintained. At high
frequencies, this may require a fast rise and fall time as well as a tightly controlled duty cycle. At lower
frequencies, these requirements are less restrictive when in x1 and x0.5 modes. The PLL, however, must have
an input duty cycle of between 40% and 60% for proper operation.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
clock circuit timing
The following table defines the timing parameters for the clock circuit signals.
switching characteristics over recommended operating conditions for on-chip crystal oscillator†
(see Figure 16)
PARAMETER
MIN
TYP
MAX
UNIT
20
MHz
60
%VO
kΩ
VO
FO
Oscillator internal supply voltage
Fundamental mode frequency range
1
Vbias
Rfbk
DC bias point (input threshold)
40
50
Feedback resistance
100
300
500
Rout
Small signal AC output impedance
AC output voltage with test crystal‡
250
500
1000
Vxoutac
Vxinac
CVDD
V
85
AC input voltage with test crystal‡
85
Vxoutl
Vxouth
Vxin = Vxinh, Ixout = 0, FO=0 (logic input)
Vxin = Vxinl, Ixout = 0, FO=0 (logic input)
Vinl
Vinh
Ω
%VO
%VO
VSS – 0.1
CVDD – 0.3
VSS + 0.3
CVDD + 0.1
V
When used for logic level input, oscillator enabled
–0.3
0.2 * VO
V
When used for logic level input, oscillator enabled
0.8 * VO
DVDD + 0.3
V
Vxinh
Cxout
When used for logic level input, oscillator disabled
0.7 * DVDD
XOUT internal load capacitance
2
Cxin
XIN internal load capacitance
td(XIN-H1)
Iinl
Delay time, XIN to H1 x1 and x0.5 modes
DVDD + 0.3
V
3
5
pF
2
3
5
pF
2
5.5
8
ns
50
µA
–50
µA
Input current, feedback enabled, Vil = 0
Iinh
Input current, feedback enabled, Vil = Vih
† This circuit is intended for series resonant fundamental mode operation.
‡ Signal amplitude is dependent on the crystal and load used.
Rd
XOUT
ROUT
CXOUT
C1
Rfbk
Crystal
VO
XIN
CXIN
C2
NOTE A: See Table 2 for value of Rd.
Figure 16. On-Chip Oscillator Circuit
28
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V
To internal
clock generator
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
clock circuit timing (continued)
The following tables define the timing requirements and switching characteristics for EXTCLK.
timing requirements for EXTCLK, all modes (see Figure 17 and Figure 18)
MIN
tr(EXTCLK)
time EXTCLK
Rise time,
tf(EXTCLK)
Fall time,
time EXTCLK
tw(EXTCLKL)
tw(EXTCLKH)
tdc(EXTCLK)
Pulse duration, EXTCLK low
Pulse duration, EXTCLK high
Duty cycle, EXTCLK [tw(EXTCLKH) / tc(H)]
Cycle time, EXTCLK, VC33
VC33-120
120
F = Fmax, x0.5 and x1 modes
1
F < Fmax
4
F = Fmax, x0.5 and x1 modes
1
F < Fmax
4
x5 mode
21
x1 mode
5.5
x0.5 mode
4.0
x5 mode
21
Cycle time, EXTCLK, VC33
VC33-150
150
VC33-120
Frequency range, 1/tc(EXTCLK), VC33
120
Fext
Frequency range, 1/tc(EXTCLK), VC33
VC33-150
150
UNIT
ns
ns
ns
x1 mode
5.5
x0.5 mode
4.0
x5 PLL mode
40
x1 and x0.5 modes, F = max
45
55
x1 and x0.5 modes, F = 0 Hz
0
100
x5 mode
83.3
200
x1 mode
16.7
x0.5 mode
tc(EXTCLK)
MAX
ns
60
%
10
x5 mode
66.7
x1 mode
13.3
200
x0.5 mode
10
x5 mode
5
x1 mode
0
60
x0.5 mode
0
100
x5 mode
5
15
x1 mode
0
75
x0.5 mode
0
100
ns
12
MH
MHz
switching characteristics for EXTCLK over recommended operating conditions, all modes
(see Figure 17 and Figure 18)
PARAMETER
MIN
Vmid
Mid-level, used to measure duty cycle
td(EXTCLK-H)
Delay time, EXTCLK to H1 and
H3
TYP
MAX
0.5 * DVDD
UNIT
V
x1 mode
2
4.5
7
x0.5 mode
2
4.5
7
ns
tr(H)
tf(H)
Rise time, H1 and H3
3
ns
Fall time, H1 and H3
3
ns
td(HL-HH)
Delay time, from H1 low to H3 high or from H3 low to H1 high
1.5
ns
tc(H)
Cycle time, H1 and H3
–1.5
x5 PLL mode
1/(5 * fext)
x1 mode
1/fext
x0.5 mode
2/fext
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• HOUSTON, TEXAS 77251–1443
ns
29
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
clock circuit timing (continued)
tc(EXTCLK)
tr(EXTCLK)
tw(EXTCLKH)
EXTCLK
tc(H)
tw(EXTCLKL)
tf(EXTCLK)
H3
td(EXTCLK-H)
td(EXTCLK-H)
tf(H)
H1
tr(H)
Figure 17. Divide-By-Two Mode
tc(EXTCLK)
tr(EXTCLK)
tw(EXTCLKH)
tf(EXTCLK)
EXTCLK
td(EXTCLK-H)
tw(EXTCLKL)
td(EXTCLK-H)
H3
tc(H)
H1
NOTE A: EXTCLK is held low.
Figure 18. Divide-By-One Mode
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td(HL-HH)
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
memory read/write timing
The following tables define memory read/write timing parameters for STRB.
timing requirements for memory read/write† (see Figure 19, Figure 20, and Figure 21)
tsu(D-H1L)R
th(H1L-D)R
VC33-120
VC33-150
MIN
MIN
MAX
MAX
UNIT
Setup time, Data before H1 low (read)
5
5
ns
Hold time, Data after H1 low (read)
–1
–1
ns
5
4
ns
–1
–1
tsu(RDY-H1H) Setup time, RDY before H1 high
th(H1H-RDY) Hold time, RDY after H1 high
td(A-RDY)
Delay time, Address valid to RDY
tv(A-D)
(A D)
Valid time, Data valid after address
PAGEx, or STRB valid
0 wait state, CL = 30 pF
1 wait state
ns
P–7‡
P–6‡
ns
9
6
ns
tc(H)+9
tc(H)+6
ns
† These timings assume a similar loading of 30 pF on all pins.
‡ P = tc(H)/2 (when duty cycle equals 50%).
switching characteristics over recommended operating conditions for memory read/write†
(see Figure 19, Figure 20, and Figure 21)
PARAMETER
td(H1L-SL)
td(H1L-SH)
VC33-120
VC33-150
MIN
MIN
MAX
MAX
UNIT
Delay time, H1 low to STRB low
–1
4
–1
3
ns
Delay time, H1 low to STRB high
–1
4
–1
3
ns
td(H1H-RWL)W Delay time, H1 high to R/W low (write)
td(H1L-A)
Delay time, H1 low to address valid
–1
4
–1
3
ns
–1
4
–1
3
ns
td(H1H-RWH)W Delay time, H1 high to R/W high (write)
Delay time, H1 high to address valid on back-to-back write cycles
td(H1H-A)W
(write)
–1
4
–1
3
ns
–1
4
–1
3
ns
5
ns
5
ns
tv(H1L-D)W
Valid time, Data after H1 low (write)
th(H1H-D)W
Hold time, Data after H1 high (write)
† These timings assume a similar loading of 30 pF on all pins.
6
0
5
0
Output load characteristics for high-speed and low-speed (low-noise) output buffers are shown in Figure 19.
High-speed buffers are used on A0 – A23, PAGE0 – PAGE3, H1, H3, STRB, and R/W. All other outputs use the
low-speed, (low-noise) output buffer.
Low-Noise Buffer
0.05 ns/pF
Output Delay (ns)
5
4
High-Speed Buffer
0.04 ns/pF
3
HIGH
SPEED
LOW
NOISE
0 pF
2.0
2.8
15 pF
2.6
3.4
30 pF
3.2
4.4
50 pF
4.0
5.25
LOAD
2
CLmax = 30 pF
1
10
20
30
40
50
Load Capacitance (pF)
Figure 19. Output Load Characteristics, Buffer Only
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
memory read/write timing (continued)
H3
H1
td(H1L-SL)
td(H1L-SH)
PAGEx, STRB
td(H1L-A)
R/W
tv(A-D)
td(H1H-RWL)W
A[23:0]
tsu(D-H1L)R
th(H1L-D)R
td(A-RDY)
D[31:0]
tsu(RDY-H1H)
th(H1H-RDY)
RDY
NOTE A: STRB remains low during back-to-back read operations.
Figure 20. Timing for Memory (STRB = 0 and PAGEx = 0) Read
H3
H1
td(H1L-SH)
td(H1L-SL)
PAGEx, STRB
td(H1H-RWL)W
td(H1H-RWH)W
R/W
td(H1L-A)
td(H1H-A)W
A[23:0]
th(H1H-D)W
tv(H1L-D)W
D[31:0]
th(H1H-RDY)
tsu(RDY-H1H)
RDY
Figure 21. Timing for Memory (STRB = 0 and PAGEx = 0) Write
32
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
XF0 and XF1 timing when executing LDFI or LDII
The following tables define the timing parameters for XF0 and XF1 during execution of LDFI or LDII.
timing requirements for XF0 and XF1 when executing LDFI or LDII (see Figure 22)
tsu(XF1-H1L)
th(H1L-XF1)
VC33-120
VC33-150
MIN
MIN
MAX
MAX
UNIT
Setup time, XF1 before H1 low
5
4
ns
Hold time, XF1 after H1 low
0
0
ns
switching characteristics over recommended operating conditions for XF0 and XF1 when executing
LDFI or LDII (see Figure 22)
PARAMETER
td(H3H-XF0L)
VC33-120
VC33-150
MIN
MIN
MAX
Delay time, H3 high to XF0 low
Fetch
LDFI or LDII
4
Decode
Read
MAX
3
UNIT
ns
Execute
H3
H1
PAGEx, STRB
R/W
A[23:0]
D[31:0]
RDY
td(H3H-XF0L)
XF0
tsu(XF1-H1L)
th(H1L-XF1)
XF1
Figure 22. Timing for XF0 and XF1 When Executing LDFI or LDII
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33
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
XF0 timing when executing STFI and STII†
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII.
switching characteristics over recommended operating conditions for XF0 when executing STFI
or STII (see Figure 23)
PARAMETER
VC33-120
VC33-150
MIN
MIN
MAX
MAX
UNIT
td(H3H-XF0H) Delay time, H3 high to XF0 high†
4
3
ns
† XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of
the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store
from executing, the address of the store will not be driven until the store can execute.
Fetch
STFI or STII
Decode
Read
Execute
H3
H1
PAGEx, STRB
R/W
A[23:0]
D[31:0]
RDY
td(H3H-XF0H)
XF0
Figure 23. Timing for XF0 When Executing an STFI or STII
34
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
XF0 and XF1 timing when executing SIGI
The following tables define the timing parameters for the XF0 and XF1 pins during execution of SIGI.
timing requirements for XF0 and XF1 when executing SIGI (see Figure 24)
tsu(XF1-H1L)
th(H1L-XF1)
VC33-120
VC33-150
MIN
MIN
MAX
MAX
UNIT
Setup time, XF1 before H1 low
5
4
ns
Hold time, XF1 after H1 low
0
0
ns
switching characteristics over recommended operating conditions for XF0 and XF1 when executing
SIGI (see Figure 24)
PARAMETER
td(H3H-XF0L)
td(H3H-XF0H)
VC33-120
VC33-150
MIN
MIN
MAX
MAX
UNIT
Delay time, H3 high to XF0 low
4
3
ns
Delay time, H3 high to XF0 high
4
3
ns
Fetch
SIGI
Decode
Read
Execute
H3
H1
tsu(XF1-H1L)
td(H3H-XF0L)
td(H3H-XF0H)
XF0
th(H1L-XF1)
XF1
Figure 24. Timing for XF0 and XF1 When Executing SIGI
POST OFFICE BOX 1443
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35
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
loading when XF is configured as an output
The following table defines the timing parameter for loading the XF register when the XFx pin is configured as
an output.
switching characteristics over recommended operating conditions for loading the XF register when
configured as an output pin (see Figure 25)
PARAMETER
tv(H3H-XF)
Valid time, XFx after H3 high
VC33-120
VC33-150
MIN
MIN
MAX
4
Fetch Load
Instruction
Decode
Read
MAX
3
Execute
H3
H1
OUTXFx Bit
(see Note A)
1 or 0
tv(H3H-XF)
XFx
NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register.
Figure 25. Timing for Loading XF Register When Configured as an Output Pin
36
POST OFFICE BOX 1443
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UNIT
ns
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
changing XFx from an output to an input
The following tables define the timing parameters for changing the XFx pin from an output pin to an input pin.
timing requirements for changing XFx from output to input mode (see Figure 26)
tsu(XF-H1L)
th(H1L-XF)
VC33-120
VC33-150
MIN
MIN
MAX
MAX
UNIT
Setup time, XFx before H1 low
5
4
ns
Hold time, XFx after H1 low
0
0
ns
switching characteristics over recommended operating conditions for changing XFx from output to
input mode (see Figure 26)
PARAMETER
tdis(H3H-XF)
VC33-120
VC33-150
MIN
MIN
MAX
Disable time, XFx after H3 high
6
Buffers Go
From Output
to Output
Execute
Load of IOF
Synchronizer
Delay
MAX
5
UNIT
ns
Value on Pin
Seen in IOF
H3
H1
tsu(XF-H1L)
I/OxFx Bit
(see Note A)
th(H1L-XF)
tdis(H3H-XF)
XFx
Output
Data
Sampled
INXFx Bit
(see Note A)
Data
Seen
NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register.
Figure 26. Timing for Changing XFx From Output to Input Mode
POST OFFICE BOX 1443
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37
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
changing XFx from an input to an output
The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin.
switching characteristics over recommended operating conditions for changing XFx from input to
output mode (see Figure 27)
PARAMETER
td(H3H-XF)
Delay time, H3 high to XFx switching from input to output
VC33-120
VC33-150
MIN
MIN
MAX
4
Execution of
Load of IOF
H3
H1
I/OxFx Bit
(see Note A)
td(H3H-XF)
XFx
NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register.
Figure 27. Timing for Changing XFx From Input to Output Mode
38
POST OFFICE BOX 1443
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MAX
3
UNIT
ns
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
reset timing
RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 28 occurs; otherwise, an additional delay of one clock cycle is
possible.
The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
Resetting the device initializes the bus control register to seven software wait states and therefore results in slow
external accesses until these registers are initialized.
HOLD is a synchronous input that can be asserted during reset. It can take nine CPU cycles before HOLDA
is granted.
The following tables define the timing parameters for the RESET signal.
timing requirements for RESET (see Figure 28)
tsu(RESET-EXTCLKL)
tsu(RESETH-H1L)
† P = tc(EXTCLK)
VC33-120
VC33-150
MIN
MIN
MAX
5
P–7
Setup time, RESET before EXTCLK low
6
Setup time, RESET high before H1 low and after ten H1 clock cycles
6
MAX
P–7†
UNIT
ns
5
ns
switching characteristics over recommended operating conditions for RESET (see Figure 28)
PARAMETER
VC33-120
VC33-150
MIN
MIN
MAX
MAX
UNIT
td(EXTCLKH-H1H)
td(EXTCLKH-H1L)
Delay time, EXTCLK high to H1 high
2
7
2
7
ns
Delay time, EXTCLK high to H1 low
2
7
2
7
ns
td(EXTCLKH-H3L)
td(EXTCLKH-H3H)
Delay time, EXTCLK high to H3 low
2
7
2
7
ns
Delay time, EXTCLK high to H3 high
2
7
2
7
ns
tdis(H1H-DZ)
tdis(H3H-AZ)
Disable time, Data (high impedance) from H1 high‡
7
6
ns
Disable time, Address (high impedance) from H3 high
7
6
ns
td(H3H-CONTROLH)
td(H1H-RWH)
Delay time, H3 high to control signals high
4
3
ns
Delay time, H1 high to R/W high
4
3
ns
td(H1H-IACKH)
Delay time, H1 high to IACK high
4
3
ns
tdis(RESETL-ASYNCH)
Disable time, Asynchronous reset signals disabled (high impedance)
from RESET low§
7
6
ns
‡ High impedance for Dbus is limited to nominal bus keeper ZOUT = 15 kΩ.
§ Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
POST OFFICE BOX 1443
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39
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
reset timing (continued)
EXTCLK
tsu(RESET-EXTCLKL)
RESET
(see Notes A and C)
td(EXTCLKH-H1H)
td(EXTCLKH-H1L)
H1
tsu(RESETH-H1L)
td(EXTCLKH-H3L)
H3
Ten H1 Clock Cycles
tdis(H1H-DZ)
D[31:0]
td(EXTCLKH-H3H)
tdis(H3H-AZ)
PAGEx, A[23:0]
td(H3H-CONTROLH)
STRB
td(H1H-RWH)
R/W
td(H1H-IACKH)
IACK
Asynchronous
Reset Signals
(see Note B)
tdis(RESETL-ASYNCH)
NOTES: A. Clock circuit is configured in ’C31-compatible divide-by-2 mode. If configured for x1 mode, EXTCLK directly drives H3.
B. Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
C. RESET is a synchronous input that can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.
D. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the
reset vector is fetched twice, with no software wait states.
E. The address and PAGE3-PAGE0 outputs are placed in a high-impedance state during reset requiring a nominal 10–22 kΩ pullup.
If not, undesirable spurious reads can occur when these outputs are not driven.
Figure 28. RESET Timing
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POST OFFICE BOX 1443
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
interrupt response timing
The following table defines the timing parameters for the INTx signals.
timing requirements for INT3–INT0 response (see Figure 29)
VC33-120
MIN
tsu(INT-H1L)
th(H1L-INT)
tw(INT)
† P = tc(H)
Setup time, INT3– INT0 before H1 low
NOM
VC33-150
MAX
5
P+5†
NOM
MAX
4
Hold time, INT3– INT0 after H1 low
Pulse duration, interrupt to ensure only one interrupt
MIN
1.5P
0
2P–5†
P+5†
UNIT
ns
1.5P
0
2P–5†
ns
ns
The interrupt (INTx) pins are synchronized inputs that can be asserted at any time during a clock cycle. The
TMS320C3x interrupts are selectable as level- or edge-sensitive. Interrupts are detected on the falling edge of
H1. Therefore, interrupts must be set up and held to the falling edge of the internal H1 for proper detection. The
CPU and DMA respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt when level mode is selected, an interrupt pulse must be set
up and held such that a logic-low condition occurs for:
D A minimum of one H1 falling edge
D No more than two H1 falling edges
D Interrupt sources whose edges cannot be ensured to meet the H1 falling edge setup and hold times must
be further restricted in pulse width as defined by tw(INT) (parameter 51) in the table above.
When EDGEMODE=1, the falling edge of the INT0–INT3 pins are detected using synchronous logic (see
Figure 7). The pulse low and high time should be two CPU clocks or greater.
The TMS320C3x can set the interrupt flag from the same source as quickly as two H1 clock cycles after it has
been cleared.
If the specified timings are met, the exact sequence shown in Figure 29 occurs; otherwise, an additional delay
of one clock cycle is possible.
POST OFFICE BOX 1443
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41
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
interrupt response timing (continued)
Reset or
Interrupt
Vector Read
Fetch First
Instruction of
Service
Routine
H3
H1
tsu(INT-H1L)‡
th(H1L-INT)
tsu(INT-H1L)†
tsu(INT-H1L)¶
INT3 –INT0 Pin
(EDGEMODE = 0)
tw(INT)§
INT3 –INT0 Pin
(EDGEMODE = 1)
INT3 –INT0
Flag
ADDR
Vector Address
First Instruction Address
Data
† Falling edge of H1 just detects INTx falling edge.
‡ Falling edge of H1 detects second INTx low, however flag clear takes precedence.
§ Nominal width.
¶ Falling edge of H1 misses previous INTx low as INTx rises.
Figure 29. INT3–INT0 Response Timing
42
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.
The following table defines the timing parameters for the IACK signal.
NOTE: The IACK instruction can be executed at anytime to signal an event using the IACK pin. The IACK
instruction is most often used within an interrupt routine to signal which interrupt has occurred. The IACK
instruction must be executed to generate the IACK pulse.
switching characteristics over recommended operating conditions for IACK (see Figure 30)
VC33-120
VC33-150
MIN
MAX
MIN
MAX
Delay time, H1 high to IACK low
–1
4
–1
3
ns
Delay time, H1 high to IACK high
–1
4
–1
3
ns
PARAMETER
td(H1H-IACKL)
td(H1H-IACKH)
Fetch IACK
Instruction
Decode IACK
Instruction
UNIT
IACK Data
Read
H3
H1
td(H1H-IACKL)
td(H1H-IACKH)
IACK
ADDR
Data
Figure 30. Interrupt Acknowledge (IACK) Timing
POST OFFICE BOX 1443
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43
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
serial-port timing parameters
The following tables define the timing parameters for the serial port.
timing requirements (see Figure 31 and Figure 32)
CLKX/R ext
tc(SCK)
time CLKX/R
Cycle time,
tw(SCK)
P lse duration,
Pulse
d ration CLKX/R high/lo
high/low
tr(SCK)
tf(SCK)
Rise time, CLKX/R
CLKX/R int
CLKX/R ext
CLKX/R int
MIN
MAX
UNIT
tc(H) * 2.6
tc(H) * 2
tc(H) * 216
ns
tc(H) + 5
[tc(SCK)/2] – 4
Fall time, CLKX/R
[tc(SCK)/2] + 4
3
3
tsu(DR-CLKRL)
time DR before CLKR low
Setup time,
th(CLKRL-DR)
Hold time,
time DR after CLKR low
lo
tsu(FSR-CLKRL)
Set p time,
Setup
time FSR before CLKR low
lo
th(SCKL-FS)
Hold time
time, FSX/R inp
inputt after CLKX/R lo
low
tsu(FSX-CLKX)
Set p time,
Setup
time external
e ternal FSX before CLKX
CLKR ext
4
CLKR int
5
CLKR ext
3
CLKR int
0
CLKR ext
4
CLKR int
5
CLKX/R ext
3
CLKX/R int
0
CLKX ext
CLKX int
–[tc(H) – 6]
–[tc(H) – 10]
ns
ns
ns
ns
ns
ns
ns
[tc(SCK)/2] – 6
tc(SCK)/2
ns
switching characteristics over recommended operating conditions (see Figure 31 and Figure 32)
PARAMETER
MIN
td(H1H-SCK)
Delay time, H1 high to internal CLKX/R
td(CLKX-DX)
Dela time
Delay
time, CLKX to DX valid
alid
td(CLKX-FSX)
Dela time,
Delay
time CLKX to internal FSX high/low
high/lo
td(CLKX-DX)V
Delay time, CLKX to first DX bit, FSX precedes
recedes CLKX
high
td(FSX-DX)V
tdis(CLKX-DXZ)
44
MAX
UNIT
4
ns
CLKX ext
6
CLKX int
5
CLKX ext
5
CLKX int
4
CLKX ext
5
CLKX int
4
ns
ns
ns
Delay time, FSX to first DX bit, CLKX precedes FSX
6
ns
Disable time, DX high impedance following last data bit from CLKX high
6
ns
POST OFFICE BOX 1443
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
data-rate timing modes
Unless otherwise indicated, the data-rate timings shown in Figure 31 and Figure 32 are valid for all serial-port
modes, including handshake. For a functional description of serial-port operation, see the TMS320C3x User’s
Guide (literature number SPRU031).
tc(SCK)
td(H1H-SCK)
H1
td(H1H-SCK)
tw(SCK)
tw(SCK)
CLKX/R
tf(SCK)
td(CLKX–DX)
td(CLKX–DX)V
th(CLKRL–DR)
Bit n-1
DX
tr(SCK)
tdis(CLKX–DXZ)
Bit 0
Bit n-2
tsu(DR–CLKRL)
DR
Bit n-1
Bit n-2
FSR
tsu(FSR–CLKRL)
td(CLKX–FSX)
td(CLKX–FSX)
FSX(INT)
th(SCKL–FS)
FSX(EXT)
th(SCKL–FS)
tsu(FSX–CLKX)
NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
Figure 31. Fixed Data-Rate Mode Timing
CLKX/R
td(CLKX–FSX)
FSX(INT)
tsu(FSX–CLKX)
td(FSX–DX)V
FSX(EXT)
td(CLKX–DX)
td(CLKX-DX)V
DX
Bit n-1
th(SCKL-FS)
FSR
tdis(CLKX-DXZ)
Bit n-2
Bit n-3
Bit 0
tsu(FSR-CLKRL)
DR
Bit n-1
Bit n-2
Bit n-3
tsu(DR–CLKRL)
th(CLKRL-DR)
NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed
data-rate mode.
Figure 32. Variable Data-Rate Mode Timing
POST OFFICE BOX 1443
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
HOLD timing
HOLD is a synchronous input that can be asserted at any time during a clock cycle. If the specified timings are
met, the exact sequence shown in Figure 33 and Figure 34 occurs; otherwise, an additional delay of one clock
cycle is possible.
The table, “timing parameters for HOLD/HOLDA”, defines the timing parameters for the HOLD and HOLDA
signals. The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set,
the device comes out of hold and prevents future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a
read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus
allowing the processor to continue (internally) until a second external write is encountered.
Figure 33, Figure 34, and the accompanying timings are for a zero wait-state bus configuration. Since HOLD
is internally captured by the CPU on the H1 falling edge one cycle before the present cycle is terminated, the
minimum HOLD width for any bus configuration is, therefore, WTCNT+3. Also, HOLD should not be deasserted
before HOLDA has been active for at least one cycle.
timing requirements for HOLD/HOLDA (see Figure 33 and Figure 34)
VC33-120
MIN
tsu(HOLD-H1L)
tw(HOLD)
Setup time, HOLD before H1 low
Pulse duration, HOLD low
switching characteristics over
(see Figure 33 and Figure 34)
recommended
VC33-150
MAX
3
ns
3tc(H)
ns
conditions
VC33-120
MIN
td(H1L-SH)H
tdis(H1L-S)
Delay time, H1 low to STRB high for a HOLD
Disable time, STRB to the high-impedance state from H1 low
ten(H1L-S)
tdis(H1L-RW)
UNIT
4
PARAMETER
Valid time, HOLDA after H1 low
MAX
3tc(H)
operating
tv(H1L-HOLDA)
tw(HOLDA)
MIN
for
HOLD/HOLDA
VC33-150
MAX
MIN
MAX
UNIT
–1
4
–1
3
2tc(H) – 4
–1
4
2tc(H) – 4
–1
3
ns
5
4
ns
Enable time, STRB enabled (active) from H1 low
5
5
ns
Disable time, R/W to the high-impedance state from H1 low
5
4
ns
ten(H1L-RW)
tdis(H1L-A)
Enable time, R/W enabled (active) from H1 low
5
5
ns
Disable time, Address to the high-impedance state from H1 low
5
4
ns
ten(H1L-A)
tdis(H1H-D)
Enable time, Address enabled (valid) from H1 low
5
5
ns
Disable time, Data to the high-impedance state from H1 high
5
4
ns
46
Pulse duration, HOLDA low
POST OFFICE BOX 1443
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ns
ns
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
HOLD timing (continued)
H3
H1
tsu(HOLD–H1L)
HOLD
tsu(HOLD–H1L)
tw(HOLD)
tv(H1L-HOLDA)
HOLDA
tw(HOLDA)
tv(H1L–HOLDA)
td(H1L-SH)H
ten(H1L-S)
tdis(H1L-S)
STRB, PAGEx
ten(H1L-RW)
tdis(H1L-RW)
R/W
ten(H1L-A)
tdis(H1L-A)
A[23:0]
tdis(H1H-D)
D[31:0]
Write Data
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 33. Timing for HOLD/HOLDA (After Write)
H3
H1
tsu(HOLD–H1L)
HOLD
tsu(HOLD–H1L)
tw(HOLD)
tv(H1L–HOLDA)
HOLDA
tw(HOLDA)
tv(H1L–HOLDA)
td(H1L-SH)H
tdis(H1L-S)
ten(H1L-S)
STRB, PAGEx
tdis(H1L-RW)
ten(H1L-RW)
R/W
tdis(H1L-A)
ten(H1L-A)
A[23:0]
D[31:0]
Read Data
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 34. Timing for HOLD/HOLDA (After Read)
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47
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
general-purpose I/O timing
Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The contents of the internal
control registers associated with each peripheral define the modes for these pins.
peripheral pin I/O timing
The following tables show the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and vice versa.
timing requirements for peripheral pin general-purpose I/O (see Note 1, Figure 35, and Figure 36)
tsu(GPIO-H1L)
th(H1L-GPIO)
VC33-120
VC33-150
MIN
MIN
MAX
MAX
UNIT
Setup time, general-purpose input before H1 low
4
3
ns
Hold time, general-purpose input after H1 low
0
0
ns
NOTE 1: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
switching characteristics over recommended operating conditions for peripheral pin
general-purpose I/O (see Note 1, Figure 35, and Figure 36)
PARAMETER
td(H1H-GPIO)
VC33-120
VC33-150
MIN
MIN
MAX
Delay time, H1 high to general-purpose output
5
MAX
4
UNIT
ns
tdis(H1H)
Disable time, general-purpose output from H1 high
7
5
ns
NOTE 1: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Execution
of Store of
PeripheralControl
Register
Buffers Go
From
Output to
Input
Synchronizer Delay
Value on Pin
Seen in
PeripheralControl
Register
H3
H1
tsu(GPIO-H1L)
I/O
Control Bit
Peripheral Pin
(see Note A)
Data Bit
th(H1L-GPIO)
tdis(H1H)
Output
Data
Sampled
Data
Seen
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 35. Change of Peripheral Pin From General-Purpose Output to Input Mode Timing
48
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
peripheral pin I/O timing (continued)
Execution of Store
of PeripheralControl Register
H3
H1
I/O
Control
Bit
td(H1H-GPIO)
td(H1H-GPIO)
Peripheral Pin
(see Note A)
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 36. Change of Peripheral Pin From General-Purpose Input to Output Mode Timing
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SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
timer pin timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers. The following
tables define the timing parameters for the timer pin.
timing requirements for timer pin (see Figure 37 and Figure 38)
VC33-120
MIN
tsu(TCLK-H1L)† Setup time, TCLK external before H1 low
th(H1L-TCLK)† Hold time, TCLK external after H1 low
† These requirements are applicable for a synchronous input clock.
VC33-150
MAX
MIN
MAX
UNIT
4
3
ns
0
0
ns
switching characteristics over recommended operating conditions for timer pin (see Figure 37 and
Figure 38)
VC33-120
PARAMETER
MIN
td(H1H-TCLK)
Delay time, H1 high to TCLK internal
valid
tc(TCLK)‡
C cle time,
Cycle
time TCLK
TCLK ext
TCLK int
MAX
Pulse duration,
duration TCLK
MIN
4
tc(H) * 2.6
tc(H) * 2
tc(H) + 6
[tc(TCLK)/2] – 4
‡ These parameters are applicable for an asynchronous input clock.
tw(TCLK)
(TCLK)‡
VC33-150
[tc(TCLK)/2] + 4
tc(H) + 5
[tc(TCLK)/2] – 4
[tc(TCLK)/2] + 4
th(H1L-TCLK)
tsu(TCLK-H1L)
th(H1L-TCLK)
tsu(TCLK-H1L)
TCLK as input
tc(TCLK)
Figure 37. Timer Pin Timing, Input
H3
H1
td(H1H-TCLK)
TCLK as output
Figure 38. Timer Pin Timing, Output
50
POST OFFICE BOX 1443
ns
tc(H) * 232
H1
td(H1H-TCLK)
ns
tc(H) * 2.6
tc(H) * 2
H3
• HOUSTON, TEXAS 77251–1443
tw(TCLK)
UNIT
3
tc(H) * 232
TCLK ext
TCLK int
MAX
ns
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
SHZ pin timing
The following table defines the timing parameter for the SHZ pin.
switching characteristics over recommended operating conditions for SHZ (see Figure 39)
PARAMETER
tdis(SHZ)
MIN
Disable time, SHZ low to all outputs, I/O pins disabled (high impedance)
0
MAX
8
UNIT
ns
SHZ
tdis(SHZ)
All I/O Pins
NOTE A: Enabling SHZ destroys TMS320VC33 register and memory contents. Assert
SHZ = 1 and reset the TMS320VC33 to restore it to a known condition.
Figure 39. Timing for SHZ
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
51
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
IEEE-1149.1 test access port timing
The following table defines the timing parameter for the IEEE-1149.1 test access port.
timing for IEEE-1149.1 test access port (see Figure 40)
VC33–120
VC33–150
MIN
MIN
tsu(TMS-TCKH)
th(TCKH-TMS)
Setup time, TMS/TDI to TCK high
5
Hold time, TMS/TDI from TCK high
5
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
0
tr (TCK)
Rise time, TCK
tf (TCK)
Fall time, TCK
MAX
5
tf(TCK)
ns
3
3
ns
3
3
ns
TMS/TDI
td(TCHL-TDOV)
th(TCHK-TMS)
TDO
Figure 40. IEEE-1149.1 Test Access Port Timings
52
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ns
10
tsu(TMS-TCKH)
0
UNIT
ns
5
10
TCK
tr(TCK)
MAX
SPRS087D – FEBRUARY 1999 – REVISED JULY 2002
MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°–ā7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
PARAMETER
°C/W
RΘJA
56
RΘJC
5
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
53
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