TI SMJ320C31

SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
D
D
D
D
D
D
D
D
D
D
D
D
D
– 55°C to 125°C Operating Temperature
Range, QML Processing
Processed to MIL-PRF-38535 (QML)
SMD Approval for 40- and 50-MHz Versions
High-Performance Floating-Point Digital
Signal Processor (DSP):
– SMJ320C31-50 (5 V)
40-ns Instruction Cycle Time
275 Million Operations Per Second
(MOPS), 50 Million Floating-Point
Operations Per Second (MFLOPS),
25 Million Instructions Per Second
(MIPS)
– SMJ320C31-40 (5 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
– SMJ320LC31-40 (3.3 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
– SMQ320LC31-40 (3.3 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
32-Bit High-Performance CPU
16- / 32-Bit Integer and 32- / 40-Bit
Floating-Point Operations
32-Bit Instruction and Data Words, 24-Bit
Addresses
Two 1K Word × 32-Bit Single-Cycle
Dual-Access On-Chip RAM Blocks
Boot-Program Loader
64-Word × 32-Bit Instruction Cache
Eight Extended-Precision Registers
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Two Low-Power Modes
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
On-Chip Memory-Mapped Peripherals:
– One Serial Port Supporting
8- / 16- / 24- / 32-Bit Transfers
– Two 32-Bit Timers
– One-Channel Direct Memory Access
(DMA) Coprocessor for Concurrent I/O
and CPU Operation
Fabricated Using 0.7 µm Enhanced
Performance Implanted CMOS (EPIC)
Technology by Texas Instruments (TI)
Two- and Three-Operand Instructions
40 / 32-Bit Floating-Point / Integer Multiplier
and Arithmetic Logic Unit (ALU)
Parallel ALU and Multiplier Execution in a
Single Cycle
Block-Repeat Capability
Zero-Overhead Loops With Single-Cycle
Branches
Conditional Calls and Returns
Interlocked Instructions for
Multiprocessing Support
Bus-Control Registers Configure
Strobe-Control Wait-State Generation
Validated Ada Compiler
Integer, Floating-Point, and Logical
Operations
32-Bit Barrel Shifter
One 32-Bit Data Bus (24-Bit Address)
Packaging
– 132-Lead Ceramic Quad Flatpack With
Nonconductive Tie-Bar (HFG Suffix)
– 141-Pin Ceramic Staggered Pin
Grid- Array Package (GFA Suffix)
– 132-Lead TAB Frame
– 132-Lead Plastic Quad Flatpack
(PQ Suffix)
description
The SMJ320C31, SMJ320LC31, and SMQ320LC31 digital signal processors (DSPs) are 32-bit, floating-point
processors manufactured in 0.72-µm triple-level-metal CMOS technology. The devices are part of the
SMJ320C3x generation of DSPs from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and TI are trademarks of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
• HOUSTON, TEXAS 77251–1443
1
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
description (continued)
The SMJ320C3x internal busing and special digital-signal-processing instruction set have the speed and
flexibility to execute up to 50 MFLOPS. The SMJ320C3x optimizes speed by implementing functions in
hardware that other processors implement through software or microcode. This hardware-intensive approach
provides performance previously unavailable on a single chip.
The SMJ320C3x can perform parallel multiply and ALU operations on integer or floating-point data in a single
cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,
internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time.
High performance and ease of use are results of these features.
General-purpose applications are greatly enhanced by the large address space, multiprocessor interface,
internally and externally generated wait states, one external interface port, two timers, one serial port, and
multiple-interrupt structure. The SMJ320C3x supports a wide variety of system applications from host processor
to dedicated coprocessor.
High-level-language support is easily implemented through a register-based architecture, large address space,
powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.
2
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
141-PIN GFA STAGGERED GRID ARRAY
PACKAGE
( BOTTOM VIEW )
TA PACKAGE
( TOP VIEW )
1
3
5
7
9
11
13
15
17
19
2
4
6
8
132
1
10
100
99
Tab Leads Up
12
14
16
18
Die Face Up
B
A
D
C
67
33
F H K M P T V
E G J L N R U W
34
TB PACKAGE
( TOP VIEW )
132-PIN HFG QUAD FLATPACK
( TOP VIEW )
ÉÉ
ÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
34
33
99
100
99
132
1
Tab Leads Up
Die Face Up
67
33
34
66
67
66
1
100
ÉÉ
ÉÉÉÉ
ÉÉ
132
ÉÉ
ÉÉ
ÉÉ
ÉÉ
66
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
3
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
SMQ320LC31 pinout (top view)
The SMQ320LC31 device is also packaged in a132-pin plastic quad flatpack (PQ Suffix). The full part numbers
are SMQ320LC31PQM40 and 5962-9760601NXB.
9
8
7
6
3
SHZ
VSS
TCLK0
VSS
2
4
MCBL/MP
EMU2
EMU1
EMU0
EMU3
TCLK1
VDD
5
A22
A23
VSS
A20
A21
VDD
VDD
17 16 15 14 13 12 11 10
A19
VSS
VSS
A11
A12
A13
A14
A15
A16
A17
A18
VDD
VSS
A10
VDD
PQ PACKAGE
(TOP VIEW)
1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
A9
18
116
VSS
A8
A7
A6
A5
VDD
A4
A3
A2
A1
A0
VSS
D31
VDD
VDD
D30
VSS
VSS
VSS
D29
D28
VDD
D27
VSS
D26
D25
D24
D23
D22
D21
VDD
D20
19
115
20
114
21
113
22
112
23
111
24
110
25
109
26
108
27
107
28
106
29
105
30
104
31
103
32
102
33
101
34
100
35
99
36
98
37
97
38
96
39
95
40
94
41
93
42
92
43
91
44
90
45
89
46
88
47
87
48
86
49
85
50
84
4
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
V DD
D5
D4
D3
D2
D1
D0
H1
H3
V DD
D7
D6
D9
D8
VSS
VSS
VSS
D12
D11
D10
V DD
V DD
D14
V DD
D13
V SS
D19
D18
D17
D16
D15
V SS
V SS
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
DX0
VDD
FSX0
VSS
CLKX0
CLKR0
FSR0
VSS
DR0
INT3
INT2
VDD
VDD
INT1
VSS
VSS
INT0
IACK
XF1
VDD
XF0
RESET
R/W
STRB
RDY
VDD
HOLD
HOLDA
X1
X2/CLKIN
VSS
VSS
VSS
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
Terminal Assignments
PIN
PIN
NUMBER
NUMBER
GFA
PKG
NAME
PQ
PKG
HFG
PKG
GFA
PKG
NAME
12
L1
A0
64
47
W9
D10
11
K2
A1
63
46
U9
D11
27
10
J1
A2
62
45
V8
D12
26
9
J3
A3
60
43
W7
D13
25
8
G1
A4
58
41
U7
D14
23
6
F2
A5
56
39
V6
D15
22
5
E1
A6
55
38
W5
D16
21
4
E3
A7
54
37
U5
D17
20
3
D2
A8
53
36
V4
D18
18
1
C1
A9
52
35
W3
D19
16
131
C3
A10
50
33
U3
D20
14
129
B2
A11
48
31
V2
D21
13
128
A1
A12
47
30
W1
D22
12
127
C5
A13
46
29
R3
D23
PQ
PKG
HFG
PKG
29
28
11
126
B4
A14
45
28
T2
D24
10
125
A3
A15
44
27
U1
D25
9
124
C7
A16
43
26
N3
D26
8
123
B6
A17
41
24
P2
D27
7
122
C9
A18
39
22
R1
D28
5
120
B8
A19
38
21
L3
D29
2
117
A7
A20
34
17
M2
D30
1
116
A9
A21
31
14
N1
D31
130
113
B10
A22
108
91
C19
DR0
129
112
A11
A23
116
99
C17
DX0
111
94
E17
CLKR0
124
107
B14
EMU0
112
95
A19
CLKX0
125
108
A13
EMU1
80
63
W19
D0
126
109
B12
EMU2
79
62
V16
D1
123
106
A15
EMU3
78
61
W17
D2
110
93
D18
FSR0
77
60
U13
D3
114
97
B18
FSX0
76
59
V14
D4
81
73
P18
HOLD
75
58
W15
D5
82
72
R19
HOLDA
73
56
U11
D6
90
64
V18
H1
72
55
V12
D7
89
65
U17
H3
68
51
W11
D8
99
82
H18
IACK
100
83
J17
INT0
67
50
V10
D9
† CVSS, VSSL, and IVSS are on the same plane.
‡ AVDD, DVDD, CVDD, and PVDD are on the same plane.
§ VSUBS connects to die metallization. Tie this pin to clean ground.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
5
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
Terminal Assignments (Continued)
PIN
PIN
NUMBER
NUMBER
PQ
PKG
HFG
PKG
GFA
PKG
NAME
PQ
PKG
HFG
PKG
GFA
PKG
NAME
103
86
E19
INT1
30
106
89
F18
INT2
35
18
P4
19
T10
VSSL†
VSSL†
107
90
G17
INT3
127
110
C11
MCBL/MP
36
20
K4
37
25
T4
92
77
L19
95
75
N17
R/W
42
34
G3
RDY
51
40
K16
94
78
K18
RESET
57
44
T8
118
101
93
76
A17
SHZ
61
52
T12
M19
STRB
69
53
R11
120
103
B16
TCLK0
70
54
J15
105
121
C15
TCLK1
71
67
W13
G5
AVDD‡
AVDD‡
AVDD‡
84
68
D10
6
130
E7
85
69
D16
15
7
E5
86
84
T16
24
15
N5
32
16
R5
101
85
D12
102
92
F16
H4
VDDL
VDDL
DVDD‡
33
23
109
96
H16
113
100
D14
IVSS†
DVSS
VSSL†
VSSL†
DVSS
CVSS†
IVSS†
DVSS
VSSL†
CVSS†
IVSS†
40
32
J5
DVDD‡
49
42
T14
DVDD‡
117
102
U15
59
48
R7
119
111
C13
65
49
R9
128
71
T18
X1
66
57
R13
VDDL
VDDL
DVDD‡
88
70
U19
X2/CLKIN
74
66
R15
87
79
J19
XF0
83
74
P16
DVDD‡
CVDD‡
96
81
G19
XF1
91
80
N15
CVDD‡
98
F6
No Connect
97
87
G15
104
88
E15
105
98
L15
VDDL
VDDL
PVDD‡
115
104
E9
121
114
E13
131
115
E11
132
118
L5
3
119
H2
4
132
M4
17
2
F4
PVDD‡
VDDL
VDDL
VSSL†
DVSS
CVSS†
DVSS
CVSS†
19
13
T6
† CVSS, VSSL, and IVSS are on the same plane.
‡ AVDD, DVDD, CVDD, and PVDD are on the same plane.
§ VSUBS connects to die metallization. Tie this pin to clean ground.
6
DVSS
IVSS†
DVSS
CVSS†
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
VSUBS§
DVSS
CVSS†
D4
DVSS
N19
DVSS
R17
DVSS
L17
DVSS
M16
DVSS
D6
DVSS
A5
DVSS
D8
DVSS
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
Terminal Functions
TERMINAL
NAME
TYPE†
DESCRIPTION
QTY
CONDITIONS
WHEN
SIGNAL IS Z TYPE‡
PRIMARY-BUS INTERFACE
D31 – D0
32
I/O/Z
32-bit data port
S
H
R
A23 – A0
24
O/Z
24-bit address port
S
H
R
R/W
1
O/Z
Read / write. R / W is high when a read is performed and low when a write is performed
over the parallel interface.
S
H
R
STRB
1
O/Z
External-access strobe
S
H
RDY
HOLD
HOLDA
1
1
1
I
Ready. RDY indicates that the external device is prepared for a transaction
completion.
I
Hold. When HOLD is a logic low, any ongoing transaction is completed. A23 – A0,
D31 – D0, STRB, and R / W are placed in the high-impedance state and all transactions over the primary-bus interface are held until HOLD becomes a logic high or until
the NOHOLD bit of the primary-bus-control register is set.
O/Z
Hold acknowledge. HOLDA is generated in response to a logic low on HOLD. HOLDA
indicates that A23 – A0, D31 – D0, STRB, and R / W are in the high-impedance state
and that all transactions over the bus are held. HOLDA is high in response to a logic
high of HOLD or the NOHOLD bit of the primary-bus-control register is set.
S
CONTROL SIGNALS
RESET
1
I
Reset. When RESET is a logic low, the device is in the reset condition. When RESET
becomes a logic high, execution begins from the location specified by the reset vector.
INT3 – INT0
4
I
External interrupts
IACK
1
O/Z
MCBL / MP
1
I
Microcomputer boot-loader / microprocessor mode-select
Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used
to indicate the beginning or the end of an interrupt-service routine.
SHZ
1
I
Shutdown high impedance. When active, SHZ shuts down the device and places all
pins in the high-impedance state. SHZ is used for board-level testing to ensure that
no dual-drive conditions occur. CAUTION: A low on SHZ corrupts the device memory
and register contents. Reset the device with SHZ high to restore it to a known
operating condition.
XF1, XF0
2
I/O/Z
External flags. XF1 and XF0 are used as general-purpose I / Os or to support
interlocked processor instruction.
S
S
R
SERIAL PORT 0 SIGNALS
CLKR0
1
I/O/Z
Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver.
S
R
S
R
CLKX0
1
I/O/Z
Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
transmitter.
DR0
1
I/O/Z
Data-receive. Serial port 0 receives serial data on DR0.
S
R
DX0
1
I/O/Z
Data-transmit output. Serial port 0 transmits serial data on DX0.
S
R
S
R
S
R
FSR0
1
I/O/Z
Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive
process using DR0.
FSX0
1
I/O/Z
Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit
process using DX0.
S
S
TIMER SIGNALS
TCLK0
1
I/O/Z
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an
output, TCLK0 outputs pulses generated by timer 0.
TCLK1
1
I/O/Z
Timer clock 1. As an input, TCLK0 is used by timer 1 to count external pulses. As an
output, TCLK1 outputs pulses generated by timer 1.
† I = input, O = output, Z = high-impedance state
‡ S = SHZ active, H = HOLD active, R = RESET active
POST OFFICE BOX 1443
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7
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
Terminal Functions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
QTY
CONDITIONS
WHEN
SIGNAL IS Z TYPE‡
SUPPLY AND OSCILLATOR SIGNALS
H1
1
O/Z
External H1 clock. H1 has a period equal to twice CLKIN.
S
H3
1
O/Z
External H3 clock. H3 has a period equal to twice CLKIN.
S
VDD
20
I
5-V supply for ’C31 devices and 3.3-V supply for ’LC31 devices. All must be
connected to a common supply plane.§
VSS
25
I
Ground. All grounds must be connected to a common ground plane.
X1
1
O
Output from the internal-crystal oscillator. If a crystal is not used, X1 should be left
unconnected.
X2 / CLKIN
1
I
Internal-oscillator input from a crystal or a clock
RESERVED¶
EMU2 – EMU0
3
I
Reserved for emulation. Use pullup resistors to VDD
EMU3
1
O/Z
Reserved for emulation
S
† I = input, O = output, Z = high-impedance state
‡ S = SHZ active, H = HOLD active, R = RESET active
§ Recommended decoupling capacitor value is 0.1 µF.
¶ Follow the connections specified for the reserved pins. Use 18 -kΩ – 22-kΩ pullup resistors for best results. All VDD supply pins must be connected
to a common supply plane, and all ground pins must be connected to a common ground plane.
8
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
functional block diagram
RAM
Block 0
(1K × 32)
Cache
(64 × 32)
32
24
RAM
Block 1
(1K × 32)
32
24
24
32
ÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
Boot
Loader
24
32
PDATA Bus
PADDR Bus
MUX
DDATA Bus
MUX
RDY
HOLD
HOLDA
STRB
R/W
D31– D0
A23 – A0
DADDR1 Bus
DADDR2 Bus
DMADATA Bus
DMAADDR Bus
32
24
24
32
32
24
24
DMA Controller
Serial Port 0
Serial-Port-Control
Register
Global-Control
Register
MUX
X1
X2 / CLKIN
H1
H3
EMU(3 – 0)
DestinationAddress
Register
REG1
TransferCounter
Register
REG2
REG1
CPU1
REG2
32
32
40
40
32-Bit
Barrel
Shifter
Multiplier
40
40
32
Data-Transmit
Register
Data-Receive
Register
Timer 0
Global-Control
Register
ALU
40
Peripheral Address Bus
CPU1
CPU2
Controller
RESET
INT(3 – 0)
IACK
MCBL / MP
XF(1,0)
VDD(19 – 0)
VSS(24 – 0)
Receive/Transmit
(R / X) Timer Register
Source-Address
Register
Peripheral Data Bus
IR
PC
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
40
ExtendedPrecision
Registers
(R7–R0)
40
40
Timer-Period
Register
TCLK0
Timer-Counter
Register
Timer 1
DISP0, IR0, IR1
Global-Control
Register
ARAU0
BK
ARAU1
Timer-Period
Register
24
24
24
32
32
Auxiliary
Registers
(AR0 – AR7)
TCLK1
Timer-Counter
Register
24
Port Control
32
STRB-Control
Register
32
32
Other
Registers
(12)
POST OFFICE BOX 1443
32
• HOUSTON, TEXAS 77251–1443
9
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
memory map†
0h
Reset, Interrupt, Trap Vector, and
Reserved Locations (64)
(External STRB Active)
0h
03Fh
040h
Reserved for Boot-Loader
Operations
FFFh
1000h
External
STRB Active
(8M Words – 64 Words)
400000h
Boot 1
Boot 2
7FFFFFh
800000h
7FFFFFh
800000h
Reserved
(32K Words)
Reserved
(32K Words)
807FFFh
808000h
External
STRB
Active
(8M Words –
4K Words)
Peripheral Bus
Memory-Mapped Registers
(6K Words Internal)
807FFFh
808000h
Peripheral Bus
Memory-Mapped Registers
(6K Words Internal)
8097FFh
809800h
8097FFh
809800h
RAM Block 0
(1K Words Internal)
RAM Block 0
(1K Words Internal)
809BFFh
809C00h
809BFFh
809C00h
RAM Block 1
(1K Words – 63 Words Internal)
RAM Block 1
(1K Words Internal)
809FFFh
80A000h
External
STRB Active
(8M Words – 40K Words)
FFFFFFh
809FC0h
809FC1h
User-Program Interrupt
and Trap Branches
(63 Words Internal)
809FFFh
80A000h
FFF000h
Boot 3
FFFFFFh
(a) Microprocessor Mode
External
STRB Active
(8M Words –
40K Words)
(b) Microcomputer/Boot-Loader Mode
† Figure 1 depicts the memory map for the SMJ320C31. See the TMS320C3x Users Guide (literature number SPRU031) for a detailed description
of this memory mapping.
Figure 1. SMJ320C31 Memory Map
10
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
memory map (continued)
00h
Reset
809FC1h
INT0
01h
INT0
809FC2h
INT1
02h
INT1
809FC3h
INT2
03h
INT2
809FC4h
INT3
04h
INT3
809FC5h
05h
XINT0
XINT0
06h
RINT0
809FC6h
RINT0
07h
08h
809FC7h
Reserved
Reserved
809FC8h
09h
TINT0
809FC9h
TINT0
0Ah
TINT1
809FCAh
TINT1
0Bh
DINT
809FCBh
DINT
0Ch
1Fh
Reserved
809FCCh
809FDFh
Reserved
20h
TRAP 0
809FE0h
TRAP 0
3Bh
TRAP 27
809FFBh
TRAP 27
3Ch
3Fh
Reserved
809FFCh
Reserved
809FFFh
(a) Microprocessor Mode
(b) Microcomputer / Boot-Loader Mode
Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations
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11
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
memory map (continued)
808000h
DMA Global Control
808004h
DMA Source Address
808006h
DMA Destination Address
808008h
DMA Transfer Counter
808020h
Timer 0 Global Control
808024h
Timer 0 Counter
808028h
Timer 0 Period Register
808030h
Timer 1 Global Control
808034h
Timer 1 Counter
808038h
Timer 1 Period Register
808040h
Serial Global Control
808042h
FSX/DX/CLKX Serial Port Control
808043h
FSR/DR/CLKR Serial Port Control
808044h
Serial R/X Timer Control
808045h
Serial R/X Timer Counter
808046h
Serial R/X Timer Period Register
808048h
Data-Transmit
80804Ch
Data-Receive
808064h
Primary-Bus Control
†Shading denotes reserved address locations
Figure 3. Peripheral Bus Memory-Mapped Registers†
12
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
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absolute maximum ratings over specified temperature range (unless otherwise noted)†
’C31
’LC31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
. . . . . . . . . . – 0.3 V to 5 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
. . . . . . . . . . – 0.3 V to 5 V
Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
. . . . . . . . . . – 0.3 V to 5 V
Continuous power dissipation (worst case) (see Note 2) . . . . . . . . . . . . . . . . . . 1.7 W
(for SMJ320C31-33)
. . . . . . . . . . . . . . 850 mW
Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
. . . . . . – –55°C to 125°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
. . . . . . . – 65°C to 150°C
Supply voltage, VDD (see Note 1)
(for SMJ320LC31-33)
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. Actual operating power is less. This value was obtained under specially produced worst-case test conditions for the TMS320C31-33
and the TMS320LC31-33, which are not sustained during normal device operation. These conditions consist of continuous parallel
writes of a checkerboard pattern to both primary and extension buses at the maximum rate possible. See normal (ICC) current
specification in the electrical characteristics table and also read Calculation of TMS320C30 Power Dissipation Application Report
(literature number SPRA020).
recommended operating conditions (see Note 3)
’C31
VDD
VSS
VIH
Supply voltage (DVDD, etc.)
’320C31-40
’320C31-50
’320LC31-40
’LC31
MIN
NOM
MAX
4.75
4.75
5
5
5.25
5.25
Supply voltage (CVSS, etc.)
MIN
NOM
MAX
3.13
3.3
3.47
V
0
High-level input voltage (except RESET)
2.1
High-level input voltage (RESET)
2.2
2.2
V
V
0.6
V
High-level output current
– 300
– 300
µA
IOL
TA
Low-level output current
2
2
mA
125
°C
125
– 0.3*
V
VDD + 0.3*
VDD + 0.3*
Low-level input voltage
–55
0.8
1.8
VIL
IOH
Operating free-air temperature
– 0.3*
0
VDD + 0.3*
VDD + 0.3*
UNIT
–55
VTH
High-level input voltage for CLKIN
3.0
VDD + 0.3*
2.5
VDD + 0.3*
V
* This parameter is not production tested.
NOTE 3: All voltage values are with respect to VSS. All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS
clock.
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(see Note 3)†
PARAMETER
TEST CONDITIONS
VOH
VOL
High-level output voltage
IZ
II
MIN
’C31
TYP‡
High-impedance current
VDD = MIN, IOH = MAX
VDD = MIN, IOH = MAX
VDD = MAX
– 20
+ 20
Input current
VI = VSS to VDD
– 10
IIP
Input current (with internal
pullup)
Inputs with internal pullups§
– 600
ICC
Supplyy current¶#
TA = 25°C,
VDD = MAX
Low-level output voltage
IDD
Supply current
Ci
Input
capacitance
Standby,
2.4
MAX
3
0.3
fx = 40 MHz
’C31-40
’LC31-40
fx = 50 MHz ’C31-50
IDLE2
Clocks shut off
All inputs except CLKIN
CLKIN
MIN
’LC31
TYP‡
MAX
2
UNIT
V
0.6
0.4
V
– 20
+ 20
µA
+ 10
– 10
+ 10
µA
20
– 600
10
µA
160
400
200
425
50
150
300
mA
µA
20
15*
15*
25
25
pF
Co
Output capacitance
20*
20*
pF
† All input and output voltage levels are TTL compatible.
‡ For ’C31, all typical values are at VDD = 5 V, TA = 25°C. For ’LC31, all typical values are at VDD = 3.3 V, TA = 25°C.
§ Pins with internal pullup devices: INT3 – INT0, MCBL / MP.
¶ Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which
are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both primary
and expansion buses at the maximum rate possible. See Calculation of TMS320C30 Power Dissipation Application Report (literature number
SPRA020).
# fx is the input clock frequency.
* This parameter is not production tested.
NOTE 3: All voltage values are with respect to VSS. All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS
clock.
14
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
VLoad
CT
Output
Under
Test
IOH
Where:
IOL
IOH
VLOAD
CT
=
=
=
=
2 mA (all outputs)
300 µA (all outputs)
Selected to emulate 50-Ω termination (typical value = 1.54 V).
80-pF typical load-circuit capacitance
Figure 4. SMJ320C31 Test Load Circuit
signal transition levels for ’C31 (see Figure 5 and Figure 6)
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Output transition times are specified as follows:
D
D
For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be
no longer high is 2 V and the level at which the output is said to be low is 1 V.
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at
which the output is said to be high is 2 V.
2.4 V
2V
1V
0.6 V
Figure 5. TTL-Level Outputs
Transition times for TTL-compatible inputs are specified as follows:
D
D
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
2.1 V and the level at which the input is said to be low is 0.8 V.
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.8 V and the level at which the input is said to be high is 2.1 V.
2.1 V
0.8 V
Figure 6. TTL-Level Inputs
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
VLoad
CT
Output
Under
Test
IOH
Where:
IOL
IOH
VLOAD
CT
=
=
=
=
2 mA (all outputs)
300 µA (all outputs)
2.15 V
80-pF typical load-circuit capacitance
Figure 7. SMJ320LC31 Test Load Circuit
signal transition levels for ’LC31 (see Figure 8 and Figure 9)
Outputs are driven to a minimum logic-high level of 2 V and to a maximum logic-low level of 0.4 V. Output
transition times are specified as follows:
D
D
For a high-to-low transition on an output signal, the level at which the output is said to be no longer high
is 2 V and the level at which the output is said to be low is 1 V.
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at
which the output is said to be high is 2 V.
2V
1.8 V
0.6 V
0.4 V
Figure 8. ’LC31 Output Levels
Transition times for inputs are specified as follows:
D
D
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
1.8 V and the level at which the input is said to be low is 0.6 V.
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.6 V and the level at which the input is said to be high is 1.8 V.
1.8 V
0.6 V
Figure 9. ’LC31 Input Levels
16
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to
shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows,
unless otherwise noted:
A
A23 – A0
H
H1 and H3
ASYNCH
Asynchronous reset signals
HOLD
HOLD
C
CLKX0
HOLDA
HOLDA
CI
CLKIN
IACK
IACK
CLKR
CLKR0
INT
INT3 – INT0
CONTROL
Control signals
RDY
RDY
D
D31 – D0
RW
R/W
DR
DR
RESET
RESET
DX
DX
S
STRB
FS
FSX/R
SCK
CLKX/R
FSX
FSX0
SHZ
SHZ
FSR
FSR0
TCLK
TCLK0, TCLK1, or TCLKx
GPI
General-purpose input
XF
XF0, XF1, or XFx
GPIO
General-purpose input/output; peripheral pin
XFIO
XFx switching from input to output
GPO
General-purpose output
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
timing
Timing specifications apply to the SMJ320C31 and SMJ320LC31.
X2/CLKIN, H1, and H3 timing
The following table defines the timing parameters for the X2/CLKIN, H1, and H3 interface signals.
timing parameters for X2/CLKIN, H1, H3 (see Figure 10, Figure 11, Figure 12, and Figure 13)
’C31-40
’LC31-40
NO.
MIN
1
2
3
4
5
6
7
8
9
10
MAX
MIN
5*
UNIT
MAX
tf(CI)
tw(CIL)
Fall time, CLKIN
Pulse duration, CLKIN low tc(CI) = min
9
7
ns
tw(CIH)
tr(CI)
Pulse duration, CLKIN high tc(CI) = min
9
7
ns
tc(CI)
tf(H)
Cycle time, CLKIN
tw(HL)
tw(HH)
Pulse duration, H1 and H3 low
tr(H)
td(HL-HH)
Rise time, H1 and H3
Rise time, CLKIN
5*
5*
25
Fall time, H1 and H3
303
20
3
P–5†
P–6†
Pulse duration, H1 and H3 high
5
4
1
X2/CLKIN
3
2
Figure 10. Timing for X2/CLKIN
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ns
5*
ns
303
ns
3
ns
P – 5†
P – 6†
3
Delay time. from H1 low to H3 high or from H3 low to H1 high
11
tc(H)
Cycle time, H1 and H3
† P = tc(CI)
* This parameter is not production tested.
18
’C31-50
ns
ns
3
ns
0
4
0
4
ns
50
606
40
606
ns
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
X2/CLKIN, H1, and H3 timing (continued)
11
9
6
H1
8
7
10
10
H3
9
7
6
8
11
Figure 11. Timing for H1 and H3
8.00
8
7.00
7
6.00
6
5.00
5
4.00
4
3.00
3
2.00
2
1.00
1
CLKIN to H1/H3 - ns
4.5 V Band
0.00
–60.00
–40.00
–20.00
5.5 V Band
0
0.00
20.00
40.00
60.00
80.00
100.00
120.00
140.00
Temperature
Figure 12. SMJ320C31 CLKIN to H1 / H3 as a Function of Temperature
(Typical)
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
X2/CLKIN, H1, and H3 timing (continued)
12
12.00
10
CLKIN to H1/H3 - ns
10.00
8
8.00
6
6.00
4
4.00
3.8 V Band
2
2.00
0.00
–60.00
2.5 V Band
0
–40.00
–20.00
0.00
20.00
40.00
60.00
80.00
100.00
Temperature
Figure 13. SMJ320LC31 CLKIN to H1 / H3 as a Function of Temperature
(Typical)
20
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120.00
140.00
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
memory read/write timing
The following table defines memory read/write timing parameters for STRB.
timing parameters for memory (STRB = 0) read/write (see Figure 14 and Figure 15)†
’C31-40
’LC31-40
NO.
12
13
14
15
16
17
18
19
20
21
22
23
’C31-50
UNIT
MIN
MAX
MIN
MAX
td(H1L-SL)
td(H1L-SH)
Delay time, H1 low to STRB low
0*
6
0*
5
ns
Delay time, H1 low to STRB high
0*
6
0*
5
ns
td(H1H-RWL)R
td(H1L-A)
Delay time, H1 high to R/W low (read)
0*
9
0*
7
ns
Delay time, H1 low to A valid
0*
10
0*
10
ns
tsu(D-H1L)R
th(H1L-D)R
Setup time, D before H1 low (read)
14
10
ns
Hold time, D after H1 low (read)
0
0
ns
tsu(RDY-H1H)
th(H1H-RDY)
Setup time, RDY before H1 high
8
6
ns
Hold time, RDY after H1 high
0
td(H1H-RWH)W
tv(H1L-D)W
Delay time, H1 high to R/W high (write)
th(H1H-D)W
td(H1H-A)W
Hold time, D after H1 high (write)
Valid time, D after H1 low (write)
0
7
ns
17
14
ns
0
Delay time, H1 high to A valid on back-to-back write cycles (write)
ns
9
0
15
ns
14
ns
24
td(A-RDY)
Delay time, RDY from A valid
7*
6*
† See Figure 16 for address bus timing variation with load capacitance greater than typical load-circuit capacitance (CT = 80 pF).
* This parameter is not production tested.
ns
H3
H1
12
13
STRB
R/W
15
14
A
16
17
24
D
18
19
RDY
NOTE A: STRB remains low during back-to-back read operations.
Figure 14. Timing for Memory (STRB = 0) Read
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
memory read / write timing (continued)
H3
H1
13
12
STRB
20
14
R/W
15
23
A
21
22
D
19
18
RDY
Figure 15. Timing for Memory (STRB = 0) Write
Change in Address-Bus Timing, ns
Address-Bus Timing Variation Load Capacitance
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Change in Load Capacitance, pF
NOTE A: 30 pF/ns slope
Figure 16. Address-Bus Timing Variation With Load Capacitance (see Note A)
22
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DIGITAL SIGNAL PROCESSORS
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XF0 and XF1 timing when executing LDFI or LDII
The following table defines the timing parameters for XF0 and XF1 during execution of LDFI or LDII.
timing for XF0 and XF1 when executing LDFI or LDII for SMJ320C31 (see Figure 17)
NO
NO.
25
’C31-40
’LC31-40
MIN
MIN
MAX
’C31-50
MIN
26
Setup time, XF1 before H1 low
9
10
8
ns
27
th(H1L-XF1)
Hold time, XF1 after H1 low
0
0
0
ns
Read
12
UNIT
Delay time, H3 high to XF0 low
Decode
13
MAX
td(H3H-XF0L)
tsu(XF1-H1L)
Fetch
LDFI or LDII
13
MAX
ns
Execute
H3
H1
STRB
R/W
A
D
RDY
25
XF0 Pin
26
27
XF1 Pin
Figure 17. Timing for XF0 and XF1 When Executing LDFI or LDII
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
XF0 timing when executing STFI and STII†
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII.
timing for XF0 when executing STFI or STII (see Figure 18)
’C31-40
’LC31-40
NO.
MIN
MAX
’C31-50
MIN
UNIT
MAX
28 td(H3H-XF0H) Delay time, H3 high to XF0 high
13
12
ns
† XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of
the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store
from executing, the address of the store will not be driven until the store can execute.
Fetch
STFI or STII
Decode
Read
Execute
H3
H1
STRB
R/W
A
D
28
RDY
XF0 Pin
Figure 18. Timing for XF0 When Executing an STFI or STII
24
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DIGITAL SIGNAL PROCESSORS
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XF0 and XF1 timing when executing SIGI
The following table defines the timing parameters for the XF0 and XF1 pins during execution of SIGI.
timing for XF0 and XF1 when executing SIGI for SMJ320C31 (see Figure 19)
NO
NO.
29
30
31
32
’C31-40
’LC31-40
MIN
MIN
MAX
MAX
13
’C31-50
MIN
UNIT
td(H3H-XF0L)
td(H3H-XF0H)
Delay time, H3 high to XF0 low
tsu(XF1-H1L)
th(H1L-XF1)
Setup time, XF1 before H1 low
9
10
8
ns
Hold time, XF1 after H1 low
0
0
0
ns
Delay time, H3 high to XF0 high
Fetch
SIGI
13
MAX
13
Decode
Read
13
12
ns
12
ns
Execute
H3
H1
29
31
30
XF0
32
XF1
Figure 19. Timing for XF0 and XF1 When Executing SIGI
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
loading when XF is configured as an output
The following table defines the timing parameter for loading the XF register when the XFx pin is configured as
an output.
timing for loading the XF register when configured as an output pin (see Figure 20)
’C31-40
’LC31-40
NO.
MIN
33
tv(H3H-XF)
Valid time, H3 high to XFx
Fetch Load
Instruction
’C31-50
MAX
MIN
13
Decode
Read
12
Execute
H3
H1
OUTXFx Bit
(see Note A)
1 or 0
33
XFx Pin
NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register.
Figure 20. Timing for Loading XF Register When Configured as an Output Pin
26
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UNIT
MAX
ns
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
changing XFx from an output to an input
The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin.
timing of XFx changing from output to input mode for SMJ320C31 (see Figure 21)
NO
NO.
34
35
th(H3H-XF)
tsu(XF-H1L)
’C31-40
’LC31-40
MIN
MIN
Hold time, XFx after H3 high
MAX
13*
Setup time, XFx before H1 low
36
th(H1L-XF)
Hold time, XFx after H1 low
* This parameter is not production tested.
Execute
Load of IOF
MAX
Buffers Go
From Output
to Output
’C31-50
MIN
13*
MAX
12*
UNIT
ns
9
10
8
ns
0
0
0
ns
Synchronizer Value on Pin
Seen in IOF
Delay
H3
H1
35
I / OxFx Bit
(see Note A)
36
34
XFx Pin
INXFx Bit
(see Note A)
Output
Data
Sampled
Data
Seen
NOTE A: I / OxFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register.
Figure 21. Timing for Change of XFx From Output to Input Mode
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27
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
changing XFx from an input to an output
The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin.
timing for XFx changing from input to output mode (see Figure 22)
’C31-40
’LC31-40
NO.
MIN
37
td(H3H-XFIO)
MAX
Delay time, H3 high to XFx switching from input to output
17
’C31-50
MIN
UNIT
MAX
15
ns
Execution of
Load of IOF
H3
H1
I / OxFx
Bit
(see Note A)
37
XFx Pin
NOTE A: I / OxFx represents either bit 1 or bit 5 of the IOF register.
Figure 22. Timing for Change of XFx From Input to Output Mode
reset timing
RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 23 occurs; otherwise, an additional delay of one clock cycle is
possible.
The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
Resetting the device initializes the primary- and expansion-bus control registers to seven software wait states
and therefore results in slow external accesses until these registers are initialized.
HOLD is an asynchronous input and can be asserted during reset.
28
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
RESET timing (see Figure 23)
’C31-40
NO
NO.
’LC31-40
Setup time, RESET before CLKIN low
10
39
td(CLKINH-H1H)
Delay time, CLKIN high to H1 high
(see Note 4)
2
14
2
14
2
10
ns
40
td(CLKINH-H1L)
Delay time, CLKIN high to H1 low
(see Note 4)
2
14
2
14
2
10
ns
41
tsu(RESETH-H1L)
Setup time, RESET high before H1 low and
after ten H1 clock cycles
9
42
td(CLKINH-H3L)
Delay time, CLKIN high to H3 low
(see Note 4)
2
14
2
14
2
10
ns
43
td(CLKINH-H3H)
Delay time, CLKIN high to H3 high
(see Note 4)
2
14
2
14
2
10
ns
44
tdis(H1H-DZ)
tdis(H3H-AZ)
Disable time, H1 high to D (high impedance)
15*
13*
12*
ns
Disable time, H3 high to A (high impedance)
9*
9*
8*
ns
Delay time, H3 high to control signals high
9*
9*
8*
ns
47
td(H3H-CONTROLH)
td(H1H-RWH)
Delay time, H1 high to R/W high
9*
9*
8*
ns
48
td(H1H-IACKH)
Delay time, H1 high to IACK high
9*
9*
8*
ns
tdis(RESETL-ASYNCH)
Disable time, RESET low to asynchronous
reset signals disabled (high impedance)
21*
21*
17*
ns
46
49
MIN
10
MAX
P†*
10
MAX
P†*
UNIT
tsu(RESET-CIL)
45
MIN
’C31-50
MAX
P†*
38
MIN
9
7
ns
ns
† P = tc(CI)
* This parameter is not production tested.
NOTE 4: See Figure 12 and Figure 13 for typical temperature dependence.
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29
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
RESET timing (continued)
CLKIN
38
RESET
(see Notes A and B)
39
40
41
H1
42
H3
Ten H1 Clock Cycles
44
D
(see Note C)
43
A
(see Note C)
45
46
Control Signals
(see Note D)
47
SMJ320C31 R/W
(see Note E)
48
IACK
Asynchronous
Reset Signals
(see Note A)
49
NOTES: A. Asynchronous reset signals include XF0 / 1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.
C. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the
reset vector is fetched twice, with no software wait states.
D. Control signals include STRB.
E. The R/W outputs are placed in a high-impedance state during reset and can be provided with a resistive pullup, nominally
18–22 kΩ, if undesirable spurious writes are caused when these outputs go low.
Figure 23. Timing for RESET
30
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
interrupt response timing
The following table defines the timing parameters for the INT signals.
timing for INT3–INT0 response (see Figure 24)
NO
NO.
50
tsu(INT-H1L)
tw(INT)
Setup time, INT3–INT0 before H1 low
’C31-40
’LC31-40
MIN
MIN
MAX
13
51
Pulse duration, interrupt to ensure only one interrupt
† P = tc(H)
* This parameter is not production tested.
P
MAX
’C31-50
MIN
15
2P†*
P
MAX
11
2P†*
P
UNIT
ns
2P†*
ns
The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The
SMJ320C3x interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1.
Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA
respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held
to:
D
D
A minimum of one H1 falling edge
No more than two H1 falling edges
The SMJ320C3x can accept an interrupt from the same source every two H1 clock cycles.
If the specified timings are met, the exact sequence shown in Figure 24 occurs; otherwise, an additional delay
of one clock cycle is possible.
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
timing parameters for INT3–INT0 response (continued)
Reset or
Interrupt
Vector Read
Fetch First
Instruction of
Service
Routine
H3
H1
50
INT3 – INT0
Pin
51
INT3 – INT0
Flag
ADDR
Vector Address
First Instruction Address
Data
Figure 24. Timing for INT3–INT0 Response
32
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.
timing for IACK (see Note 5 and Figure 25)
’C31-40
’LC31-40
NO.
MIN
52
53
td(H1H-IACKL)
td(H1H-IACKH)
’C31-50
MAX
MIN
UNIT
MAX
Delay time, H1 high to IACK low
9
7
ns
Delay time, H1 high to IACK high
9
7
ns
NOTE 5: IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle
(H1 rising) of the read phase of the IACK instruction. Because of pipeline conflicts, IACK remains low for one cycle even if the decode
phase of the IACK instruction is extended.
Fetch IACK
Instruction
Decode IACK
Instruction
IACK Data
Read
H3
H1
52
53
IACK
ADDR
Data
Figure 25. Timing for IACK
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
serial-port timing for SMJ320C31-40 and SMJ320LC31-40 (see Figure 26 and Figure 27)
’C31-40
’LC31-40
NO.
MIN
54
td(H1H-SCK)
Delay time, H1 high to internal CLKX/R
55
tc(SCK)
(SCK)
Cycle time
time, CLKX/R
56
tw(SCK)
(SCK)
Pulse duration
duration, CLKX/R high/low
57
tr(SCK)
tf(SCK)
Rise time, CLKX/R
58
13
CLKX/R ext
CLKX/R int
CLKX/R ext
CLKX/R int
tc(H)x2.6
tc(H)x2
tc(H)+10
[tc(SCK)/2]–5
Fall time, CLKX/R
tc(H)x232
[tc(SCK)/2]+5
7
7
CLKX ext
30
CLKX int
17
ns
ns
ns
ns
ns
59
td(C
d(C-DX)
DX)
Delay time,
time CLKX to DX valid
60
tsu(DR-CLKRL)
(DR CLKRL)
Setup time,
time DR before CLKR low
61
th(CLKRL
DR)
h(CLKRL-DR)
Hold time
time, DR from CLKR low
62
td(C
FSX)
d(C-FSX)
Delay time
time, CLKX to internal FSX high/low
63
tsu(FSR-CLKRL)
(FSR CLKRL)
Setup time,
time FSR before CLKR low
64
th(SCKL
h(SCKL-FS)
FS)
Hold time,
time FSX/R input from CLKX/R low
65
tsu(FSX-C)
(FSX C)
Setup time,
time external FSX before CLKX
66
td(CH
DX)V
d(CH-DX)V
Delay
y time,, CLKX to first DX bit,, FSX
precedes CLKX high
67
td(FSX-DX)V
Delay time, FSX to first DX bit, CLKX precedes FSX
30*
ns
td(CH-DXZ)
Delay time, CLKX high to DX high impedance following last data
bit
17*
ns
68
CLKR ext
9
CLKR int
21
CLKR ext
9
CLKR int
0
POST OFFICE BOX 1443
ns
27
CLKX int
15
CLKR ext
9
CLKR int
9
CLKX/R ext
9
CLKX/R int
0
CLKX ext
CLKX int
–[tc(H)–8]*
[tc(H)–21]*
ns
ns
ns
[tc(SCK)/2]–10*
tc(SCK)/2*
CLKX ext
30*
CLKX int
18*
• HOUSTON, TEXAS 77251–1443
ns
ns
CLKX ext
* This parameter is not production tested.
34
UNIT
MAX
ns
ns
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
serial-port timing for SMJ320C31-50 (see Figure 26 and Figure 27)
’C31-50
NO
NO.
54
MIN
td(H1H-SCK)
Delay time, H1 high to internal CLKX/R
55
tc(SCK)
(SCK)
Cycle time
time, CLKX/R
56
tw(SCK)
(SCK)
Pulse duration
duration, CLKX/R high/low
57
tr(SCK)
tf(SCK)
Rise time, CLKX/R
58
MAX
10
CLKX/R ext
CLKX/R int
CLKX/R ext
CLKX/R int
tc(H)x2.6
tc(H)x2
tc(H)+10
[tc(SCK)/2]–5
Fall time, CLKX/R
tc(H)x232
[tc(SCK)/2]+5
6
6
CLKX ext
24
CLKX int
16
UNIT
ns
ns
ns
ns
ns
59
td(C
d(C-DX)
DX)
Delay time,
time CLKX to DX valid
60
tsu(DR-CLKRL)
(DR CLKRL)
Setup time,
time DR before CLKR low
61
th(CLKRL
h(CLKRL-DR)
DR)
Hold time
time, DR from CLKR low
62
td(C
d(C-FSX)
FSX)
Delay time
time, CLKX to internal FSX high/low
63
tsu(FSR-CLKRL)
(FSR CLKRL)
time FSR before CLKR low
Setup time,
64
th(SCKL
h(SCKL-FS)
FS)
Hold time,
time FSX/R input from CLKX/R low
65
tsu(FSX-C)
(FSX C)
Setup time,
time external FSX before CLKX
66
td(CH
DX)V
d(CH-DX)V
Delay
y time,, CLKX to first DX bit,, FSX
precedes CLKX high
67
td(FSX-DX)V
Delay time, FSX to first DX bit, CLKX precedes FSX
24*
ns
68
td(CH-DXZ)
Delay time, CLKX high to DX high impedance following last
data bit
14*
ns
CLKR ext
9
CLKR int
17
CLKR ext
7
CLKR int
0
ns
ns
CLKX ext
22
CLKX int
15
CLKR ext
7
CLKR int
7
CLKX/R ext
7
CLKX/R int
0
CLKX ext
CLKX int
– [tc(H) – 8]*
– [tc(H) – 21]*
ns
ns
ns
ns
[tc(SCK)/2] – 10*
tc(SCK)/2*
CLKX ext
24*
CLKX int
14*
ns
ns
* This parameter is not production tested.
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
data-rate timing modes
Unless otherwise indicated, the data-rate timings shown in Figure 26 and Figure 27 are valid for all serial-port
modes, including handshake. For a functional description of serial-port operation, see subsection 8.2.12 of the
TMS320C3x User’s Guide (literature number SPRU031).
55
54
H1
54
56
56
CLKX/R
58
57
66
61
Bit n-1
DX
68
59
Bit n-2
Bit 0
60
DR
Bit n-1
Bit n-2
FSR
63
62
62
FSX(INT)
64
FSX(EXT)
64
65
NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
Figure 26. Timing for Fixed Data-Rate Mode
36
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
data-rate timing modes (continued)
CLKX/R
62
FSX(INT)
67
65
FSX(EXT)
59
68
66
Bit n-1
64
DX
Bit n-2
Bit n-3
Bit 0
FSR
63
Bit n-1
DR
Bit n-2
Bit n-3
60
61
NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed
data-rate mode.
Figure 27. Timing for Variable Data-Rate Mode
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
HOLD timing
HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 27 occurs; otherwise, an additional delay of one clock cycle is
possible.
The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device
comes out of hold and prevents future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a
read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus
allowing the processor to continue until a second write is encountered.
timing for HOLD/HOLDA (see Figure 28)
NO
NO.
69
70
71
72
73
tsu(HOLD-H1L)
tv(H1L-HOLDA)
tw(HOLD)†
Setup time, HOLD before H1 low
tw(HOLDA)
td(H1L-SH)H
Pulse duration, HOLDA low
’C31-40
’LC31-40
’C31-50
MIN
MIN
MIN
13
0†
Valid time, HOLDA after H1 low
Pulse duration, HOLD low
MAX
MAX
13
9
2tc(H)
tcH–5*
0*
MAX
10
9
2tc(H)
tcH–5*
0*
UNIT
ns
7
2tc(H)
32*
ns
ns
ns
Delay time, H1 low to STRB high for a HOLD
0*
9
0*
9
0*
7
ns
0*
9*
0*
9*
0*
7*
ns
74
tdis(H1L-S)
Disable time, H1 low to STRB to the
high-impedance state
75
ten(H1L-S)
Enable time, H1 low to STRB enabled (active)
0*
9
0*
9
0*
7
ns
76
tdis(H1L-RW)
Disable time, H1 low to R/W to the
high-impedance state
0*
9*
0*
9*
0*
8*
ns
77
ten(H1L-RW)
Enable time, H1 low to R/W enabled (active)
0*
9
0*
9
0*
7
ns
78
tdis(H1L-A)
Disable time, H1 low to address to the
high-impedance state
0*
9*
0*
10*
0*
8*
ns
79
ten(H1L-A)
Enable time, H1 low to address enabled (valid)
0*
13
0*
13
0*
10
ns
tdis(H1H-D)
Disable time, H1 high to data to the
high-impedance state
0*
12*
0*
9*
0*
10*
ns
80
† HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown
in Figure 28 occurs; otherwise, an additional delay of one clock cycle is possible.
* This parameter is not production tested.
38
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
HOLD timing (continued)
H3
H1
69
69
71
HOLD
70
70
72
HOLDA
74
73
75
STRB
76
77
R/W
78
79
A
80
D
Write Data
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 28. Timing for HOLD/HOLDA
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
general-purpose I/O timing
Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The contents of the internal
control registers associated with each peripheral define the modes for these pins.
peripheral pin I/O timing
The table, timing parameters for peripheral pin general-purpose I/O, defines peripheral pin general-purpose I/O
timing parameters.
timing requirements for peripheral pin general-purpose I/O (see Note 6 and Figure 29)
’C31-33
NO.
MIN
81
82
tsu(GPIO-H1L)
th(H1L-GPIO)
Setup time, general-purpose input before H1 low
Hold time, general-purpose input after H1 low
MAX
’C31-40
’LC31-40
MIN
MAX
’C31-50
MIN
UNIT
MAX
12
10
9
ns
0
0
0
ns
83
td(H1H-GPIO)
Delay time, general-purpose output after H1 high
15
13
10
ns
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
H3
H1
82
81
83
83
Peripheral
Pin
(see Note A)
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 29. Timing for Peripheral Pin General-Purpose I/O
40
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
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changing the peripheral pin I/O modes
The following tables show the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and vice versa.
timing requirements for peripheral pin changing from general-purpose output to input mode
(see Note 6 and Figure 30)
’C31-40
’LC31-40
NO.
MIN
84
85
th(H1H)
tsu(GPIO-H1L)
Hold time, peripheral pin after H1 high
’C31-50
MAX
MIN
13
Setup time, peripheral pin before H1 low
9
UNIT
MAX
10
9
ns
ns
86
th(H1L-GPIO)
Hold time, peripheral pin after H1 low
0
0
ns
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Execution
of Store of
PeripheralControl
Register
Buffers Go
From
Output to
Input
Synchronizer Delay
Value on Pin
Seen in
PeripheralControl
Register
H3
H1
85
I/O
Control Bit
86
84
Peripheral
Pin
(see Note A)
Data Bit
Output
Data
Sampled
Data
Seen
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 30. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
timing for peripheral pin changing from general-purpose input to output mode (see Note 6 and
Figure 31)
’C31-40
’LC31-40
NO.
MIN
MAX
’C31-50
MIN
UNIT
MAX
87
td(H1H-GPIO) Delay time, H1 high to peripheral pin switching from input to output
13
10
ns
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Execution of Store
of PeripheralControl Register
H3
H1
I/O
Control
Bit
87
Peripheral
Pin
(see Note A)
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 31. Timing for Change of Peripheral Pin From General-Purpose Input to Output Mode
42
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• HOUSTON, TEXAS 77251–1443
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
timer pin timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers.
The following tables define the timing requirements for the timer pin.
timing for timer pin (see Figure 32 and Note 7)
’C31-40,
’LC31-40
’C31-50
NO.
MIN
88
Setup time, TCLK external before H1 low
89
tsu(TCLK-H1L)
th(H1L-TCLK)
90
td(H1H-TCLK)
Delay time, H1 high to TCLK internal valid
91
tc(TCLK)
(TCLK)
UNIT
MAX
10
Hold time, TCLK external after H1 low
ns
0
ns
9
TCLK ext
Cycle time
time, TCLK
TCLK int
tc(H)×2.6
tc(H)×2
tc(H)×232*
ns
ns
tc(H)+10
ns
[tc(TCLK)/2]–15
[tc(TCLK)/2]+5
NOTE 7: Numbers 88 and 89 are applicable for a synchronous input clock. Timing parameters 91 and 92 are applicable for an asynchronous
input clock.
* This parameter is not production tested.
92
tw(TCLK)
(TCLK)
TCLK ext
Pulse duration
duration, TCLK high/low
TCLK int
H3
H1
89
90
88
Peripheral
Pin
(see Note A)
90
92
91
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 32. Timing for Timer Pin
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• HOUSTON, TEXAS 77251–1443
43
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
SHZ pin timing
The following table defines the timing parameter for the SHZ pin.
timing parameters for SHZ (see Figure 33)
’C31
’LC31
NO.
MIN
93
tdis(SHZ)
Disable time, SHZ low to all O, I/O pins disabled (high impedance)
† P = tc(CI)
* This parameter is not production tested.
H3
H1
SHZ
93
All I/O Pins
NOTE A: Enabling SHZ destroys SMJ320C3x register and memory contents.
Assert SHZ = 1 and reset the SMJ320C3x to restore it to a known
condition.
Figure 33. Timing for SHZ
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
0*
UNIT
MAX
2P†*
ns
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
part order information
TECHNOLOGY
POWER
SUPPLY
OPERATING
FREQUENCY
5962-9205803MXA
0.72-µm CMOS
5 V ± 5%
40 MHz
Ceramic 141-pin staggered PGA
DSCC SMD
SMJ320C31GFAM40
0.72-µm CMOS
5 V ± 5%
40 MHz
Ceramic 141-pin staggered PGA
QML
SM320C31GFAM40
0.72-µm CMOS
5 V ± 5%
40 MHz
Ceramic 141-pin staggered PGA
Std
DEVICE
PACKAGE TYPE
PROCESSING
LEVEL
5962-9205803MYA
0.72-µm CMOS
5 V ± 5%
40 MHz
Ceramic 132-pin quad flatpack with
nonconductive tie bar.
SMJ320C31HFGM40
0.72-µm CMOS
5 V ± 5%
40 MHz
Ceramic 132-lead quad flatpack with a
nonconductive tie bar
QML
SM320C31HFGM40
0.72-µm CMOS
5 V ± 5%
40 MHz
Ceramic 132-lead quad flatpack with a
nonconductive tie bar
Std
5962-9205803Q9A
0.72-µm CMOS
5 V ± 5%
40 MHz
C31–40 KGD (known good die)
SMJ320C31KGDM40B
0.72-µm CMOS
5 V ± 5%
40 MHz
C31–40 KGD (known good die)
QML
5962-9205804MXA
0.72-µm CMOS
5 V ± 5%
50 MHz
Ceramic 141-pin staggered PGA
DSCC SMD
SMJ320C31GFAM50
0.72-µm CMOS
5 V ± 5%
50 MHz
Ceramic 141-pin staggered PGA
QML
SM320C31GFAM50
0.72-µm CMOS
5 V ± 5%
50 MHz
Ceramic 141-pin staggered PGA
Std
DSCC SMD
DSCC SMD
DSCC SMD
5962-9205804MYA
0.72-µm CMOS
5 V ± 5%
50 MHz
Ceramic 132-pin quad flatpack with
nonconductive tie bar.
SMJ320C31HFGM50
0.72-µm CMOS
5 V ± 5%
50 MHz
Ceramic 132-lead quad flatpack with
nonconductive tie bar
QML
SM320C31HFGM50
0.72-µm CMOS
5 V ± 5%
50 MHz
Ceramic 132-lead quad flatpack with
nonconductive tie bar
Std
5962-9760601NXB
0.72-µm CMOS
3.3 V ± 5%
40 MHz
Plastic 132-lead good flatpack
SMQ320LC31PQM40
0.72-µm CMOS
3.3 V ± 5%
40 MHz
Plastic 132-lead good flatpack
5962-9760601Q9A
0.72-µm CMOS
3.3 V ± 5%
40 MHz
LC31–40 KGD (known good die)
DSCC SMD
SMJ320LC31KGDM40B
0.72-µm CMOS
3.3 V ± 5%
40 MHz
LC31–40 KGD (known good die)
QML
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DSCC SMD
QML
45
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
part order information (continued)
SMJ
PREFIX
SMJ =
SM =
SMQ =
320
(L)
C
31
GFA
M
50
SPEED RANGE
40 = 40 MHz
50 = 50 MHz
MIL-PRF-38535 (QML)
Standard Processing
Plastic (QML)
TEMPERATURE RANGE
M = – 55°C to 125°C
L =
0°C to 70°C
DEVICE FAMILY
320 = SMJ320 Family
PACKAGE TYPE
GFA = 141-Pin Ceramic Staggered Pin Grid
Array Ceramic Package
HFG = 132-Pin Ceramic Quad Flatpack with a
nonconductive tie bar
PQ
= 132-lead Plastic Quad Flatpack
TA
= 132-lead TAB frame with
polyimide encapsulant
TB
= 132-lead TAB frame, bare-die
option
KGD = Known Good Die
TECHNOLOGY
L = Low Voltage
(3.3–V option)
TECHNOLOGY
C = CMOS
DEVICE
31 = ’320C31 or ’320LC31
Figure 34. Device Nomenclature
46
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
SMJ320C31 (Rev. 6) Inner Lead Bond Information for TAB
Die Designator
132
Pad Number One
(Origin)
Die Side Number 4
100
99
1
Die Side Number 3
8051.8 µm
(317 mils)
XXXX
Die Side Number 1
33
67
34
Die Side Number 2
7518.4 µm
(296 mils)
66
Figure 35. Die Numbering Format
(See Table 1)
The inner lead bond (ILB) pitch for the TAB leadframe is the same as the die bond pad pitch. Table 1 provides
a reference for the following:
A.
The TAB lead numbers. The TAB lead numbers are the same as the die bond pad numbers.
B.
The ’C31 signal identities in relation to the pad numbers
C.
Signal functions that fan out to more than one test pad location. (There are 132 bond pad locations,
132 TAB leads, and 244 test pad locations.)
D.
The ’C31 X-,Y-coordinates, where bond pad 1 serves as the origin, (0,0)
E.
The ILB pitch for the TAB leadframe
In addition, the following notes are significant:
F.
X-,Y-coordinate data is in microns.
G.
Coordinate origin is at (0,0) (center of bond pad 1).
H.
Average pitch is 202 µm (7.95 mils).
I.
The active silicon dimensions are 7889,00 µm × 7353,25 µm (311.00 mils × 289.00 mils).
J.
The die size is approximately 7518,40 µm × 8051,80 µm (317.00 mils × 296.00 mils).
K.
Distance from diced silicon to polyimide support ring is approximately 635.00 µm (25 mils).
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
Table 1. Die Pad/TAB Lead Information : rev 6.1 (0,72 µm)
DIE SIDE #1
48
C31 DIE BOND PAD
LOCATIONS
DIE/TAB BOND PAD
IDENTITY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
A9
DVSS
A8
A7
A6
A5
AVDD
A4
A3
A2
A1
A0
CVSS
D31
VDDL
VDDL
D30
VSSL
VSSL
DVSS
D29
D28
DVDD
D27
IVSS
D26
D25
D24
D23
D22
D21
DVDD
D20
X-COORDINATE OF
THE DIE BOND PAD
(mm)
Y-COORDINATE OF
THE DIE BOND PAD
(mm)
0.00
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
0.00
– 224.46
– 426.24
– 650.70
– 875.16
– 1099.62
– 1302.48
– 1504.26
– 1728.72
– 1953.18
– 2177.64
– 2402.10
– 2604.96
– 2828.34
– 3100.32
– 3262.68
– 3463.20
– 3670.38
– 3832.74
– 4011.66
– 4256.64
– 4481.10
– 4669.56
– 4950.54
– 5153.40
– 5333.58
– 5536.44
– 5739.30
– 5942.16
– 6145.02
– 6347.88
– 6522.48
– 6695.46
PITCH OF LEAD
(#,# REFERENCES
WHICH DIE BONDS)
(mm)
224.46 (1, 2)
201.78 (2, 3)
224.46 (3, 4)
224.46 (4, 5)
224.46 (5, 6)
202.86 (6, 7)
201.78 (7, 8)
224.46 (8, 9)
224.46 (9, 10)
224.46 (10, 11)
224.46 (11, 12)
202.86 (12, 13)
223.38 (13, 14)
271.98 (14, 15)
162.36 (15, 16)
200.52 (16, 17)
207.18 (17, 18)
162.36 (18, 19)
178.92 (19, 20)
244.98 (20, 21)
224.46 (21, 22)
188.46 (22, 23)
280.98 (23, 24)
202.86 (24, 25)
180.18 (25, 26)
202.86 (26, 27)
202.86 (27, 28)
202.86 (28, 29)
202.86 (29, 30)
202.86 (30, 31)
174.60 (31, 32)
172.98 (32, 33)
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
Table 1. Die Pad/TAB Lead Information : rev 6.1 (0,72 µm) (continued)
DIE SIDE #2
C31 DIE BOND PAD
LOCATIONS
DIE/TAB BOND PAD
IDENTITY
X-COORDINATE OF
THE DIE BOND PAD
(mm)
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
DVSS
D19
D18
D17
D16
D15
CVSS
D14
DVDD
D13
IVSS
D12
D11
D10
VDDL
VDDL
D9
D8
DVSS
VSSL
VSSL
D7
D6
DVDD
D5
D4
D3
D2
D1
D0
H1
H3
DVDD
396.72
577.44
780.30
990.36
1200.42
1410.48
1598.94
1786.32
1974.78
2162.16
2350.62
2538.00
2748.06
2958.12
3150.90
3313.26
3499.38
3709.44
3897.90
4068.00
4230.36
4416.48
4626.54
4815.00
5002.38
5212.44
5422.50
5632.56
5842.62
6052.68
6262.74
6472.80
6646.86
POST OFFICE BOX 1443
Y-COORDINATE OF
THE DIE BOND PAD
(mm)
–7219.80
• HOUSTON, TEXAS 77251–1443
PITCH OF LEAD
(#,# REFERENCES
WHICH DIE BONDS)
(mm)
180.72 (34, 35)
202.86 (35, 36)
210.06 (36, 37)
210.06 (37, 38)
210.06 (38, 39)
188.46 (39, 40)
187.38 (40, 41)
188.46 (41, 42)
187.38 (42, 43)
188.46 (43, 44)
187.38 (44, 45)
210.06 (45, 46)
210.06 (46, 47)
192.78 (47, 48)
162.36 (48, 49)
186.12 (49, 50)
210.06 (50, 51)
188.46 (51, 52)
170.10 (52, 53)
162.36 (53, 54)
186.12 (54, 55)
210.06 (55, 56)
188.46 (56, 57)
187.38 (57, 58)
210.06 (58, 59)
210.06 (59, 60)
210.06 (60, 61)
210.06 (61, 62)
210.06 (62, 63)
210.06 (63, 64)
210.06 (64, 65)
174.06 (65, 66)
49
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
Table 1. Die Pad/TAB Lead Information : rev 6.1 (0,72 µm) (continued)
DIE SIDE #3
50
C31 DIE BOND PAD
LOCATIONS
DIE/TAB BOND PAD
IDENTITY
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
DVSS
CVSS
IVSS
X2
X1
HOLDA
HOLD
CVDD
RDY
STRB
R/W
RESET
XF0
CVDD
XF1
IACK
INT0
DVSS
VSSL
INT1
VDDL
VDDL
INT2
INT3
DR0
CVSS
FSR0
CLKR0
CLKX0
IVSS
FSX0
PVDD
DX0
X-COORDINATE OF
THE DIE BOND PAD
(mm)
Y-COORDINATE OF
THE DIE BOND PAD
(mm)
7136.64
–6714.54
–6555.96
– 6402.42
– 6241.86
– 6072.30
– 5780.16
– 5574.60
– 5392.62
– 5116.14
– 4898.16
– 4673.70
– 4453.74
– 4235.76
– 4032.90
– 3809.52
– 3585.06
– 3365.10
– 3168.72
– 2988.54
– 2791.26
– 2590.56
– 2428.20
–2232.18
–2018.70
–1750.32
–1547.46
–1345.68
–1121.22
–896.76
–693.90
–492.12
–289.26
–15.48
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
PITCH OF LEAD
(#,# REFERENCES
WHICH DIE BONDS)
(mm)
158.58 (67, 68)
153.54 (68, 69)
160.56 (69, 70)
169.56 (70, 71)
292.14 (71, 72)
205.56 (72, 73)
181.98 (73, 74)
276.48 (74, 75)
217.98 (75, 76)
224.46 (76, 77)
219.96 (77, 78)
217.98 (78, 79)
202.86 (79, 80)
223.38 (80, 81)
224.46 (81, 82)
219.96 (82, 83)
196.38 (83, 84)
180.18 (84, 85)
197.28 (85, 86)
200.70 (86, 87)
162.36 (87, 88)
196.02 (88, 89)
213.48 (89, 90)
268.38 (90, 91)
202.86 (91, 92)
201.78 (92, 93)
224.46 (93, 94)
224.46 (94, 95)
202.86 (95, 96)
201.78 (96, 97)
202.86 (97, 98)
273.78 (98, 99)
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
Table 1. Die Pad/TAB Lead Information : rev 6.1 (0,72 µm) (continued)
DIE SIDE #4
C31 DIE BOND PAD
LOCATIONS
DIE/TAB BOND PAD
IDENTITY
X-COORDINATE OF
THE DIE BOND PAD
(mm)
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
VSUBS†
SHZ
DVSS
TCLK0
PVDD
TCLK1
EMU3
EMU0
EMU1
EMU2
MCMP
CVSS
A23
A22
VDDL
VDDL
A21
A20
VSSL
DVSS
A19
AVDD
A18
A17
A16
A15
A14
A13
A12
A11
AVDD
A10
CVSS
6705.00
6480.90
6298.92
6125.94
5951.88
5721.30
5439.24
5248.08
5063.40
4878.72
4694.04
4526.46
4324.68
4129.02
3862.62
3700.26
3421.98
3226.50
3052.44
2901.06
2728.08
2554.02
2381.04
2185.38
1989.72
1794.06
1598.40
1316.34
1120.68
925.02
750.96
577.98
403.92
Y-COORDINATE OF
THE DIE BOND PAD
(mm)
452.52
PITCH OF LEAD
(#,# REFERENCES
WHICH DIE BONDS)
(mm)
224.10 (100, 101)
181.98 (101, 102)
172.98 (102, 103)
174.06 (103, 104)
230.58 (104, 105)
282.06 (105, 106)
191.16 (106, 107)
184.68 (107, 108)
184.68 (108, 109)
184.68 (109, 110)
167.58 (110, 111)
201.78 (111, 112)
195.66 (112, 113)
266.40 (113, 114)
162.36 (114, 115)
278.28 (115, 116)
195.48 (116, 117)
174,06 (117, 118)
151.38 (118, 119)
172.98 (119, 120)
174.06 (120, 121)
172.98 (121, 122)
195.66 (122, 123)
195.66 (123, 124)
195.66 (124, 125)
195.66 (125, 126)
282.06 (126, 127)
195.66 (127, 128)
195.66 (128, 129)
174.06 (129, 130)
172.98 (130, 131)
174.06 (131, 132)
† VSUBS connects to die metallization. Tie this pin to clean ground.
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51
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
MECHANICAL DATA
GFA (S-CPGA-P141)
CERAMIC PIN GRID ARRAY PACKAGE
1.080 (27,43)
SQ
1.040 (26,42)
0.900 (22,86) TYP
0.100 (2,54) TYP
0.050 (1,27) TYP
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
2
1
0.026 (0,66)
0.006 (0,15)
4
3
6
5
8
7
10
9
12
11
16
14
13
15
18
17
19
0.145 (3,68)
0.105 (2,67)
0.034 (0,86) TYP
0.022 (0,56)
0.016 (0,41)
0.140 (3,56)
DIA TYP
0.120 (3,05)
0.048 (1,22) DIA TYP
4 Places
4040133/D 04/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-128
Thermal Resistance Characteristics
PARAMETER
52
°C/W
RθJA
4.3
RθJC
39.0
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
MECHANICAL DATA
HFG (S-CQFP-F132)
CERAMIC QUAD FLATPACK WITH TIE-BAR
0.960 (24,38)
TYP SQ
0.945 (24,00)
0.800 (20,32) TYP SQ
”A”
33
0.225 (5,72)
Tie Bar Width
0.175 (4,45)
1
34
132
1.210 (30,73)
TYP
2.015 (51,18)
1.990 (50,55)
100
2.025 (51,44) MAX
66
67
99
“C”
“B”
0.061 (1,55)
DIA TYP
0.059 (1,50)
132
(0,33)
0.013
0.006 (0,15)
Braze
0.040 (1,02)
0.030 (0,76)
0.025 (0,64)
DETAIL “A”
0.014 (0,36)
0.002 (0,05)
0.010 (0,25)
0.005 (0,12)
0.020 (0,51) MAX
0.116 (2,95) MAX
DETAIL “B”
DETAIL “C”
4040231-8 / F 04/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier.
This package can be hermetically sealed with a metal lid.
The terminals will be gold plated.
Thermal Resistance Characteristics†
PARAMETER
RθJA
°C/W
2.1
RθJC
44.3
† Falls within MIL-STD-1835 CMGA7-PN and CMGA19-PN and JEDEC MO-067AG and MO-066AG, respectively
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
53
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
PQ (S-PQFP-G***)
PLASTIC QUAD FLATPACK
100 LEAD SHOWN
13
1 100
89
14
88
0.012 (0,30)
0.008 (0,20)
0.006 (0,15) M
”D3” SQ
0.025 (0,635)
0.006 (0,16) NOM
64
38
0.150 (3,81)
0.130 (3,30)
39
63
Gage Plane
”D1” SQ
”D” SQ
0.010 (0,25)
0.020 (0,51) MIN
”D2” SQ
0°– 8°
0.046 (1,17)
0.036 (0,91)
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
LEADS ***
100
132
MAX
0.890 (22,61)
1.090 (27,69)
MIN
0.870 (22,10)
1.070 (27,18)
MAX
0.766 (19,46)
0.966 (24,54)
MIN
0.734 (18,64)
0.934 (23,72)
MAX
0.912 (23,16)
1.112 (28,25)
MIN
0.888 (22,56)
1.088 (27,64)
NOM
0.600 (15,24)
0.800 (20,32)
DIM
”D”
”D1”
”D2”
”D3”
4040045 / C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
54
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
MECHANICAL DATA
TA (35 OR 70 mm WITH PROTECTIVE FILM)
SMJ320C31 244-PIN TAB FRAME (PG6) SOCKET,
132 OLB/ILB 0,30-mm PITCH
0,31 × 32 = 9,62
0,29
9,58
100
132
99
1
0,31
9,62
× 32 =
0,29
9,58
0,31
9,62
× 32 =
0,29
9,58
Tab Leads Up
Die Face Up
67
33
34
2,25
(4 Places)
NOTES: A.
B.
C.
D.
E.
F.
66
0,31 × 32 = 9,62
0,29
9,58
14,00
(2 Places)
4081548/A 11/95
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
The OLB lead width is 0,120 ± 0,03 mm.
The ILB lead width is 0,0832 ± 0,015 mm.
The tape width is 35 mm.
The TA is encapsulated die with polyimide overcoat.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
55
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026B– APRIL 1998 – REVISED APRIL 1999
MECHANICAL DATA
TB (35 OR 70 mm WITHOUT PROTECTIVE FILM)
SMJ320C31 244-PIN TAB FRAME (PG6) SOCKET,
132 OLB/ILB 0,30-mm PITCH
0,31 × 32 = 9,62
0,29
9,58
100
132
99
1
0,31
9,62
× 32 =
0,29
9,58
0,31
9,62
× 32 =
0,29
9,58
Tab Leads Up
Die Face Up
67
33
34
2,25
(4 Places)
66
0,31 × 32 = 9,62
0,29
9,58
14,00
(2 Places)
4081549/A 11/95
NOTES: A.
B.
C.
D.
E.
F.
56
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
The OLB lead width is 0,120 ± 0,03 mm.
The ILB lead width is 0,0832 ± 0,015 mm.
The tape width is 35 mm.
The TB is bare die.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
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