TI PAL16R4

TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16L8-30M, TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A − FEBRUARY 1984 − REVISED DECEMBER 2010
D
D
D
DEVICE
I
INPUTS
3-STATE
O
OUTPUTS
REGISTERED
Q
OUTPUTS
I/O
PORTS
PAL16L8
10
2
0
6
4
PAL16R4
8
0
4 (3-state
buffers)
PAL16R6
8
0
6 (3-state
buffers)
2
8 (3-state
buffers)
0
PAL16R8
8
0
I
I
I
I
I
I
I
I
I
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
TIBPAL16L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
O
D
Propagation Delay
C Suffix . . . 25 ns Max
M Suffix . . . 30 ns Max
Functionally Equivalent, but Faster Than
PAL16L8A, PAL16R4A, PAL16R6A, and
PAL16R8A
Power-Up Clear on Registered Devices (All
Register Outputs Are Set High, but Voltage
Levels at the Output Pins Go Low)
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
Dependable Texas Instruments Quality and
Reliability
TIBPAL16L8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J OR W PACKAGE
(TOP VIEW)
I
I
I
VCC
D High-Performance Operation:
I
I
I
I
I
3 2
1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
I/O
I/O
I/O
I/O
I/O
I
GND
I
O
I/O
description
4
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMPACT™ circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for further
reduction in board space.
The TIBPAL16’ C series is characterized from 0°C
to 75°C. The TIBPAL16’ M series is characterized
for operation over the full military temperature
range of −55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IMPACT is a trademark of Texas Instruments.
PAL is a registered trademark of Advanced Micro Devices Inc.
Copyright © 2010, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
15
7
14
8
13
9
12
10
11
TIBPAL16R6’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J OR W PACKAGE
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
TIBPAL16R8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J OR W PACKAGE
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
GND
2
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
Q
Q
Q
Q
Q
Q
Q
Q
OE
POST OFFICE BOX 655303
I/O
6
5
17
6
16
7
15
8
14
9 10 11 12 13
I/O
Q
Q
Q
Q
TIBPAL16R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
I
I
I
4
3 2
I/O
16
1 20 19
18
1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
Q
Q
Q
Q
Q
TIBPAL16R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
I
I
I
4
3 2
Q
5
3 2
OE
I/O
I/O
17
4
OE
I/O
Q
4
I
I
I
I
I
1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
• DALLAS, TEXAS 75265
OE
Q
Q
18
I
I
CLK
VCC
3
VCC
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
I
GND
19
I
I
CLK
VCC
20
2
I
GND
1
I
I
CLK
VCC
CLK
I
I
I
I
I
I
I
I
GND
TIBPAL16R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
GND
TIBPAL16R4’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J OR W PACKAGE
(TOP VIEW)
Q
Q
Q
Q
Q
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
functional block diagrams (positive logic)
TIBPAL16L8’
&
32 × 64
16 ×
10
I
16
6
16
EN ≥ 1
7
O
7
O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
7
I/O
6
TIBPAL16R4’
OE
CLK
EN 2
C1
&
32 × 64
I
16 ×
8
≥1
8
I=1 2
Q
1D
8
Q
8
Q
8
Q
16
4
4
16
EN ≥ 1
7
I/O
7
I/O
7
I/O
7
I/O
4
4
denotes fused inputs
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
functional block diagrams (positive logic)
TIBPAL16R6’
OE
CLK
EN 2
C1
&
32 × 64
I
16 ×
8
≥1
8
I=1 2
Q
1D
8
Q
8
Q
8
Q
8
Q
8
Q
16
6
2
16
EN ≥ 1
7
I/O
I/O
7
2
6
TIBPAL16R8’
OE
CLK
EN 2
C1
&
32 × 64
I
16 ×
8
8
8
≥1
I=1 2
8
Q
8
Q
8
Q
8
Q
8
Q
8
Q
8
Q
16
16
8
denotes fused inputs
4
Q
1D
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
logic diagram (positive logic)
I
1
First
Fuse
Numbers
I
I
I
I
I
I
I
I
2
3
4
5
6
7
8
9
Increment
0
4
8
12
16
20
24
28
0
32
64
96
128
160
192
224
31
19
256
288
320
352
384
416
448
480
18
512
544
576
608
640
672
704
736
17
768
800
832
864
896
928
960
992
16
1024
1056
1088
1120
1152
1184
1216
1248
15
1280
1312
1344
1376
1408
1440
1472
1504
14
1536
1568
1600
1632
1664
1696
1728
1760
13
1792
1824
1856
1888
1920
1952
1984
2016
12
11
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
logic diagram (positive logic)
CLK
1
First
Fuse
Numbers
I
I
I
I
I
I
I
I
2
3
4
5
6
7
8
9
Increment
0
4
8
12
16
20
24
31
19
256
288
320
352
384
416
448
480
18
512
544
576
608
640
672
704
736
I=1
1D
768
800
832
864
896
928
960
992
I=1
1D
1024
1056
1088
1120
1152
1184
1216
1248
I=1
1D
1280
1312
1344
1376
1408
1440
1472
1504
I=1
1D
17
I/O
I/O
Q
C1
16
Q
C1
15
Q
C1
14
Q
C1
1536
1568
1600
1632
1664
1696
1728
1760
13
1792
1824
1856
1888
1920
1952
1984
2016
12
11
Fuse number = First fuse number + Increment
6
28
0
32
64
96
128
160
192
224
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
I/O
I/O
OE
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
logic diagram (positive logic)
CLK
1
First
Fuse
Numbers
I
I
I
I
I
I
I
I
2
3
4
5
6
7
8
9
Increment
0
4
8
12
16
20
24
28
31
0
32
64
96
128
160
192
224
19
256
288
320
352
384
416
448
480
I=1
1D
512
544
576
608
640
672
704
736
I=1
1D
768
800
832
864
896
928
960
992
I=1
1D
1024
1056
1088
1120
1152
1184
1216
1248
I=1
1D
1280
1312
1344
1376
1408
1440
1472
1504
I=1
1D
1536
1568
1600
1632
1664
1696
1728
1760
I=1
1D
18
I/O
Q
C1
17
Q
C1
16
Q
C1
15
Q
C1
14
Q
C1
13
Q
C1
1792
1824
1856
1888
1920
1952
1984
2016
12
11
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
I/O
OE
7
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
logic diagram (positive logic)
CLK
1
First
Fuse
Numbers
I
I
I
I
I
I
I
I
2
3
4
5
6
7
8
9
Increment
0
4
8
12
16
20
24
31
I=1
1D
256
288
320
352
384
416
448
480
I=1
1D
512
544
576
608
640
672
704
736
I=1
1D
768
800
832
864
896
928
960
992
I=1
1D
1024
1056
1088
1120
1152
1184
1216
1248
I=1
1D
1280
1312
1344
1376
1408
1440
1472
1504
I=1
1D
1536
1568
1600
1632
1664
1696
1728
1760
I=1
1D
1792
1824
1856
1888
1920
1952
1984
2016
I=1
1D
19
Q
C1
18
Q
C1
17
Q
C1
16
Q
C1
15
Q
C1
14
Q
C1
13
Q
C1
12
Q
C1
11
Fuse number = First fuse number + Increment
8
28
0
32
64
96
128
160
192
224
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
OE
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
NOTE 1: These ratings apply, except for programming pins, during a programming cycle.
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
5.5
V
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
V
IOH
High-level output current
−3.2
mA
IOL
Low-level output current
24
mA
fclock
Clock frequency
30
MHz
2
0
High
10
Low
15
tw
Pulse duration,
duration clock (see Note 2)
ns
tsu
Setup time, input or feedback before clock↑
20
ns
th
Hold time, input or feedback after clock↑
0
ns
TA
Operating free-air temperature
0
25
75
°C
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are
for clock high or low only, but not for both simultaneously.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
TYP†
2.4
3.3
MAX
UNIT
−1.5
V
VIK
VCC = 4.75 V,
II = −18 mA
VOH
VCC = 4.75 V,
IOH = −3.2 mA
VOL
VCC = 4.75 V,
IOL = 24 mA
VCC = 5
5.25
25 V
V,
VO = 2
2.7
7V
VCC = 5
5.25
25 V
V,
VO = 0
0.4
4V
II
VCC = 5.25 V,
VI = 5.5 V
IIH
VCC = 5.25 V,
VI = 2.7 V
20
μA
IIL
VCC = 5.25 V,
VI = 0.4 V
−0.25
mA
IO‡
VCC = 5.25 V,
VO = 2.25 V
−125
mA
ICC
VCC = 5.25 V,
VI = 0,
100
mA
IOZH
IOZL
Outputs
I/O ports
Outputs
I/O ports
0.35
V
0.5
20
100
−20
−250
0.1
−30
Outputs open
75
V
μA
A
μA
A
mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one-half of the short-circuit output current, I .
OS
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
tpd
I, I/O
O, I/O
tpd
CLK↑
Q
ten
OE↓
Q
tdis
OE↑
Q
ten
I, I/O
tdis
I, I/O
PARAMETER
TYP†
MAX
15
25
ns
10
15
ns
15
20
ns
10
20
ns
O, I/O
14
25
ns
O, I/O
13
25
ns
TEST CONDITIONS
fmax
†
30
R1 = 500 Ω,
R2 = 500 Ω,
See Figure 3
All typical values are at VCC = 5 V, TA = 25°C.
10
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MHz
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
NOTE 1: These ratings apply, except for programming pins, during a programming cycle.
recommended operating conditions
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
5.5
V
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
V
IOH
High-level output current
−2
mA
IOL
Low-level output current
12
mA
fclock
Clock frequency
25
MHz
2
0
tw
Pulse duration,
duration clock (see Note 2)
tsu
Setup time, input or feedback before clock↑
th
Hold time, input or feedback after clock↑
TA
Operating free-air temperature
High
15
Low
20
ns
25
ns
0
ns
−55
25
125
°C
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are
for clock high or low only, but not for both simultaneously.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
VCC = 4.5 V,
II = −18 mA
VOH
VCC = 4.5 V,
IOH = −2 mA
VOL
VCC = 4.5 V,
IOL = 12 mA
VCC = 5
5.5
5V
VO = 2
2.7
7V
VCC = 5
5.5
5 V,
V
VO = 0
0.4
4V
VCC = 5
5.5
5 V,
V
VI = 5
5.5
5V
VCC = 5.5 V,
VI = 2.7 V
IOZH
IOZL
II
Outputs
I/O ports
Outputs
I/O ports
Pin 1, 11
All others
MIN
TYP†
2.4
3.2
0.25
I/O ports
IIL
†
‡
V
V
0.4
−20
−250
0.2
0.1
V
μA
A
μA
A
mA
50
100
μA
20
VCC = 5
5.5
5V
V,
VI = 0
0.4
4V
IOS‡
VCC = 5.5 V,
VO = 0.5 V
ICC
VCC = 5.5 V,
VI = 0,
All others
−1.5
20
All others
I/O ports
UNIT
100
Pin 1, 11
IIH
MAX
−0.25
−0.2
−30
Outputs open
75
mA
−250
mA
105
mA
All typical values are at VCC = 5 V, TA = 25°C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to
avoid test-equipment degradation.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
tpd
I, I/O
O, I/O
tpd
CLK↑
Q
ten
OE↓
Q
tdis
OE↑
Q
ten
I, I/O
tdis
I, I/O
PARAMETER
TYP†
MAX
15
30
ns
10
20
ns
15
25
ns
10
25
ns
O, I/O
14
30
ns
O, I/O
13
30
ns
TEST CONDITIONS
fmax
†
25
R1 = 390 Ω,
R2 = 750 Ω,
See Figure 4
All typical values are at VCC = 5 V, TA = 25°C.
12
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MHz
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic also is available, upon request, from the nearest TI field sales office or local authorized TI
distributor, by calling Texas Instruments at +1 (972) 644−5580, or by visiting the TI Semiconductor Home Page
at www.ti.com/sc.
preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With VCC at 5 V and Pin 1 at VIL, raise Pin 11 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the
voltage level at the output pin.
VIHH
Pin 11
td
tsu
tw
VIL
td
VIH
Pin 1
VIL
Registered I/O
Input
VIH
VIL
Output
VOH
VOL
NOTE 3: td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 V
Figure 1. Preload Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
power-up reset (see Figure 2)
Following power up, all registers are set high. This feature provides extra flexibility to the system designer and
is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important
that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until
all applicable input and feedback setup times are met.
VCC
5V
4V
tpd†
(600 ns TYP, 1000 ns MAX)
VOH
Active-Low
Registered Output
1.5 V
VOL
tsu‡
CLK
1.5 V
1.5 V
VIH
VIL
tw
†
‡
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
PARAMETER MEASUREMENT INFORMATION
7V
S1
R1
From Output
Under Test
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR 3-STATE OUTPUTS
3.5 V
Timing
Input
0.3 V
1.3 V
3.5 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
3.5 V
1.3 V
tdis
0.3 V
In-Phase
Output
tpd
1.3 V
1.3 V
tpd
tpd
Out-of-Phase
Output
(see Note D)
1.3 V
1.3 V
VOH
Waveform 1
S1 Closed
(see Note B)
VOL
VOH
VOL
1.3 V
tdis
ten
Waveform 2
S1 Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V
0.3 V
ten
1.3 V
tpd
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.3 V
0.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
Input
1.3 V
tw
th
tsu
Data
Input
3.5 V
High-Level
Pulse
1.3 V
≈3.5 V
VOL + 0.3 V
VOL
VOH
1.3 V
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf ≤ 2 ns, duty cycle = 50%
D. When measuring propagation delay times of 3-state outputs from low to high, switch S1 is closed.
When measuring propagation delay times of 3-state outputs from high to low, switch S1 is open.
E. Equivalent loads may be used for testing.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™ PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
PARAMETER MEASUREMENT INFORMATION
5V
S1
R1
From Output
Under Test
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR 3-STATE OUTPUTS
3V
Timing
Input
0
1.5 V
3V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
In-Phase
Output
1.5 V
tpd
tpd
Out-of-Phase
Output
(see Note D)
1.5 V
1.5 V
1.5 V
VOH
Waveform 1
S1 Closed
(see Note B)
VOL
VOH
VOL
tdis
1.5 V
tdis
ten
Waveform 2
S1 Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
0
ten
0
tpd
1.5 V
3V
Output
Control
(low-level
enabling)
3V
1.5 V
tpd
1.5 V
0
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
0
3V
Low-Level
Pulse
1.5 V
0
Input
1.5 V
tw
th
tsu
Data
Input
3V
High-Level
Pulse
1.5 V
≈3.3 V
VOL + 0.5 V
VOL
VOH
1.5 V
VOH − 0.5 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2 ns, duty cycle = 50%
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 4. Load Circuit and Voltage Waveforms
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
5962-85155052A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596285155052A
TIBPAL16
L8-30MFKB
5962-8515505RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8515505RA
TIBPAL16L8-30M
JB
5962-8515505SA
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-8515505SA
TIBPAL16L8-30M
WB
5962-85155062A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596285155062A
TIBPAL16
R8-30MFKB
5962-8515506RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8515506RA
TIBPAL16R8-30M
JB
5962-8515506SA
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-8515506SA
TIBPAL16R8-30M
WB
5962-85155072A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596285155072A
TIBPAL16
R6-30MFKB
5962-8515507RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8515507RA
TIBPAL16R6-30M
JB
5962-8515507SA
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-8515507SA
TIBPAL16R6-30M
WB
5962-85155082A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596285155082A
TIBPAL16
R4-30MFKB
5962-8515508RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8515508RA
TIBPAL16R4-30M
JB
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
25-Sep-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
5962-8515508SA
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-8515508SA
TIBPAL16R4-30M
WB
JM38510/50605BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
50605BRA
JM38510/50606BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
50606BRA
JM38510/50607BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
50607BRA
JM38510/50608BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
50608BRA
M38510/50605BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
50605BRA
M38510/50606BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
50606BRA
M38510/50607BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
50607BRA
M38510/50608BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
50608BRA
TIBPAL16L8-25CFN
ACTIVE
PLCC
FN
20
46
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
0 to 75
16L8-25
TIBPAL16L8-25C
N
TIBPAL16L8-25CJ
OBSOLETE
CDIP
J
20
TBD
Call TI
Call TI
TIBPAL16L8-25CN
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 75
TIBPAL16L8-30MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596285155052A
TIBPAL16
L8-30MFKB
TIBPAL16L8-30MJ
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
TIBPAL16L8-30M
J
TIBPAL16L8-30MJB
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8515505RA
TIBPAL16L8-30M
JB
TIBPAL16L8-30MWB
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-8515505SA
TIBPAL16L8-30M
WB
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
25-Sep-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
TIBPAL16R4-25CFN
ACTIVE
PLCC
FN
20
Eco Plan
Lead/Ball Finish
(2)
46
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
CU NIPDAU
Level-3-245C-168 HR
(4/5)
0 to 75
16R4-25
TIBPAL16R4-25C
N
TIBPAL16R4-25CJ
OBSOLETE
CDIP
J
20
TBD
Call TI
Call TI
TIBPAL16R4-25CN
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 75
TIBPAL16R4-30MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596285155082A
TIBPAL16
R4-30MFKB
TIBPAL16R4-30MJ
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
TIBPAL16R4-30M
J
TIBPAL16R4-30MJB
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8515508RA
TIBPAL16R4-30M
JB
TIBPAL16R4-30MWB
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-8515508SA
TIBPAL16R4-30M
WB
TIBPAL16R6-25CFN
ACTIVE
PLCC
FN
20
46
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
0 to 75
16R6-25
TIBPAL16R6-25CN
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 75
TIBPAL16R6-25C
N
TIBPAL16R6-30MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596285155072A
TIBPAL16
R6-30MFKB
TIBPAL16R6-30MJ
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
TIBPAL16R6-30M
J
TIBPAL16R6-30MJB
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8515507RA
TIBPAL16R6-30M
JB
TIBPAL16R6-30MWB
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-8515507SA
TIBPAL16R6-30M
WB
TIBPAL16R8-25CFN
ACTIVE
PLCC
FN
20
46
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-245C-168 HR
0 to 75
16R8-25
TIBPAL16R8-25CN
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 75
TIBPAL16R8-25C
N
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
25-Sep-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
TIBPAL16R8-30MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596285155062A
TIBPAL16
R8-30MFKB
TIBPAL16R8-30MJB
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8515506RA
TIBPAL16R8-30M
JB
TIBPAL16R8-30MWB
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-8515506SA
TIBPAL16R8-30M
WB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 4
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 5
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated