SCBS787 − NOVEMBER 2003 D Controlled Baseline D D D D D D D D D D D D D Latch-Up Performance Exceeds 500 mA Per − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Member of the Texas Instruments WidebusE Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Supports Unregulated Battery Operation Down To 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. D D JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Thin Shrink Small-Outline (DGG) Package DGG PACKAGE (TOP VIEW) 1OEAB 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2OEAB 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OEBA 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OEBA description/ordering information The SN74LVTH16652 is a 16-bit bus transceiver designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright 2003, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$( !,'&$% &!" $ %)(&&#$% )(! $-( $(!"% (.#% %$!'"($% %$#,#!, /#!!#$0 !,'&$ )!&(%%1 ,(% $ (&(%%#!+0 &+',( $(%$1 #++ )#!#"($(!% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCBS787 − NOVEMBER 2003 description/ordering information (continued) Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVTH16652. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 85°C TSSOP − DGG Tape and reel CLVTH16652IDGGREP LH16652EP † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCBS787 − NOVEMBER 2003 FUNCTION TABLE DATA I/O† INPUTS OPERATION OR FUNCTION OEAB OEBA CLKAB CLKBA SAB SBA A1−A8 B1−B8 L H H or L H or L X X Input Input Isolation L H ↑ ↑ X X Input H ↑ H or L X Input H H ↑ ↑ X X‡ Input Unspecified‡ Store A and B data X X Input Output Store A in both registers L X H or L ↑ X Unspecified‡ Input Hold A, store B L L ↑ ↑ X X X‡ Output Input Store B in both registers L L X X X L Output Input Real-time B data to A bus Store A, hold B L L X H or L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H H or L X H X Input Output Stored A data to B bus Output Stored A data to B bus and stored B data to A bus H L H or L H or L H H Output † The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CLKAB CLKBA SAB X X X SBA L ↑ X ↑ X ↑ ↑ X X X SBA X X X OEAB OEBA H L STORAGE FROM A, B, OR A AND B SAB L SBA X CLKAB CLKBA SAB SBA H or L H or L H H TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions 4 CLKBA X BUS A BUS A CLKAB CLKBA SAB CLKAB X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A OEAB OEBA X H L X L H BUS B OEAB OEBA H H BUS B OEAB OEBA L L BUS A BUS A BUS B SCBS787 − NOVEMBER 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCBS787 − NOVEMBER 2003 logic diagram (positive logic) 1OEBA 1OEAB 1CLKBA 1SBA 1CLKAB 1SAB 56 1 55 54 2 3 One of Eight Channels 1A1 1D C1 5 52 1B1 1D C1 To Seven Other Channels 2OEBA 2OEAB 2CLKBA 2SBA 2CLKAB 2SAB 29 28 30 31 27 26 One of Eight Channels 2A1 1D C1 15 42 1D 2B1 C1 To Seven Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCBS787 − NOVEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) MIN MAX 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 V Input voltage 5.5 V IOH IOL High-level output current −32 mA Low-level output current 64 mA ∆t/∆v Input transition rise or fall rate 10 ns/V ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature −40 High-level input voltage 2 Outputs enabled V V µs/V 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCBS787 − NOVEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT −1.2 V VIK VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = −18 mA IOH = −100 µA VOH VCC = 2.7 V, VCC = 3 V, IOH = −8 mA IOH = −32 mA IOL = 100 µA IOL = 24 mA 0.2 VCC = 2.7 V IOL = 16 mA IOL = 32 mA 0.4 IOL = 64 mA VI = 5.5 V 0.55 VOL VCC = 3 V Control inputs VCC = 0 or 3.6 V, VCC = 3.6 V, Ioff II(hold) A or B ports V 2 0.5 10 ±1 20 VCC = 3.6 V VI = VCC VI = 0 VCC = 0, VI or VO = 0 to 4.5 V VI = 0.8 V VCC = 3 V µA 1 −5 ±100 µA 75 VI = 2 V VI = 0 to 3.6 V VCC = 3.6 V§, V 0.5 VI = VCC or GND VI = 5.5 V II A or B ports‡ VCC−0.2 2.4 µA −75 ±500 IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE/OE = don’t care ± 100 µA IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE/OE = don’t care ±100 µA ICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high 0.19 Outputs low 5 Outputs disabled ∆ICC¶ VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 Cio mA 0.19 0.2 4 mA pF 10 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Unused pins at VCC or GND § This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) VCC = 3.3 ± 0.3 V MIN fclock tw Clock frequency MAX VCC = 2.7 V MIN 150 Pulse duration, CLK high or low 150 3.3 3.3 1.2 1.5 2 2.8 Setup time, A or B before CLKAB↑ or CLKBA↑ Data high tsu Hold time, CLKAB or CLKBA A or B after CLKAB↑ CLKBA↑ Data high 0.5 0 th Data low 0.5 0.5 Data low POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX MHz ns ns ns 7 SCBS787 − NOVEMBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) VCC = 2.7 V TYP† MAX 1.3 2.7 4.2 4.7 1.3 2.8 4.2 4.7 1 2.4 3.4 3.9 1 2.1 3.4 3.9 1 2.7 4.5 5.4 1 3 4.5 5.4 1 2.4 4.3 5.2 1 2.3 4.3 5.2 2 3.9 5.6 6.1 2 3.4 5.4 6.1 1.3 2.7 4.2 4.9 1.3 2.6 4.2 4.9 1.3 3.5 5.5 6.2 1.3 3.2 5.5 6.2 MIN 150 CLK B or A A or B B or A SAB or SBA B or A OEBA A OEBA A OEAB B OEAB B † All typical values are at VCC = 3.3 V, TA = 25°C. 8 VCC = 3.3 V ± 0.3 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN UNIT MAX 150 MHz ns ns ns ns ns ns ns SCBS787 − NOVEMBER 2003 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V Timing Input LOAD CIRCUIT 1.5 V 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1.5 V Output 1.5 V VOL tPHL 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPLZ 3V 1.5 V tPZH VOH Output Output Waveform 1 S1 at 6 V (see Note B) tPLH 1.5 V 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CLVTH16652IDGGREP ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04717-01XE ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF SN74LVTH16652-EP : • Catalog: SN74LVTH16652 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device CLVTH16652IDGGREP Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 15.6 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CLVTH16652IDGGREP TSSOP DGG 56 2000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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