SCBS772 − NOVEMBER 2003 D Controlled Baseline D D D D D D D D Bus Hold on Data Inputs Eliminates the − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Supports Unregulated Battery Operation Down to 2.7 V Ioff and Power-Up 3-State Support Hot Insertion D D Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) PW PACKAGE (TOP VIEW) LEBA OEBA A1 A2 A3 A4 A5 A6 A7 A8 CEAB GND † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CEBA B1 B2 B3 B4 B5 B6 B7 B8 LEAB OEAB description/ordering information This octal transceiver is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVTH543 contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register, to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA inputs. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 85°C TSSOP − PW Tape and reel SN74LVTH543IPWREP LH543EP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated ! " #$%! " &$'(#! )!% )$#!" # ! "&%##!" &% !*% !%" %+" "!$%!" "!)) ,!- )$#! &#%"". )%" ! %#%""(- #($)% !%"!. (( &%!%" POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCBS772 − NOVEMBER 2003 description/ordering information (continued) When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. FUNCTION TABLE† INPUTS OEAB A OUTPUT B X X X Z X H X Z L H L X L L L L B0‡ L L L L H CEAB LEAB H X H † A-to-B data flow is shown; B-to-A flow control is the same, except that it uses CEBA, LEBA, and OEBA. ‡ Output level before the indicated steady-state input conditions were established logic diagram (positive logic) OEBA CEBA LEBA OEAB CEAB LEAB A1 2 23 1 13 11 14 C1 3 1D C1 1D To Seven Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 22 B1 SCBS772 − NOVEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) MIN MAX 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 V Input voltage 5.5 V IOH IOL High-level output current −32 mA Low-level output current 64 mA ∆t /∆v Input transition rise or fall rate 10 ns/V ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature −40 High-level input voltage 2 Outputs enabled V V µs/V 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCBS772 − NOVEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT −1.2 V VIK VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = −18 mA IOH = −100 µA VOH VCC = 2.7 V, VCC = 3 V, IOH = −8 mA IOH = −32 mA IOL = 100 µA IOL = 24 mA 0.2 VCC = 2.7 V IOL = 16 mA IOL = 32 mA 0.4 VOL VCC = 3 V Control inputs Ioff II(hold) A or B ports V 2 0.5 VCC = 3.6 V, VCC = 0 or 3.6 V, 0.55 ±1 VI = 5.5 V VI = 5.5 V 10 VCC = 3.6 V VI = VCC VI = 0 1 VCC = 0, VI or VO = 0 to 4.5 V VI = 0.8 V VCC = 3 V VI = 2 V VI = 0 to 3.6 V VCC = 3.6 V§ IOZPU IOZPD VCC = 0 to 1.5 V, VO = 0.5 to 3 V, OE = don’t care VCC = 1.5 V to 0, VO = 0.5 to 3 V, OE = don’t care ICC VCC = 3.6 V, IO = 0, VI = VCC or GND 20 µA ±500 VI = 3 V or 0 VO = 3 V or 0 Cio ±100 µA ±100 µA 0.19 5 Outputs disabled Ci µA 75 −75 Outputs low VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND µA −5 ±100 Outputs high ∆ICC¶ V 0.5 IOL = 64 mA VI = VCC or GND II A or B ports‡ VCC−0.2 2.4 mA 0.19 0.2 4 pF pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Unused terminals are at VCC or GND. § This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. 4 9 mA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCBS772 − NOVEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V MIN tw tsu th Pulse duration, LEAB or LEBA low MAX VCC = 2.7 V MIN 3.3 3.3 0.4 0.4 1 1.5 A or B before LEAB or LEBA↑ Data high A or B before CEAB or CEBA↑ Data high 0.2 0.2 Data low 0.7 1.2 A or B after LEAB or LEBA↑ Data high 1.5 0.6 Data low 1.3 1.5 A or B after CEAB or CEBA↑ Data high 1.6 0.5 Data low 1.4 1.6 Setup time Hold time Data low UNIT MAX ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL LE A or B tPZH tPZL OE A or B tPHZ tPLZ OE A or B tPZH tPZL CE A or B tPHZ tPLZ CE A or B PARAMETER VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN TYP† MAX 1.3 2.5 3.7 4.3 1.3 2.5 3.7 4.3 1.3 2.9 4.7 5.9 1.3 2.9 4.7 5.9 1.1 2.9 4.9 6.2 1.1 3.2 4.9 6.2 2 3.4 5.3 5.9 2 3.7 5.3 5.9 1.3 3.2 5.3 6.8 1.3 3.5 5.3 6.8 2.3 3.8 5.4 5.9 2.3 3.9 5.4 5.6 MIN UNIT MAX ns ns ns ns ns ns † All typical values are at VCC = 3.3 V, TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCBS772 − NOVEMBER 2003 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPHL tPLH VOH 1.5 V Output 1.5 V VOL VOH Output 1.5 V Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 1.5 V VOL 1.5 V 0V tPLZ tPZL 3V 1.5 V Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ tPZH tPLH tPHL 2.7 V Output Control 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVTH543IPWREP ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04677-01XE ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF SN74LVTH543-EP : • Catalog: SN74LVTH543 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jul-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVTH543IPWREP Package Package Pins Type Drawing TSSOP PW 24 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.95 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jul-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVTH543IPWREP TSSOP PW 24 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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