User's Guide SLVU549 – December 2011 TPS7A1601EVM-046 This user’s guide describes operational use of theTPS7A1601EVM-046 evaluation module (EVM) as a reference design for engineering demonstration and evaluation of the TPS7A1601, low-dropout (LDO) linear regulator. Included in this user’s guide are setup instructions, a schematic diagram, layout and thermal guidelines, a bill of materials, and test results. 1 2 3 4 5 6 7 Contents Introduction .................................................................................................................. Setup ......................................................................................................................... 2.1 Input/Output Connectors and Jumper Descriptions ........................................................... 2.2 Equipment Setup ................................................................................................... Operation ..................................................................................................................... Test Results ................................................................................................................. 4.1 Turnon Sequence .................................................................................................. 4.2 Output Load Transient ............................................................................................. 4.3 Power Good ........................................................................................................ Thermal Guidelines and Layout Recommendations ................................................................... Board Layout ................................................................................................................ Schematic and Bill of Materials ........................................................................................... 7.1 Schematic ........................................................................................................... 7.2 Bill of Materials ..................................................................................................... 2 2 2 2 3 3 3 3 4 4 5 7 7 7 List of Figures 1 Turnon Sequence ........................................................................................................... 3 2 Load Step and Transient Response ...................................................................................... 4 3 Power Good Operation ..................................................................................................... 4 4 Top-Layer Silkscreen ....................................................................................................... 5 5 Top-Layer Routing .......................................................................................................... 6 6 Bottom-Layer Routing ...................................................................................................... 6 7 TPS7A1601EVM-046 Schematic ......................................................................................... 7 List of Tables 1 Thermal Resistance, θJA, and Maximum Power Dissipation........................................................... 5 2 TPS7A1601EVM-046 Bill of Materials ................................................................................... 7 PowerPAD is a trademark of Texas Instruments. SLVU549 – December 2011 Submit Documentation Feedback TPS7A1601EVM-046 Copyright © 2011, Texas Instruments Incorporated 1 Introduction 1 www.ti.com Introduction The Texas Instruments TPS7A1601EVM-046 evaluation module helps design engineers to evaluate the operation and performance of the TPS7A16xx family of linear regulators for use in their own circuit applications. This particular EVM configuration contains a single linear regulator with internal thermal and current-limit shutdowns. The TPS7A1601 also has enable (disable), PG (Power Good), and user-programmable PG circuitry in an extremely small DGN (MSOP-8) PowerPAD™ package. The regulator, including external components, is capable of delivering up to 100 mA to the load depending on the input/output power dissipation across the part. The TPS7A16xx does not require an input capacitor, and the output capacitor only needs to be ≥ 2.2 µF (effective minimum) for stability; however, for conservative design practice accounting for widely varying noise environments and dynamic line/load conditions, a 1-µF input capacitor and a 0.01-µF feedforward capacitor have been used in the design. 2 Setup This section describes the jumpers and connectors on the EVM as well as how to properly connect, set up, and use the TPS7A1601EVM. 2.1 Input/Output Connectors and Jumper Descriptions J1 – VIN 2.1.1 J1 is the input power supply voltage connector. Twist the positive input lead and ground return lead from the input power supply, and keep them as short as possible to minimize EMI transmission. Add additional bulk capacitance between J1 and J2 if the supply leads are greater than 6 inches. For example, an additional 47-µF electrolytic capacitor connected from J1 to ground can improve the transient response of the TPS7A1601, while eliminating unwanted ringing on the input due to long-wire connections. J2 – GND 2.1.2 J2 is the ground-return connector for the input power supply. J3 – GND 2.1.3 J3 is the output ground-return connector J4 – VOUT 2.1.4 J4 is the regulated output voltage connector. JP1 – EN 2.1.5 SP1 is the output enable. To enable the output, connect a jumper to short the ON pin 1 to the EN center pin 2. To disable the output, connect a jumper to short EN pin 2 to OFF pin 3. J5 – PG 2.1.6 J5 is Power Good. If a jumper is installed across J5, the PG signal is pulled up to Vout and the signal can be monitored via TP1 (test point 1). The user can also pull up the signals themselves by connecting directly to pin 1 of J5. The maximum pullup voltage that can be used on the PG pin is 5.5 V. 2.1.7 J6– Input Diode Bypass The EVM is populated with a 100-V, 300-mA protection diode on the input. This diode can be bypassed by connecting a jumper across J6. 2.2 Equipment Setup • 2 Turn off the input power supply after verifying that its output voltage is set to greater than 6 V (60 V maximum). Connect the positive voltage lead from input power supply to VIN at the J1 connector of the EVM. Connect the ground lead from the input power supply to GND at the J2 connector of the EVM. TPS7A1601EVM-046 Copyright © 2011, Texas Instruments Incorporated SLVU549 – December 2011 Submit Documentation Feedback Operation www.ti.com • • 3 Operation • • • 4 Connect a 0-A to 100-mA load between an OUT pin at connector J4, and a GND pin at connector J3. Disable the output by connecting the jumper on JP1 from the EN pin to the OFF pin. Turn on the input power supply. For initial operation, set the input power supply, VIN – J1, to 10 V Enable the output by reconnecting the jumper on JP1 from the EN pin to the ON pin. Vary the respective loads and VIN voltages as necessary for test purposes. Test Results This section provides typical performance waveforms for the TPS7A1601EVM-046 printed-circuit board. 4.1 Turnon Sequence Figure 1 shows the turnon/off characteristic where VIN is preset to 10 V, the output drives full load, and the EN turnon is stepped to 10 V (C2, red). The output soft start (C1, yellow) shows a monotonic rise time of approximately 60 ms. The output voltage start-up ramp is not load dependant. EN Vout Iout Vin Figure 1. Turnon Sequence 4.2 Output Load Transient Figure 2 shows the load transient response (OUT – C1, yellow) for a full-load step transient from 10 mA to 100 mA (C4, green). VIN is set at 10 V. SLVU549 – December 2011 Submit Documentation Feedback TPS7A1601EVM-046 Copyright © 2011, Texas Instruments Incorporated 3 Thermal Guidelines and Layout Recommendations www.ti.com Vout Iout Figure 2. Load Step and Transient Response 4.3 Power Good Figure 3 shows the operation of the Power Good (PG) output. Vin (6 V) is present and the chip is enabled (c1, gold) The PG output (C3, blue) goes HIGH approximately 1.5 ms after Vout (C2, red) goes into regulation. Vout PG Iout EN Figure 3. Power Good Operation 5 Thermal Guidelines and Layout Recommendations Thermal management is a key component of design for any power converter and is especially important when the power dissipation in the LDO regulator is high. Use the following formula to approximate the maximum power dissipation for the particular ambient temperature: TJ = TA + PD × θJA 4 TPS7A1601EVM-046 Copyright © 2011, Texas Instruments Incorporated SLVU549 – December 2011 Submit Documentation Feedback Board Layout www.ti.com Where TJ is the junction temperature, TA is the ambient temperature, PD is the power dissipation in the device (W), and θJA is the thermal resistance from junction to ambient. All temperatures are in degrees Celsius. The maximum silicon junction temperature, TJ, must not be allowed to exceed 150°C. The layout design must use copper trace and plane areas effectively, as thermal sinks, in order not to allow TJ to exceed the absolute maximum rating under all temperature conditions and voltage conditions across the part. The designer must consider carefully the thermal design of the PCB for optimal performance over temperature. For this EVM, Figure 5 shows that the PCB top GND plane has six, 6-mil, thermal via connections to the bottom-side copper GND plane to dissipate heat. The PCB is a two-layer board with 2-oz. copper on top and bottom layers. The DGN package drawing can be found at the Texas Instruments Web site in the product folder for the TPS7A16xx LDO linear regulator. Table 1 repeats information from the Dissipation Ratings Table of the TPS7A16xx data sheet for comparison with the thermal resistance, θJA, calculated for this EVM layout to show the wide variation in thermal resistances for given copper areas. The High-K value is determined using a standard JEDEC High-K (2s2p) board having dimensions of 3-inch x 3-inch with 1-oz internal power and ground planes and 2-oz copper traces on top and bottom of the board. Table 1. Thermal Resistance, θJA, and Maximum Power Dissipation Board Package θJA Max Dissipation without Derating (TA = 25°C) Max Dissipation without Derating (TA = 70°C) High-K DGN 55.09°C/W 1.8 mW 998 mW TPS7A1601EVM-046 DGN 38.89°C/W 2.57 W 1.41.W The thermal resistance for the TPS7A1601EVM-046, θJA, is the measured value for this particular layout scheme. The maximum power dissipation is proportional to the volume of copper volume connected to the package. 6 Board Layout Figure 4. Top-Layer Silkscreen SLVU549 – December 2011 Submit Documentation Feedback TPS7A1601EVM-046 Copyright © 2011, Texas Instruments Incorporated 5 Board Layout www.ti.com Figure 5. Top-Layer Routing Figure 6. Bottom-Layer Routing 6 TPS7A1601EVM-046 Copyright © 2011, Texas Instruments Incorporated SLVU549 – December 2011 Submit Documentation Feedback Schematic and Bill of Materials www.ti.com 7 Schematic and Bill of Materials 7.1 Schematic Figure 7. TPS7A1601EVM-046 Schematic 7.2 Bill of Materials Table 2. TPS7A1601EVM-046 Bill of Materials Count RefDes Value Description Size Part Number MFR 1 C1 1.0uF Capacitor, Ceramic, 100V, X7R, 10% C1206 STD STD 1 C2 0.001uF Capacitor, Ceramic,100V 603 STD STD 1 C3 0.01uF Capacitor, Ceramic, Low Inductance, 50V, X7R, 10% 603 STD STD 1 C4 10.0uF Capacitor, Ceramic, 50V, X7R, 10% 1210 STD STD 1 R1 3.16M Resistor, Chip, 1/16W, 1% 603 STD STD 1 R2 1.0M Resistor, Chip, 1/16W, 1% 603 STD STD 1 R3 100K Resistor, Chip, 1/16W, 1% 603 STD STD 1 D1 1N4148WS0 Diode, Small Signal, 300-mA, 100V SOD-323 1N4148WS Fairchild 2 J5, J8 PEC02SAAN Header, Male 2-pin, 100mil spacing 0.100 inch x 2 PEC02SAAN Sullins 4 J1–J4 PEC02SAAN Header, Male 2-pin, 100mil spacing 0.100 inch x 2 PEC02SAAN Sullins 1 JP1 PEC03SAAN Header, Male 3-pin, 100mil spacing 0.100 inch x 3 PEC03SAAN Sullins 1 U1 TPS7A1601DGN IC, 60 V, 5 µA Iq LDO, 100mA Linear Regulator HTSSOP TPS7A1601DGN TI 1 TP1 5000 Test Point, Red, Thru Hole Color Keyed 0.100 x 0.100 inch 5000 Keystone SLVU549 – December 2011 Submit Documentation Feedback TPS7A1601EVM-046 Copyright © 2011, Texas Instruments Incorporated 7 Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives. Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. 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TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. EVM Warnings and Restrictions It is important to operate this EVM within the input voltage range of 3 V to 60 V and the output voltage range of 1.2 V to20 V . Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 100° C. The EVM is designed to operate properly with certain components above 100° C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. 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