FEDL2215-01 1Semiconductor ML2215 This version: May 2001 Speech Synthesizer plus Music LSI with On-Chip 3 Mbit Mask ROM GENERAL DESCRIPTION The ML2215 is an ADPCM-based Speech Synthesizer LSI with on-chip 3 Mbit Mask ROM for storing multiple speech data. In addition, the LSI has a built-in Music Generator circuit that can generate music by automatically acquiring user-defined musical notes data from the ROM. The ML2215 contains a 12-bit D/A Converter and Low Pass Filter, and enables a user to readily built a message and music playback sub-system by simply adding an external speaker and driving amplifier. FEATURES • On-Chip 3 Mbit Mask ROM • Serial Interface: User-selectable Mask options for 2-pin or 3-pin interfacing • 3 Speech Synthesis Algorithms for user selection 4-bit ADPCM/8-bit OKI Non-Linear PCM/8-bit PCM/Music • Sampling Frequency (At 4.096 MHz External Clock) 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.7 kHz, 12.8 kHz, 16.0 kHz • Built-in Music Generator function User-definable 31 musical scales, 60 musical notes, and 30 tempos • User-defined Phrases up to 247 phrases, including music. • Built-in 12-bit D/A Converter • Built-in Low Pass Filter • Driver for piezo-speaker (MD pin) • External Clock: Frequency can be selected as Mask option 4.096 MHz, 8.192 MHz, 16.384 MHz • Power Supply Voltage: 2.4 to 5.5 V • Package: 20-pin plastic SSOP (SSOP20-P-44-0.65-K) (Product name: ML2215-xxxMB) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: ML2215-xxxMA) 1/26 FEDL2215-01 1Semiconductor ML2215 BLOCK DIAGRAM Address Controller 19 bit Multiplexer Phrase Address Latch 3 Mbit ROM ADPCM Synthesizer 19 bit Address Counter ST SD SI BUSY I/O Interface MELODY NAR CLK PCM Synthesizer 12 bit DAC VREF Timing Controller LPF RESET VDD GND MD AOUT 2/26 FEDL2215-01 1Semiconductor ML2215 PIN CONFIGURATION (TOP VIEW) NC 1 20 NC NC 1 24 NC NAR 2 19 SD NC 2 23 NC BUSY 3 18 SI MD 4 17 RESET NC 5 16 NC NC 6 15 NC VREF 7 14 NC 3 22 NC NAR 4 21 SD BUSY MD 5 20 SI 6 19 RESET NC VREF 7 18 NC GND 8 17 ST AOUT GND 8 13 ST AOUT 9 12 CLK NC 10 11 VDD 9 16 CLK NC 10 15 VDD NC 11 14 NC NC 12 13 NC 20-Pin Plastic SSOP 24-Pin Plastic SOP NC: No connection Leave the NC pin open. Note : If the 20-Pin Plastic SSOP is used, contact the Oki sales office for availability and specifications. 3/26 FEDL2215-01 1Semiconductor ML2215 PIN DESCRIPTIONS Pin Symbol Type Description 17 (19) RESET l “L” input to this pin turns the LSI into standby mode. At this point, output from the AOUT pin rises up to VDD level, having the LSl initialized internally. By “H” input to the pin the AOUT output returns to 1/2 VDD level. 2 (4) NAR O This pin outputs a signal showing empty/full status of the Phase Address Latch Resister. “H” level indicates the register is empty, and thus the LSI is ready to accept serial data input. At powering up, the pin outputs “H level”. 3 (5) BUSY O Output “L” level while output signal is present either at the AOUT or MD pin. At powering up, the pin outputs “H” level. 4 (6) MD O Music output pin 7 (7) VREF I DAC reference pin. Leave this pin open when not used. 9 (9) AOUT O Analog output pin Ground pin 8 (8) GND — 12 (16) CLK l 18 (20) Sl l Serial clock input pin l Serial data input pin. Input a phrase code corresponding to a phrase address through this pin. 19 (21) SD External clock input pin 13 (17) ST l This pin is used when 3-pin interfacing is selected. When 3-pin inter-facing is selected, input to the SD and Sl pins is valid while the ST pin being held “L”. When this pin is at “H” level, speech synthesis is started. When 2-pin interfacing is selected, connect this pin to GND. Mask option allows the user to select either 3-pin interfacing or 2-pin interfacing. 11 (15) VDD — Power supply pin. Insert 0.1 µF or larger bypass capacitor between this pin and the GND pin. * 20-pin plastic SSOP (24-pin plastic SOP) 4/26 FEDL2215-01 1Semiconductor ML2215 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Power Supply Voltage Condition VDD Input Voltage VIN Storage Temperature TSTG Ta = 25°C — Rating Unit –0.3 to +7.0 V –0.3 to VDD+0.3 V –55 to +150 °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Range Unit Power Supply Voltage VDD — 2.4 to 5.5 V Operating Temperature TOP — –40 to +85 °C 4.096 External Clock Frequency fEXTCK Selected as Mask options 8.192 MHz 16.384 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 2.4 to 5.5 V, GND = 0 V, Ta = –40 to 85°C) Parameter “H” Input Voltage Symbol Condition Min. Typ. Max. Unit VIH — 0.87 × VDD — — V “L” Input Voltage VIL — — — 0.13 × VDD V “H” Output Voltage VOH lOH = –500 µA VDD–0.3 — — V “L” Output Voltage VOL lOL = 1 mA — — 0.4 V “H” Input Current IIH VIH = VDD — — 10 µA “L” Input Current IIL VIL = GND –10 — — µA Operating Power Consumption IDD — — 1 4 mA Standby Power Consumption IDS1 Ta = –40 to +50°C — — 10 µA Standby Power Consumption IDS2 Ta = 50 to +85°C — — 30 µA |VDAE| — — — 40 mV DA Output Relative Error 5/26 FEDL2215-01 1Semiconductor ML2215 AC Characteristics (VDD = 2.4 to 5.5 V, GND = 0 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit fduty — 40 50 60 % RESET Input Pulse Width tW(RST) — 10 — — µs RESET Input Time after Powering Up tD(RST) — 0 — — µs Serial Clock Pulse Width tW(Sl) — 350 — — ns Start Pulse Width tSDST With 2-pin interfacing 1 — — µs Serial Data Setup Time tSDS — 1 — — µs Serial Data Hold Time tSSD — 1 — — µs Serial Clock Setup Time tSlS With 3-pin interfacing 1 — — µs Serial Clock Hold Time tSSI With 3-pin interfacing 1 — — µs CLK Duty Cycle Analog Characteristics (VDD = 2.4 to 5.5 V, GND = 0 V, Ta = –40 to +85°C) Symbol Condition Min. Typ. Max. Unit AOUT Output Voltage Range Parameter VAO — VDD/4 — VDD V AOUT Pull-up Resistor Value RAO — 0.5 — 4.5 kΩ 6/26 FEDL2215-01 1Semiconductor ML2215 AOUT Equivalent Circuit RAO Internal reference voltage AOUT Internal control signal As shown above, the ML2215 uses current type DACs. 7/26 FEDL2215-01 1Semiconductor ML2215 TIMING DIAGRAM 1. At powering up tD(RST) VDD RESET tw(RST) BUSY 2. Activating the LSI and Standby status 2.1 When 2-pin interfacing selected as Mask option RESET tSDST SD tSDS tSSD tW(SI) SI NAR BUSY AOUT 2.2 When 3-pin interfacing selected as Mask option RESET STC SD tSIS tSSI SI NAR BUSY AOUT 8/26 Phrase 1 address setting AOUT BUSY NAR SD SI RESET Phrase 2 address setting Phrase 1 playback Phrase 2 address setting Phrase 1 playback Phrase 1 address setting 2) Continuous playback by BUSY AOUT BUSY NAR SD SI RESET 1) Continuous playback by NAR 3. Continuous Playback Timing 3.1 When 2-pin interfacing selected as Mask option Phrase 2 playback Phrase 3 address setting Phrase 2 playback Phrase 3 address setting Phrase 3 playback STOP cord input Phrase 3 playback STOP cord input FEDL2215-01 1Semiconductor ML2215 9/26 Phrase 1 address setting AOUT BUSY NAR SD SI ST RESET Phrase 2 address setting Phrase 1 playback Phrase 2 address setting Phrase 1 playback Phrase 1 address setting 2) Continuous playback by BUSY AOUT BUSY NAR SD SI ST RESET 1) Continuous playback by NAR 3.2 When 3-pin interfacing selected as Mask option Phrase 2 playback Phrase 3 address setting Phrase 2 playback Phrase 3 address setting Phrase 3 playback STOP cord input Phrase 3 playback STOP cord input FEDL2215-01 1Semiconductor ML2215 10/26 FEDL2215-01 1Semiconductor ML2215 FUNCTIONAL DESCRIPTION 1. Specifying a user-defined phrase code for playback The LSI allows a user to define up to 247 phrases. To playback a user-defined phrase, input a phrase code (phrase address) in serial order, starting with the MSB, through the SD pin. SD MSB 2SB 3SB 4SB 5SB 6SB 7SB LSB SI Figure 1.1 Timing for Phrase Code Input When more than 8 SI clocks are input, the first 8-clock data is taken as valid data. Table 1.1 shows phrase codes for user-defined phrases. Table 1.1 Phrase Code for User-defined Phrase MSB to LSB Code Description 00000000 Stop Code 00000001 • • 11110111 User-defined Phrase Codes 11111000 • • 11111111 Test Codes* Note: * No test codes could be used to represent a user-defined phrase. 2. Use-Prohibited Area in on-chip Mask ROM As shown in the Table 2.1, the last 3 bytes of on-chip Mask ROM are use-prohibited. Be sure not to use the last 3 bytes when you prepare ROM data using an analyzing tool. Table 2.1 shows addresses that are prohibited to use, and Figure 2.1 shows the address map of on-chip Mask ROM. Table 2.1 User’s Data Area and Use-Prohibited Area in on-chip Mask ROM User’s Data Area Use-Prohibited Area 007C8 to 5FFFC 5FFFD, 5FFFE, 5FFFF 11/26 FEDL2215-01 1Semiconductor ML2215 00000H 007C7H 007C8H 5FFFCH 5FFFDH 5FFFFH Phrase Control Table Area User’s Date Area Test Date Area Figure 2.1 Mask ROM Address Map 3. Mask Options The following mask options are available to choose an interfacing type and an external clock frequency, as shown in Table 3.1. Table 3.1 Mask Options Option Interfacing Type External Clock Frequency A 3-pin Interfacing 4.096 MHz B 3-pin Interfacing 8.192 MHz C 3-pin Interfacing 16.384 MHz D 2-pin Interfacing 4.096 MHz E 2-pin Interfacing 8.192 MHz F 2-pin Interfacing 16.384 MHz 4. Interfacing Types Mask option allows a user to select a interfacing type and a frequency of external clock input. Available options are listed in Table 3.1 below. 4.1 2-pin Controlled Serial Input Interface 2-pin interfacing uses the SD and SI pins to control interfacing. Pull the ST pin down to “L”. tSDST SD SI NAR BUSY Figure 4.1 Timing Chart of Serial Input As shown in Figure 4.1, serial data input is enabled by entering 1 µsec or longer “L” input (the Start-bit input) to the SD pin. Serial data input to the SD pin is fetched to the internal register in synchronization with the falling edge of the SI’s 8th clock as a phrase code for a user-defined phrase. 12/26 FEDL2215-01 1Semiconductor ML2215 You must input the external clock to the CLK pin. Otherwise, serial data input cannot be acquired internally, regardless tSDST ≥ 1 µs or tSDST < 1 µs. tSDST tSDST SD SI NAR BUSY Figure 4.2 Timing Chart of Serial Input As shown in Figure 4.2, re-inputting the Start-bit before the SI’s 8th clock cancels the preceding serial data entry, and 8-clock data following the Start-bit is taken as valid data. 4.2 3-pin Controlled Serial Input Interface 3-pin interfacing uses the SD, SI and ST pins to control interfacing. ST SD SI NAR BUSY Figure 4.3 Timing Chart of Serial Input When 3-pin interfacing is selected, input to the SD and SI pins is enabled while the ST pin being held “L”. Serial data input to the SD pin is acquired to the internal register in synchronization with the falling edge of the SI’s 8th clock as an 8-bit phrase code for a user-defined phrase. If the ST pin is brought back to “H” before the SI’s 8th clock, the preceding entry is cancelled, and 8-clock data after the ST pin being brought back to “L” again is taken as valid data. 13/26 FEDL2215-01 1Semiconductor ML2215 5. External Clock Input Mask option allows a user to choose an external clock frequency, as shown in Table 5.1. Table 5.1 External Clock Frequency and Sampling Frequency External Clock Frequency 4.096 MHz Internal Sampling Frequency 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.7 kHz, 12.8 kHz, 16.0 kHz 8.192 MHz 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.7 kHz, 12.8 kHz, 16.0 kHz 16.384 MHz 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.7 kHz, 12.8 kHz, 16.0 kHz When an external clock frequency were chosen as Mask option and a different frequency input were made, the sampling frequency changes in proportion to the actual input frequency. For example, while 4.096 MHz external clock frequency option was selected as Mask option, and when 6.144 MHz external clock is actually input, then the sampling frequency changes accordingly, e.g. sampling frequency at 1.5 times of those shown in Table 5.1. 6. Stop Code The Stop code input (Table 1.1) to the SD pin during playback let the LSI stop playback on the SI’s falling edge following to the LSB input, and the AOUT fall down to 1/2 VDD level. If the LSI playbacks a music phrase, music stops as well. Timings for the Stop code input are shown below, for 2-pin interfacing in Figure 6.1 and for 3-pin interfacing in Figure 6.2 respectively. SD SI BUSY STOP Figure 6.1 Timing for Stop Code Input - 2-pin Interfacing ST SD SI BUSY STOP Figure 6.2 Timing for Stop Code Input - 3-pin Interfacing 14/26 FEDL2215-01 1Semiconductor ML2215 7. Volume Setting The volume of the AOUT pin can be adjusted by applying voltage to the VREF pin. 5 Amplitude Voltage (Vp-p) 4 3 2 1 0 0 1 2 3 4 5 VREF (V) Figure 7.1 VREF – AOUT Amplitude Figure 7.1 shows the relationship between the VREF voltage and the AOUT amplitude. Set the VREF voltage in the range of 1 to 4 V. The relationship is given by the equation: AOUT (p-p) ≅ 5 − VREF (VREF = 1 to 4 V). When a volume is not adjusted, leave the VREF pin open. 8. Music Generator The Music Generator circuit initiates music output via the MD pin by activating a user-defined music phrase from an external controller. The Music Generator outputs music, automatically acquiring musical notes data stored in the Mask ROM. Acquiring the last note code where the end-bit is set to “1”, results in stopping playback. A user can define a music phrase by entering the starting address and tempo data in the Phrase Control Table, and codes for musical notes and the end-bit information in the User’s Data area. These data for a music phrase, based on the score of music, can be created and entered by using an OKI’s Analyzing Tool according to coding rules and formats described later in this document. 8.1 Tempo Data Tempo data for a music phrase can be defined in the Phrase Control Table while preparing ROM data. Tempo cannot be changed from an external controller. Tempo data defines a beat and rhythm for a music phrase. Table 8.1 lists tempos (the count of quarter notes per minute) available for user’s selection. 15/26 FEDL2215-01 1Semiconductor ML2215 Table 8.1 Tempos for Music Phrases TEMPO 0H TP4 TP3 TP2 TP1 TP0 0 0 0 0 0 Tempo = 625 1H 0 0 0 0 1 = 625 2H 0 0 0 1 0 = 416.7 3H 0 0 0 1 1 = 312.5 4H 0 0 1 0 0 = 250 5H 0 0 1 0 1 = 208.3 6H 0 0 1 1 0 = 178.6 7H 0 0 1 1 1 = 156.7 8H 0 1 0 0 0 = 138.9 9H 0 1 0 0 1 = 125 AH 0 1 0 1 0 = 113.6 BH 0 1 0 1 1 = 104.2 CH 0 1 1 0 0 = 96.2 DH 0 1 1 0 1 = 89.3 EH 0 1 1 1 0 = 83.3 FH 0 1 1 1 1 = 78.1 10H 1 0 0 0 0 = 73.5 11H 1 0 0 0 1 = 69.4 12H 1 0 0 1 0 = 65.8 13H 1 0 0 1 1 = 62.5 14H 1 0 1 0 0 = 59.5 15H 1 0 1 0 1 = 56.8 16H 1 0 1 1 0 = 54.3 17H 1 0 1 1 1 = 52.1 18H 1 1 0 0 0 = 50 19H 1 1 0 0 1 = 48.1 1AH 1 1 0 1 0 = 46.3 1BH 1 1 0 1 1 = 44.6 1CH 1 1 1 0 0 = 43.1 1DH 1 1 1 0 1 = 41.7 1EH 1 1 1 1 0 = 40.3 1FH 1 1 1 1 1 = 39.1 16/26 FEDL2215-01 1Semiconductor ML2215 8.2 Musical Note Data Musical note data consists of 2 bytes and is stored in the Mask ROM’s User’s Data area, where a user can define scale, note and the end-bit for a music phrase. Table 8.2 shows the coding format for musical note data. Table 8.2 Coding Format for Musical Note Data The First Byte The Second Byte NSB 7SB 6SB 5SB 4SB 3SB 2SB LSB END-Bit 0 L5 L4 L3 L2 L1 L0 Musical Note Code N7 N6 N5 N4 N3 N2 N1 N0 Musical Scale Code (1) Musical Scale Code Musical scale code is defined at the second byte. The following equation shows output frequency from the Music Generator circuit at 4.096 MHz external clock. 32 (N + 2) kHz (“N” is integer between 4 to 127) Co-relationship between “N” and musical scale can be calculated as follows: N = 27N7 + 26N6 +25N5 + 24N4 + 23N3 + 22N2 + 21N1 + 20N0 When all values for N7 to N2 are set to “0”, no music is reproduced during the period specified by the note code. At this instance, the values of N1 and N0 have no significance (Don’t care). Table 8.3 shows major musical scales (keys) and their corresponding scale codes. 17/26 FEDL2215-01 1Semiconductor ML2215 Table 8.3 Musical Scales and Corresponding Scale Codes Musical Scale Frequency (Hz) N7 N6 N5 N4 N3 N2 N1 N0 N7 to N0 C1 261.22 1 1 1 1 0 0 1 1 F3H Cis 1 Scale Code 277.06 1 1 1 0 0 1 0 1 E5H D1 293.58 1 1 0 1 1 0 0 0 D8H Dis1 310.68 1 1 0 0 1 1 0 0 CCH 1 E 329.90 1 1 0 0 0 0 0 0 C0H F1 349.73 1 0 1 1 0 1 0 1 B5H Fis 369.94 1 0 1 0 1 0 1 1 ABH 1 G 392.64 1 0 1 0 0 0 0 1 A1H Gis1 415.58 1 0 0 1 1 0 0 0 98H A 441.38 1 0 0 0 1 1 1 1 8FH Ais1 467.15 1 0 0 0 0 1 1 1 87H 1 492.31 1 0 0 0 0 0 0 0 80H 2 C 524.59 0 1 1 1 1 0 0 0 78H Cis2 556.52 0 1 1 1 0 0 0 1 71H 587.16 0 1 1 0 1 0 1 1 6BH 1 1 B 2 D Dis 2 621.36 0 1 1 0 0 1 0 1 65H E2 659.79 0 1 0 1 1 1 1 1 5FH F2 695.65 0 1 0 1 1 0 1 0 5AH Fis2 744.19 0 1 0 1 0 1 0 0 54H 780.49 0 1 0 1 0 0 0 0 50H 831.17 0 1 0 0 1 0 1 1 4BH 876.71 0 1 0 0 0 1 1 1 47H 927.54 0 1 0 0 0 0 1 1 43H 2 G Gis 2 A2 Ais 2 2 B 984.62 0 0 1 1 1 1 1 1 3FH C3 1049.18 0 0 1 1 1 0 1 1 3BH Cis3 1103.45 0 0 1 1 1 0 0 0 38H D3 1185.19 0 0 1 1 0 1 0 0 34H 31H Dis 3 1254.90 0 0 1 1 0 0 0 1 3 E 1306.12 0 0 1 0 1 1 1 1 2FH F3 1391.30 0 0 1 0 1 1 0 0 2CH Fis3 1488.37 0 0 1 0 1 0 0 1 29H (2) Musical Note Code The first byte of music data code is where a user can define musical note code. Table 8.4 shows musical notes and their corresponding note codes (L5 to L0). When all bits are set to “0”, the duration or beat of the note is identical to that of the code with L0 alone set to “1” (1/64). 18/26 FEDL2215-01 1Semiconductor ML2215 Table 8.4 Musical Notes and Corresponding Note Codes Musical Note Note Code L5 L4 L3 L2 L1 L0 L5 to L0 1 1 1 1 1 1 3FH 1 0 1 1 1 1 2FH 0 1 1 1 1 1 1FH 0 1 0 1 1 1 17H 0 0 1 1 1 1 0FH 0 0 1 0 1 1 0BH 0 0 0 1 1 1 07H 0 0 0 1 0 1 05H When N6 to N0 are set to “0” in scale code definition, the code means “Rest”. Table 8.5 shows rests and their corresponding rest codes (L5 to L0). Table 8.5 Rests and Corresponding Rest Codes Rest Rest Code L5 L4 L3 L2 L1 L0 L5 to L0 1 1 1 1 1 1 3FH 0 1 1 1 1 1 1FH 0 1 0 1 1 1 17H 0 0 1 1 1 1 0FH 0 0 0 1 1 1 07H 0 0 0 0 1 1 03H The following formula can be used to calculate the duration or beat of a musical note (including rest), that is defined by a note code and tempo code. 1.5 × (TP+1) × (L+1) msec (Where TP is integer between 1 to 31, and L is integer between 4 to 63) TP is a numerical value defined in the Phrase Control Table and its bit correspondence to tempo data can be calculated as follows: TP = 24TP4 + 23TP3 + 22TP2 + 21TP1 + 20TP0 Meanwhile, L is defined by a musical note code, and its bit correspondence to the musical note code can be calculated as follows: L = 25L5 + 24L4 + 23L3 + 22L2 + 21L1 + 20L0 19/26 FEDL2215-01 1Semiconductor ML2215 (3) End-Bit The end-bit is set at the first byte, the MSB, of music phrase data. As soon as the LSI starts to output the last note code where the end-bit is set to “1”, the Music Generator circuit issues an end-music interrupt call and stops playback after the last note code has been output. 8.3 Sample Musical Note Codes Table 8.6 shows sample codes to output a part of musical score shown in Figure 8.3. =120 Figure 8.3 Table 8.6 Coding Sample Note Code 1st Byte Musical Note 7 6 END —* 2nd Byte 5 4 3 2 1 0 7 6 5 4 3 2 1 0 L5 L4 L3 L2 L1 L0 N7 N6 N5 N4 N3 N2 N1 N0 Hexadecimal 2 G 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 2F50H D2 0 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0F6BH G2 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 0 1750H 2 0 0 0 0 0 1 1 1 0 1 1 0 1 0 1 1 076BH 2 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 0 1750H 2 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0747H 2 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 3F3FH 2 1 0 1 1 1 1 1 1 0 1 0 1 0 0 0 0 BF50H D G A B G Note: * Bit 6 of the first byte can be either “0” or “1” (Don’t care bit), so is set to “0” in the above sample codes. 20/26 FEDL2215-01 1Semiconductor ML2215 9. Buzzer You can define a buzz phrase by setting a frequency and sound type in the Phrase Control Table and a buzz phrase in the User’s Data area. To start buzzer output via the MD pin, activate a buzz phrase. To stop buzzer output, enter the Stop Code. 4 buzzing sound types, intermittent 1, intermittent 2, single and continuous, and 3 50%-duty frequencies, at 0.5 kHz, 1.0 kHz and 2.0 kHz, are available for user selection, depending on buzzer output mode setup in the Phrase Control Table. Figure 9.1 shows output wave-form in respective output modes. Black-filled wave-form indicates buzz output signal at 0.5/1.0/2.0 kHz. STOP BUSYB 8 Hz OUTPUT MD ON OFF (a) TP1 = 0, TP0 = 0 (intermittent 1) STOP BUSYB 8 Hz 1 Hz OUTPUT MD ON OFF (b) TP1 = 0, TP0 = 1 (intermittent 2) STOP BUSYB 32 Hz OUTPUT MD ON OFF (c) TP1 = 1, TP0 = 0 (single) STOP BUSYB ON OUTPUT MD OFF (d) TP1 = 1, TP0 = 1 (continuous) Figure 9.1 Output Wave-form from the Buzzer Driver in Each Output Mode 21/26 FEDL2215-01 1Semiconductor ML2215 10. Low Pass Filter ML2213’s analog output goes through the built-in Low Pass Filter. The Figure 10.1 below shows Frequency Characteristics and Table 10.1 shows Cut-off Frequency of the LPF. No analog output passing through the LPF is available on this chip. [dB] 20 10 0 –10 –20 –30 –40 –50 –60 –70 –80 10 100 1k 10 k [Hz] Figure 10.1 LPF Frequency Characteristics (fSAM = 8 kHz) Table 10.1 LPF Cut-off Frequency Sampling Frequency (kHz) (fSAM) Cut-off Frequency (kHz) (fCUT) 4.0 1.2 5.3 1.6 6.4 2.0 8.0 2.5 10.6 3.2 12.8 4.0 16.0 5.0 11. AOUT Connecting Circuit It is recommended to connect a capacitor of 0.01 to 0.033 µF to the AOUT pin. The circuit diaram is as shown below. AOUT 0.01 to 0.033 µF The capacitor is used for improving a voice quality. Check the voice quality before determining the capacitor value. If the voice quality is excellent without connecting a capacitor, no capacitor is required. 22/26 FEDL2215-01 1Semiconductor ML2215 APPLICATION CIRCUITS When 2-pin interfacing is selected (Fix the ST pin to GND.) SD SI ST MCU VDD ML2215 AMP AOUT RESET BUSY NAR CLK MD AMP Piezoelectric speaker GND 23/26 FEDL2215-01 1Semiconductor ML2215 PACKAGE DIMENSIONS (Unit : mm) SSOP20-P-44-0.65-K Mirror Finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.088 TYP. 1/Jan. 22, 1999 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/26 FEDL2215-01 1Semiconductor ML2215 (Unit: mm) SOP24-P-430-1.27-K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.58 TYP. 5/Oct. 13, 1998 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 25/26 FEDL2215-01 1Semiconductor ML2215 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd. 26/26